TW423139B - Method for forming barrier layer on copper surface - Google Patents

Abstract

The present invention provides a method for forming barrier layer on copper surface, which comprises: first, forming a copper member having an exposed surface on the surface of the semiconductor substrate; then, comprehensively forming a diffusion barrier layer such as tantalum nitride; next, removing the diffusion barrier layer on an area beyond the surface of the above mentioned copper interconnects. With the method of the present invention, the performance of the device can be promoted.

Description

423139423139

2月係有關於-種半導體積體f路的製造流程，特 別是有關於一種在銅金屬内連線形成擴散阻障層 (diffusion barrier iayer)的製造流程。 不 線，半 連線當 多層内 助接觸 之間或 由於銅 的材質 的特性 件均少不了用來傳輸電訊的金屬導 元件亦然，各個元件必藉由適當的内 方得以發揮所欲達成之功能。在今日 除了製作各層導線圖案之外，更須藉 i a)構成，以作為元件接觸區與導線 間的聯繫通道。在内連線材質方面， 性，高延展性等優點’成為廣受矚目 由於銅金屬易向氧化層等絕緣層擴散 的銅内連線表面形成一擴散阻障層。 論何種電子元 導體積體電路 作電性連接， 連線製程中， 孑L(contact v 是多層導線之 金屬的高傳導 之一。然而， ’必須在裸露 以下即利用第1A〜1E圖，以說明習知技術具有銅擴散 阻障層（氮化矽層）之銅金屬内連線製造流程。 首先’請參照第1A圖’其顯示半導體基底1〇上方形成 有裸露出上表面的銅金屬内連線12 ^ 接著’請參照第1B圖，在上述半導體基底10表面全面 性形成氮化矽層（S i 3 N 4) 1 4，用以當作銅的擴散阻障層。 然後’請參照第1 C圖，在上述氮化矽層1 4構成的擴散阻障 層上方形成氧化材料構成的絕緣層1 6。 之後’請參照第1 D圖，進行選擇性蝕刻步驟以形成具 有介層孔17以及溝槽18的雙鑲嵌接觸孔，接著，請參照苐 1E圖’在上述雙鑲嵌接觸孔内填入銅金屬，以形成銅金屬 内連線。February is about a manufacturing process of a semiconductor integrated circuit f, in particular, a manufacturing process of forming a diffusion barrier iayer in copper metal interconnects. In the case of non-wired, semi-wired, multi-layered internal contact, or due to the characteristics of the copper material, the metal conducting elements used to transmit telecommunications are also indispensable. Each element must perform its desired function by an appropriate internal device. In addition to making various layers of wire patterns today, i a) must also be used as a communication channel between the component contact area and the wires. In terms of the material of the interconnector, the advantages such as flexibility and high ductility have attracted much attention because the copper interconnects on the surface of the copper interconnects which easily diffuse into the insulating layer such as an oxide layer form a diffusion barrier layer. Regarding what kind of electronic conductive body circuit is used for electrical connection, in the connection process, 孑 L (contact v is one of the high conductivity of the metal of the multi-layer wire. However, 'must be exposed below, that is, using Figures 1A ~ 1E, To explain the manufacturing process of a copper metal interconnect with a copper diffusion barrier layer (silicon nitride layer) according to the conventional technology. First, please refer to FIG. 1A, which shows that a copper metal with an exposed upper surface is formed on the semiconductor substrate 10. Interconnect 12 ^ Then, 'Please refer to FIG. 1B, a silicon nitride layer (S i 3 N 4) 1 4 is formed on the surface of the semiconductor substrate 10 as a diffusion barrier layer for copper. Then' Please Referring to FIG. 1C, an insulating layer 16 made of an oxide material is formed over the diffusion barrier layer composed of the silicon nitride layer 14 described above. Then, referring to FIG. 1D, a selective etching step is performed to form a dielectric layer. The double damascene contact hole of the hole 17 and the trench 18 is then filled with copper metal in the double damascene contact hole as shown in FIG. 1E to form a copper metal interconnect.

第4頁 五、發明說明（2) 藉由上 構成的絕緣 (k)高達6〜9 矽材料當作 件效能（p e r 有鑑於 形成阻障層 屬内連線的 根據上 障層的方法 一具有裸露 擴散阻障層 的上述含纽 上述銅 構件係銅金 阻障層係厚 屬層。 再者， 括選擇性蝕 為了攀 僅’下文特 明如下： 圖式之簡單 第1 A圖 述製程，雖然可有效地防止銅金屬往氧化材料 層擴散，然而，由於氮化矽材料的介電常數 ，遠大於介電常數約為4的氧化層，利用氮化 擴散阻障層，將増加導線的RC延遲，而影響元 formance) ° 此，本發明的目的在於提供一種在銅金屬表面 的方法，藉由變更擴散阻障層的材料以及銅金 製造步騍，可提高元件效能。 述目的，本發明提供一種在銅金屬表面形成阻 ，包括下列步驟：（a)在半導體基底表面形成 表面的銅金屬構件；（b)全面性形成一含鈕之 ，以及（c)去除上述銅金屬構件表面以外區 之擴散阻障層。 金屬表面形成擴散阻障層的方法，其中銅金 屬插塞或是銅金屬内連線。而上述含鈕之擴 度介於30埃〜1 000埃之間的氮化鈕層或是鉅金 上述步驟（c)去除含钽之擴散阻障層的方法包 刻法以及化學機械研磨法。 本發明之上述㈣、特徵、和優點能更明顯易 舉一較佳實施例，並配合所附圖式，作詳細說 說明： 〜第1E圖為習知技術具有鋼擴散阻障層（氮化石夕Page 4 V. Description of the invention (2) With the insulation (k) up to 6 ~ 9 made of the above silicon material as a piece of performance (per the method based on the upper barrier layer in which the barrier layer belongs to the interconnections has The above-mentioned copper member containing the diffusion barrier layer and the above-mentioned copper member system is a copper-gold barrier layer, which is a thick metal layer. Furthermore, the selective etching process is specifically described below: The simple process of FIG. 1A illustrates the process, Although it can effectively prevent copper metal from diffusing into the oxidized material layer, the dielectric constant of the silicon nitride material is much larger than the oxide layer with a dielectric constant of about 4, and the nitrided diffusion barrier layer is used to increase the RC of the wire. Delay, which affects the element's performance) ° Therefore, the object of the present invention is to provide a method on the surface of copper metal, which can improve the device performance by changing the material of the diffusion barrier layer and the copper-gold manufacturing steps. For the stated purpose, the present invention provides a copper metal surface forming resistor, including the following steps: (a) forming a copper metal member on the surface of a semiconductor substrate; (b) forming a button with a comprehensive structure; and (c) removing the copper Diffusion barrier layer outside the surface of the metal member. A method for forming a diffusion barrier layer on a metal surface, in which a copper metal plug or a copper metal interconnect is used. The button-containing nitride layer or giant gold with an expansion between 30 angstroms and 1,000 angstroms. The method of step (c) for removing the diffusion barrier layer containing tantalum includes engraving and chemical mechanical polishing. The above-mentioned features, advantages, and advantages of the present invention can be more clearly described as a preferred embodiment, and will be described in detail in conjunction with the accompanying drawings: ~ Figure 1E is a conventional technology having a steel diffusion barrier layer (nitride) Xi

C4 1 3 9C4 1 3 9

五、發明說明（3) 層）之銅金屬内連線製程剖面示意圖。 第2 A圖〜第2E圖為根據本發明實施例具有鋼擴散阻障 層（氮化组層）之銅金屬内連線製程剖面示意圖。月 符號之說明 100〜半導體基底。 102~銅金屬構件（銅金屬内連線）。 104〜含鈕之擴散阻障層（氮化鈕層）。 104a〜含鈕之擴散阻障物。 10 6〜氧化絕緣層。 1 0 7〜介層孔。 108~溝槽。 110〜雙鑲嵌式銅内連線。 實施例 以下利用第2Α圖至第2Ε圖，以說明本發明實施例具有 銅擴散阻障層（氮化钽層）之鋼金屬内連線製造流程。 首先’請參照第2Α圖，其為本發明之起始步驟，其顯 示形成有若干積體電路元件（MOS電晶體等）之半導體基底 100 ’上述半導體基底100上方形成一具有裸露出上表面的 銅金屬構件102，上述銅金屬構件102例如為鋼金屬插塞< 是銅金屬内連線，而其些微凹陷的表面是由於經過化學機 械研磨法（chemical mechanical polishing ;CMP)處理所 致。另外，銅金屬構件102的底部及侧壁亦可形成圖未顯 示的氮化鈦（ΠΝ)等薄層。 接著’請參照第2B圖’在上述半導體基底100表面全V. Description of the invention (3) Layer) The schematic diagram of the copper metal interconnect process. Figures 2A to 2E are schematic cross-sectional views of a copper metal interconnect process with a steel diffusion barrier layer (nitriding group layer) according to an embodiment of the present invention. Explanation of the month symbol 100 ~ semiconductor substrate. 102 ~ copper metal components (copper metal interconnects). 104 ~ A diffusion barrier layer (nitride button layer) containing a button. 104a ~ Diffusion barrier with buttons. 10 6 ~ oxidized insulating layer. 1 0 7 ~ via hole. 108 ~ groove. 110 ~ Double inlaid copper interconnects. Examples The following uses Figures 2A to 2E to illustrate the manufacturing process of a steel metal interconnect with a copper diffusion barrier layer (tantalum nitride layer) according to an embodiment of the present invention. First, please refer to FIG. 2A, which is the initial step of the present invention, which shows a semiconductor substrate 100 formed with a number of integrated circuit elements (MOS transistors, etc.). The copper metal member 102 is, for example, a steel metal plug < is a copper metal interconnect, and the slightly concave surface is caused by chemical mechanical polishing (CMP) treatment. In addition, a thin layer such as titanium nitride (ΠN) may be formed on the bottom and side walls of the copper metal member 102. Next, please refer to FIG. 2B.

第6頁Page 6

五、發明說明（4) 面性形成一厚度介於30〜1000埃的含组之擴散阻障層1〇4， 例如以化學氣相沈積法（chemical vapor deposition ; CVD)形成之氮化鉅層（TaN)、或是以物理濺鍍法形成之钽 金屬層（T a)等，其中以氮化鈕層具有較佳的擴散阻障能 力，可有效地阻隔裸露的銅往後述之氧化絕緣層（ox i de insulated)擴散。 然後，請參照第2C圖，利用微影製程（負光阻 (negative photoresi st)之塗佈、曝光、顯影、烘烤）形 成光阻圖案（未顯示），然後利用蝕刻步驟以蝕刻未被光阻 圖案覆蓋的含鈕之擴散阻障層104，以去除上述銅金屬構 件102以外區域的含钽之擴散阻障層1〇4，而留下覆蓋於銅 金屬構件102的阻障物l〇4a。當然亦可利用化學機械研磨 法（CMP)取代上述微影製程以及蝕刻步驟，以去除多餘的 擴散阻障層104。去除多餘氮化钽層等構成的擴散阻障層 的目的是，由於氮化钽等材料具有導電能力，為了避免内 連線之間短路必須去除。 其次’請參照第2D圖，利用例如四乙氧基矽烷（TE0S) 等氣體當作反應氣體，並且以化學氣相沈積法以全面性形 成覆蓋上述半導體基底1〇〇以及阻障物l〇4a的氧化絕緣層 106。 最後，請參照第2 E圖，利用傳統方法進行兩階段選擇 性蝕刻上述氧化絕緣層，以形成露出上述阻障物1 〇 4 a之鑲 嵌式接觸孔DC，上述鑲嵌式接觸孔包括介層孔1 〇 7以及溝 槽1 08。然後利用物理氣相沈積法（pvD)或是電鍍沈積法V. Description of the invention (4) Planar formation of a group-containing diffusion barrier layer 104 having a thickness of 30 to 1000 angstroms, such as a giant nitride layer formed by chemical vapor deposition (CVD) (TaN), or a tantalum metal layer (T a) formed by a physical sputtering method. Among them, the nitride button layer has a better diffusion barrier ability, which can effectively block the oxidized insulating layer described later on the bare copper. (Ox i de insulated) Diffusion. Then, referring to FIG. 2C, a photoresist pattern (not shown) is formed by using a lithography process (coating, exposure, development, and baking of negative photoresi st), and then an etching step is used to etch the unlit photoresist. The button-containing diffusion barrier layer 104 covered by the resist pattern removes the tantalum-containing diffusion barrier layer 104 in areas other than the above-mentioned copper metal member 102, and leaves a barrier 104 covering the copper metal member 102 . Of course, chemical mechanical polishing (CMP) can be used instead of the lithography process and the etching step to remove the excess diffusion barrier layer 104. The purpose of removing the diffusion barrier layer formed by the redundant tantalum nitride layer and the like is that since materials such as tantalum nitride have conductivity, it must be removed in order to avoid short circuits between the interconnects. Secondly, please refer to FIG. 2D, use a gas such as tetraethoxysilane (TE0S) as a reaction gas, and comprehensively form the semiconductor substrate 100 and the barrier 104a by chemical vapor deposition.的 oxidative insulating layer 106. Finally, referring to FIG. 2E, a conventional method is used to selectively etch the oxide insulating layer in two stages to form a mosaic contact hole DC that exposes the above-mentioned barrier 104a, and the mosaic contact hole includes a via hole 1 07 and groove 1 08. Then use physical vapor deposition (pvD) or electroplating

五、發明說明（5) (electroplating)在上述接觸孔DC内填入銅金屬等材料， 以形成雙鑲嵌式銅内連線11〇。 發明特徵及功效 本發明在鋼金屬内連線等構件形成後，採用低介電常 數（low k)之氮化鈕等材料當作擴散阻障層，並且配合銅 金屬内連線以外的擴散阻障層之去除步驟，不但可有效地 防止銅金屬往氧化絕緣層的牌邶 、麽 ± 一 嚐的擴政，並且可減少RC時間延 遲，而提高元件效能。 丁」、 雖然本發明已 限定本發明，任何熟習此項技蓺者 ’然其並非用 神和範圍内’當可作更動與潤； ：離本發明之 當視後附之申請專利範圍所界^本發明之保護範5. Description of the invention (5) (electroplating) Filling the above-mentioned contact hole DC with a material such as copper metal to form a double-inlaid copper interconnecting line 110. Features and Effects of the Invention After the formation of steel metal interconnects and other components, the present invention uses materials such as low-k dielectric nitride buttons as diffusion barriers, and cooperates with diffusion barriers other than copper metal interconnects. The step of removing the barrier layer can not only effectively prevent the copper metal from expanding to the oxide insulating layer, but also reduce the RC time delay and improve the device performance. Ding ", although the present invention has limited the invention, any person skilled in the art," but he does not use God and the scope "should be able to make changes and embellishments;: from the scope of the patent application attached to the present invention ^ Protection scope of the present invention

第8頁Page 8

Claims (1)

^23139 六、申請專利範圍 1. 一種在銅金屬表面形成阻障層的方法，包括下列步 驟 構件 ，）在半導體基底表面形成一具有裸露表面的銅金屬 C b)全面性形成一含钽之擴散阻障層；以及 (c)去除上述銅金層構件表面以外區域的上述含纽之 擴散阻障層。 2. 如申請專利範圍第1項所述之銅金屬表面形 阻障層的方法，其中上述銅金屬構件係銅金屬插塞了· 3. 如申請專利範圍第1項所述之銅金屬表面形 P且障層的方法，其中上述銅金屬構件係銅金屬内連 4·如申請專利範圍第1項所述之銅金屬表面形 阻障層的方法，其中上述含钽之擴散阻障層係钽金 5. 如申請專利範圍第4項所述之銅金屬表面形成阻障 層的方法’其中上述钽金屬層的厚度介於3〇埃丨〇〇〇埃之 間。 6. 如申請專利範圍第1項所述之銅金屬表面形擦 阻障層的方法，其中上述含钽之擴散阻障層係氮化 7. 如申請專利範圍第6項所述之銅金屬表面形成阻障 層的方法’其中上述氮化鉅層的厚度介於30埃、1000埃之 間。 、 8·如申請專利範圍第1項所述之銅金屬表面形成阻障 層的方法’其中步驟（C)去除含钽之擴散阻障層的方法為 選擇性蝕刻法。^ 23139 6. Scope of patent application 1. A method for forming a barrier layer on a copper metal surface, including the following steps: (1) forming a copper metal with a bare surface on the surface of a semiconductor substrate; c) comprehensively forming a diffusion containing tantalum A barrier layer; and (c) removing the button-containing diffusion barrier layer in a region other than the surface of the copper-gold layer member. 2. The method for forming a barrier layer on a copper metal surface as described in item 1 of the scope of patent application, wherein the copper metal member is a copper metal plug. 3. The surface shape of the copper metal as described in item 1 of the scope of patent application P and a barrier layer method, in which the above-mentioned copper metal member is a copper metal interconnect 4. The method of forming a barrier layer on a copper metal surface as described in item 1 of the scope of the patent application, wherein the diffusion barrier layer containing tantalum is tantalum Gold 5. The method for forming a barrier layer on the surface of a copper metal as described in item 4 of the scope of the patent application, wherein the thickness of the tantalum metal layer is between 30 Angstroms and 1,000 Angstroms. 6. The method for forming a friction barrier layer on the surface of a copper metal as described in item 1 of the scope of patent application, wherein the diffusion barrier layer containing tantalum is nitrided 7. The surface of the copper metal as described in item 6 of the scope of patent application Method of forming a barrier layer 'wherein the thickness of the above nitrided giant layer is between 30 angstroms and 1000 angstroms. 8. A method for forming a barrier layer on the surface of a copper metal as described in item 1 of the scope of the patent application, wherein the method for removing the diffusion barrier layer containing tantalum in step (C) is a selective etching method. 第9頁Page 9 六、申請專利範圍 之鋼金屬表面形成 之擴散阻障層的方 阻障 法為 9.如申請專利範圍第1項所述 層的方法，其中步驟（c)去除含纽 化學機械研磨法。 層 10·如申請專利範圍第丨項所 的方法，其中步驟（c)更包括下列步驟屬表面形成阻障 (i)全面性形成一氧化絕緣層； 组 (i i )選擇性蝕刻上述氧化絕緣層 之擴散阻障層的鑲嵌式接觸孔。S 以形成露出上述含 包括下列 用以當作鋼 11. 一種在銅金屬表面形成阻障層的 步驟： ' 具有裸露表面的銅金屬 (a)在半導體基底表面形成一 内連線； (b)全面性形成一纽金屬層或氮化紐層 擴散阻障層；以及 (c)去除上述銅金屬内連線表面以外區域的上述組金 屬層或氮化组層。 12·如申請專利範圍第11項所述之鋼金屬表面形成阻 障層的方法’其中步驟（c)去除组金屬或氮化短層的方法 為選擇性蝕刻法·> 13.如申請專利範圍第11項所述之銅金屬表面形成阻 k 障層的方法，其中步驟（c)去除钽金屬或氮化钽層的方法 為化學機械研磨法。 14.如申請專利範圍第11項所述之鋼金屬表面形成阻 障層的方法，其中上述钽金屬或氮化组層的厚度介於30埃6. The method of applying the diffusion barrier layer formed on the surface of steel and metal in the scope of patent application is 9. The method of the layer described in item 1 of the scope of patent application, wherein step (c) removes the chemical mechanical polishing method. Layer 10: The method as described in the first item of the patent application scope, wherein step (c) further includes the following steps: forming a barrier on the surface (i) comprehensively forming an oxide insulating layer; group (ii) selectively etching the oxide insulating layer Mosaic contact hole of the diffusion barrier layer. S to form the exposed layer including the following for use as steel 11. A step of forming a barrier layer on a copper metal surface: 'a copper metal with an exposed surface (a) forms an interconnect on the surface of a semiconductor substrate; (b) Forming a button metal layer or a nitride button layer diffusion barrier comprehensively; and (c) removing the above-mentioned group metal layer or nitride group layer in a region other than the surface of the copper metal interconnect line. 12. The method for forming a barrier layer on the surface of a steel metal as described in item 11 of the scope of the patent application, wherein the method for removing the group metal or the short nitrided layer in step (c) is a selective etching method; > 13. As a patent application The method for forming a k-barrier layer on the surface of a copper metal as described in item 11, wherein the method of removing the tantalum metal or tantalum nitride layer in step (c) is a chemical mechanical polishing method. 14. The method for forming a barrier layer on the surface of a steel metal as described in item 11 of the scope of the patent application, wherein the thickness of the tantalum metal or nitride group layer is between 30 angstroms 第10頁 423139 六、申請專利範圍 〜1 0 0 0埃之間。 15.如申請專利範圍第11項所述之銅金屬表面形成阻 障層的方法，其中步驟（c)更包括下列步驟： (i )全面性形成一氧化絕緣層； (i i )選擇性蝕刻上述氧化絕緣層，以形成露出上述鈕 金屬層或氮化钽層的鑲嵌式接觸孔。Page 10 423139 VI. The scope of patent application is between 100 Angstroms. 15. The method for forming a barrier layer on the surface of a copper metal according to item 11 of the scope of patent application, wherein step (c) further includes the following steps: (i) forming a comprehensive oxide insulating layer; (ii) selectively etching the above The insulating layer is oxidized to form a mosaic contact hole exposing the button metal layer or the tantalum nitride layer. 第11頁Page 11