TW423128B - Chip scale package structure - Google Patents

Chip scale package structure Download PDF

Info

Publication number
TW423128B
TW423128B TW088118628A TW88118628A TW423128B TW 423128 B TW423128 B TW 423128B TW 088118628 A TW088118628 A TW 088118628A TW 88118628 A TW88118628 A TW 88118628A TW 423128 B TW423128 B TW 423128B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
wafer
package structure
filler particles
Prior art date
Application number
TW088118628A
Other languages
Chinese (zh)
Inventor
Ching-Huei Su
Su Tau
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW088118628A priority Critical patent/TW423128B/en
Application granted granted Critical
Publication of TW423128B publication Critical patent/TW423128B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

This invention is about chip scale package (CSP) structure that mainly includes a semiconductor chip installed on the substrate surface and sealed by an encapsulation body. This encapsulation body includes a resin base material that is divided into the first layer and the second layer. This resin base material includes plural filler particles, in which the content of the filler particle in the first layer is smaller than the content of the filler particle in the second layer. Because the coefficient of thermal expansion (CTE) of filler particle is smaller, the CTE of the second layer is smaller to function as the buffer of the stress generated by CTE mismatch between substrate and chip. Additionally, the content of filler particle in the second layer is larger such that the invasion of water moisture can be effectively prevented and the problem of delamination or die cracking can be improved.

Description

423128 五、發明說明〇) 發明領域·+ 本發明係有關於一種晶片尺寸級封裝構造之封膠體， 其特別有關於一種用以密封設在基板上之半導體晶片的封 膠體。 先前技術： 習用之晶片尺寸級封裝構造（chip scale package, CSP)如第一、二、三圖所示，其一般皆包含一半導體晶片 110藉由一彈性體（elastomer)120設於一基板130之上表 面。該晶片尺寸級封裝構造一般具有一封膠體150用以密 封該半導體晶片110並且提供絕緣《該封膠體150 —般包含 一單層構造。 由於該半導體晶片110與基板130熱膨脹係數差異相當 大（半導體晶片之熱膨脹係數（coefficient of thermal expansion，CTE)約為3-5ppm/°C，基板之熱膨脹係數 (CTE)約為20-30ppm/°C)，因此該半導體晶片iio與基板 130會隨溫度變化而產生不同的膨脹或收縮量。而這會產 生切變（shear)應力或彎曲（bend)應力作用於該封膠體150 上《此外’由於該基板130的可撓特性，該基板在封裝製 程中以及溫度變化時，有扭曲或彎曲的傾向，因此其更擴 大該破壞性應力所導致的問題；同時，該因應力而彎翹之 晶片尺寸級封裝構造在壓力鋼試驗（pressure cook test, PCT)或其他的可靠度測試（reliability test)中，極易產 生封膠想剝落（peeling)以及層裂（delaroination)或晶片 破裂（die cracking)的問題。 第4頁 423128423128 V. Description of the invention 0) Field of the invention The present invention relates to a sealing compound for a wafer-size package structure, and particularly relates to a sealing compound for sealing a semiconductor wafer provided on a substrate. Prior technology: The conventional chip scale package (CSP) is shown in the first, second, and third figures, and generally includes a semiconductor chip 110 and an elastomer 120 on a substrate 130. On the surface. The wafer-scale package structure generally has a colloid 150 to seal the semiconductor wafer 110 and provide insulation. The encapsulant 150 generally includes a single-layer structure. Because the thermal expansion coefficient of the semiconductor wafer 110 and the substrate 130 are quite different (the coefficient of thermal expansion (CTE) of the semiconductor wafer is about 3-5 ppm / ° C, and the thermal expansion coefficient (CTE) of the substrate is about 20-30 ppm / ° C). Therefore, the semiconductor wafer 110 and the substrate 130 may have different expansion or contraction amounts with temperature changes. This will cause shear stress or bend stress to act on the encapsulant 150. In addition, due to the flexible nature of the substrate 130, the substrate is distorted or bent during the packaging process and when the temperature changes. Tends to expand the problem caused by the destructive stress; meanwhile, the wafer-size package structure warped by the stress is subjected to a pressure cook test (PCT) or other reliability test However, problems such as peeling of the sealant and delaroination or die cracking are easily caused. Page 4 423128

五、發明說明（2) 發明概要： 本發明之主要目的係提供一種晶>!尺寸級封裝構造 (chip scale package， CSP)，其包含一半導趙晶片設於 一基板，其特徵在於該半導體晶片係為一具有至少兩眉媾 造之封膠體密封以及絕緣，藉此改善封裝構造層裂或晶片 破裂的問題。 根據本發明一較佳實施例之晶片尺寸級封裝構造，其 主要係包含一半導體晶片設於一基板之上表面並且被一封 膠體密封。該半導體晶片具有複數個晶片銲墊位於其正面 中央。該基板具有一槽縫對應於該半導雜晶片之複數個晶 片鮮塾。該基板設有一用以與外界形成電性連接之構造， 並且該半導體晶片之複數個晶片銲墊係電性連接至該用以 與外界形成電性連接之構造。 該封膠體包含一上封勝體設於該基板之上表面且環繞 該半導體晶片，以及一下封膠體設於該基板之槽縫内。該 封膠體係包含一樹脂基料（resin base material)分為第 一層以及第二層，其中該上封膠艎之第二層係設於該上封 膠體之第一層與基板間’而該下封膠體之第一層係位於該 半導體晶片與該下封膠體之第二層間。該樹脂基料含有& 數個填充物顆粒（filler particle)，其中在第一層中之 填充物顆粒含量係小於在第二層中之填充物顆粒含量。 於該填充物顆粒之熱膨脹係數（C T E)較樹脂基料小，因此 第二層之熱膨脹係數較第一層小’藉此可緩衝由於基板 晶片熱膨脹係數不一致（CTE mismatch)所產生之應力。、 7 〇此V. Description of the invention (2) Summary of the invention: The main object of the present invention is to provide a crystal chip package (CSP), which includes a half of the semiconductor chip on a substrate, which is characterized by the semiconductor The chip is a sealant with at least two eyebrows formed to seal and insulate, thereby improving the problem of chipping or chipping of the package structure. A wafer-scale package structure according to a preferred embodiment of the present invention mainly includes a semiconductor wafer provided on an upper surface of a substrate and sealed with a gel. This semiconductor wafer has a plurality of wafer pads located at the center of its front surface. The substrate has a slot corresponding to a plurality of wafers of the semiconductor chip. The substrate is provided with a structure for forming an electrical connection with the outside, and a plurality of wafer pads of the semiconductor wafer are electrically connected to the structure for forming an electrical connection with the outside. The sealant includes an upper sealant disposed on an upper surface of the substrate and surrounding the semiconductor wafer, and a lower sealant disposed in a slot of the substrate. The sealant system includes a resin base material divided into a first layer and a second layer, wherein the second layer of the upper sealant is disposed between the first layer of the upper sealant and the substrate. The first layer of the undersealing colloid is located between the semiconductor wafer and the second layer of the undersealing colloid. The resin base contains & several filler particles, wherein the content of filler particles in the first layer is smaller than the content of filler particles in the second layer. The thermal expansion coefficient (C T E) of the filler particles is smaller than that of the resin base material. Therefore, the thermal expansion coefficient of the second layer is smaller than that of the first layer ', thereby buffering the stress caused by the CTE mismatch of the substrate wafer. , 7 〇 this

423128 ' ___ _ 五、發明說明（3) 外’該第二層中之填充物顆粒含量較大，因此可有效防止 水氣入侵，藉此改善封裝構造層裂或晶片破裂的問題。 根據本發明另一較佳實施例之晶片尺寸級封裴構造， 其主要係包含一半導趙晶片設於一基板之上表面並且被__ 封膠體密封。該半導體晶片具有複數個晶片銲墊位於其正 面兩侧。該基板具有至少兩槽縫對應於該半導體晶片之複 數個晶片銲墊。該基板設有一用以與外界形成電性連接之 構造，並且該半導體晶片之複數個晶片銲墊係電性連接至 該用以與外界形成電性連接之構造。該封膠體設於該基板 之上表面，其環繞該半導體晶片並且填滿該基板之至少兩 槽縫。該封膠體係包含一樹脂基料分為第一層以及第二 層，其中該第二層大致係設於第一層與基板間。該樹脂基 料含有複數個填充物顆粒（fi 1 ler particle)，其中在第 一層中之填充物顆粒含量係小於在第二層中之填充物顆粒 含量。由於該第二層之熱膨脹係數較小，藉此可緩衝由於 基板與晶片熱膨脹係數不一致（CTE mismatch)所產生之應 力》此外，該第二層中之填充物顆粒含量較大，因此可有 效防止水氣入侵，藉此改善封裝構造層裂或晶片破裂的問 題。 圚示說明： 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯特徵，下文特舉本發明較佳實施例，並配合所附圖 示，作詳細說明如下〇 第1圖：習用之晶片尺寸級封裝構造（chip scale423128 '___ _ V. Description of the invention (3) Outer' The second layer has a larger content of filler particles, so it can effectively prevent water vapor intrusion, thereby improving the problem of package structure cracks or chip cracks. According to another preferred embodiment of the present invention, a wafer-size sealing structure is mainly composed of a half-guide wafer disposed on an upper surface of a substrate and sealed by a sealing compound. The semiconductor wafer has a plurality of wafer pads on both sides of its front surface. The substrate has at least two slots corresponding to a plurality of wafer pads of the semiconductor wafer. The substrate is provided with a structure for forming an electrical connection with the outside, and a plurality of wafer pads of the semiconductor wafer are electrically connected to the structure for forming an electrical connection with the outside. The sealing compound is disposed on the upper surface of the substrate, surrounds the semiconductor wafer and fills at least two slots of the substrate. The sealant system includes a resin base material divided into a first layer and a second layer, wherein the second layer is roughly disposed between the first layer and the substrate. The resin matrix contains a plurality of filler particles, wherein the content of filler particles in the first layer is smaller than the content of filler particles in the second layer. Because the thermal expansion coefficient of the second layer is small, it can buffer the stress caused by the CTE mismatch between the substrate and the wafer. In addition, the content of filler particles in the second layer is large, which can effectively prevent Water vapor intrusion can improve the problem of chipping or chipping of the package structure. Description: In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiment of the present invention in detail with the accompanying drawings. Figure 1: Conventional use 1. chip scale package structure

第6頁 4 2312 8 五、發明說明（4) package, CSP)之剖面圖； 第 2圖：另一習用 曰 曰曰 η 尺寸級封裝構造之剖 面圖； 第 3圖：另一習用 晶片 尺寸級封裝構造之剖 面圖； 第 4圖：根據本發明第 一較佳實施例之晶片 尺寸級封 裝構造之剖面圖； 第 5圖：根據本發明第二較佳實施例之晶片 尺寸級封 裝構造之剖面圖；及 第 6圖：根據本發明第三較佳實施例之晶片 尺寸級封 裝構造之剖面圖。 圖號說明： 110 半導體晶片 120 彈性體 130 基板 150 封膠體 200 尺寸級封裝構造 210 半導體晶片 2 12 晶片銲墊 220 基板 2 2 0a 槽縫 222 錫球銲墊 224 導線 226 錫球 230 彈性體 240a 上封膠體 240b 下封膠體 300 晶片尺寸級封裝構造 310 半導體晶片 312 晶片銲墊 320 基板 3 2 0a 槽縫 322 錫球銲墊 324 晶片連接墊 326 連接線 328 錫球 330 彈性體 340 封膠體 400 晶片尺寸級封裝構造 410 半導體晶片 412 晶片銲墊 420 基板Page 6 4 2312 8 V. Description of the invention (4) A cross-sectional view of package, CSP); Figure 2: A cross-sectional view of another conventional η-size package structure; Figure 3: Another conventional wafer-size class Sectional view of package structure; FIG. 4: Sectional view of a wafer-size package structure according to a first preferred embodiment of the present invention; FIG. 5: Sectional view of a wafer-size package structure according to a second preferred embodiment of the present invention And FIG. 6 are cross-sectional views of a wafer-scale package structure according to a third preferred embodiment of the present invention. Description of drawing number: 110 semiconductor wafer 120 elastomer 130 substrate 150 sealing compound 200 size package structure 210 semiconductor wafer 2 12 wafer pad 220 substrate 2 2 0a slot 222 solder ball pad 224 wire 226 solder ball 230 elastomer 240a Sealant 240b Under sealant 300 Wafer size package structure 310 Semiconductor wafer 312 Wafer pad 320 Substrate 3 2 0a Slot 322 Solder ball pad 324 Wafer connection pad 326 Connecting wire 328 Solder ball 330 Elastomer 340 Sealant 400 Wafer size Level Package Structure 410 Semiconductor Wafer 412 Wafer Pad 420 Substrate

第7頁 423128 五、發明說明（5) 420a槽缝 422 錫球銲墊 424 導線 426 錫球 430 封膠體 44G 彈性體 發明說明： 第四圖係為根據本發明第一較佳實施例之晶片尺寸級 封裝構造200 ’其主要係包含一半導體晶片21〇設於一基板 220之上表面。該半導體晶片21〇具有複數個晶片銲墊212 位於其正面中央。該基板220具有一槽縫220a對應於該半 導趙晶片2 I 0之複數個晶片銲墊。該半導體晶片2 ϊ 〇係利用 一彈性體（61狂51:〇!^1〇230固著於該基板2 20之上表面。該 基板220之上表面設有複數個錫球銲墊222以及複數條導線 224。該複數個錫球銲墊222係經由該基板220上之導電線 路（conductive trace)連接至相對應之複數條導線2 24之 一端。該複數條導線2 24之另一端係連接至該半導體晶片 210之晶片銲墊212。該基板2 20具有複數個孔對應於該複 數個錫球銲墊2 22設置。該每一個錫球銲墊2 22設有一錫球 226用以與外界電性溝通。 請再參照第四圖’根據本發明之晶片尺寸級封裝構造 200 ’其具有一封膠體用以防止外界水氣或雜質進入其 中°該封膠體包含一上封膠體240a形成於該基板220之上 表面且環繞該半導體晶片210，以及一下封膠體240b形成 於該基板220之槽縫220a内以包覆該複數條導線224。該 膠趙係包含一樹脂基料（resin base material)例如環 樹脂基料（熱膨脹係數約為65 ppm/它），其分為第一層 封 氧 以及第二層。該樹脂基料含有複數個填充物顆粒（fnierPage 7 423128 V. Description of the invention (5) 420a slot 422 solder ball pad 424 wire 426 solder ball 430 sealant 44G elastomer description of the invention: The fourth figure is the wafer size according to the first preferred embodiment of the present invention The level packaging structure 200 ′ mainly includes a semiconductor wafer 210 disposed on an upper surface of a substrate 220. The semiconductor wafer 21 has a plurality of wafer pads 212 located at the center of its front surface. The substrate 220 has a plurality of slot pads 220a corresponding to the semiconductor wafer 2 I 0. The semiconductor wafer 2 〇 〇 is fixed on the upper surface of the substrate 2 20 using an elastomer (61 狂 51: 〇! ^ 1〇230. The upper surface of the substrate 220 is provided with a plurality of solder ball pads 222 and a plurality of Wires 224. The plurality of solder ball pads 222 are connected to one end of a corresponding plurality of wires 2 24 via a conductive trace on the substrate 220. The other ends of the plurality of wires 2 24 are connected to The wafer pads 212 of the semiconductor wafer 210. The substrate 2 20 has a plurality of holes corresponding to the plurality of solder ball pads 22. Each of the solder ball pads 22 is provided with a solder ball 226 to communicate with the outside. Please refer to the fourth figure again for the wafer size package structure 200 according to the present invention, which has a colloid to prevent outside moisture or impurities from entering into it. The encapsulant includes an upper encapsulant 240a formed on the substrate. An upper surface of 220 surrounds the semiconductor wafer 210, and a lower sealant 240b is formed in the slot 220a of the substrate 220 to cover the plurality of wires 224. The glue system includes a resin base material such as a resin base material. Ring resin base (Thermal expansion coefficient of about 65 ppm / it), which is divided into a first layer and a second oxygen blocking layer resin binder comprising a plurality of filler particles (fnier

C3〗28 五、發明說明（6) particle)例如二氧化矽（si 1 ica)顆粒（熱膨脹係數（CTE) _ 約為3 ppm/ °C)或聚合物含浸玻璃織維（fiberglass)顆 粒’其中在第一層中之填充物顆粒含量係小於在第二層中-之填充物顆粒含量》該上封膠體2 40 a之第二層係設於該上 封膠體240a之第一層與基板220間，而該下封膠體240b之 第一層係位於該半導體晶片210與該下封膠體240b之第二 層間。 該封膠體之製造方法如下：（Α)利用一注膠閥 (dispenser)將膠體（即含有填充物顆粒之樹脂基料）點 在基板上想要形成封膠體之位置；（B)將該膠體以大約 100-120 °C進行預硬化（Drecure)30分鐘；以及（C) 將該膠 體以大約170-180 °C進行後硬化（postcure)4小時。在該預 硬化製程中，該封裝構造2 0 0之半導體晶片2 1 0係保持在該 基板220之上，藉此一力量例如重力會作用在該膠體，使 得該填充物顆粒沉降（subside)而形成第一層以及第二 層。如第四圖所示，當預硬化製程完成時，大部份的填充 物顆粒會沉降至該膠體之第二層。較佳地，在第一層中之 填充物顆粒的數量為5到1〇重量百分比，並且在第二層中 之填充物顆粒的數量為6〇到70重量百分比。該預硬化製程 之溫度以及時間可以調整以得到所要的組成。本發明所使 用之樹脂基料也可包含適當的硬化劑、催化劑、顏料等 (如熟悉該技藝者所習知）。 根據本發明之較佳實施例，該封膠體之第一層含有約5 到10重量百分比之二氧化矽（silica)顆粒，第二層含有約 笫9頁C3〗 28 5. Description of the invention (6) particle) For example, silicon dioxide (si 1 ica) particles (coefficient of thermal expansion (CTE) _ about 3 ppm / ° C) or polymer-impregnated fiberglass particles (of which The content of filler particles in the first layer is less than the content of filler particles in the second layer-the second layer of the top-sealing colloid 2 40 a is provided on the first layer of the top-sealing colloid 240 a and the substrate 220 The first layer of the undersealing gel 240b is located between the semiconductor wafer 210 and the second layer of the undersealing gel 240b. The manufacturing method of the sealing gel is as follows: (A) using a dispenser to point the colloid (that is, the resin base material containing filler particles) on the substrate at the position where the sealing gel is to be formed; (B) the colloid Drecure was pre-cured at about 100-120 ° C for 30 minutes; and (C) the colloid was post-cure at about 170-180 ° C for 4 hours. In the pre-hardening process, the semiconductor wafer 2 1 0 of the package structure 2 0 is held on the substrate 220, whereby a force such as gravity will act on the colloid, causing the filler particles to subside and A first layer and a second layer are formed. As shown in Figure 4, when the pre-hardening process is completed, most of the filler particles will settle to the second layer of the colloid. Preferably, the number of filler particles in the first layer is 5 to 10 weight percent, and the number of filler particles in the second layer is 60 to 70 weight percent. The temperature and time of the pre-hardening process can be adjusted to obtain the desired composition. The resin base used in the present invention may also contain appropriate hardeners, catalysts, pigments, etc. (as is known to those skilled in the art). According to a preferred embodiment of the present invention, the first layer of the sealing gel contains about 5 to 10 weight percent of silica particles, and the second layer contains about 笫 9 pages.

Μ ^23128 五'發明說明（7) 6〇到70重量百分比之二氧化矽（si lica)顆粒；該封膠體之 。第一層之CTE約為60 pp“°C，第二層之CTE約為25ppm/ C °由於填充物顆粒之熱膨脹係數較樹脂基料之熱膨脹係 數小，因此該封膠體第二層之熱膨脹係數較小，藉此可緩 衝由於基板與晶片熱膨脹係數不一致（CTE mismatch)所產 生之應力。 由於該封膠體240a第二層中之填充物顆粒含量較大， 因此可有效防止水氣入侵晶片210與彈性體230以及彈性體 230與基板220間之介面，藉此改善層裂或晶片破裂的問 題°此外，由於該封膠體24 Ob第二層中之填充物顆粒含量 較大，因此可有效防止水氣進入藉此保護該導線224不受 腐飯。 第五圖係為根據本發明第二較佳實施例之晶片尺寸級 封裝構造300，其主要係包含一半導體晶片31〇設於一基板 320之上表面。該半導體晶片31〇具有複數個晶片銲墊312 位於其正面中央。該基板320具有一槽縫320a對應於該半 導體晶片3 1 0之複數個晶片銲墊。該半導體晶片3 j 〇係利用 一彈性體（61381〇11161')330固著於該基板3 20之上表面。該 基板3 20之上表面設有複數個錫球銲墊3 22以及複數條晶片 連接墊324。該複數個錫球銲墊322係經由該基板320上之 導電線路（conductive trace)(未示於圖中）連接至相對 應之複數條晶>1連接墊324。該基板320之複數條晶片連接 塾324係藉由複數條連接線（bonding wire)326電性連接至 該半導體晶片310之晶片銲堅312。該每一個錫球銲塾322^ 23128 Five 'invention description (7) 60 to 70 weight percent of silicon dioxide (silica) particles; The CTE of the first layer is about 60 pp "° C, and the CTE of the second layer is about 25 ppm / C ° Because the thermal expansion coefficient of the filler particles is smaller than that of the resin base, the thermal expansion coefficient of the second layer of the sealant Smaller, which can buffer the stress caused by the CTE mismatch between the substrate and the wafer. Due to the large content of filler particles in the second layer of the sealing compound 240a, it can effectively prevent water vapor from invading the wafer 210 and The elastic body 230 and the interface between the elastic body 230 and the substrate 220, thereby improving the problem of spalling or chip breaking. In addition, because the content of the filler particles in the second layer of the sealing body 24 Ob is large, it can effectively prevent water The gas enters to protect the wire 224 from rotten rice. The fifth figure is a wafer-size package structure 300 according to the second preferred embodiment of the present invention, which mainly includes a semiconductor wafer 31, which is disposed on a substrate 320. Upper surface. The semiconductor wafer 31 has a plurality of wafer pads 312 at the center of its front surface. The substrate 320 has a slot 320a corresponding to the plurality of wafer pads of the semiconductor wafer 310. The semiconductor wafer 3 j 〇 is fixed on the upper surface of the substrate 3 20 by an elastomer (61381〇11161 ') 330. The upper surface of the substrate 3 20 is provided with a plurality of solder ball pads 3 22 and a plurality of wafers. Connection pads 324. The plurality of solder ball pads 322 are connected to the corresponding plurality of crystals > 1 connection pads 324 via conductive traces (not shown) on the substrate 320. The substrate 320 The plurality of wafer connection pads 324 are electrically connected to the wafer bonding pads 312 of the semiconductor wafer 310 through a plurality of bonding wires 326. The solder ball pads 322 each

•π 第10頁 423128 五、發明說明（8) 設有一錫球3 2 8用以與外界電性溝通。 請再參照第五圖’根據本發明之晶片尺寸級封裝構造 3〇〇 ’其同樣具有一封膠體340用以防止外界水氣或雜質進 入其中。該封膠體340之位置及組成大致類同於第四圖中 之封膠體。 第六圖揭示根據本發明第三較佳實施例之晶片尺寸級 封裝構造400 ’其主要係包含一半導體晶片41〇設於一基板 420之上表面並且被—封膠體43〇密封。該半導體晶片41〇 具有複數個晶片銲墊位4 1 2於其正面兩側。該基板4 2 0具有 至少兩槽縫420a對應於該半導體晶片41〇之複數個晶片銲 墊。該半導體晶片410係利用一彈性體（elast〇mer)44〇 固著於該基板4 20之上表面。該基板4 20之上表面設有複數 個錫球銲墊422以及複數條導線424。該複數個錫球銲墊 422係經由該基板420上之導電線路（conductive trace)連 接至相對應之複數條導線424之一端。該複數條導線424之 另一端係連接至該半導體晶片41〇之晶片銲墊412。該基板 420具有複數個孔對應於該複個錫球鋅墊422設置。該每一 個錫球銲墊4 22設有一錫球4 26用以與外界電性溝通。 請再參照第六圖’根據本發明之晶片尺寸級封裝構造 400 ’其亦具有一封膠體用以防止外界水氣或雜質進入其 中°該封膠體430設於該基板420之上表面，其環繞該半導 趙晶片410並且填滿該基板420之至少兩槽縫420a。該封膠 趙430之組成大致類同於第四圖中之封滕體。 根據本發明之晶片尺寸級封裝構造，其封膠體包含一• π Page 10 423128 V. Description of the invention (8) A solder ball 3 2 8 is provided for electrical communication with the outside world. Please refer to the fifth figure again. The wafer-scale package structure 300 according to the present invention also has a colloid 340 to prevent outside moisture or impurities from entering it. The position and composition of the sealant 340 are similar to those of the sealant in the fourth figure. The sixth figure reveals a wafer-size-level package structure 400 'according to a third preferred embodiment of the present invention, which mainly includes a semiconductor wafer 41 on an upper surface of a substrate 420 and sealed by a sealant 43. The semiconductor wafer 41 has a plurality of wafer pads 4 1 2 on both sides of the front surface. The substrate 4 2 0 has at least two slits 420 a corresponding to a plurality of wafer pads of the semiconductor wafer 4 10. The semiconductor wafer 410 is fixed to the upper surface of the substrate 4 20 by using an elastomer 44o. A plurality of solder ball pads 422 and a plurality of wires 424 are provided on the upper surface of the substrate 4 20. The plurality of solder ball pads 422 are connected to one end of the corresponding plurality of wires 424 via a conductive trace on the substrate 420. The other ends of the plurality of wires 424 are connected to a wafer pad 412 of the semiconductor wafer 41. The substrate 420 has a plurality of holes corresponding to the plurality of solder ball zinc pads 422. Each of the solder ball pads 4 22 is provided with a solder ball 4 26 for electrical communication with the outside world. Please refer to FIG. 6 again. The chip-size package structure 400 according to the present invention also has a piece of gel to prevent outside moisture or impurities from entering it. The sealing gel 430 is disposed on the upper surface of the substrate 420 and surrounds the substrate. The semiconductor wafer 410 fills at least two slots 420 a of the substrate 420. The composition of the sealant Zhao 430 is roughly similar to that of the sealer in the fourth figure. According to the wafer-size package structure of the present invention, the encapsulant includes a

第11頁 423128 五、發明說明（9) 樹脂基料分為第一層以及第二層。該樹脂基料含有複數個 填充物顆粒，其中在第一層中之填充物顆粒含量係小於在 第二層中之填充物顆粒含量。由於該第二層中之填充物顆 粒含量較大，因此可有效防止水氣入侵，藉此改善封裝構 造層裂或晶片破裂的問題以及保護導線不受水氣腐蝕。 另外，由於樹脂基料相對於填充物顆粒具有較佳之表 面附著力（surface adhesion)，因此該封膠體之第一層 (大部份由樹脂基料組成）與半導體晶片間具有較佳之附 著力。此外，由於樹脂基料之熱膨脹係數大於填充物顆 粒，因此在封膠完成後該封膠體冷卻時，該封膠體之第一 層可以收縮而更有效地固定該半導體晶片。 雖然本發明已以前述較佳實施例揭示，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與修改，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。Page 11 423128 V. Description of the invention (9) The resin base material is divided into a first layer and a second layer. The resin base contains a plurality of filler particles, wherein the content of filler particles in the first layer is smaller than the content of filler particles in the second layer. Due to the large content of filler particles in the second layer, it can effectively prevent the intrusion of moisture, thereby improving the problem of chipping or chipping of the package structure and protecting the wires from corrosion by moisture. In addition, because the resin matrix has better surface adhesion with respect to the filler particles, the first layer of the sealant (mostly composed of the resin matrix) and the semiconductor wafer have better adhesion. In addition, since the thermal expansion coefficient of the resin base material is larger than the filler particles, when the sealant is cooled after the sealant is completed, the first layer of the sealant can shrink to more effectively fix the semiconductor wafer. Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

第12頁Page 12

Claims (1)

4 2 3 12 8 六、申請專利範圍 1 、一種晶 一基板 一用以 一半導 其中該半導 體晶片之複 半導體晶片 形成電性連 —封膠 環繞該半導 其中該封膠 為第一層以 顆粒（f i 1 1 e 充物顆粒重 片尺寸 ，具有 與外界 體晶片 體晶片 數個晶 之複數 接之構 體，其 體晶片 體包含 及第二 r part 量百分 級封裝構造，其係包含： 上表面 下表面以及一槽縫 形成電 具有複 之正面 片銲墊 個晶片 造；及 包含一 ，及一 一樹脂 層，其 i c 1 e ) 比不同 性連接之構造，設於該基板； 數個晶片銲墊位於其正面中央， 設於該基板之上表面使得該半導 係對應於該基板之槽縫，並且該 銲墊係電性連接至該用以與外界 上封膠體設於該基板之上表面且 下封膠體設於該基板之槽縫内， 基料（resin base material)分 中該樹脂基料含有複數個填充物 ，並且該第一層以及第二層之填 2 、依申請專利範圍第1項之晶片尺寸級封裝構造，其中 該上封膠體之第二層係設於該上封膠體之第一層與基板 間，且該下封膠體之第一層係位於該半導體晶片與該下封 膠體之第二層間。4 2 3 12 8 VI. Application Patent Scope 1. A crystal-substrate—a semi-conductor semiconductor wafer in which the semiconductor wafer is electrically connected—a sealant surrounds the semi-conductor where the sealant is the first layer of particles (The size of fi 1 1 e filling particles is heavy, and it has a structure that is connected with several crystals of the external body wafer. The body wafer body contains a second r part with a hundred-percent grade packaging structure. It includes: The lower surface of the surface and a slot are formed by a wafer having a plurality of front surface pads; and a structure including one and one resin layers whose ic 1 e) ratio is different than that provided on the substrate; several wafers The solder pad is located on the front center of the substrate, and is disposed on the upper surface of the substrate so that the semiconductor system corresponds to the slot of the substrate. The solder pad is electrically connected to the substrate for sealing the gel with the outside. The surface and the under-sealing colloid are set in the slot of the substrate. The resin base material contains a plurality of fillers, and the first layer and the second layer are filled. Please refer to the wafer size package structure of item 1 in the patent, wherein the second layer of the overmolding colloid is located between the first layer of the overmolding colloid and the substrate, and the first layer of the undermolding colloid is located in the semiconductor Between the wafer and the second layer of the undersealing colloid. 第13頁 423128 六、申請專利範圍 在第二層中之填充物顆粒的數量為6 0到70重量百分比 、依申請專利範圍第4項之晶片尺寸級封裝構造，其中.. 在第一層中之填充物顆粒的數量為5到1〇重量百分比。 6 、依申請專利範圍第1項之晶片尺寸級封裝構造，其中 該填充物顆粒包含二氧化矽（silica)顆粒。 7 、依申請專利範圍第1項之晶片尺寸級封裝構造，其中 該填充物顆粒包含聚合物含浸玻璃纖維 粒。 8 、一種晶片尺寸級封裝構造，其係包含： 一基板’具有一上表面、一下表面以及至少兩槽縫； 一，以與外界形成電性連接之構造，設於該基板； 一半導體晶片具有複數個晶片銲墊位於其正面兩侧， 其中該半導體晶片之正面設於該基板之上表面使得該半導 體晶片之複數個晶片銲墊係對應於該基板之槽縫，並且該 半導體晶片之複數個晶片銲墊係電性連接至該用以與外界 形成電性連接之構造； 一封穆體設於該基板之上表面’其環繞該半導體晶片 ϋ且填滿該基板之至少兩槽縫’該封膠體包含一樹脂基料 (resin base material)分為第一層以及第二層，其中該 樹脂基料含有複數個填充物顆粒（fi丨ler particle)\並Page 13 423128 VI. The number of filler particles in the second layer of the patent application ranges from 60 to 70% by weight, and the chip size package structure according to item 4 of the patent application scope, where: in the first layer The number of filler particles is 5 to 10 weight percent. 6. The wafer-size package structure according to item 1 of the patent application scope, wherein the filler particles include silica particles. 7. The wafer-size package structure according to item 1 of the patent application scope, wherein the filler particles include polymer-impregnated glass fiber particles. 8. A wafer-scale package structure, comprising: a substrate having an upper surface, a lower surface, and at least two slots; a structure provided on the substrate to form an electrical connection with the outside; a semiconductor wafer having A plurality of wafer pads are located on both sides of the front side, wherein the front side of the semiconductor wafer is provided on the upper surface of the substrate such that the plurality of wafer pads of the semiconductor wafer correspond to the slots of the substrate, and the plurality of semiconductor wafers The wafer pad is electrically connected to the structure for forming an electrical connection with the outside world; a body is provided on the upper surface of the substrate 'it surrounds the semiconductor wafer and fills at least two slots of the substrate'; The sealing compound includes a resin base material divided into a first layer and a second layer, wherein the resin base material contains a plurality of filler particles. 423128 六、申請專利範圍 且該第一層以及第二層之填充物顆粒重量百分比不同。 9 、依申請專利範圍第8項之晶片尺寸級封裝構造，其中 該第二層大致係設於第一層與基板間。 1 0 、依申請專利範圍第9項之晶片尺寸級封裝構造，其 中第一層之熱膨脹係數大於第二層之熱膨脹係數。 1 1 、依申請專利範圍第9項之晶片尺寸級封裝構造，其 中在第二層中之填充物顆粒的數量為60到70重量百分比。 1 2 、依申請專利範圍第1 1項之晶片尺寸級封裝構造， 其中在第一層中之填充物顆粒的數量為5到10重量百分 比。 1 3、依申請專利範圍第8項之晶片尺寸級封裝構造，其 中該填充物顆粒包含二氧化矽（silica)顆粒。 1 4、依申請專利範圍第8項之晶片尺寸級封裝構造，其 中該填充物顆粒包含聚合物含浸玻璃纖維（fiberglass)顆 粒。423128 6. Scope of patent application And the weight percentages of the filler particles of the first layer and the second layer are different. 9. The chip-size package structure according to item 8 of the scope of the patent application, wherein the second layer is roughly disposed between the first layer and the substrate. 10. The chip-size package structure according to item 9 of the patent application, wherein the thermal expansion coefficient of the first layer is greater than that of the second layer. 1 1. The wafer-size package structure according to item 9 of the patent application, wherein the number of filler particles in the second layer is 60 to 70 weight percent. 12. The chip-size package structure according to item 11 of the patent application scope, wherein the number of filler particles in the first layer is 5 to 10 weight percent. 1 3. The chip-size package structure according to item 8 of the patent application, wherein the filler particles include silica particles. 14. The chip-size package structure according to item 8 of the patent application, wherein the filler particles include polymer-impregnated fiberglass particles. 第15頁Page 15
TW088118628A 1999-10-26 1999-10-26 Chip scale package structure TW423128B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW088118628A TW423128B (en) 1999-10-26 1999-10-26 Chip scale package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW088118628A TW423128B (en) 1999-10-26 1999-10-26 Chip scale package structure

Publications (1)

Publication Number Publication Date
TW423128B true TW423128B (en) 2001-02-21

Family

ID=21642785

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088118628A TW423128B (en) 1999-10-26 1999-10-26 Chip scale package structure

Country Status (1)

Country Link
TW (1) TW423128B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170188B2 (en) * 2004-06-30 2007-01-30 Intel Corporation Package stress management

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170188B2 (en) * 2004-06-30 2007-01-30 Intel Corporation Package stress management
US7179689B2 (en) 2004-06-30 2007-02-20 Intel Corporation Package stress management

Similar Documents

Publication Publication Date Title
JP2712618B2 (en) Resin-sealed semiconductor device
US20060049528A1 (en) Semiconductor chip stack structure and method for forming the same
KR101398404B1 (en) Plastic overmolded packages with mechanically decoupled lid attach attachment
US6028347A (en) Semiconductor structures and packaging methods
JP2001144213A (en) Method for manufacturing semiconductor device and semiconductor device
US7190082B2 (en) Low stress flip-chip package for low-K silicon technology
TW423128B (en) Chip scale package structure
US6265768B1 (en) Chip scale package
US20030111716A1 (en) Wirebonded multichip module
US8686547B1 (en) Stack die structure for stress reduction and facilitation of electromagnetic shielding
JPS6077446A (en) Sealed semiconductor device
USH73H (en) Integrated circuit packages
TWI254422B (en) Chip package and producing method thereof
TW591727B (en) Method for producing a protection for chip edges and arrangement for the protection of chip edges
JPH11340380A (en) Semiconductor device
JPS62210651A (en) Resin sealed type semiconductor device
JPH0345542B2 (en)
JPS63293930A (en) Electrode in semiconductor device
JPS63107156A (en) Resin packaged type semiconductor device
JP3196821B2 (en) Resin-sealed circuit device
US4974054A (en) Resin molded semiconductor device
JPH0777226B2 (en) Semiconductor device and manufacturing method thereof
JP3305308B2 (en) Method for manufacturing semiconductor device
JP2003246845A (en) Liquid epoxy resin composition for sealing semiconductor, and semiconductor device
JP2504465B2 (en) Semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent