__ = _ 五、發明說明（5) 〔n—袖无 一部份SOG留在金屬導線14上。 【較佳實施例的詳細說明】 (請先閲讀背面之泫意事項再填寫本頁> 本發明將根據後附的圖式作詳細的說明。本發明提 出一，成層間介電層的方法，以提供：在間隔為〇1μιΠ 或更寬的間隙15中良好的間隙覆蓋率，低的介電常數， 消除接觸窗毒化的問題，並且製程簡單者。 本發明的製程摘要如下面的表中： 圖 步驟 - 1 开> 成分離的導線14於一基底上 1 形成均勻的第一氧化矽層16(阻障層）pE—SiH』 2000A 1 關鍵^驊，形成第一 SOG層18(例的218 1900A) _其大部分填入金屬導線μ之間的凹谷π中而沒有 留下太多在金屬導線上方 1 回流(加熱及硬化）第一 S0G層18(間棟填充S® ♦此一回流程序使金屬導線14表面上不留任何第一 s〇G層18， 並且在金屬導線14間之間隙内的填充厚度19係介於ιοοοΑ 和3000 A範圍内。 1 形成第二氧化矽層24(PE-SiH4 7000A)於第一S0G層18和均 勻的第一氧化矽層16上 2 形成第二500層28(例如是人11丨6(15^1^1的211 -200〇人）（平 坦fcs曝 2 3 4 於430°C硬化第二S0G層28約30分鐘 回蝕刻第二S0G層（5000A) 形成一絕緣蓋層（Si02*SiN) ~ 經濟部智慧財產局員工消費合作社印製 如第1圖所示者，提供一半導體構造12 1〇。此半導 體構造12 10包括一半導體基底10及形成於其中的各種半導 體元件，像是源極、汲極、閘電極、電晶體、電容器、位 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 416120 五、發明説明（1 ) 【發明的領域】 本發明係有關於半導體元件介電層的製造，且特別是 有關於一種使用旋覆玻璃（SOG)以形成金屬層間介電層 (IMD)的方法，以應用於半微米以下之半導體元件。 【習知技藝】 為了使電路能更小、更快、及較不昂貴，半導體元件 的尺寸持續地縮小化。然而此一縮小化的趨勢造成許多新 的挑戰。半導體元件中導線之間的高品質介電層是製造次 微米尺寸之積體電路所亟需的，在像是基底表面上的複晶 矽閘極’或是基底上方的金屬導線等導線上，便需要這些 高品質介電層。超大塑積體電路(VLSI)需要使内連導線、 導線空間等缩小化，結果使得基底表面上的製程步驟增加。 當導線間距離小於〇.15μιη時這點特別容易造成問題。 半微米以下半導體元件之金屬層間介電層的製程需求 包括：（1)填充導體（金屬導線）間之窄溝槽（間隙）時不產生孔 隙，（2)平坦的表面以利後續金屬層的定義和蝕刻，（3)避免 水氣傳遞的穩定性，以及(4)表現一淨壓縮應力。 經濟部中央標準局貝工消費合作社印裝 (讀先閱讀背面之注意事項再填寫本頁) 業界已有不少平坦化的改良方法。例如，Matsunuira的 美國專利第5,459,105號描述了一種使用PESi〇2’〇rTEOS ’ SOG，回蝕刻，和pESi〇2的金屬層間介電層的平坦化方法。 Yang的美國專利第5,482,900號和M〇ghadai1的美國專利第 5,426,076號亦揭示了平坦化的方法。位於3500 Garrett Drive, Santa Clara CA 9554-2827(電話 408-562-0330)的 Allied Signal公司在其高級微電子材科部門的產品文件中，則提出 ___- _3_______ 本紙張尺度適用中國國本樓卑（CNS ) A4規格（2l0x 297公餘） 416120 經濟部智慧財產局員工消費合作社印製 A7 ----—-l γ ” Ί / ? '正__ 五、發明說明（n) L____j南充 由於不當的局部SOG回蝕刻使s〇G留在中而造成。 雖然有許多針對接觸窗側壁之間隙壁製程被提出，但這 些製程都會增加製程的複雜度和生產的成本。此外，為 了消除接觸窗毒化的問題，也有人建議以其他材質層取 代旋覆玻璃層，像是以高密度電漿化學氣相沈積（仙pCVD) 程序所形成的氧化矽層等。然而，S0G層具有比上述其他 材質層更低的介電常數，可降低線寬0.35μπ]以下產品的 RC延遲。基本上，S0G的介電常數約為3，而ΡΕ-氧化矽 的介電常數則約為4。 與習知之S0G製程比較，本發明具有下列特徵： ♦本發明的一個特徵在於第一 S0G層18具有回流性 質’因此S0G可填入金屬導線間大於的間隙中。 在回流程序後，只有少量甚或沒有第一 S0G層18仍留在 金屬導線15上。參見第1圖。 ♦本發明的第一 S0G層18係A11 ied Signal公司型 號 Accuspin 418 SOP 和 Hitachi Chemical 公司型號 HSG-2209S-R7等有機物旋覆玻璃的新應用。 ♦第一 S0G層18和第二S0G層28具有不同的塗佈功 能和性質。第一 S0G層18可填入金屬導線14之間大於 或等於Ο.ίμιη的緊密間隙中，而不會留在金屬導線14表 面上。第二S0G層28則是一平坦化犧牲層，作為回姓刻 平坦化之用。第二S0G層28並不具備第一 S0G層18的 可回流性質。 ♦第二S0G層28在回蝕刻程序中被去除，用以平坦化 13 本紙張尺度適用令國囤家標準（CNS)A4規格（210 X 297公釐） -1.---11--------敦--------訂---------線 {請先閲讀背面之注意事項再填寫本頁) 416120 Λ7 ΙΓ 五、發明説明（2 ) 了 Accuspin 418 可回流之 SOP(X-18)，以及 Accuglass T-ll 系列 SOG-(lll, 211，311)。 然而，這些方法可作進一步改良，以符合上述製程上 的需求並克服上述的缺點。 【發明之概述】 本發明之一個目的，即在提供一種製造金屬層間介電 層的方法，其包含一旋覆玻璃層以填滿導線之間小於〇.15μιη 的間隙，並消除接觸窗毒化(poison via)的問題。 本發明另一個目的，在提供一種製造金屬層間介電層 的方法，其在填充小於0.15μηι的間隙時容許使用厚的阻障 層（barrier layer)覆於金屬導線上，並保持低的介電常數以改 善RC延遲。 本發明再一個目的，在提供一種製造金屬層間介電層 的方法，其包括一改良的S0G程序，以提供優異的間隙填 充性質，並保持低的介電常數。 經濟部中央標準局貝工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 線！ 為了達成上述目的，本發明提出一種製造半導體元件 金屬層間介電層的方法。該方法首先形成分離的導線14於 包括基底的半導體構造上。其次，在分離的導線和半導體 構造上，以PECVD-SiH4程序形成厚度均勻的第一氧化矽層 (阻障層）16，而覆蓋阻障層16的分離導線14之間具有間隙 15 〇 在一重要步驟中，形成一新穎的第一旋覆玻璃層18於 第一氧化矽層上。有一點很重要，本發明的第一旋覆玻璃 層具有優異的間隙填充覆蓋率，並且有著在適當溫度加熱 _4_ 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐）__ = _ V. Description of the invention (5) [n—No SOG is left on the metal wire 14. [Detailed description of the preferred embodiment] (Please read the intention on the back before filling this page> The present invention will be described in detail according to the attached drawings. The present invention proposes a method for forming an interlayer dielectric layer In order to provide: good gap coverage in the gap 15 with an interval of 0.1 μm or wider, low dielectric constant, eliminating the problem of contact window poisoning, and simple process. The process summary of the present invention is as shown in the following table : Figure Step-1 Open > Separate wires 14 on a substrate 1 Form a uniform first silicon oxide layer 16 (barrier layer) pE—SiH 2000A 1 Key to form a first SOG layer 18 (eg 218 1900A) _ Most of it is filled into the valley π between the metal wires μ without leaving too much above the metal wires. 1 Reflow (heating and hardening) The first S0G layer 18 (Stoker filled S® ♦ this A reflow procedure does not leave any first SOG layer 18 on the surface of the metal wire 14, and the filling thickness 19 in the gap between the metal wires 14 is in the range of ιοοΑ and 3000 A. 1 Forming a second silicon oxide layer 24 (PE-SiH4 7000A) on the first SOG layer 18 and uniform A second 500 layer 28 is formed on 2 of the first silicon oxide layer 16 (for example, person 11 丨 6 (211-200 people of 15 ^ 1 ^ 1) (flat fcs exposed 2 3 4 and hardened the second S0G layer at 430 ° C) 28 Etching back the second SOG layer (5000A) in about 30 minutes to form an insulating cap layer (Si02 * SiN) ~ Printed as shown in Figure 1 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, providing a semiconductor structure 12 10. The semiconductor structure 12 10 includes a semiconductor substrate 10 and various semiconductor elements formed therein, such as a source electrode, a drain electrode, a gate electrode, a transistor, a capacitor, and a paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 416120 V. Description of the Invention (1) [Field of the Invention] The present invention relates to the manufacture of dielectric layers for semiconductor elements, and in particular to a method of using spin-on-glass (SOG) to form interlayer dielectrics. Layer (IMD) method to apply to semiconductor devices below half a micron. [Knowledge] In order to make circuits smaller, faster, and less expensive, the size of semiconductor devices has continued to shrink. However, this reduction Trends have led to many new Challenge. High-quality dielectric layers between conductors in semiconductor devices are urgently needed to make sub-micron-sized integrated circuits, such as polycrystalline silicon gates on the surface of a substrate or metal wires over the substrate. On-line, these high-quality dielectric layers are needed. Very large plastic integrated circuits (VLSI) need to reduce interconnecting wires, wire space, etc., resulting in increased process steps on the surface of the substrate. When the distance between the wires is less than 0.15 μm This is particularly problematic. The process requirements for the interlayer dielectric layer of semiconductor elements below half a micrometer include: (1) no pores are generated when filling the narrow trenches (gap) between conductors (metal wires), and (2) a flat surface to facilitate subsequent metal layers. Define and etch, (3) stability to avoid water vapor transmission, and (4) exhibit a net compressive stress. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (read the precautions on the back before filling out this page) There are many flattening improvements in the industry. For example, U.S. Patent No. 5,459,105 to Matsunuira describes a planarization method for a metal interlayer dielectric layer using PESi02'OrTEOS 'SOG, etch-back, and pESio2. Methods of planarization are also disclosed in Yang's U.S. Patent No. 5,482,900 and Moghadai's U.S. Patent No. 5,426,076. Allied Signal, located at 3500 Garrett Drive, Santa Clara CA 9554-2827 (telephone 408-562-0330) in its Advanced Microelectronic Materials Division product documentation, proposes that ___- _3_______ This paper standard applies to China's national building BC (CNS) A4 specification (2l0x 297 public) 416120 Printed by A7, Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs -------- l γ ”Ί /? '正 __ V. Description of the invention (n) L____j Improper local SOG etchback causes SOC to remain in the middle. Although there are many proposed barrier wall processes for the side walls of contact windows, these processes will increase the complexity of the process and the cost of production. In addition, in order to eliminate the contact window For the problem of poisoning, it has also been suggested to replace the spin-on glass layer with other material layers, such as a silicon oxide layer formed by a high-density plasma chemical vapor deposition (xpCVD) process. However, the SOG layer has other materials than those mentioned above. The lower dielectric constant of the layer can reduce the RC delay of products below line width 0.35μπ]. Basically, the dielectric constant of SOG is about 3, and the dielectric constant of PE-silicon oxide is about 4. S0G system In comparison, the present invention has the following features: ♦ One feature of the present invention is that the first SOG layer 18 has reflow properties so that SOG can be filled into the gaps between the metal wires that are larger than the first SOG layer after the reflow process. 18 is still on the metal wire 15. See Figure 1. ♦ The first S0G layer 18 of the present invention is a new application of organic spin-on glass such as A11 ied Signal company model Accuspin 418 SOP and Hitachi Chemical company model HSG-2209S-R7 ♦ The first S0G layer 18 and the second S0G layer 28 have different coating functions and properties. The first S0G layer 18 can be filled into a tight gap greater than or equal to 0. Ιμιη between the metal wires 14 without leaving On the surface of the metal wire 14. The second SOG layer 28 is a flattening sacrificial layer for planarization of the engraving. The second SOG layer 28 does not have the reflowable property of the first SOG layer 18. ♦ Second The S0G layer 28 was removed during the etch-back process to flatten the 13 paper sizes. Applicable to the national standard (CNS) A4 specification (210 X 297 mm) -1 .--- 11 ------ --Tun -------- Order --------- Line {Please read the back Precautions to fill out this page) 416120 Λ7 ΙΓ V. invention is described in (2) of the SOP Accuspin 418 Reflow of (X-18), and Accuglass T-ll series SOG- (lll, 211,311). However, these methods can be further improved to meet the needs of the above process and overcome the above disadvantages. [Summary of the invention] It is an object of the present invention to provide a method for manufacturing a metal interlayer dielectric layer, which includes a spin-on glass layer to fill a gap of less than 0.15 μm between wires and eliminate contact window poisoning ( poison via). Another object of the present invention is to provide a method for manufacturing a metal interlayer dielectric layer, which allows a thick barrier layer to be used to cover a metal wire when filling a gap smaller than 0.15 μm, and keeps the dielectric low. Constant to improve RC delay. Still another object of the present invention is to provide a method for manufacturing a metal interlayer dielectric layer, which includes an improved SOG process to provide excellent gap filling properties and maintain a low dielectric constant. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the precautions on the back before filling this page) Online! In order to achieve the above object, the present invention proposes a method for manufacturing a metal interlayer dielectric layer of a semiconductor element. The method first forms separate wires 14 on a semiconductor structure including a substrate. Secondly, on the separated wires and the semiconductor structure, the first silicon oxide layer (barrier layer) 16 having a uniform thickness is formed by the PECVD-SiH4 procedure, and the separated wires 14 covering the barrier layer 16 have a gap 15 between them. In an important step, a novel first spin-on-glass layer 18 is formed on the first silicon oxide layer. It is important that the first spin-on glass layer of the present invention has excellent gap-fill coverage and is heated at an appropriate temperature. _4_ This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm).
(l ;v -、I ；'W _；l! 發明說明（12) — 底下的氧化矽層24。 本發明雖然已以若干較佳實施例揭露如上，然其並 非用以限定本發明’任何熟習此項技藝者，在不脫離本 發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明的保護範圍當視後附之申請專利範圍所界定者為 準。 符號說明】 10〜半導體基底； 導線； 16〜第一氧化矽層 19〜填充厚度； 12~半導體結構； 15〜間隙； 18〜第一旋覆玻璃層； 24~第二氧化矽層； 28〜第二旋覆玻璃層；30〜絕緣蓋層； 118~旋覆玻璃層； 119〜部分厚度 I----I--—'—ft —---裂------— —訂 - -------線 (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 第87mo每明書修正頁 A7 B7 修正g(l; v-, I; 'W _; l! Description of the invention (12)-the underlying silicon oxide layer 24. Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention' any Those skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. Symbol Description] 10 ~ Semiconductor substrate; Wire; 16 ~ First silicon oxide layer 19 ~ Fill thickness; 12 ~ Semiconductor structure; 15 ~ Gap; 18 ~ First spin-on glass layer; 24 ~ Second silicon oxide layer; 28 ~ Second spin-on Glass layer; 30 ~ insulating cover layer; 118 ~ spin-on glass layer; 119 ~ part thickness I ---- I ---'- ft ----- crack --- --- order---- ---- Line (Please read the precautions on the back before filling in this page} Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy This paper is sized for the Chinese National Standard (CNS) A4 (210 X 297 mm) Book correction page A7 B7 correction g
經濟部智慧財產局員工消費合作社印製 五、發明說明（3) 下回流的性質。在回流程序之後，第一旋覆玻璃層18不 再覆於金屬導線上而是填入金屬導線之間的凹谷15中。 參見第1圖和第5B圖。適當加熱第一旋覆玻璃層使其回 流，藉此使所有第一旋覆玻璃層18從分離的導線14上 方流入導線的間隙中。 接下來，利用電漿加強化學氣相沈積（PECVD)-SiH4 程序沈積第二氧化破層2 4 ’覆於第一氧化石夕層16和間隙 15中的第一旋覆玻璃層18上。接著形成第二旋覆玻璃層 28(平坦化SOG)於第二氧化碎層24上。施行一回敍刻程 序以去除全部的第' —旋覆玻璃層和部分的第-氧化砂 層。最後，形成一絕緣蓋層3 0覆於第二氡化石夕層上。此 一絕緣蓋層30係由氧化石夕或氮化;e夕所形成。 本發明具有下列特徵： ♦本發明的一個特徵在於第一 S0G層18具有回流性 質’因此SOG可填入金屬導線間大於〇 15μιη的間隙中。 在回流程序後’只有少量甚或沒有第一 S0G層18仍留在 金屬導線15上。參見第1圖。 ♦本發明的第一 S0G層18係Al 1 ied Signal公司型 號 Accuspiπ 418 SOP 和 Hi tachi Chemica 1 公司型號· HSG-2209S-R7等有機物旋覆玻璃的新應用。 ♦第一 S0G層18和第二S0G層28具有不同的塗佈功 能和性質。第一 S0G層18可填入金屬導線14之間大於或 等於0· Ιμιη的緊密間隙中，而不會留在金屬導線14表面上。 第二S0G層28則是一平坦化犧牲層，作為回餘刻平坦化 k紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公复） I. 11---^-----裝·-------訂-------1 -線 (請先閱fi'背面之注意事項再填寫本頁) Λ7 1口 經濟部中央標準局身工消費合作社印裝 五、發明説明（4 ) 一~~--- 之用。第二SOG層28並不具備第一 SOG層18的可回流性 質。 ； ♦第二SOG層28在回蝕刻程序中被去除，用以平坦 化底下的氧化矽層24。 本發明提供一種改良的層間（或金屬層間）介電層。本 發明提供一金屬層間介電層16、18、24、30，其容許在填 充小於0·15μιη的間隙15時使用厚的阻障層16覆於金屬導 線14上《第一 SOG層18優異的間隙填充性質，使其可在 不縮小阻障層16厚度的情況下將間隙填滿。第一 8〇(}層18 可保持低的介電常數以改善RC延遲。再者，藉由將接觸窗 上方的第二SOG層28完全去除，可消除接觸窗毒化的問 題。 【圖式之簡單說明】 為了讓本發明半導體元件之上述目的、特徵、和優點 能更明顯易懂，下文特舉出若干較佳實施例，並配合所附 圖式，作詳細說明如下： 第1至4圖為剖面圖，用以繪示根據本發明製造半導 體元件金屬層間介電層的方法； 第5Α圖顯示回流處理之前，旋轉塗佈在半導體構造 上的SOG層； 第5Β圖顯示本發明間隙填充性質優異之第一 s〇G層 18受熱回流的效應，所有的第一 s〇g層18均從金屬導線 14上方流到間隙15中；以及 第5C圖顯示習知的S0G1〗8，雖然也作回流但是仍有 {請先閱讀背面之注意事項再填寫本頁) 、-=*Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (3) The nature of the return flow. After the reflow process, the first spin-on glass layer 18 is no longer overlaid on the metal wires but is filled in the valleys 15 between the metal wires. See Figures 1 and 5B. The first spin-on glass layer is appropriately heated to flow back, so that all the first spin-on glass layers 18 flow from above the separated wires 14 into the gaps of the wires. Next, a plasma-enhanced chemical vapor deposition (PECVD) -SiH4 process is used to deposit a second oxide breakdown layer 2 4 ′ over the first oxide layer 16 and the first spin-on glass layer 18 in the gap 15. Next, a second spin-on glass layer 28 (planarized SOG) is formed on the second oxide shatter layer 24. A retrospective engraving procedure was performed to remove all of the first-coated glass layer and part of the first-oxide sand layer. Finally, an insulating cap layer 30 is formed to cover the second fossilized layer. This insulating cap layer 30 is formed of oxidized stone or nitride. The present invention has the following features: ♦ One feature of the present invention is that the first SOG layer 18 has a reflow property 'so that SOG can be filled into the gap between the metal wires larger than 0.15 μm. After the reflow procedure, only a small amount or even no first SOG layer 18 remains on the metal wire 15. See Figure 1. ♦ The first SOG layer 18 of the present invention is a new application of organic spin-on glass such as Al 1 ied Signal company model Accuspiπ 418 SOP and Hi tachi Chemica 1 company model HSG-2209S-R7. ♦ The first SOG layer 18 and the second SOG layer 28 have different coating functions and properties. The first SOG layer 18 may be filled in a tight gap between the metal wires 14 that is greater than or equal to 0.1 μm, without remaining on the surface of the metal wires 14. The second S0G layer 28 is a flattening sacrificial layer, which is used as the back-planning flattening k paper standard to apply Chinese National Standard (CNS) A4 specification (210 X 297 public copy) I. 11 --- ^ ----- Packing ------- order ------- 1-line (please read the precautions on the back of fi 'before filling in this page) Λ7 1-port printed by the Workers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 、 Explanation of invention (4) 1 ~~ --- Use. The second SOG layer 28 does not have the reflowable properties of the first SOG layer 18. ♦ The second SOG layer 28 is removed during the etch-back process to planarize the underlying silicon oxide layer 24. The present invention provides an improved interlayer (or metal interlayer) dielectric layer. The present invention provides a metal interlayer dielectric layer 16, 18, 24, 30, which allows a thick barrier layer 16 to be used to cover a metal wire 14 when filling a gap 15 smaller than 0. 15 μm. The first SOG layer 18 is excellent The gap filling property makes it possible to fill the gap without reducing the thickness of the barrier layer 16. The first 80 () layer 18 can maintain a low dielectric constant to improve the RC delay. Furthermore, by completely removing the second SOG layer 28 above the contact window, the problem of poisoning the contact window can be eliminated. Brief Description] In order to make the above-mentioned objects, features, and advantages of the semiconductor device of the present invention more comprehensible, several preferred embodiments are listed below and described in detail with the accompanying drawings as follows: Figures 1 to 4 FIG. 5A is a cross-sectional view illustrating a method for manufacturing a metal interlayer dielectric layer of a semiconductor element according to the present invention; FIG. 5A shows a SOG layer spin-coated on a semiconductor structure before reflow processing; and FIG. 5B shows a gap filling property of the present invention The excellent first SOG layer 18 is affected by thermal reflow, and all the first SOG layers 18 flow from above the metal wire 14 into the gap 15; and FIG. 5C shows the conventional SOG1 [8], although Reflow but still (Please read the precautions on the back before filling this page),-= *
I -I 1 I 1 I I- I - I · ^紙張尺度適用中國國家揉準（CNS ) Λ4規格（210x^97^ __ = _ 五、發明說明（5) 〔n—袖无 一部份SOG留在金屬導線14上。 【較佳實施例的詳細說明】 (請先閲讀背面之泫意事項再填寫本頁> 本發明將根據後附的圖式作詳細的說明。本發明提 出一，成層間介電層的方法，以提供：在間隔為〇1μιΠ 或更寬的間隙15中良好的間隙覆蓋率，低的介電常數， 消除接觸窗毒化的問題，並且製程簡單者。 本發明的製程摘要如下面的表中： 圖 步驟 - 1 开> 成分離的導線14於一基底上 1 形成均勻的第一氧化矽層16(阻障層）pE—SiH』 2000A 1 關鍵^驊，形成第一 SOG層18(例的218 1900A) _其大部分填入金屬導線μ之間的凹谷π中而沒有 留下太多在金屬導線上方 1 回流(加熱及硬化）第一 S0G層18(間棟填充S® ♦此一回流程序使金屬導線14表面上不留任何第一 s〇G層18， 並且在金屬導線14間之間隙内的填充厚度19係介於ιοοοΑ 和3000 A範圍内。 1 形成第二氧化矽層24(PE-SiH4 7000A)於第一S0G層18和均 勻的第一氧化矽層16上 2 形成第二500層28(例如是人11丨6(15^1^1的211 -200〇人）（平 坦fcs曝 2 3 4 於430°C硬化第二S0G層28約30分鐘 回蝕刻第二S0G層（5000A) 形成一絕緣蓋層（Si02*SiN) ~ 經濟部智慧財產局員工消費合作社印製 如第1圖所示者，提供一半導體構造12 1〇。此半導 體構造12 10包括一半導體基底10及形成於其中的各種半導 體元件，像是源極、汲極、閘電極、電晶體、電容器、位 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部中夹標準局員工消費合作社印製 6120 ΗΊ 五、發明説明（6 ) 元線、導線、介電層等。圖中顯示的薄層10 12包括(但未 顯示）形成在導線層下方各種可能的半導體元件，像是 FETs、電容器、絕緣及導電層。 分離的導線14(例如：圖案，鋁金屬導線）形成於包括 基底10的半導體構造12上。該分離的導線14最好是鋁合 金金屬導線。由鋁合金構成的金屬導線具有嚴苛的阻障層16 厚度限制，其造成狹窄的間隙（約0.1至〇.2μπι的間隙）而需 要使用本發明新穎的第一 SOG層18。 其次，一均勻的第一氧化矽層（阻障層）16形成於分離 的導線14和半導體構造上。此第一氧化矽層16並未填滿 或封閉任何分離導線14之間的間隙。此第一氧化矽層16 可以PECVD-SiH4或TEOS製程來形成。第一氧化矽層16 的厚度最好是介於500A和2000A範圍内。 分離的導線14(覆蓋有阻障層16)之間具有間隙15(亦即 凹谷）。間隙15代表阻障層16表面之間的空間（凹谷）。最 窄的間隙15(基底上的）的寬度係大於Ο.ΐμπι者，最好是大 於0.15μπι者，窄間隙的寬度15最好是介於0.15μιη和0.5μπι 之間。整個基底上間隙的寬度可作任意變化並沒有最大寬 度的限制。從圖中可看出，間隙15係小於金屬導線14加 上阻障層16厚度兩倍後的實際間隔。 在本發明重要的步驟中，一新穎的第一旋覆玻璃（SOG) 層形成在第一氧化矽層16上。很重要的是此第一 SOG層 必須具有在加熱後回流的特性，使得第一 SOG層不會留在 金屬導線14的上方，特別是其間隙15大於Ο.ΐμπι甚或大 _8_ 本紙張尺度適用中國國家嘌準（CNS ) Α4規格（2丨0Χ297公犛） (請先閱讀背面之注意事項再填寫本頁) --° 線 經濟部中央標準局員工消費合作社印製 -6120 Λ: Η7 五、發明説明（7 ) 於0·15μπι者，最好是介於〇.15μηι和0·3μπι者。此第一 SOG 層最好是由下列材料所形成：Hitachi Chemical的HSG-2209S-R7(Hitachi Chemical &3，Shinjuku-MitsuiBldg.，2-l-1, Nishi-shinjuku, Shinjuku-ku, Tokyo, 163-0449, Japan) > Allied Signal型號218的旋覆玻璃和Allied Signal的 ACCUSPIN X18旋覆玻璃（Allied Signal公司高級微電子材 料部門，3500 Garrett Drive, Santa Clara CA 9554-2827，美國 電話 408-562-0330)。 為提供填滿〇.15μηι間隙所需第一 SOG層最好具備下 列的溶液參數：黏滯度介於2.80和2.9cP(25°C)，固含量百 分比介於20和22%(25。(：，4小時），閃點介於59和61°F之 間（以乙醇為基準）。 第一 SOG層係於溫度介於400°C至450°C(tgt=430°C)作 回流處理（烘烤與硬化）約10至200分鐘，最好是介於20和 40分鐘（tgt=30分鐘）之間。針對使用Allied Signal公司的 Accuspin 418可回流S〇p者，本案發明人發現其填充間隙 的寬度可低至Ο.ίμιη。此點不同於Allied Signal公佈的聲明 指出Accuspin 418可回流s〇P最多僅可填充0.15μιη之間 隙。因此本發明方法是Accuspin418可回流SOP的新用法。 不同於習知之製程，並不對本發明的第一 SOG層作回 钱刻以去除金屬導線14上的SOG層。如此可避免金屬導 線14在回银刻程序中受到電漿侵蝕而提高良率。 第5Α、5Β、和5C圖顯示本發明第一 SOG層18與標 準SOG層118相異之處β第5Α圖顯示金屬導線I4和均勻 本錄尺度適用中關家"膽2971楚i~—-- (請先閱讀背面之注意事項再填寫本頁) -* 線 經濟部中央標準局員工消資合作社印製 416120 ]Γ 五、發明説明（8 ) 的第一氧化矽層16。金屬導線14之間具有間隙15。第5C 圖顯示旋轉塗覆在半導體構造上的SOG層118。標準SOG 層118與本發明間隙填充性質優異的SOG層18，在旋轉塗 覆後均具有如第5A圖之SOG層18所示的形狀。 i 第5B圖顯示本發明間隙填充性質優異的SOG層18經 回流處理（加熱）後的效應。所有的SOG層18均從金屬導線 14上方流入間隙15中。相反地，第5C圖顯示習知的SOG 層118即使經過回流處理，仍有部分厚度119(大於50A)留 在金屬導線14上。本發明與習知技藝最主要的差異在於本 發明的第一 SOG層18具有優異的間隙填充性質，可流入 0.15μιη及更寬的間隙中而不會在金屬導線14的上方（亦即 頂點）留下任何厚度。 第一旋覆玻璃層可以下列步驟形成：提供Allied Signal 公司型號Accuspin 218之可回流SOP及型號X18之旋覆玻 璃溶液，並以介於2000和5000ι·ρπι範圍内的速度旋轉塗覆 該第一旋覆玻璃溶液約0.5至3分鐘，以及在溫度介於150 °(：至300°C範圍内硬化處理該第一旋覆玻璃溶液約10至200 分鐘。第一旋覆玻璃層的厚度係介於1000A和3000A範圍 内。 可施行一選擇性濕式或乾式回蝕刻以確保所有的第一 S0G層18(厚度介於1至50A的微量）從金屬導線14上方去 除。 如第2圖所示者，沈積第二氧化矽層24覆於第一係氧 化層和間隙中的第一旋覆玻璃層上。第二氧化矽層24可以 _10_ 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐) (請先閱讀背面之注意事項再填寫本頁)I -I 1 I 1 I I- I-I · ^ The paper size is applicable to the Chinese National Standard (CNS) Λ4 size (210x ^ 97 ^ __ = _ V. Description of the invention (5) [n—Sleeve without a part of SOG Stay on the metal wire 14. [Detailed description of the preferred embodiment] (Please read the notice on the back before filling this page> The present invention will be described in detail based on the attached drawings. The present invention proposes one, A method for forming an interlayer dielectric layer to provide: good gap coverage in a gap 15 with a gap of 〇1μιΠ or wider, low dielectric constant, eliminating the problem of contact window poisoning, and a simple process. The process summary is shown in the following table: Figure Step-1 Open > Separate wires 14 on a substrate 1 Form a uniform first silicon oxide layer 16 (barrier layer) pE-SiH 2000A 1 Key to form First SOG layer 18 (example 218 1900A) _ Most of it is filled into the valley π between the metal wires μ without leaving much above the metal wires 1 Reflow (heating and hardening) The first S0G layer 18 ( Filled with S® ♦ This reflow process does not leave any first SOG layer on the surface of the metal wire 14 1 8, and the filling thickness 19 in the gap between the metal wires 14 is between ιοοο A and 3000 A. 1 Form a second silicon oxide layer 24 (PE-SiH4 7000A) on the first SOG layer 18 and the uniform first A second 500 layer 28 is formed on the silicon oxide layer 16 (for example, person 11 丨 6 (211 ^ 200 people of 15 ^ 1 ^ 1) (flat fcs exposed 2 3 4 at 430 ° C to harden the second S0G layer 28 about Re-etch the second SOG layer (5000A) in 30 minutes to form an insulating cap layer (Si02 * SiN) ~ printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown in Figure 1, providing a semiconductor structure 12 10. This semiconductor Structure 12 10 includes a semiconductor substrate 10 and various semiconductor elements formed therein, such as a source, a drain, a gate electrode, a transistor, a capacitor, and a paper. The paper size is applicable to China National Standard (CNS) A4 (210 X 297) (Mm) Printed by the Consumer Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs 6120 ΗΊ V. Description of the Invention (6) Element wires, wires, dielectric layers, etc. The thin layer 10 12 shown in the figure includes (but not shown) formed on the wire Various possible semiconductor components below the layer, such as FETs, capacitors, Edge and conductive layer. Separate wires 14 (eg, patterns, aluminum metal wires) are formed on the semiconductor structure 12 including the substrate 10. The separate wires 14 are preferably aluminum alloy metal wires. Metal wires made of aluminum alloy have The severe barrier layer 16 has a thickness limitation, which results in a narrow gap (a gap of about 0.1 to 0.2 μm) and requires the use of the novel first SOG layer 18 of the present invention. Second, a uniform first silicon oxide layer (barrier layer) 16 is formed on the separated wires 14 and the semiconductor structure. The first silicon oxide layer 16 does not fill or close any gaps between the separated wires 14. The first silicon oxide layer 16 can be formed by a PECVD-SiH4 or TEOS process. The thickness of the first silicon oxide layer 16 is preferably in the range of 500A and 2000A. There is a gap 15 (ie, a valley) between the separated wires 14 (covered with the barrier layer 16). The gap 15 represents a space (valley) between the surfaces of the barrier layer 16. The width of the narrowest gap 15 (on the substrate) is greater than 0.1 μm, preferably greater than 0.15 μm, and the width of the narrow gap 15 is preferably between 0.15 μm and 0.5 μm. The width of the gap on the entire substrate can be arbitrarily changed and is not limited by the maximum width. It can be seen from the figure that the gap 15 is smaller than the actual interval after the metal wire 14 plus the barrier layer 16 is twice as thick. In an important step of the present invention, a novel first spin-on-glass (SOG) layer is formed on the first silicon oxide layer 16. It is very important that this first SOG layer has the characteristics of reflow after heating, so that the first SOG layer will not stay above the metal wire 14, especially the gap 15 is larger than 0. ΐμπι or even large China National Purification Standard (CNS) Α4 specification (2 丨 0 × 297 gong) (Please read the precautions on the back before filling this page)-° Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs -6120 Λ: Η7 V. Description of the invention (7) Those with 0.15 μm, preferably those with 0.15 μm and 0.3 μm. This first SOG layer is preferably formed of the following material: Hitachi Chemical's HSG-2209S-R7 (Hitachi Chemical & 3, Shinjuku-MitsuiBldg., 2-l-1, Nishi-shinjuku, Shinjuku-ku, Tokyo, 163-0449, Japan) > Allied Signal Model 218 Laminated Glass and Allied Signal's ACCUSPIN X18 Laminated Glass (Allied Signal Advanced Microelectronic Materials Division, 3500 Garrett Drive, Santa Clara CA 9554-2827, US Phone 408- 562-0330). To provide the first SOG layer required to fill the 0.15 μm gap, it is best to have the following solution parameters: viscosity between 2.80 and 2.9 cP (25 ° C), solid content percentage between 20 and 22% (25. ( :, 4 hours), flash point is between 59 and 61 ° F (based on ethanol). The first SOG layer is reflowed at a temperature between 400 ° C and 450 ° C (tgt = 430 ° C). (Baking and hardening) about 10 to 200 minutes, preferably between 20 and 40 minutes (tgt = 30 minutes). For those who use Allied Signal's Accuspin 418 reflowable Sop, the inventor of this case found that The width of the filling gap can be as low as 0. Ιμιη. This point is different from the statement issued by Allied Signal that Accuspin 418 can reflow the gap only at most 0.15μιη. Therefore, the method of the present invention is a new usage of Accuspin418 reflowable SOP. Unlike the conventional process, the first SOG layer of the present invention is not engraved to remove the SOG layer on the metal wire 14. In this way, the metal wire 14 can be prevented from being eroded by plasma during the silver etch back process to improve the yield. Figures 5A, 5B, and 5C show the first SOG layer 18 and the standard SOG layer 11 of the present invention 8Differences β Figure 5A shows the metal wire I4 and the uniform size of this record applies to Zhongguanjia " Dan 2971 Chu i ~-(Please read the precautions on the back before filling this page)-* Department of Wire Economy Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 416120] Ⅴ. The first silicon oxide layer 16 of the invention description (8). There is a gap 15 between the metal wires 14. Figure 5C shows the SOG layer spin-coated on the semiconductor structure 118. The standard SOG layer 118 and the SOG layer 18 having excellent gap-filling properties of the present invention have the shape shown in FIG. 5A as the SOG layer 18 after spin coating. I FIG. 5B shows that the present invention has excellent gap-filling properties. The effect of the SOG layer 18 after reflow treatment (heating). All the SOG layers 18 flow into the gap 15 from above the metal wire 14. In contrast, FIG. 5C shows that the conventional SOG layer 118 is partially reflowed The thickness 119 (greater than 50A) is left on the metal wire 14. The main difference between the present invention and the conventional technique is that the first SOG layer 18 of the present invention has excellent gap-filling properties and can flow into 0.15 μm and wider gaps. Not above the metal wire 14 (I.e., the apex) leaves any thickness. The first spin-on glass layer can be formed by the following steps: provide a reflowable SOP of Allied Signal company model Accuspin 218 and a spin-on glass solution of model X18, and the range is between 2000 and 5000 ι · ρπι The first spin-coated glass solution is spin-coated for about 0.5 to 3 minutes at an internal speed, and the first spin-coated glass solution is hardened at a temperature between 150 ° C: to 300 ° C for about 10 to 200 minutes. The thickness of the first spin-on glass layer is in the range of 1000A and 3000A. A selective wet or dry etch-back can be performed to ensure that all of the first SOG layer 18 (a trace amount between 1 and 50 A in thickness) is removed from above the metal wire 14. As shown in FIG. 2, a second silicon oxide layer 24 is deposited on the first oxide layer and the first spin-on glass layer in the gap. The second silicon oxide layer 24 can be _10_ This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
*1T 線—— 經濟部中央標準局员工消費合作社印衷 416120 五、發明説明（9 ) PECVD-SiH4或TEOS製程來形成，但最好是以PECVD-SiH4 製程來形成。第二氧化矽層24的厚度係介於3000A和 10000A 範圍内（tgt=700〇A)。 仍然請參見第2圖，形成第二旋覆玻璃層28覆於第二 氡化矽層24上。第二旋覆玻璃層可以一「平坦化s〇G」來 形成。可用的第二SOG層例如是：Allied Signal公司的 八〇〇1^1333 1'-11系列800，型號111、211、或311。 第二旋覆玻璃層可選擇性地在溫度介於400°C至450。(： (tgt=430°C)範圍内進行硬化處理約10至200分鐘（tgt=30分 鐘）。此硬化處理可提供更高的穩定性。 第二旋覆玻璃層的厚度係介於1000A和5000A範圍 内，最好是約 2000A(tgt=2000A)。 如第3圖所示者，施行一回姓刻程序以去除全部的第 二旋覆玻璃層28和部分的第二氧化矽層24，其去除的總厚 度係介於約3000A和7000A之間（tgt=500〇A)。此一回蝕刻 程序最好是一乾式蝕刻程序，例如是使用CF4或CHF3者。 繼續請參見第4圖，形成一絕緣蓋層30覆於第一氧化梦層 上，該絕緣蓋層30最好是由氧化矽或氮化矽所形成。絕緣 蓋層30的厚度係介於1000A和5〇〇〇A之間’最好是約為 3000A。 _______π _ 本紙張尺度適用中國國家樣準（CNS )/以规格丨_ 210X297公楚） I,--------' '------1玎------線 (請先閲讀背面之注意事項再填寫本頁) 416120 五、發明説明（10) 表1 本發明金屬層間介電層（IMD)的製造流程* 1T Line——Intentions of Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 416120 V. Description of Invention (9) PECVD-SiH4 or TEOS process, but it is best to use PECVD-SiH4 process. The thickness of the second silicon oxide layer 24 is in the range of 3000A and 10000A (tgt = 700oA). Still referring to FIG. 2, a second spin-on glass layer 28 is formed on the second silicon halide layer 24. The second spin-on glass layer can be formed by a "flattening SOG". The second SOG layer that can be used is, for example, the 8001 ^ 1333 1'-11 series 800, model 111, 211, or 311 of Allied Signal. The second spin-on glass layer can be selectively at a temperature between 400 ° C and 450 ° C. (: (Tgt = 430 ° C) for about 10 to 200 minutes (tgt = 30 minutes). This hardening treatment provides higher stability. The thickness of the second spin-on glass layer is between 1000A and In the range of 5000A, it is preferably about 2000A (tgt = 2000A). As shown in FIG. 3, a family name engraving process is performed to remove all the second spin-on glass layer 28 and part of the second silicon oxide layer 24. The total thickness removed is between about 3000A and 7000A (tgt = 50000A). This time the etching process is preferably a dry etching process, such as those using CF4 or CHF3. Continue to see Figure 4, An insulating cap layer 30 is formed to cover the first oxide layer. The insulating cap layer 30 is preferably formed of silicon oxide or silicon nitride. The thickness of the insulating cap layer 30 is between 1000A and 5000A. It's best to be about 3000A. _______ π _ This paper size is applicable to China National Standard (CNS) / to specifications 丨 _ 210X297 Gongchu I, -------- '' ------ 1玎 ------ line (please read the notes on the back before filling this page) 416120 V. Description of the invention (10) Table 1 Manufacturing process of the metal interlayer dielectric layer (IMD) of the present invention
層別 材質 參數 下限 選用值 上限 第一氧化矽層 ~ PE-SiH4 氧化矽 厚度(A) 500A 2000A 3000A 第一 SOG層 (間隙填充用） Allied signal 218 厚度（A) ιοοοΑ 1900A 2000A Hitachi HSG- 2209S-R7 厚度(A) ιοοοΑ 2000A 硬化第一 SOG層 18 溫度 於 430°c 施行30 分鐘 第二氧化矽層24 -PE-SiH4 厚度（A) 3000A 7000A ΙΟΟΟΟΑ 第二SOG層 (平坦化之用） Allied signal 211 厚度(人) ιοοοΑ 2000A 3000Λ 於430°C硬化第二 SOG層約30分鐘 回钱刻S0G層 SOG 厚度(A) ιοοοΑ 3000A 5000A II--------' -------ΐτ------.^ (請先閱讀背面之注意事項再填寫本頁) 【本發明的好處】 經濟部中央標準局員工消費合作社印裂 目前現有的SOG平坦化製程並無法充分地填滿導線14 之間小於0.15μπι(0.1μπι)的間隙。解決上述間隙填充問題的 方法之一為降低阻障層16的厚度。然而，若阻障層16的 厚度降低過多，金屬導線14在接下來的電漿回蝕刻程序中 將受到損傷。 現今SOG製程的另一個缺點為接觸窗毒化的問題，其 中SOG層118會遺留在金屬導線上方的接觸窗中。此點可 _12_ 本紙張尺度適用中國國家標準（CNS ) Λ4規格{ 2丨0Χ297公释） 416120 經濟部智慧財產局員工消費合作社印製 A7 ----—-l γ ” Ί / ? '正__ 五、發明說明（n) L____j南充 由於不當的局部SOG回蝕刻使s〇G留在中而造成。 雖然有許多針對接觸窗側壁之間隙壁製程被提出，但這 些製程都會增加製程的複雜度和生產的成本。此外，為 了消除接觸窗毒化的問題，也有人建議以其他材質層取 代旋覆玻璃層，像是以高密度電漿化學氣相沈積（仙pCVD) 程序所形成的氧化矽層等。然而，S0G層具有比上述其他 材質層更低的介電常數，可降低線寬0.35μπ]以下產品的 RC延遲。基本上，S0G的介電常數約為3，而ΡΕ-氧化矽 的介電常數則約為4。 與習知之S0G製程比較，本發明具有下列特徵： ♦本發明的一個特徵在於第一 S0G層18具有回流性 質’因此S0G可填入金屬導線間大於的間隙中。 在回流程序後，只有少量甚或沒有第一 S0G層18仍留在 金屬導線15上。參見第1圖。 ♦本發明的第一 S0G層18係A11 ied Signal公司型 號 Accuspin 418 SOP 和 Hitachi Chemical 公司型號 HSG-2209S-R7等有機物旋覆玻璃的新應用。 ♦第一 S0G層18和第二S0G層28具有不同的塗佈功 能和性質。第一 S0G層18可填入金屬導線14之間大於 或等於Ο.ίμιη的緊密間隙中，而不會留在金屬導線14表 面上。第二S0G層28則是一平坦化犧牲層，作為回姓刻 平坦化之用。第二S0G層28並不具備第一 S0G層18的 可回流性質。 ♦第二S0G層28在回蝕刻程序中被去除，用以平坦化 13 本紙張尺度適用令國囤家標準（CNS)A4規格（210 X 297公釐） -1.---11--------敦--------訂---------線 {請先閲讀背面之注意事項再填寫本頁)Upper limit of layer material parameter selection value upper limit First silicon oxide layer ~ PE-SiH4 Silicon oxide thickness (A) 500A 2000A 3000A First SOG layer (for gap filling) Allied signal 218 Thickness (A) ιοοοΑ 1900A 2000A Hitachi HSG- 2209S- R7 thickness (A) ιοοοΑ 2000A hardened first SOG layer 18 temperature 30 minutes at 430 ° c for 30 minutes second silicon oxide layer 24 -PE-SiH4 thickness (A) 3000A 7000A ΙΟΟΟΟΑ second SOG layer (for planarization) Allied signal 211 Thickness (person) ιοοοΑ 2000A 3000Λ Harden the second SOG layer at 430 ° C for about 30 minutes and pay back the engraved SOG thickness of SOG layer (A) ιοοοΑ 3000A 5000A II -------- '------- ΐτ ------. ^ (Please read the notes on the back before filling out this page) [Benefits of the invention] The current consumer SOG of the Central Bureau of Standards of the Ministry of Economic Affairs has cracked the existing SOG flattening process and cannot fully fill it. The gap between the full wires 14 is less than 0.15 μm (0.1 μm). One way to solve the above gap filling problem is to reduce the thickness of the barrier layer 16. However, if the thickness of the barrier layer 16 is reduced too much, the metal wire 14 will be damaged in the subsequent plasma etch-back process. Another disadvantage of today's SOG processes is the problem of contact window poisoning, in which the SOG layer 118 is left in the contact window above the metal wires. This point can be _12_ This paper size applies the Chinese National Standard (CNS) Λ4 specification {2 丨 0 × 297 public release) 416120 Printed by A7 of the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs -------- l γ ”Ί /? '正__ 5. Description of the invention (n) L____j Nanchong was caused by improper local SOG etchback to keep s0G in the middle. Although there are many barrier wall processes for contact window sidewalls, these processes will increase the complexity of the process In addition, in order to eliminate the problem of contact window poisoning, it is also suggested to replace the spin-on glass layer with another material layer, such as silicon oxide formed by high-density plasma chemical vapor deposition (sencent pCVD) process. Layer, etc. However, the SOG layer has a lower dielectric constant than the other material layers mentioned above, which can reduce the RC delay of products below 0.35μπ. Basically, the dielectric constant of SOG is about 3, and PE-silicon oxide The dielectric constant is about 4. Compared with the conventional SOG process, the present invention has the following characteristics: ♦ One feature of the present invention is that the first SOG layer 18 has a reflow property. Therefore, SOG can be filled between After the reflow process, only a small amount or even no first SOG layer 18 remains on the metal wire 15. See Figure 1. ♦ The first SOG layer 18 of the present invention is A11 ied Signal company model Accuspin 418 SOP and Hitachi New application of organic company spin-on glass such as Model HSG-2209S-R7. ♦ The first SOG layer 18 and the second SOG layer 28 have different coating functions and properties. The first SOG layer 18 can be filled into the metal wire 14 In a tight gap greater than or equal to 0. Ιμιη, and will not remain on the surface of the metal wire 14. The second SOG layer 28 is a planarization sacrificial layer for planarizing the engraved back. The second SOG layer 28 It does not have the reflowable properties of the first SOG layer 18. ♦ The second SOG layer 28 was removed during the etch-back process to flatten the 13 paper sizes. Applicable to China National Standard (CNS) A4 (210 X 297) (Mm) -1 .--- 11 -------- Tun -------- Order --------- Line {Please read the notes on the back before filling this page )
(l ;v -、I ；'W _；l! 發明說明（12) — 底下的氧化矽層24。 本發明雖然已以若干較佳實施例揭露如上，然其並 非用以限定本發明’任何熟習此項技藝者，在不脫離本 發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明的保護範圍當視後附之申請專利範圍所界定者為 準。 符號說明】 10〜半導體基底； 導線； 16〜第一氧化矽層 19〜填充厚度； 12~半導體結構； 15〜間隙； 18〜第一旋覆玻璃層； 24~第二氧化矽層； 28〜第二旋覆玻璃層；30〜絕緣蓋層； 118~旋覆玻璃層； 119〜部分厚度 I----I--—'—ft —---裂------— —訂 - -------線 (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）(l; v-, I; 'W _; l! Description of the invention (12)-the underlying silicon oxide layer 24. Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention' any Those skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. Symbol Description] 10 ~ Semiconductor substrate; Wire; 16 ~ First silicon oxide layer 19 ~ Fill thickness; 12 ~ Semiconductor structure; 15 ~ Gap; 18 ~ First spin-on glass layer; 24 ~ Second silicon oxide layer; 28 ~ Second spin-on Glass layer; 30 ~ insulating cover layer; 118 ~ spin-on glass layer; 119 ~ part thickness I ---- I ---'- ft ----- crack --- --- order---- ---- Line (Please read the precautions on the back before filling this page} Printed on the paper by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)