五、發明說明（1) 本發明是有關於一種雙鑲敌（dual damascene)結構製 程，且特別是有關於一種適用於深次微米技術之雙鑲嵌杜 構製程。 入…- 習知一種雙鑲嵌結構製程，主要是先在預定的位置定- 義出雙鑲嵌溝渠後，然後再將金屬填入定義出.來的雙镶嵌 溝渠内’便可形成一可作為金屬内連線之鑲嵌結構。為使- 此習知製程更清楚可見，玆將於第1A〜1D圖詳細說明之。 首先’請參照第1A圖’提供一包含有半導體元件之基 底100。其次’依序形成一第一内金屬介電層11〇、一餘刻 阻絕層1 2 0，例如氮化物層，以及一第二内金屬介電層丨3 〇 於基底100上。然後’再以微影程序形成一光阻圖案14〇於 第一内金屬介電層130上’並且於雙鎮嵌結構預定處形成 —露出第二内金屬介電層1 30表面之蝕刻開口 145。 其次，請參照第1 B圖，以光阻圖案1 40作為蝕刻罩 幕’依序蝕刻去除未被光阻圖案140所覆蓋之第二内金屬 介電層1 30、蝕刻阻絕層1 20以及第一内金屬介電層1丨〇， 形成一貫穿第二内金屬介電層130、蝕刻阻絕層12〇以及第 一内金屬介電層110的溝渠丨5〇。然後，先去除光阻圖案 140後’再以微影程序形成另一光阻圖案16〇於第二内金屬 介電層130上’此光阻圖案16〇在雙鑲嵌結構預定處並且具 有一範圍涵蓋溝渠150且寬度大於溝渠150之蝕刻開口 1 6 5 〇 接著’請參照第1 c圖，以光阻圖案1 60作為蝕刻罩 幕’去除未被光阻圖案16〇所覆蓋之第二内金屬介電層至5. Description of the invention (1) The present invention relates to a dual damascene structure process, and more particularly to a dual damascene structure process suitable for deep sub-micron technology. Into ...- Learn about a dual-mosaic structure process, which is mainly defined at a predetermined location-after defining the dual-mosaic trench, and then filling the metal with the defined dual-mosaic trench, you can form a metal that can be used as a metal. Inlaid mosaic structure. In order to make this process more clearly visible, it will be explained in detail in Figures 1A ~ 1D. First, "refer to Fig. 1A", a substrate 100 including a semiconductor element is provided. Secondly, a first inner metal dielectric layer 110, a resist layer 1220, such as a nitride layer, and a second inner metal dielectric layer 3o are sequentially formed on the substrate 100. Then 'form a photoresist pattern 1440 on the first inner metal dielectric layer 130 by a lithography process' and form it at a predetermined position of the double-embedded structure-exposing the etching opening 145 on the surface of the second inner metal dielectric layer 130. . Secondly, referring to FIG. 1B, the photoresist pattern 1 40 is used as an etching mask to sequentially etch and remove the second inner metal dielectric layer 1 30, the etching stop layer 1 20, and the first An inner metal dielectric layer 110 forms a trench penetrating through the second inner metal dielectric layer 130, the etching stopper layer 120, and the first inner metal dielectric layer 110. Then, the photoresist pattern 140 is removed first, and then another photoresist pattern 16 is formed on the second inner metal dielectric layer 130 by a lithography process. The photoresist pattern 16 is at a predetermined position of the dual damascene structure and has a range. The etched openings covering the trench 150 and having a width greater than the trench 150 16 5 〇 Then 'refer to FIG. 1 c and use the photoresist pattern 160 as an etching mask' to remove the second internal metal not covered by the photoresist pattern 16 Dielectric layer to
415024- 五、發明說明（2) 蝕刻阻絕層1 20為止，並且與先前所形成的溝渠〗5〇共同形 成一如圖所示之雙鑲嵌溝渠17〇。 最後’請參照第1D圖，先形成一阻障層（barr ier layer) 175適順性地覆蓋於第二内金屬介電層13〇表面以及 雙鑲嵌溝渠170之内壁’然後再形成一導電性較佳的金屬 層180於阻障層175上’並且將雙鑲嵌溝渠17〇填滿。然 後，以化學機械研磨法或者回蝕刻法依序去除位在第二内 金屬介電層130表面之多餘金屬層u〇和阻障層175後，便 可形成一作為金屬内連線用的雙鑲嵌結構185。 然而’如上所述之雙鑲嵌結構製程，應用於線寬逐漸 縮小的技術’例如深次微米技術以下時，雙鑲嵌結構之尺 寸勢必跟著縮小化，微影製程中的光阻臨界尺寸（CD)較難 控制’故雙鑲换溝渠之定義將會有對不準之現象，或者_因 為雙鑲嵌結構之尺寸縮小而造成雙鑲嵌溝渠之寬度過小， 使得金屬之溝填動作不易進行’增加雙鑲散結構製程之難 度。 有鑑於此，本發明為解決如上所述之缺點，因此在雙 鑲嵌溝渠之定義製程中’乃先定義出寬度較習知製程寬的 雙鑲嵌溝渠’然後再利用習知的側壁子製程，於雙鑲嵌溝 渠之内壁形成絕緣側壁子’用以調整所需要的雙鑲嵌溝渠 寬度’除可有效克服因為雙鑲嵌溝渠尺寸縮小化而造成的 對不準現象外，且由於本發明所揭示的雙鑲嵌溝渠之寬度 較大’因此便可使金屬較易被填到此雙鑲嵌溝渠内，使此 雙鑲嵌結構可被應用到深次微米以下之製程。415024- V. Description of the invention (2) Etching the resist layer 120 and forming a double mosaic trench 17 as shown in the figure with the previously formed trench [50]. Finally, please refer to FIG. 1D, first form a barrier layer 175 to cover the surface of the second inner metal dielectric layer 13 and the inner wall of the dual damascene trench 170 comfortably, and then form a conductive layer. The preferred metal layer 180 is on the barrier layer 175 'and fills the dual damascene trenches 170. Then, a chemical mechanical polishing method or an etch-back method is used to sequentially remove the excess metal layer u0 and the barrier layer 175 located on the surface of the second inner metal dielectric layer 130 to form a double layer for metal interconnections. Mosaic structure 185. However, the 'dual-damascene manufacturing process mentioned above is applied to the technology of gradually decreasing line width', such as below the deep sub-micron technology, the size of the dual-damascene structure will inevitably decrease, and the critical size of the photoresist in the lithography process (CD) Difficult to control 'Therefore, the definition of double inlaid trenches will be inaccurate, or _ the width of double inlaid trenches will be too small due to the reduced size of the double inlaid structure, making it difficult to perform metal trench filling operations' Difficulty of the scattered structure process. In view of this, the present invention solves the disadvantages as described above, so in the process of defining a dual-mosaic trench, 'the dual-mosaic trench having a wider width than a conventional process is first defined', and then the conventional sidewall process is used. The inner wall of the double-mosaic trench forms an insulating side wall 'for adjusting the required width of the double-mosaic trench'. In addition to effectively eliminating the misalignment caused by the reduction in the size of the double-mosaic trench, the double-mosaic trench The width of the trench is relatively large, so that the metal can be easily filled into the dual-mosaic trench, so that the dual-mosaic structure can be applied to processes below the sub-micron depth.
第5頁 415024 五、發明說明（3) 本發明之特徵是揭不一種適用於深次微米技術之雙鑲 嵌結構製程，其步驟包括*· (3)提供一包含有半導體元件 之基底；（b)依序形成一個由一第一内金屬介電層、一蝕 刻阻絕層以及一第二内金屬介電層所構成之堆疊結構於該 基底上；（c)以雙鑲嵌程序定義該堆疊結構，並且在雙鑲 嵌結構之預定處形成一貫穿該堆疊結構且露出該基底表面 之雙鑲嵌溝渠：（d)在該雙鑲嵌溝渠之側壁形成一絕緣侧 壁子；（e)依序形成一阻障層以及一金屬層於該第二内金 屬介電層表面，並且溝填該雙鑲嵌溝渠；以及（f)去除位 在該第二内金屬介電層表面多餘的該阻障層以及該金屬 層’形成一由該阻障層和該金屬層所構成之雙鑲嵌結構。 如上所述之製程’其中該第一内金屬介電層之材料係 選自氮化矽、矽石、複晶氮矽化合物所構成之族群；該第 二内金屬介電層之材料係選自氮化矽、矽石、複晶氮矽化 ^物所構成之族群；而蝕刻阻絕層之材料可為氮化矽或氮 开;I 2 ί祕步驟⑷之側壁子的形成步驟包括：全面性地 ^ '、層於該第二内金屬介電層表面以及該雙鑲嵌溝 金屬介電層表及該向性蝕刻去除位在該第二内 = = :成1緣側壁子，其中該絕緣層為化 選自氮化鈕或氮化：所矽層。此外，該阻障層係 銅、鋁、鋁鋼入合 成之族群，而該金屬層則係選自 本發明之：枯矽鋼合金所構成之族群。 d炙另—特徵是描千£ ^ 句不另一種適用於深次微米技術 415024 五、發明說明（4) 之雙鑲嵌結構製程，其步驟包括：（a)提供一包含有半導 體元件之基底；（b)依序形成一個由一第一内金屬介電 層、一蝕刻阻絕層以及一第二内金屬介電層所構成之堆疊 結構於該基底上；（c)以微影程序和蝕刻技術定義該堆疊 結構，並且在雙鑲嵌結構之預定處形成一貫穿該堆疊結構 且露出該基底表面之第一溝渠：（d)再次定義該第一溝渠 兩側之該第二内金屬介電層，形成一包含該第一溝渠且寬 度大於該第一溝渠之第二溝渠，完成一由該第一溝渠和該 第二溝 一溝渠 子；（f 介電層 該第二 形成一 如 選自氮 金屬介 成之族 物。步 全面性 雙鑲嵌 在該第 層，並 形成一 渠所構成之雙鑲嵌溝渠；（e)在該雙鑲嵌溝渠之第 和第二溝渠之側壁分別形成一第一、第二絕緣侧壁 )依序形成一阻障層以及一金屬層於該第二内金屬 表面，並且溝填該雙鑲嵌溝渠；以及（g)去除位在 内金屬介電層表面多餘的該阻障層以及該金屬層， 由該阻障層和該金屬層所構成之雙鑲叙結構。 上所述之製程’其中該第一内金屬介電層之材料係 化矽、矽石、複晶氮化物所構成之族群；該第二内 電層之材料係選自氮化梦、石夕石、複晶氮化物所構 群；而餘刻阻絕層之材料可為氮化矽或氣氧梦化 驟（e)之第一、第二絕緣侧壁子的形成步驟包括： 地形成一絕缘詹於該第二内金屬介電層表面以及該 溝渠之内壁壁以及底部；以及非等向性蝕刻去除= 二内金屬介電層表面以及該雙鑲嵌溝渠底部之絕 於該雙鎮嵌溝渠之第一溝渠和第二溝渠之側壁分別 第一、第二絕緣侧壁子，其中該絕緣層為化學氣相Page 5 415024 V. Description of the invention (3) The present invention is characterized by uncovering a dual damascene structure process suitable for deep sub-micron technology. The steps include *. (3) providing a substrate containing a semiconductor element; (b) ) Sequentially forming a stacked structure composed of a first inner metal dielectric layer, an etch stop layer and a second inner metal dielectric layer on the substrate; (c) defining the stacked structure by a dual damascene procedure, And a double mosaic trench that penetrates the stacked structure and exposes the surface of the substrate is formed at a predetermined position of the dual mosaic structure: (d) an insulating sidewall is formed on the sidewall of the dual mosaic trench; (e) a barrier is sequentially formed Layer and a metal layer on the surface of the second inner metal dielectric layer and trench filling the dual damascene trench; and (f) removing the barrier layer and the metal layer which are redundant on the surface of the second inner metal dielectric layer 'Form a dual damascene structure composed of the barrier layer and the metal layer. The process as described above, wherein the material of the first inner metal dielectric layer is selected from the group consisting of silicon nitride, silica, and polycrystalline silicon nitride compound; the material of the second inner metal dielectric layer is selected from A group consisting of silicon nitride, silica, and polycrystalline silicon silicide; and the material of the etch stop layer may be silicon nitride or nitrogen; I 2 ⑷ The step of forming the sidewalls includes: comprehensively ^ 'Layered on the surface of the second inner metal dielectric layer, the surface of the dual damascene trench metal dielectric layer, and the directional etching removal is located in the second inner ==: forming a side wall, wherein the insulating layer is The change is selected from a nitride button or a nitride: silicon layer. In addition, the barrier layer is a group consisting of copper, aluminum, and aluminum steel, and the metal layer is selected from the group consisting of a dry silicon steel alloy according to the present invention. d—Another feature is the description of the method of double-damascene structure suitable for deep sub-micron technology 415024 5. Invention Description (4), the steps include: (a) providing a substrate containing a semiconductor element; (B) sequentially forming a stacked structure composed of a first inner metal dielectric layer, an etch stop layer and a second inner metal dielectric layer on the substrate; (c) lithography process and etching technology Defining the stacked structure, and forming a first trench penetrating the stacked structure and exposing the substrate surface at a predetermined position of the dual damascene structure: (d) defining the second inner metal dielectric layer on both sides of the first trench again, Forming a second trench including the first trench and having a width greater than the first trench, and completing a trench from the first trench and the second trench; (f the second formation of the dielectric layer as selected from nitrogen metal Introduced family. Steps are comprehensively double inlaid on the first layer and form a double inlaid trench formed by a canal; (e) a first and a second are formed on the side walls of the first and second trenches of the double inlaid trench, respectively. (Two insulated side walls) Forming a barrier layer and a metal layer on the second inner metal surface, and filling the double damascene trench; and (g) removing the barrier layer and the metal layer that are redundant on the surface of the inner metal dielectric layer, by A double damascene structure composed of the barrier layer and the metal layer. The process described above, wherein the material of the first inner metal dielectric layer is a group consisting of siliconized silicon, silica, and polycrystalline nitride; the material of the second inner electrical layer is selected from the group consisting of Nitride Dream and Shi Xi Group consisting of stone, polycrystalline nitride; and the material of the remaining barrier layer may be silicon nitride or gas-oxygen dreaming step (e). The first and second insulating sidewall forming steps include: forming an insulation on the ground Zhan Yu on the surface of the second inner metal dielectric layer and the inner wall and bottom of the trench; and anisotropic etching removal = the surface of the second inner metal dielectric layer and the bottom of the double damascene trench are absolutely the same as those of the double town embedded trench The sidewalls of the first trench and the second trench are respectively first and second insulating sidewalls, wherein the insulating layer is a chemical vapor phase
第7頁 Η 415024 五、發明說明（5) 氧化層’例如氧化石夕層。此外，該阻障層係選自氮 =鈕或鼠化鈦所構成之族群；而該金屬層則係選自銅、 鋁、鋁銅合金和鋁矽銅合金所構成之族群。 為使本發明之優點和特徵更清楚可見，兹將以根據本 ^明之較佳實施例’並配合相關圖式，詳細說明如下。 圖式之簡單說明： 第1A〜1D圖顯示的是習知一種雙鑲嵌結構之剖面製 程。 第2A〜2D圖顯示的則是根據本發明之—實施例的雙鑲 嵌結構之剖面製程。 實施例： 首先，清參照第2A圖’提供一包含有半導體元件之基 底200。其次，依序形成一第一内金屬介電層21〇、一蝕刻 阻絕層220以及一第二内金屬介電層23〇於基底2〇〇上。然 後，再以微影程序形成一光阻圖案240於第二内金屬介電 層230上，並且在雙鑲嵌結構預定處形成一露出第二内金 屬介電層230表面之開口 245 ’用以定義雙鑲嵌結構中寬度 較小的溝渠部位。此開口 2 4 5之寬度比上述之習知雙鑲嵌 製程中之蝕刻開口 145的寬度來得寬。 _ 然後’請參照第2 B圖’以光阻圖案2 4 0作為蝕刻罩 幕’蝕刻去除未被光阻圖案240所覆蓋之第二内金屬介電 層230、蝕刻阻絕層220以及第一内金屬介電層210，形成 一露出基底200表面之溝渠250。然後，先去除光阻圖案 240後，再以微影程序形成另一光阻圖案260於第二内金屬Page 7 Η 415024 V. Description of the invention (5) Oxidation layer ', such as a stone oxide layer. In addition, the barrier layer is selected from the group consisting of nitrogen = button or titanium nitride; and the metal layer is selected from the group consisting of copper, aluminum, aluminum-copper alloy, and aluminum-silicon-copper alloy. In order to make the advantages and features of the present invention more clearly visible, the following describes in detail the preferred embodiments according to the present invention in conjunction with related drawings. Brief description of the drawings: Figures 1A to 1D show the cross-section process of a conventional dual-mosaic structure. Figures 2A to 2D show a cross-section process of a dual-embedded structure according to an embodiment of the present invention. Embodiment: First, referring to FIG. 2A, a substrate 200 including a semiconductor element is provided. Secondly, a first inner metal dielectric layer 21, an etch stop layer 220, and a second inner metal dielectric layer 23 are sequentially formed on the substrate 2000. Then, a photoresist pattern 240 is formed on the second inner metal dielectric layer 230 by a lithography process, and an opening 245 ′ is formed at a predetermined position of the dual damascene structure to expose the surface of the second inner metal dielectric layer 230 to define Smaller trench area in the double mosaic structure. The width of this opening 2 4 5 is wider than the width of the etching opening 145 in the conventional dual damascene process described above. _ Then 'Please refer to Figure 2B' using the photoresist pattern 2 4 0 as an etching mask 'to etch and remove the second inner metal dielectric layer 230, the etching stop layer 220 and the first inner layer which are not covered by the photoresist pattern 240. The metal dielectric layer 210 forms a trench 250 exposed on the surface of the substrate 200. Then, after removing the photoresist pattern 240, another photoresist pattern 260 is formed on the second inner metal by a lithography process.
415024 五、發明說明（6) 介電層230表面，且光阻圖案260並有一寬度大於開口 245 且包含溝渠250之蝕刻開口 265。同樣地，蝕刻開口 265之 寬度大於上述習知製程之蝕刻開口 1 65的寬度。 接著’請參照第2C圖，再以光阻圖案260作為蝕刻罩 幕刻去除開口 265下所露出之第二内金屬介電層230至 姓刻阻絕層220為止’完成一開口較寬的雙鑲嵌溝渠280， 可使導電性較佳的金屬在後續製程中較易被填入此雙鑲嵌 溝渠280内。 然後’先以化學氣相沉積法’全面性形成一絕緣層 (未顯示），例如氧化矽層’於第二内金屬介電層23〇表面 以及雙鑲嵌溝渠280之側壁以及其底部，然後再以非等向 ，蝕刻製程去除位在第二内金屬介電層23〇表面以及雙鑲 肷溝渠280底部之氧化層’並於雙鑲嵌溝渠28〇之側壁形成 一絕緣側壁子2 7 0。 最後’請參照第2 D圖’先形成一阻障層2 8 5適順性地 覆蓋第「内金屬介電層表面以及雙鑲嵌蝕刻溝渠28〇之内 壁’然後在形成一金屬層290於該阻障層285表面上，並且 將雙鑲嵌溝渠280填滿。接著，再以回蝕刻法或者化學機 械研磨法依序去除位在第二内金屬介電層23〇表面之多餘 金屬層290以及阻障層285 ’便可形成—適用於次微米技術 之雙鑲嵌結構300。 根據本發明揭示如上的製程，由於在雙鑲嵌溝渠之定 義製程中，本發明乃先定義出寬度較習知製程寬的雙鑲嵌 溝渠，其寬度可視需要加以調整，然後再利用習知的側壁415024 V. Description of the invention (6) The surface of the dielectric layer 230, and the photoresist pattern 260 does not have an etching opening 265 that is wider than the opening 245 and includes the trench 250. Similarly, the width of the etching opening 265 is larger than the width of the etching opening 165 in the conventional process. Then “Please refer to FIG. 2C, and then use the photoresist pattern 260 as an etch mask to remove the second inner metal dielectric layer 230 exposed to the opening 265 to the last etch stop layer 220” to complete a double opening with a wide opening. The trench 280 can allow a metal with better conductivity to be easily filled into the dual-mosaic trench 280 in subsequent processes. Then, a chemical vapor deposition method is first used to comprehensively form an insulating layer (not shown), such as a silicon oxide layer, on the surface of the second inner metal dielectric layer 23 and the sidewalls and bottoms of the dual damascene trenches 280, and then An anisotropic etching process removes the oxide layer on the surface of the second inner metal dielectric layer 23 and the bottom of the dual damascene trench 280 and forms an insulating sidewall 270 on the sidewall of the dual damascene trench 28. Finally, 'please refer to Figure 2D', first form a barrier layer 2 8 5 to cover the surface of the inner metal dielectric layer and the inner wall of the dual damascene etched trench 280 in conformity, and then form a metal layer 290 on the surface. On the surface of the barrier layer 285, the dual damascene trenches 280 are filled. Then, the excess metal layer 290 and the barrier layer on the surface of the second inner metal dielectric layer 23 are sequentially removed by an etch-back method or a chemical mechanical polishing method. The barrier layer 285 'can be formed—a dual damascene structure 300 suitable for sub-micron technology. According to the present invention, the above-mentioned process is disclosed. Since the dual damascene trench is defined in the process, the present invention first defines a wider width than the conventional process. Double inlaid trenches, whose width can be adjusted as needed, then using the conventional side walls
五、 子 所 尺 的 雙 之 限 和： 内 所 發明說明（7) Ϊ;二；=溝渠之内壁形成絕緣侧壁子，用： 寸縮小化而造成的對不準現象 ，鎮砍溝渠 雙鑲嵌溝渠之寬度較大，因此便可崎揭示 鑲嵌溝渠内’使此雙鎮# f金屬較易破填到此 製程。 便此雙鑲嵌結構可被應用到深次微米以下 雖然本發日月p lV , 定本發明，任付，佳只施例揭露如上，然其並非用以 苑圍内，所作二=1此技藝者，在不脫離本發明之精神 ，因此本發明之畜種更動，潤询均落在本發明之範圍 界定者為準。利保護範圍當視後附之申請專利範圍V. The sum of the doubles of the ruler: Explanation of the invention (7) Ϊ; two; = the inner wall of the trench forms an insulating side wall, and uses: The width of the ditch is relatively large, so it can be revealed that the inlaid ditch will make this double town's metal easier to fill into this process. Therefore, the dual mosaic structure can be applied to sub-micron depths. Although this issue of the sun and the moon p lV, the present invention, any payment, Jia only the example disclosed above, but it is not used in the garden, made two = 1 this artist Without departing from the spirit of the present invention, the changes in the breed of the present invention, and the inquiries that fall within the scope of the present invention shall prevail. Scope of patent protection