TW415012B - Method for manufacturing shallow trench isolation without reverse narrow channel effect - Google Patents

Abstract

In accordance with the method for manufacturing shallow trench isolation without reverse narrow channel effect, a field doped region is formed within a substrate prior to the formation of a shallow trench. The shallow trench is then formed and a portion of the filed doped region is remained beside the shallow trench. An insulating material is formed to fill the shallow trench such that the depletion region beside the shallow trench isolation is eliminated, and the reverse narrow channel effect and leakage can be removed as the doped concentration is increased.

Description

415012 五、發明說明（l) 本發明係有關於消除反窄通道效應（reverse narrow channel effect， RNCE)的淺隔離凹槽隔離（shallow trench isolation)的製造方法，特別有關於先形成場摻 植區於上述隔離凹槽的側邊來消除反窄通道效應的淺隔離 凹槽隔離的製造方法。 隨著半導體裝置的集積度不斷地提高，半導體裝置的 製程也必須要不斷地更新。舉例而言，原本在微米製程 中，用來做為隔離用途的場氧化物（field oxide)，到 了深次微米製程（0.25/zm以下）時，由於場氧化物需佔 用較大的面積’故會影響裝置的平整性。另外，在製作場 氧化物時’不可避免地會產生烏嘴效應（bird’s beak effect) ’而無論如何改變場氧化物的製程，均難以將烏 嘴兩側的長度控制至1 # m以下，結果其將會影響到製作的 準確度。所以在0. 25 /zm以下的製程，一般乃以淺隔離凹 槽隔離製程來做為主要的隔離方法。 請參照第1圖’第1圖（a )至（d )係顯示用以說明習 知淺隔離凹槽隔離的製造方法的剖面圖。習知淺隔離凹槽 隔離的製造方法包括下列步驟。 (1) 如第1圖（a)所示’於半導體基板1〇上形成襯 墊氧化物（pad oxide)層112及氮化物（nitride)層 114。 (2) 如第1圖（b)所示’藉由微影技術 (photol i thography )及蝕刻製程而於上述襯墊氧化物層 112及氮化物層114形成開口 122。415012 V. Description of the invention (l) The present invention relates to a manufacturing method of shallow trench isolation for eliminating reverse narrow channel effect (RNCE), and particularly relates to forming a field doped region first A manufacturing method of shallow isolation groove isolation on the side of the isolation groove to eliminate the anti-narrow channel effect. As the degree of integration of semiconductor devices continues to increase, the manufacturing process of semiconductor devices must also be continuously updated. For example, in the micron process, the field oxide used for isolation purposes, to the deep sub-micron process (below 0.25 / zm), because the field oxide needs to occupy a larger area, so Will affect the flatness of the device. In addition, when making field oxides, 'bird's beak effect will inevitably occur'. However, no matter how the process of field oxides is changed, it is difficult to control the length of both sides of the mouthpiece to less than 1 # m. It will affect the accuracy of production. Therefore, for processes below 0.25 / zm, the shallow isolation trench isolation process is generally used as the main isolation method. Please refer to Fig. 1 '. Figs. 1 (a) to (d) are cross-sectional views for explaining a conventional manufacturing method of shallow isolation groove isolation. The conventional shallow isolation groove isolation manufacturing method includes the following steps. (1) As shown in FIG. 1 (a), a pad oxide layer 112 and a nitride layer 114 are formed on a semiconductor substrate 10. (2) As shown in FIG. 1 (b) ', an opening 122 is formed in the pad oxide layer 112 and the nitride layer 114 by a photolithography technique and an etching process.

_ 415012 五、發明說明（2) (3 )如第1圖（c )所示，藉由非等向性蝕刻，而於 上述半導體基板10形成貫穿上述氮化物層114及襯墊氧化 物層112的隔離凹槽132。 (4)如第1圖（d)所示，首先，沈積氧化物於上述 隔離凹槽132及氮化物層114上，然後以回蝕刻（etch back)或化學機械研磨（chemical Mechanical Polish) 來去除上述氮化物層114上的氧化物，而於上述隔離凹槽 132内形成隔離氧化物142。然後，蝕刻去除上述氮化物層 114及襯墊氧化物層112。 然而’在上述的例子中，由於非等向性（乾式）蝕刻 的界定步驟會在隔離凹槽132與半導體基板10的接面（尤 其疋在隔離凹槽132的側邊）造成晶隙性（interstitial )缺陷’因此當進行通道離子植入及隨後的回火（Anneal )製程而形成例如NM〇s電晶體時，植入通道區的硼離子 (Boron)便會重新分佈（Redistributi〇n)，朝半導體 基板10與隔離氧化物142的接面擴散。因此，半導體元件 (例如NM0S電晶體）便會在通道中央具有較高的摻植濃 度’而在通道邊緣具有較低的摻植濃度。再者，這種硼離 子的分佈亦會導致反窄通道效應（RNCE )，使半導體元件 (例如NM0S電晶體）的臨界電壓（Vth)下降a 另外’由於爛離子會因擴散效應而穿透至隔離凹槽 132與半導體基板1〇的接面，而形成空乏區，因此隨後形 成的電晶體70件（例如NM0S電晶體）亦會出現漏電流的問 題。_ 415012 V. Description of the invention (2) (3) As shown in FIG. 1 (c), the semiconductor substrate 10 is formed through the nitride layer 114 and the pad oxide layer 112 through anisotropic etching.的 离 槽 132。 The isolation groove 132. (4) As shown in FIG. 1 (d), firstly, an oxide is deposited on the isolation groove 132 and the nitride layer 114, and then removed by etch back or chemical mechanical polishing. An oxide on the nitride layer 114 forms an isolation oxide 142 in the isolation groove 132. Then, the nitride layer 114 and the pad oxide layer 112 are removed by etching. However, in the above example, the step of defining anisotropic (dry) etching will cause intergranularity at the interface between the isolation groove 132 and the semiconductor substrate 10 (especially at the side of the isolation groove 132) ( interstitial) defects'. Therefore, when channel ion implantation and subsequent Anneal process are performed to form, for example, NMOS transistors, boron ions implanted in the channel region will be redistributed (Redistribution). Diffusion toward the interface between the semiconductor substrate 10 and the isolation oxide 142. Therefore, semiconductor devices (such as NMOS transistors) will have a higher doping concentration ' in the center of the channel and a lower doping concentration at the edge of the channel. In addition, this distribution of boron ions will also cause an inverse narrow channel effect (RNCE), which will reduce the critical voltage (Vth) of semiconductor elements (such as NMOS transistors) a. In addition, 'the rotten ions will penetrate to the The interface between the isolation groove 132 and the semiconductor substrate 10 forms a vacant region. Therefore, 70 transistors (such as NMOS transistors) formed later will also have a problem of leakage current.

415012 五'發明說明（3) 第2圖便是反窄通道效應的示意圖。於此圖中，半導 體基板20具有淺隔離凹槽隔離區22、24，用以界定半導體 元件（例如NMOS電晶體）的範圍。複晶矽閘極26則形成於 淺隔離凹槽隔離區22、24之間，用以構成半導體元件（例 如關〇S電晶體）。當半導體元件進行通道區離子植入時， 硼離子會因複晶矽間極26的形狀而聚集在複晶矽閉極26兩 側。另外，植入通道區的硼離子亦會因回火製程或立他高 溫製程而擴散至半導體基板20及淺隔離凹槽隔離22 了 24的 接面而形成空乏區。因此，半導體元件（例如nm〇S電晶 體）的通道便會變窄，使臨界電壓（vth)亦隨之下降。 請參考第3圖（a)及第3圖（b)，其分別顯示第2圖 A-A’剖面及B-B’剖面的硼離子濃度分佈圖。圈中，硼離子 會因複晶矽閘極26的形狀而聚集在複晶矽閘極26兩側的淡 摻植源/汲極區28。另外，通道邊緣（β_Β，）的硼離子濃 度則會因擴散效應而低於通道中央（Α_Α，）的硼離子濃 度。 / 有鑑於此，本發明之目的係為了解決上述問題而提供 一種j除反窄通道效應的淺隔離凹槽隔離的製造方法，適 用於半導體基板，且上述製造方法包括下列步驟：於上述 半導體基板上形成遮蔽層，且上述遮蔽層形成有開口，以 界定出上述隔離凹槽的範圍；以上述遮蔽層為罩幕，經由 ^述開口而摻植雜質至上述半導體基板，以形成場摻植 區’以上述遮蔽層為罩幕’經由上述開口而對上述半導體 基板施行蝕刻，以形成隔離凹槽，同時上述場摻植區的剩415012 Five 'invention description (3) Figure 2 is a schematic diagram of the anti-narrow channel effect. In this figure, the semiconductor substrate 20 has shallow isolation groove isolation regions 22, 24 to define a range of semiconductor elements (such as NMOS transistors). The complex silicon gate 26 is formed between the shallow isolation groove isolation regions 22 and 24 to form a semiconductor element (such as a transistor). When the semiconductor device is ion-implanted in the channel region, boron ions are collected on both sides of the closed-crystal silicon 26 due to the shape of the closed-crystal silicon 26. In addition, the boron ions implanted in the channel region will also diffuse to the semiconductor substrate 20 and the shallow isolation groove to isolate the interface between the substrate 24 and the substrate 24 due to the tempering process or the high-temperature process. Therefore, the channel of a semiconductor device (such as a nmOS crystal) becomes narrower, and the threshold voltage (vth) also decreases accordingly. Please refer to Fig. 3 (a) and Fig. 3 (b), which show the boron ion concentration distribution diagrams of the A-A 'section and the B-B' section of Fig. 2, respectively. In the circle, boron ions will be concentrated on the lightly doped source / drain regions 28 on both sides of the polycrystalline silicon gate 26 due to the shape of the polycrystalline silicon gate 26. In addition, the boron ion concentration at the channel edge (β_Β,) will be lower than the boron ion concentration at the channel center (Α_Α,) due to the diffusion effect. In view of this, an object of the present invention is to provide a manufacturing method for shallow isolation groove isolation in addition to an anti-narrow channel effect in order to solve the above problem, which is suitable for a semiconductor substrate, and the manufacturing method includes the following steps: A masking layer is formed on the masking layer, and the masking layer is formed with an opening to define the range of the isolation groove. The masking layer is used as a mask, and impurities are implanted into the semiconductor substrate through the opening to form a field doped region. 'Take the shielding layer as a mask' to etch the semiconductor substrate through the opening to form an isolation groove, and at the same time, the remaining portion of the field doped region is etched.

第6頁 415012 五、發明說明（4) 餘部份留於上述隔離凹槽的侧邊；以及於上述隔離凹槽形 成絕緣物。 其中，上述雜質為硼或銦離子。且上述隔離凹槽較上 述場捧植區深，而使上述場播植區的剩餘部份留於上述隔 離凹槽的側邊。又上述場摻植區的形成方法係於摻植上述 雜質至上述半導體基板後，更包括驅入的步驟。再者，上 述遮蔽層係由形成於上述半導體基板上的襯墊氧化物層及 形成於上述襯墊氧化物層上的氮化物層所構成。此外，上 述絕緣物為氧化物。尚且更包括去除上述遮蔽層的步驟。 依據本發明之消除反窄通道效應的淺隔離凹槽隔離的 製造方法，由於形成隔離凹槽之前，先形成場摻植區，接 著形成隔離凹槽’同時上述場摻植區的剩餘部份留於上述 隔離凹槽的侧邊，然後於上述隔離凹槽形成絕緣物，故可 消除位於上述隔離凹槽側邊的空乏區，且增加此處的雜質 濃度，而可消除反窄通道效應及漏電現象。 ^為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉較佳實施例’並配合所附圖式，作詳細說明 如下：Page 6 415012 V. Description of the invention (4) The remainder is left on the side of the above isolation groove; and an insulation is formed in the above isolation groove. The impurities are boron or indium ions. And the above-mentioned isolation groove is deeper than the above-mentioned field planting area, so that the remaining portion of the above-mentioned field planting area is left on the side of the above-mentioned isolation groove. Furthermore, the method for forming the field doped region is based on doping the impurity onto the semiconductor substrate, and further includes a driving step. The shielding layer is composed of a pad oxide layer formed on the semiconductor substrate and a nitride layer formed on the pad oxide layer. The insulator is an oxide. The method further includes the step of removing the shielding layer. According to the manufacturing method of the shallow isolation groove isolation for eliminating the anti-narrow channel effect according to the present invention, before forming the isolation groove, a field doped region is formed first, and then an isolation groove is formed, while the remaining portion of the field doped region is left. An insulator is formed on the side of the isolation groove, and then an empty area is formed on the side of the isolation groove. Therefore, the impurity concentration here can be increased, and the anti-narrow channel effect and leakage can be eliminated. phenomenon. ^ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, hereinafter, “the preferred embodiments are enumerated” and the accompanying drawings are described in detail as follows:

圖 H ^ 1 is ( \ _ A 、a J至（d )係顯示用以說明習知淺隔離凹槽 隔離=製造方法的剖面圖； 第^圖係顯示用以說明反窄通道效應的立體示意圖； ^ ^圖（a )及（b )係分別顯示第2圖A-A’剖面及B-B’ 剖面的硼離+普ώ 雕于濃度分佈圖；以及Figure H ^ 1 is (\ _ A, a J to (d) is a cross-sectional view used to explain the conventional shallow isolation groove isolation = manufacturing method; Figure ^ is a three-dimensional schematic diagram used to explain the anti-narrow channel effect ; ^ ^ (A) and (b) are the concentration distribution diagrams showing the boron ionization and general sales on the A-A 'section and B-B' section of Fig. 2, respectively; and

415012 五、發明說明（5) 第4圖（a )至（f )係顯示用以說明本發明之消除反 窄通道效應的淺隔離凹槽隔離的製造方法的剖面圖。 〔符號說明〕 10、20、40〜半導體基板；112 '412〜襯墊氧化物 層；114、414〜氮化物層；122、42〜開口； 132 '452〜 隔離凹槽；142〜隔離氧化物；22、24〜淺隔離凹槽隔離 區；26〜複晶矽閘極；28〜淡摻植源/汲極區；41〜遮蔽 層；432〜淺場摻植區；442〜場摻植區；462〜絕緣物。 實施例 請參照第4圖（a )至（f )，第4圖（a )至（f )係顯 示用以說明本發明之消除反窄通道效應的淺隔離凹槽隔離 的製造方法的剖面圖。本發明之消除反窄通道效應的淺隔 離凹槽隔離的製造方法係適用於半導體基板40，且上述製 造方法包括下列步驟^ 步驟一 如第4圖（a)及（b)所示，於上述半導體基板40上 形成遮蔽層41，且上述遮蔽層41形成有開口 42，以界定出 隔離凹槽的範圍。 例如，如第4圖（a)所示，首先於半導體基板4〇上可 藉由熱氧化來形成襯墊氧化物（pad oxide)層412以及沈 積氮化物（nitride)層414於上述襯墊氧化物層412，以 形成上述遮蔽層41。然後，如第4圖（b)所示，藉由微影 技術（photol i thography )及蝕刻製程而於上述氮化物層 414形成開口 42，而可保留襯墊氧化物層412。415012 V. Description of the invention (5) Figures 4 (a) to (f) are cross-sectional views showing the manufacturing method of the shallow isolation groove isolation for eliminating the reverse narrow channel effect of the present invention. [Explanation of symbols] 10, 20, 40 ~ semiconductor substrate; 112'412 ~ pad oxide layer; 114, 414 ~ nitride layer; 122, 42 ~ opening; 132'452 ~ isolation groove; 142 ~ isolation oxide 22, 24 ~ shallow isolation groove isolation area; 26 ~ complex silicon gate; 28 ~ lightly doped source / drain area; 41 ~ shielding layer; 432 ~ shallow field doped area; 442 ~ field doped area 462 ~ insulator. Please refer to FIGS. 4 (a) to (f) for the embodiment. FIGS. 4 (a) to (f) are cross-sectional views showing a method for manufacturing a shallow isolation groove isolation for eliminating the anti-narrow channel effect of the present invention. . The manufacturing method of the shallow isolation groove isolation for eliminating the anti-narrow channel effect of the present invention is applicable to the semiconductor substrate 40, and the above-mentioned manufacturing method includes the following steps ^ The steps are as shown in FIG. 4 (a) and (b), as described above A shielding layer 41 is formed on the semiconductor substrate 40, and the shielding layer 41 is formed with an opening 42 to define a range of the isolation groove. For example, as shown in FIG. 4 (a), firstly, a pad oxide layer 412 and a deposited nitride layer 414 may be formed on the semiconductor substrate 40 by thermal oxidation to oxidize the pad. The object layer 412 forms the above-mentioned shielding layer 41. Then, as shown in FIG. 4 (b), an opening 42 is formed in the nitride layer 414 through photolithography and an etching process, and the pad oxide layer 412 can be retained.

415012 五、發明說明（6) 步驟二 如=4圖（c)及（d)所示，以上述遮蔽層41為軍 述開口42而摻植雜質至上述半導體基板40，以 形成％摻植區442。 例如首第‘圖（c)所示，離子植入蝴或銅離 子至上述半導體基板4〇，而形成淺場摻植區如。然後， 如第4圖（d)所示，施行熱驅入（drive_in)，而形成上 述場捧植區4 4 2。 步驟三 如第4圖（e)所示，以上述遮蔽層41為罩幕，經由上 述開口42而對上述半導體基板4〇施行姓刻，以形成隔離凹 槽452 ’同時上述場摻植區442的剩餘部份留於上述隔離凹 槽452的侧邊。亦即，使上述隔離凹槽452較上述場摻植區 442 深。 例如’以上述遮蔽層41為罩幕，並藉由非等向性蝕刻 (乾式钮刻），而於上述半導體基板40形成上述隔離凹槽 452 ’同時使上述場掺植區442的剩餘部份留於上述隔離凹 槽452的側邊。 步驟四 如第4圖（f)所示，於上述隔離凹槽452形成絕緣物 462。 例如’首先’沈積氧化物於上述隔離凹槽452及氮化 物層414上’然後以回钱刻（etch back)或化學機械研磨 (Chemical Mechanical Polish)來去除上述氮化物層415012 V. Description of the invention (6) Step 2 As shown in Figures 4 (c) and (d), the above-mentioned shielding layer 41 is used as the military opening 42 and impurities are implanted into the above-mentioned semiconductor substrate 40 to form a% -doped region. 442. For example, as shown in the first figure (c), ion implantation of butterfly or copper ions into the above semiconductor substrate 40 forms a shallow-field doped region such as that shown in FIG. Then, as shown in FIG. 4 (d), a thermal drive (in_drive) is performed to form the field planting area 4 4 2. Step 3, as shown in FIG. 4 (e), using the shielding layer 41 as a mask, and engraving the semiconductor substrate 40 through the opening 42 to form an isolation groove 452 ′ and the field doped region 442. The remaining portion is left on the side of the isolation groove 452. That is, the isolation groove 452 is made deeper than the field implanted region 442. For example, 'the shielding layer 41 is used as a mask and the isolating groove 452 is formed on the semiconductor substrate 40 by anisotropic etching (dry button engraving)' while the remaining portion of the field implanted region 442 is formed It stays on the side of the above-mentioned isolation groove 452. Step 4 As shown in FIG. 4 (f), an insulator 462 is formed in the isolation groove 452. For example, "first" deposit an oxide on the isolation groove 452 and the nitride layer 414, and then remove the nitride layer by etch back or chemical mechanical polishing.

415012 五、發明說明（7) 414上的氧化物，而於上述隔離凹槽452内形成上述絕緣物 4 62。然後，蝕刻去除上述氮化物層414及襯墊氧化物層 412 〇 如上 凹槽隔離 摻植區， 份留於上 緣物，故 此處的雜 雖然 限定本發 神和範圍 當視後附 所述， 的製造 接著形 述隔離 可消除 質濃度 本發明 明，任 内，當 之申請 依據本發 方法，由 成隔離凹 凹槽的側 位於上述 ，而可消 已以較佳 何熟習此 可作更動 專利範圍 於形成隔 槽，同時 邊，然後 隔離凹槽 除反窄通 實施例揭 項技藝者 與潤娜， 所界定者 離凹槽之前 上述場摻植 於上述隔離 側邊的空乏 道效應及漏 露如上，然 ’在不脫離 因此本發明 為準。 應的淺隔離 ，先形成場 區的剩餘部 凹槽形成絕 區，且增加 電現象^ 其並非用以 本發明之精 之保護範圍415012 V. Description of the invention (7) The oxide on 414 forms the insulator 4 62 in the isolation groove 452. Then, the nitride layer 414 and the pad oxide layer 412 are removed by etching, as described above. The grooves isolate the implanted area as above, and remain in the upper edge. The manufacturing process is followed by the description of isolation to eliminate the mass concentration. The present invention states that when the application is based on the method of the present invention, the side of the isolation recess is located above, but it can be used to modify the scope of the patent. In the formation of the separation grooves, the sides are then separated, and the isolation groove is removed. In addition, the artist and Run Na are exposed in the embodiment. The defined field is embedded in the above-mentioned isolation side, and the leakage is as above. However, the present invention shall prevail without departing from it. Should be shallow isolation, the remaining part of the field area is formed first, the grooves form an insulation area, and the electrical phenomenon is increased ^ It is not used to protect the scope of the invention

Claims (1)

415012 六、申請專利範圍-- 1. 種/肖除反窄通道效應的淺隔離凹槽隔離的製造方 法適用於半導體基板，且上述製造方法包括下列步驟： 於上述半導體基板上形成遮蔽層，且上述遮蔽層形成 有開口，以界定出上述隔離凹槽的範圍； 以上述遮蔽層為罩幕，經由上述開口而摻植雜質至上 述半導體基板’以形成場掺植區； 以上述遮蔽層為罩幕，經由上述開口而對上述半導體 基板施行蝕刻，以形成隔離凹槽，同時上述場摻植區的剩 餘部伤留於上述隔離凹槽的側邊；以及 於上述隔離凹槽形成絕緣物。 2. 如申請專利範圍第丨項所述的消除反窄通道效應的 淺隔離凹槽隔離的製造方法，其中上述雜質為硼離子。 3·如申請專利範圍第丨項所述的消除反窄通道效應的 淺隔離凹槽隔離的製造方法，其中上述雜質為銦。 4.如申請專利範圍第1、2或3項所述的消除反窄通道 效應的淺隔離凹槽隔離的製造方法，其中上述隔離凹槽較 上述場掺植區深’而使上述場摻植區的剩餘部份留於上述 隔離凹槽的側邊。 5·如申請專利範圍第4項所述的消除反窄通道效應的 淺隔離凹槽隔離的製造方法，其中上述場摻植區的形成方 法係於摻植上述雜質至上述半導體基板後，更包括驅入的 步驟。 6,如申請專利範圍第5項所述的消除反窄通道效應的 淺隔離凹槽隔離的製造方法，其中上述遮蔽層係由形成於415012 6. Scope of patent application-1. The manufacturing method of the shallow isolation groove isolation method that eliminates the anti-narrow channel effect is applicable to semiconductor substrates, and the above manufacturing method includes the following steps: forming a shielding layer on the above semiconductor substrate, and The shielding layer is formed with an opening to define the range of the isolation groove. The shielding layer is used as a mask, and impurities are implanted into the semiconductor substrate through the opening to form a field doped region. The shielding layer is used as a mask. The semiconductor substrate is etched through the opening to form an isolation groove, and at the same time, the remaining portion of the field doped region remains on the side of the isolation groove; and an insulator is formed in the isolation groove. 2. The manufacturing method of shallow isolation groove isolation to eliminate the anti-narrow channel effect according to item 丨 of the patent application scope, wherein the impurity is boron ion. 3. The manufacturing method of shallow isolation groove isolation to eliminate the anti-narrow channel effect according to item 丨 of the patent application scope, wherein the impurity is indium. 4. The manufacturing method of shallow isolation groove isolation to eliminate the anti-narrow channel effect according to item 1, 2, or 3 of the scope of the patent application, wherein the isolation groove is deeper than the field implantation region, and the field is implanted. The rest of the area is left on the side of the isolation groove. 5. The manufacturing method of shallow isolation groove isolation to eliminate the anti-narrow channel effect as described in item 4 of the scope of the patent application, wherein the method of forming the field doped region is after doping the impurity onto the semiconductor substrate, further including Drive-in steps. 6. The manufacturing method of shallow isolation groove isolation to eliminate the anti-narrow channel effect according to item 5 of the scope of patent application, wherein the above-mentioned shielding layer is formed by 4UQ12 六、申請專利範圍 上述半導體基板上的襯墊氣化物層及形成於上述襯墊氧化 物層上的氮化物層所構成。 7 ·如申請專利範圍第6 述的消除反窄通道效應的 淺隔離^ ^ 僧離的製造方法，其中上述絕緣物為氧化物^ 8，如申請專利範圍第7項所述的消除反窄通道效應的 隔離凹槽隔離的製造方法，其中更包括去除上述遮蔽層 的步驟。 ”4UQ12 VI. Scope of patent application Consists of a pad gasification layer on the semiconductor substrate and a nitride layer formed on the pad oxide layer. 7 · The shallow isolation method for eliminating the anti-narrow channel effect as described in the scope of the patent application No. 6 ^ ^ The manufacturing method of the monk's separation, wherein the insulator is an oxide ^ 8, the anti-narrow channel is eliminated as described in the scope of the patent application No. 7 The manufacturing method of the effect isolation groove isolation further includes a step of removing the shielding layer. "