TW413889B

TW413889B - Transistor structure using bipolar junction transistor to avoid antenna effect and manufacturing method

Info

Publication number: TW413889B
Application number: TW88110724A
Authority: TW
Inventors: Jiau-Ren Shr; Suei-Hung Chen; Jian-Shing Li; Chung-Rung Lin
Original assignee: Taiwan Semiconductor Mfg
Priority date: 1999-06-25
Filing date: 1999-06-25
Publication date: 2000-12-01

Abstract

There is disclosed a transistor structure using bipolar junction transistor to avoid antenna effect, which comprises: a MOS transistor with a gate structure configured on a semiconductor substrate; a bipolar junction transistor whose emitter is connected with the gate structure of the MOS transistor; and a diffusion region which electrically contacts with the collector of the bipolar junction transistor. The manufacturing method comprises the following steps: forming a first MOS transistor, a first bipolar junction transistor, a first diffusion region, a second MOS transistor, a second bipolar junction transistor, and a second diffusion region on a semiconductor substrate respectively; forming an inter-dielectric layer with a plurality of openings on the surface of the semiconductor substrate so that the emitters of the first and the second bipolar junction transistors are electrically connected with the gate structure through those openings, and the collectors of the first and the second bipolar junction transistors are electrically connected with the ion diffusion region.

Description

413889 五、發明說明（1) 本發明係有關於一種半導體積體電路之製造方法及其構造’且特別是有關於一種能夠避免因為天線效應 (antenna effect)所造成的電流破壞積體電路之雙載子電晶體之製造方法及其構造。在此，請參考第1圖’以詳細說明因天線效應所造成之電流破壞積體電路之示意圖；如第1圖所示，於該半導體積體電路中具有一半導體基板10，以及用以定義出元件之主動區域的場氧化層FOX，在場氧化層fox間，則存在一閘極絕緣層12覆蓋在該半導體基板1〇之表面，而在該閘極絕緣層1 2上則形成一電晶體之閘極1 4，以及複數層經定義過圖案之導電層16，用以作為該半導體積體電路之金屬内連線。在此需注意的是，該導電層1 6是以一經定義過圖案之光阻層（未標示於圖中）為罩幕，經乾蝕刻（dry etching)而形成；而以目前之技術言之，此步驟係利用電漿蝕刻法，亦即利用外加之高電壓使得原本中性之氣體分子被激發或解離成帶電之離子使直接撞擊該導電層16之表面而完成其蝕刻之過程D因此，當導電層丨6蝕刻至終點附近時，電漿中之帶電離子便會經由該導電層16所暴露出來的侧邊表面而流至該電晶體閘極丨4及閘極絕緣層丨2 ;而此時之導電層16係非常類似於一個天線接收器，故之「天線效應」。豕邊此外，由於外加之高電壓使得大量電流隨之產生，以流進該電晶體之閘極丨4與閘極絕緣層丨2之電流量更大，413889 V. Description of the invention (1) The present invention relates to a manufacturing method and structure of a semiconductor integrated circuit ', and in particular to a pair of circuits capable of avoiding damage to the integrated circuit due to a current caused by an antenna effect. Manufacturing method and structure of carrier transistor. Here, please refer to FIG. 1 'for a detailed description of the current-damaged integrated circuit caused by the antenna effect. As shown in FIG. 1, there is a semiconductor substrate 10 in the semiconductor integrated circuit, and is used to define A field oxide layer FOX out of the active area of the device. Between the field oxide layer fox, a gate insulating layer 12 is covered on the surface of the semiconductor substrate 10, and an electrical layer is formed on the gate insulating layer 12 The gates 14 of the crystal and a plurality of conductive layers 16 having a defined pattern are used as metal interconnections of the semiconductor integrated circuit. It should be noted here that the conductive layer 16 is formed by using a photoresist layer (not shown in the figure) with a defined pattern as a mask and dry etching. According to the current technology, This step is a plasma etching method, that is, the use of an external high voltage to make the original neutral gas molecules be excited or dissociated into charged ions and directly hit the surface of the conductive layer 16 to complete its etching process D. Therefore, When the conductive layer 6 is etched near the end point, the charged ions in the plasma will flow to the transistor gate 4 and the gate insulation layer 2 through the side surface exposed by the conductive layer 16; and The conductive layer 16 at this time is very similar to an antenna receiver, hence the "antenna effect". In addition, due to the high voltage applied, a large amount of current is generated, so that the current flowing into the gate of the transistor and the gate insulation layer of the transistor are larger.

4X3889 五、發明說明（2) 因而造成該電晶體之閘極絕緣層1 2被流過之電流破壞’進而影響電晶體的品質。因此，為了解決天線效應對半導體積體電路所造成的嚴重破壞，習知之方法係為在原來之半導體積體電路之閘-極處再外接一個反偏P/N二極體18接面之路徑；由於P/N二極想18接面之崩潰電壓較電晶體之崩潰電壓要小，因此當進行蝕刻之步驟時，此P/N接面便可以提供該天線電流一個放電的路徑’所以大量的電流不會流進該半導體積體電路之閘極’藉以達到保護該閘極及其氧化層之目的。然而，在這個日新月異的時代，隨著製程技術的提升’電晶體的體積亦隨之下降，因此P/N接面二極體之崩清電壓會逐漸變低’而無可避免的是漏電流的上升；並且’ P/N接面二極體之崩潰電壓無法隨著蝕刻機台之電漿性質作調整，亦成為其缺點之一。有鑑於此，本發明之主要目的在於提供一種能夠避免半導體積體電路之閘極受到天線電流破壞的結構及其製造 =法，其不會使漏電流增加，也可藉由調整雙載子接面電 b曰體之基極（base)寬度與離子之濃度來配合不同的電漿蝕刻機台。電晶損壞上，係與為了達到本發明之主要目體之結構，用於保護一閘，包括一雙載子接面電晶該雙載子接面電晶體具有該閘極結構做電性連接；的，係提供一種雙載子接面極結構使其免受天線電流之體，設置於一半導體基板之一射極和一集極，且該射極以及一擴散區，係與該雙載4X3889 V. Description of the invention (2) As a result, the gate insulating layer 12 of the transistor is damaged by the current flowing therethrough, thereby affecting the quality of the transistor. Therefore, in order to solve the serious damage caused by the antenna effect on the semiconductor integrated circuit, the conventional method is to connect a reverse-biased P / N diode 18 junction path at the gate-pole of the original semiconductor integrated circuit. ; Because the breakdown voltage of the P / N two-pole junction 18 is smaller than the breakdown voltage of the transistor, when the etching step is performed, this P / N junction can provide a discharge path for the antenna current. The current will not flow into the gate of the semiconductor integrated circuit to protect the gate and its oxide layer. However, in this rapidly changing era, with the improvement of process technology, the volume of the transistor will also decrease, so the breakdown voltage of the P / N junction diode will gradually decrease, and inevitably the leakage current And the breakdown voltage of the 'P / N junction diode cannot be adjusted with the plasma properties of the etching machine, which has also become one of its disadvantages. In view of this, the main object of the present invention is to provide a structure capable of preventing the gate of a semiconductor integrated circuit from being damaged by antenna current, and a manufacturing method thereof, which does not increase the leakage current, and can also adjust the double-carrier connection Surface electricity b refers to the body's base width and ion concentration to match different plasma etching machines. The transistor damage is related to the structure for achieving the main purpose of the present invention, and is used to protect a gate, including a bipolar junction transistor, which has the gate structure for electrical connection. ; Is to provide a dual carrier junction electrode structure to protect it from antenna current, which is arranged on an emitter and a collector of a semiconductor substrate, and the emitter and a diffusion region are related to the dual carrier

413889 五、發明說明（3) 子接面電晶體之集極做電性接觸。而該種以雙載子接面電晶體避免天線效應之電晶體結構之製造方法’係適用於一半導體基板上，包括下列步驟··於該半導體基板上形成一具有第一型離子之導電層；定義此導電層之圖案，並於該導電層之部分位置濃摻雜入第二型離子以於半導體基板上形成一第一、第二閘極結構以及一具有第一型離子與一具有第二型離子之島狀結構；植入第二型離子至該第一閘極結構兩側下方之半導韹基板中、具有第一型離子之島狀結構、及該具有第一型離子之島狀結構側下方之該半導體基板中以形成第一MOS電晶體、第一雙載子接面電晶體、以及第一擴散區；植入第一型離子至第二閘極結構兩侧下方之半導體基板中、具有第二型離子之島狀結構、及具有第二型離子之島狀結構側下方之半導體基板中以形成第二 MOS電晶體、第二雙載子接面電晶體、以及第二擴散區·，於半導體基板之表面形成一内層介電層，並於該内層介電層中分別形成複數個開口以分別露出第一、第二閘極結構’第一、第二雙載子接面電晶體之射極與第一、第二雙載子接面電晶體之集極與第一、第二擴散區之表面；以及透過該等開口形成導電層，而於第一開口與第二開口間形成一金屬内連線，且於該等第三開口中形成一金屬栓以作為一接觸區’以使第一、第二雙載子接面電晶體之射極與閘極結構作電性連接，以及第一、第二雙載子接面電晶體之集極與離子擴散區做電性連接。為讓本發明之上述目的、特徵、和優點能更明顯易413889 V. Description of the invention (3) The collector of the junction junction transistor is in electrical contact. The manufacturing method of the transistor structure using a bipolar junction transistor to avoid antenna effect is applicable to a semiconductor substrate, and includes the following steps: forming a conductive layer with a first type ion on the semiconductor substrate ; Define the pattern of this conductive layer, and dopantly doped the second type ions at a part of the conductive layer to form a first and second gate structure on the semiconductor substrate and a first type ion and a first type ion Island type structure of type 2 ions; second type ions are implanted into the semiconducting substrate on both sides of the first gate structure, an island type structure having the first type ions, and an island having the first type ions A first MOS transistor, a first bipolar junction transistor, and a first diffusion region are formed in the semiconductor substrate below the structure-like side; a first type ion is implanted into the semiconductor below the sides of the second gate structure A second MOS transistor, a second bipolar junction transistor, and a second MOS transistor, a second ambiode junction transistor, and a second semiconductor substrate under the island structure having the second type ions are formed in the substrate. In the scattered region, an inner dielectric layer is formed on the surface of the semiconductor substrate, and a plurality of openings are formed in the inner dielectric layer to expose the first and second gate structures, respectively, and the first and second bipolar junctions. The emitter of the surface transistor is connected to the surfaces of the collector of the surface transistor and the first and second diffusion regions; and a conductive layer is formed through the openings, and the first opening and the second A metal interconnect is formed between the openings, and a metal plug is formed in the third openings as a contact area to enable the emitter and gate structures of the first and second bipolar junction transistors to be electrically connected. Sexual connection, and the collectors of the first and second bipolar junction transistors are electrically connected to the ion diffusion region. In order to make the above objects, features, and advantages of the present invention more obvious and easier

第6頁 413889 五、發明說明（4) 僅下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：圖式之簡單說明：第1圖顯示因餘刻金屬而產生天線效應之示意圖；第2圖顯示習知之加入P/N二極體以避免天線效應而保護半導體積體電路之閘極之示意圖；以及第3A〜3L圖顯示依據本發明之避免電流破壞積體電路之雙載子接面電晶體之製造流程剖面圖。符號說明島狀結構 Gl、G2閘極光阻層 N型/P型離子浃摻雜區域 S / D源/汲極 10、30矽基板 U閘電極 18二極體 31閘極絕緣層 33a ' 33b PR1-PR3 N'/P-34 絕緣間隔物 12 閘極絕緣層 16 導電層 STI淺溝槽隔離區 32 導電層 E 射極 B基極 C 集極 N+ N型離子濃摻雜區 P+ P型離子濃摻雜區 35a NPN雙載子接面電晶體 35b PNP雙載子接面電晶體 38a、38b 第二開口 Ml a、37lb金屬内連線 36 内層介電層 3 7a、3 7b 第一開 t? 39a、39b 第三開口Page 6 413889 V. Description of the invention (4) Only a preferred embodiment is given below, and in conjunction with the attached drawings, the detailed description is as follows: Brief description of the drawings: Fig. 1 shows the antenna generated by the metal etched away. Schematic diagram of the effect; FIG. 2 shows a conventional schematic diagram of a gate of a semiconductor integrated circuit which is protected by adding P / N diodes to avoid antenna effects; and FIGS. 3A to 3L show the avoidance of current damage to the integrated circuit according to the invention A cross-sectional view of the manufacturing process of a bipolar junction transistor. Symbol description Island structure G1, G2 Gate photoresistive layer N-type / P-type erbium-doped region S / D source / drain 10, 30 Silicon substrate U gate electrode 18 Diode 31 Gate insulating layer 33a '33b PR1 -PR3 N '/ P-34 insulating spacer 12 gate insulating layer 16 conductive layer STI shallow trench isolation region 32 conductive layer E emitter B base C collector N + N-type ion heavily doped region P + P-type ion concentration Doped region 35a NPN junction junction transistor 35b PNP junction junction transistor 38a, 38b Second opening Mla, 37lb Metal interconnect 36 Inner dielectric layer 3 7a, 3 7b First opening t? 39a, 39b Third opening

413889 五、發明說明（5) 391a、391b金屬栓實施例在此’請參考第3A〜3K圖所示之流程剖面圖，以更具體地瞭解依據本發明之避免電流破壞積體電路之雙載子接_ 面電晶體之製造方法及其裝置之較佳實施例。請參考第3A-3C圖，係提供一半導體基板，並於該半導體基板上形成一具有第一型離子之導電層；例如，先在石夕基板30上形成隔離用之淺溝槽隔離區（shaH〇w trench413889 V. Description of the invention (5) Examples of 391a, 391b metal bolts are here. 'Please refer to the cross-sectional view of the flow chart shown in Figures 3A to 3K for a more specific understanding of the double load of the integrated circuit according to the present invention to avoid current damage. A preferred embodiment of a method and device for manufacturing a sub-connected surface transistor. Please refer to FIGS. 3A-3C, a semiconductor substrate is provided, and a conductive layer having a first type ion is formed on the semiconductor substrate; for example, a shallow trench isolation region for isolation is first formed on the Shixi substrate 30 ( shaH〇w trench

isolation)STI 以界定出元件區（active region)，如第3A 圖所示；接著’請參考第3B圖，以化學氣相沈積法 (Chemical Vapor Deposition，CVD)在該矽基板 30 之表面依序沈積一層閘極絕緣層，例如是二氧化矽層3丨，以及一層導電層，例如是複晶矽層32 ’；最後，如第3C圖所示，植入第一型離子，例如是p型離子，至複晶矽層32中。接下來，定義該導電層之圖案，並於部分導電層中濃摻雜入第二型離子以於該半導體基板上形成一第一、第二閘極結構以及一具有第一型離子以及一具有第二型離子之島狀結構；例如’如第3D圖所示，係利用光學微影術 (Photolithography)以及蝕刻製程（etching),定義該複晶石夕層32以及該二氧化矽層31之圖案，而在該矽基板3〇之表面形成一閘極結構G1、G2以及一島狀結構33a、33b ;接著’請參考第3E圖’定義一光阻層PRi，使露出島狀結構 3 3b表面，其次，以光阻層ΡΙη為遮蔽層，濃摻雜入n型離子至該具有P型離子之島狀結構3 3t)中而形成一具有1^型離isolation) STI to define the active region, as shown in Figure 3A; then 'Please refer to Figure 3B, in order to chemical vapor deposition method (Chemical Vapor Deposition (CVD) on the surface of the silicon substrate 30 Deposit a gate insulating layer, such as a silicon dioxide layer 3 丨, and a conductive layer, such as a polycrystalline silicon layer 32 ′; Finally, as shown in FIG. 3C, a first type ion is implanted, such as a p-type Ions, into the polycrystalline silicon layer 32. Next, a pattern of the conductive layer is defined, and a part of the conductive layer is heavily doped with second-type ions to form a first and second gate structure and a first-type ion and a first-type ion on the semiconductor substrate. The island structure of the second type ion; for example, 'as shown in FIG. 3D, the photolithography and etching process are used to define the polycrystalline stone layer 32 and the silicon dioxide layer 31. Pattern, and a gate structure G1, G2, and an island structure 33a, 33b are formed on the surface of the silicon substrate 30; then, 'Please refer to FIG. 3E' to define a photoresist layer PRi to expose the island structure 3 3b On the surface, the photoresist layer PIη is used as a shielding layer, and n-type ions are strongly doped into the island structure 3 3t) having P-type ions to form a 1 ^ -type ion.

413889413889

子之島狀結構33b » 之後’可選擇是否形成淡摻雜區域（LDD)N—、p ， ΐ ί置m如第3f圖所示’依序定義光阻層以做為離子植入罩幕（未顯示於圖中），接著，分別植入第二、第一離子，例如是N型、P型離子以在該等複晶矽所構二φ 極結構G1、G2兩側下方之矽基板3〇表面處 ‘ (LDD)N-與P—。 X欠侈雜&域接下來要進行的步驟係為植入第二型離子至該極結構兩側下方之半導體基板中、具有第一型離子之結構、及該具有第一型離子之島狀結構侧下方之該基板中以形成第一MOS電晶體、第—雙載子接面電晶體、以及第一擴散區；在此，請參考第3G 3I圖首先，請參考第3G圖，沈積並回蝕刻一層絕緣層，例如是二氧化矽層 (未標示於圖中）於該矽基板3〇之表面，以於該等島狀結構33a、33b及閘極結構gi、G2之側壁形成絕緣間隔物34 ; 接下來，請參照第3H圖，定義一光阻層pR2以做為離子植入罩幕，其暴露出閘極G1、及其兩侧之矽基板3〇、以及島狀結構33a之部分表面和島狀結構33a側邊之部分矽基板 3〇，其中，島狀結構33a表面為光阻層PR2覆蓋之部分係用以作為NPN雙載子接面電晶體之p型基極B ;其次，植入N型離子至該具有P型離子之島狀結構3 3a中以形成一NpN雙載子接面電晶體35a，其具有N型之射極e、N型之集極c，而具有P型離子之區域則為基極B ;並於淡摻雜區N_處形成濃摻雜區而作為一 NM0S電晶體之源/汲極（S/D);以及濃摻 413889 五、發明說明（7) 雜入N型離子至NPN雙載子接面電晶體35a側邊下方之矽基板30中以形成一 N型離子擴散區N+。接著，進行類似之步驟，亦即植入第一型離子至該第二閘極結構兩側下方之半導體基板中、具有第二型離子之島狀結構、及該具有第二型離子之島狀結構側下方之該半導體基板中以形成第二MOS電晶體、第二雙載子接面電晶體、以及第一擴散區；在此，請參看第31圖，在移除上述之光阻層PR2之後’利用相同的方法，定義光阻層pR3為罩幕’以進行離子植入，而在該具有N型離子之島狀結構33b 形成一PNP雙載子接面電晶體35b，其具有f>型射極E、P型集極C，而具有N型離子之區域則為基極B ;並形成一pM〇s 電晶體之源/汲極（S/D)以及於該pNP雙載子接面電晶體侧邊下方之矽基板30中形成一 p型離子擴散區p+。接下來，於該半導體基板之表面全面性形成一内層介電層，並於該内層介電層中分別形成第—開口、第二開口、以及第三開口以分別露出該第一、第二閘極結構該第一、第二雙載子接面電晶體之該射極、以及該第一、第二雙載子接面電晶體之集極與該第一、第二擴散區表面；例如，依據第3J圖之圖式，在移除上述之光阻層pR3之 f ’係以化學氣相沈積法（CVD)全面性沈積一層二氧化矽層36於該碎基板30之表面並覆蓋該等雙載子接面電晶體 a、35b以及該等閘極結構G1、G2 ;接著請參考第 J U用光學微影術以及姓刻製程，在該二氧切層％中形成第一開口37a、37b、第二開口38a 、以及第三第10頁 413889 五、發明說明（8) 開口 39a、3 9b以分別露出該等NMOS/PMOS電晶體之閘極結構Gl、G2、該NPN/PNP雙載子接面電晶體之射極E與集極 C、以及該等擴散區N+、P+表面；其中，位於該第三開口 3 9 a、39b内之絕緣間隔物34在此蝕刻之製程中被移除。之後，要進行的是透過該等開口形成導電層，而於該第一開口與第二開口間形成一金屬内連線，且於該等第三開口中形成一金屬栓以作為一接觸區，以使該第一、第二雙載子接面電晶艎之該射極與該閘極結構作電性連接，以及該第一、第二雙載子接面電晶體之該集極與該離子擴散區做電性連接；例如，請參考第3L圖，係沈積—層金屬鎢（未標示於圖中）於該二氧化矽層36之表面並填滿該第一開口37a、37b、第二開口38 a、38b、以及第三開〇 3 9 a、3 9 b，並回蝕刻該金屬鎢至該二氧化矽層3 6夕表面以形成金屬鑛检塞’接著，沈積一金屬銘層，並經由餘刻定義其圖案之後，分別於該第一開口與第二開口間留下一層金屬鋁内連線371a、371b ’以使該雙載子接面電晶體 3 5a、3 5b之射極E與該閘極結構Gl、G2做電性連接，而於該第三開口39中所形成之金屬栓塞則作為一接觸區391 、 a、391b以使該雙載子接面電晶體35a、35b之集極c與該離子擴散區N+、P+做電性接觸。在此需注意的是，該離子^ 散區N+係接地，而另一離子擴散區P+則接電源電壓Vdd。 ' 於此實施例之構造中’該等雙載子接面電晶雜之射極係利用金屬内連線而與該MOS電晶體之閘極相連，而其集極則藉由一接觸區與一離子擴散區呈電性連結因而提供了Sub-island-like structure 33b »Later, 'can choose whether to form a lightly doped region (LDD) N —, p, 置 m m as shown in Figure 3f' sequentially define a photoresist layer as an ion implantation mask (Not shown in the figure), and then implant the second and first ions, such as N-type and P-type ions, respectively, to form silicon substrates under the two φ-pole structures G1 and G2 of the polycrystalline silicon. 30 ′ at the surface (LDD) N- and P-. The next steps of the X-poor & domain are implanting the second type ions into the semiconductor substrate below the two sides of the polar structure, the structure having the first type ions, and the island having the first type ions. A first MOS transistor, a first double-junction junction transistor, and a first diffusion region are formed in the substrate below the structure-like side; here, please refer to FIG. 3G and 3I. First, please refer to FIG. 3G to deposit An etching layer is etched back, such as a silicon dioxide layer (not shown in the figure) on the surface of the silicon substrate 30 to form insulation on the sidewalls of the island structures 33a, 33b and the gate structures gi, G2. Spacer 34; Next, referring to FIG. 3H, define a photoresist layer pR2 as the ion implantation mask, which exposes the gate electrode G1, the silicon substrate 30 on both sides thereof, and the island structure 33a. Part of the surface and a part of the silicon substrate 30 on the side of the island structure 33a. The surface of the island structure 33a covered by the photoresist layer PR2 is used as the p-type base B of the NPN bipolar junction transistor. Secondly, implant N-type ions into the island-like structure 3 3a with P-type ions in the shape An NpN bipolar junction transistor 35a has an N-type emitter e, an N-type collector c, and a region with a P-type ion is the base B; and is formed at the lightly doped region N_ The heavily doped region serves as the source / drain (S / D) of an NMOS transistor; and the heavily doped 413889 V. Description of the invention (7) N-type ions are doped to the side of the NPN bipolar junction transistor 35a below the side An N-type ion diffusion region N + is formed in the silicon substrate 30. Then, similar steps are performed, that is, implanting a first type ion into a semiconductor substrate below the two sides of the second gate structure, an island structure having a second type ion, and an island shape having a second type ion. A second MOS transistor, a second bipolar junction transistor, and a first diffusion region are formed in the semiconductor substrate below the structure side; here, referring to FIG. 31, the photoresist layer PR2 is removed. Afterwards, 'using the same method, the photoresist layer pR3 is defined as a mask' for ion implantation, and a PNP amphiphilic junction transistor 35b is formed on the island structure 33b having N-type ions, which has f > Type emitter E, P type collector C, and the region with N type ions is the base B; and a source / drain (S / D) of a pM0s transistor is formed and is connected to the pNP double carrier A p-type ion diffusion region p + is formed in the silicon substrate 30 below the surface transistor side. Next, an inner dielectric layer is formed on the surface of the semiconductor substrate, and first, second, and third openings are formed in the inner dielectric layer to expose the first and second gates, respectively. Pole structure of the emitter of the first and second amplicons and the collector of the first and second amplicons and the surfaces of the first and second diffusion regions; for example, According to the diagram of FIG. 3J, after removing the photoresist layer pR3 f ′, a silicon dioxide layer 36 is comprehensively deposited on the surface of the broken substrate 30 by chemical vapor deposition (CVD) and covers the The bipolar junction transistors a, 35b and the gate structures G1, G2; then, please refer to the JU lithography and the engraving process to form the first openings 37a, 37b in the dioxygenation layer%. The second opening 38a and the third page 10 413889 V. Description of the invention (8) The openings 39a and 39b expose the gate structures G1 and G2 of the NMOS / PMOS transistor, respectively, and the NPN / PNP bipolar The emitter E and the collector C of the junction transistor, and the surfaces of the diffusion regions N +, P +; The third opening 3 9 a, an insulating spacer 39b 34 is removed within the etching in the manufacturing process. After that, it is necessary to form a conductive layer through the openings, form a metal interconnect between the first opening and the second opening, and form a metal plug in the third openings as a contact area. So that the emitter of the first and second double-carrier junction transistors are electrically connected to the gate structure, and the collector of the first and second double-carrier junction transistors are connected to the gate electrode The ion diffusion region is electrically connected; for example, please refer to FIG. 3L, where a layer of metal tungsten (not shown in the figure) is deposited on the surface of the silicon dioxide layer 36 and fills the first openings 37a, 37b, and the first Two openings 38a, 38b, and third openings 03a, 39b, and etch back the metal tungsten to the surface of the silicon dioxide layer 36 to form a metal mine plug. Next, a metal layer is deposited. After defining its pattern through the remaining time, a layer of metal aluminum interconnects 371a, 371b 'are left between the first opening and the second opening, respectively, so that the double-carrier junction transistor 3 5a, 3 5b is radiated. The electrode E is electrically connected to the gate structures G1 and G2, and a metal plug formed in the third opening 39 As a contact region 391, a, 391b so that the bipolar junction transistor 35a, 35b of the collector c from N + diffusion region, P + make electrical contact. It should be noted here that the ion diffusion region N + is grounded, and the other ion diffusion region P + is connected to the power supply voltage Vdd. 'In the structure of this embodiment' the emitters of the bipolar junction transistor are connected to the gate of the MOS transistor by a metal interconnect, and the collector is connected to the gate via a contact area. An ion diffusion region is electrically connected and thus provides

第11頁 413889 五、發明說明（9) 天線電流一金屬導線流該天線電流之’使其免此外，下，可依不度及其中所雖然本限定本發明神和範圍内當視後附之個放電的路徑，亦即，入時，這個雙裁子接面一個放電的路徑，使電受損害。該雙載子接面電晶體在同蝕刻機台之電漿特性摻雜離子之濃度以決定發明已以較佳實施例揭何熟習此項技藝者，當可作更動與潤飾，申請專利範圍所界定者當大量的天線電流隨著電晶趙之設置能夠提供流遠離閘極並因此保護具有低的漏電流之特性而調整基極（base)之寬其崩潰電壓。露如上，然其並非用以 ’在不脫離本發明之精因此本發明之保護範圍為準。 (Page 11 413889 V. Description of the invention (9) The antenna current-a metal wire flows the antenna current so as to avoid it. In addition, it can be inferred and its contents. Although this definition is within the scope of the present invention, it should be attached as This discharge path, that is, at the time of entry, this pair of cutouts meets a discharge path, causing electricity to be damaged. The dopant junction transistor has the same plasma characteristics of the etching machine as doped ion concentration to determine the invention has been revealed in a preferred embodiment. Those skilled in the art can make changes and retouching. The definer adjusts the collapse voltage of the base when a large amount of antenna current is provided with the transistor Zhao to provide a current away from the gate and thus protects the characteristics of low leakage current. As shown above, it is not intended to be used without departing from the spirit of the present invention, so the scope of protection of the present invention shall prevail. (

第12頁Page 12

Claims

413889413889

六、申請專利範圍 1. 一種以雙載子接面電晶體避免天線林愈士殊效·應之電晶嵌制造方法’適用於一半導體基板上，包括下列步驟$ 11裝於該半導體基板上形成一具有第一型離子之導電定義該導電層之圖案’並於該導電層之部分位置換雜入第二型離子以於該半導體基板上形成一第一、第1 極結構以及一具有第一型離子與一具有第二型離子之: 結構；植入第二型離子至該第一閘極結構兩側下方之該半導體基板中、該具有第一型離子之島狀結構、及該具有第— 型離子之島狀結構側下方之該半導體基板中以形成第一 MOS電晶體、第一雙載子接面電晶體、以及第一擴散區；植入第一型離子至該第二閘極結構兩側下方之該半導體基板中、具有第二型離子之島狀結構、及該具有第二型離子之島狀結構側下方之該半導體基板中以形成第二電晶體、第二雙載子接面電晶體、以及第二擴散區· 於該半導體基板之表面形成—内層介^層，並於該内層介電層中分別形成複數個開口以分別露出該第一、第二閘極結構，該第一、第二雙載子接面電晶體之該射極與該第-、第二雙載子接面電晶體之集極與該第―、第二擴散區之表面；以及透過該等開口形成導電層’而於該第一開口與第二開口間形成-金屬内連線，且於該等第三開口中形成一金屬栓以作為一接觸區，以使該第一、第二雙載子接面電晶體之該射極與該閘極結構作電性連接，以及該第一、第6. Scope of Patent Application 1. A double-carrier junction transistor to avoid the antenna Lin Yushi's special effect and response should be applied to a semiconductor substrate, including the following steps: $ 11 mounted on the semiconductor substrate Form a conductive pattern with a first type ion to define the pattern of the conductive layer, and insert a second type ion at a part of the conductive layer to form a first and a first electrode structure on the semiconductor substrate and a first electrode structure having a first A type ion and a type II ion: a structure; implanting a second type ion into the semiconductor substrate below both sides of the first gate structure, the island structure having the first type ion, and the Forming a first MOS transistor, a first bipolar junction transistor, and a first diffusion region in the semiconductor substrate below the island structure side of the first type ion; implanting a first type ion into the second gate In the semiconductor substrate below both sides of the electrode structure, an island structure having a second type ion, and the semiconductor substrate below the island structure side having a second type ion to form a second transistor, a second pair Sub-junction transistor and second diffusion region are formed on the surface of the semiconductor substrate-an inner interlayer, and a plurality of openings are formed in the inner dielectric layer to expose the first and second gate structures, respectively. The emitters of the first and second amplicons and the collectors of the first and second amplicons and the surfaces of the first and second diffusion regions; and Wait until the openings form a conductive layer 'to form a metal interconnect between the first and second openings, and form a metal plug in the third openings as a contact area so that the first and second The emitter of the bipolar junction transistor is electrically connected to the gate structure, and the first and the first

413889 六、申請專利範圍二雙載子接面電晶體之該集極與該離子擴散區做電性連接。 2.如申請專利範圍第1項所述之製造方法，其中，在形成該導電層之前更包括形成一層閘極絕緣層於該半導體- 基板之表面。 4 3. 如申請專利範圍項所述之製造方法，其中，該閘極絕緣層係為二氧4 g層。 4. 如申請專利範圍第1項所述之製造方法，其中，該半導體基板係為矽基板。 5. 如申請專利範圍第1項所述之製造方法，其中，該導電層係為複晶矽層。 6. 如申請專利範圍第1項所述之製造方法，其中，該第一型離子係為P型離子，而第二型離子係為N型離子。 7. 如申請專利範圍第1項所述之製造方法，其中，該第一型離子係為N型離子，而第二型離子係為P型離子。 8. 如申請專利範圍第1項所述之製造方法，其中，該第一雙載子接面電晶體係為NPN形式，而第一MOS電晶體係為NMOS形式。 9. 如申請專利範圍第1項所述之製造方法，其中，該第二雙載子接面電晶體係為PNP形式，而第二MOS電晶體係為PMOS形式。 1 0.如申請專利範圍第1項所述之製造方法，其中，該第一雙載子接面電晶體係為PNP形式，而第一MOS電晶體係為PMOS形式。413889 6. Scope of patent application The collector of the two-carrier junction transistor is electrically connected to the ion diffusion region. 2. The manufacturing method according to item 1 of the patent application scope, wherein before forming the conductive layer, it further comprises forming a gate insulating layer on the surface of the semiconductor-substrate. 4 3. The manufacturing method as described in the scope of the patent application, wherein the gate insulating layer is a 4 g layer of oxygen. 4. The manufacturing method according to item 1 of the scope of patent application, wherein the semiconductor substrate is a silicon substrate. 5. The manufacturing method according to item 1 of the scope of patent application, wherein the conductive layer is a polycrystalline silicon layer. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the first-type ion is a P-type ion and the second-type ion is an N-type ion. 7. The manufacturing method according to item 1 of the scope of patent application, wherein the first type ion is an N type ion and the second type ion is a P type ion. 8. The manufacturing method according to item 1 of the scope of patent application, wherein the first ambipolar junction transistor system is an NPN form, and the first MOS transistor system is an NMOS form. 9. The manufacturing method according to item 1 of the scope of patent application, wherein the second ambipolar junction transistor system is a PNP form, and the second MOS transistor system is a PMOS form. 10. The manufacturing method according to item 1 of the scope of patent application, wherein the first ambipolar junction transistor system is a PNP form, and the first MOS transistor system is a PMOS form.

第14頁 413889 六、申請專利範圍 11.如申請專利範圍第1項所述之製造方法，其t，該第二雙載子接面電晶體係為NPN形式，而第二MOS電晶體係為NMOS形式。 12_如申請專利範圍第1項所述之製造方法，其中，在. 形成該等MOS電晶體與該等雙載子接面電晶體之前，更包括沈積並回蝕刻一層絕緣層至該半導體基板之表面以在該等閘極結構與该等島狀結構之側壁形成絕緣間隔物。 13. 如申請專利範圍第12項所述之製造方法，其中，該絕緣間隔物之材質係為二氧化矽。 14. 如申請專利範圍第1項所述之製造方法，其中該内層介電層之材質係為二氧化紗。 15. 如申請專利範圍第1項所述之製造方法，其中該金屬栓之材質係為鎢。 16. 如申請專利範圍第丨項所述之製造方法，其中，該金屬内連線之材質係為鋁。 17. —種以雙載子接面電晶體避免天線效應之電晶體結構，包括：一NMOS電晶體，具有一閘極構造’係設置於一半導體基板上；、 - ΝΡΝ雙載子接面電晶體，具有射極、基極、盘集極’其中，該射極係與該M〇s電晶體之該閘 ^ 連；以及载子接面電晶體一接地之N型擴散區，係與該雙之集極做電性接觸。Page 14 413889 6. Application scope of patent 11. The manufacturing method as described in item 1 of the scope of application for patent, wherein t, the second bipolar junction transistor system is in the form of NPN, and the second MOS transistor system is NMOS form. 12_ The manufacturing method according to item 1 of the scope of patent application, wherein, before forming the MOS transistors and the bipolar junction transistors, it further comprises depositing and etching back an insulating layer to the semiconductor substrate. The surface is formed with insulating spacers between the gate structures and the sidewalls of the island structures. 13. The manufacturing method according to item 12 of the scope of patent application, wherein the material of the insulating spacer is silicon dioxide. 14. The manufacturing method as described in item 1 of the scope of patent application, wherein the material of the inner dielectric layer is a dioxide yarn. 15. The manufacturing method described in item 1 of the scope of patent application, wherein the material of the metal plug is tungsten. 16. The manufacturing method as described in item 丨 of the patent application scope, wherein the material of the metal interconnect is aluminum. 17. —A transistor structure with a double-junction junction transistor to avoid antenna effects, including: an NMOS transistor with a gate structure 'set on a semiconductor substrate; and-NPN double-junction junction transistor The crystal has an emitter, a base, and a disc collector, wherein the emitter is connected to the gate of the Mos transistor; and a grounded N-type diffusion region of the carrier junction transistor is connected to the The pair of collectors makes electrical contact.

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六、申請專利範圍 18.—種以雙載子接面電晶體避免天線效應之結構，包括：一 Ρ Μ 0 S電晶體’具有一閘極構造，係設置於一半導體基板上； ' 一 ΡΝΡ雙載子接面電晶體’具有射極、基極、與集極，其中’該射極係與該MOS電晶體之該閘極構造相連；以及一接電源之Ν型擴散區，係與該雙載子接面電晶體之集極做電性接觸。 19.如申請專利範圍第1_18項所述之構造，其中，該雙載子接面電晶體之該射極係透過金屬鎢拴塞以及一金屬鋁内連線而與該閘極構電性連接。 20.如申請專利範圍第該擴散區係以一金屬鎢栓 18項所述之構造’其中，】與該雙載子接面電晶體之該集極做電性連接。 21 ·如申請專利範圍第1 該半導體基板係為矽基板。 ^8項所述之構造’其中章文Sixth, the scope of patent application 18. A structure to avoid antenna effect by using a double-carrier junction transistor, including: A P MOS transistor 'has a gate structure and is arranged on a semiconductor substrate;' a PNP The bipolar junction transistor has an emitter, a base, and a collector, wherein the emitter is connected to the gate structure of the MOS transistor; and an N-type diffusion region connected to a power source is connected to the The collector of the bipolar junction transistor is in electrical contact. 19. The structure as described in claims 1-18 of the scope of the patent application, wherein the emitter of the bipolar junction transistor is electrically connected to the gate structure through a metal tungsten plug and a metal aluminum interconnect. . 20. According to the scope of the patent application, the diffusion region is a structure described in item 18 of a metal tungsten plug, wherein:] is electrically connected to the collector of the bipolar junction transistor. 21 · If the scope of patent application is the first, the semiconductor substrate is a silicon substrate. ^ Constructions described in item 8 'of which

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