411608 _^ 五、發明説明（） (請先閱讀背面之注意事項再填寫本莨) 發明領域： 本發明揭露一種有關於半導體元件製程， 叮别是有關 一種具有改善靜電故電防護電阻之短通道金氧半 t 电晶體的 製程之方法。 發明背景： 自適入1 990年代以來積體電路的製程便造入一新的 極超大型積體ULSI電路的紀元，而欲達到ULSI的目標， 毫無疑問的是滅少晶片的尺寸，不管是金氧半電晶體 (MOSFET)的源極，汲極或者是閘極皆是如此，元件尺十 的減小’不但，可以促使單位MOSFET的成本大幅度下 降，更可增加元件的迷度（元件的速度表現幾乎和元件尺 寸的平方長成反比），而更受到客户的歡迎。 經濟部智慧財產局R工消費合作社印製 不過’當元件的尺寸減小的同時，例如，由微米的箄 級減到次微米的等級，或更小時，兀件的表現（performance) 便要面對更嚴苛的考驗。舉例來説，一些問題像熱載子效 應（hot carrier effect)，和透穿效應（punchthrough)都是互 補式金氧半電晶體（CMOS)尺寸變小時所必要面對的两個 最主要限制。造一步説，例如寄生電容、寄生電阻也都是 當元件尺寸減小時必須要避免的問題。411608 _ ^ V. Description of the invention () (Please read the notes on the back before filling in this 莨) Field of the invention: The present invention discloses a process related to the manufacturing of semiconductor components, and it is related to a short channel with improved electrostatic and electrical protection resistance. Method for manufacturing metal-oxygen half-t transistor. Background of the Invention: Since the integration of integrated circuit manufacturing processes since the 1990s has created a new era of very large integrated ULSI circuits, and to achieve the goal of ULSI, there is no doubt that the size of the chip is reduced, whether it is The source, drain, or gate of a metal-oxide-semiconductor (MOSFET) is the same. The reduction of the element size can not only greatly reduce the cost of the unit MOSFET, but also increase the obscuration of the element (element The speed performance is almost inversely proportional to the square length of the component size), and is more welcomed by customers. Printed by the R & D Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, but when the size of the component is reduced, for example, from the micron level to the sub-micron level, or less, the performance of the components must be faced with. To tougher tests. For example, some issues such as hot carrier effect and punchthrough are two of the most important limitations that must be faced when the size of complementary metal-oxide-semiconductor (CMOS) becomes smaller. For example, parasitic capacitance and parasitic resistance are also issues that must be avoided when the component size is reduced.
其它’要留意的限制因素是，在次微米尺寸時，MOS ________2 本紙張尺度適用中國國家標準（CNS) A4規格（2)0X297公釐） 411608____ 五、發明説明（） (請先聞讀背面之注意事項再填寫本頁) 之源//汲、極和複晶閘極的電導率的問題。例如在1 μηι的製 程技術進步到〇.5μιη時，擴散區的片電阻值會由以口增 加至5〇 Ω/口而不利於速度的增進。一自我對準（self-aligned) 的夕化物技術，術語稱之為「salic ide j的製程包括：全面 形成金爲帛’之後再退火以形成金層矽化物在複晶矽的閘 極’以及源/汲極的區域形成金厲矽化物接觸區（contact) 等* Salidde不僅可以降低M〇s源/汲極及閘極的電阻， 並且也提供一個乾淨的矽化物_矽基板的界面，此外，它 也不需要額外的微影或蝕刻步驟，另外它更是一自我對準 的一個製程。 另一重要且伴隨MI0SFET元件尺寸減小而發生之元 件損壞的問題是：靜電荷放電（electric sutic discharge;簡 稱ESD)的行為iESD可以輕而易皋的經由輸出入端和電 源線俦輸至元件的内部而破壞整個元件，例如.可以很容 易的經由個人取用時，不經意的碰觸IC的接脚而意外的 產生高的電歷。結果造成元件的閘極氧化壻的崩憒。因此， 在製造MOS元件的同時也顺便把ESD的防護電路一倂製 造是掻為重要的事。 經濟部智慧財產局員工消費合作社印製 然而’將源/汲極也製作金屬矽化物和輕滲雜汲極區 (low doped drain ;簡稱LDD)之结構卻可能會損軎ESD針 閉極氧化層的性能。這樣一來，表示金層矽化物可能使得 ESD防護電路變得無效。Chen先生在Pr〇ceeding 〇f the EOS/ESD Symposium (1988)第2 12·頁的參考資料提出提 出 Shallower junctions and thicker salicide have 3 ——---* 3 本紙張尺度通用t國國家標準（CNS > A4规格（210X297公釐） A7 411608 _B7___ 五、發明説明（） negative impact on the ESD capability of a process’’，這 樣的概念。Others' note that the limiting factor is that at the sub-micron size, MOS ________2 This paper size applies Chinese National Standard (CNS) A4 specifications (2) 0X297 mm) 411608____ V. Description of the invention () (Please read the first Note: Please fill in this page again.) // The issue of the conductivity of the source / sink, pole and complex gate. For example, when the process technology of 1 μm is advanced to 0.5 μm, the sheet resistance value of the diffusion region will increase from 50 to 50 Ω / port, which is not conducive to speed improvement. A self-aligned oxide technology, termed "salic ide j. The process includes: forming gold as a whole, and then annealing to form a gold layer silicide at the gate of polycrystalline silicon" and The source / drain region forms a gold silicide contact area, etc. * Salidde can not only reduce the resistance of the Mos source / drain and gate, but also provide a clean silicide_silicon substrate interface. In addition, It also does not require additional lithography or etching steps. In addition, it is a self-aligning process. Another important component damage problem that occurs with the reduction in the size of MI0SFET devices is: electrostatic charge discharge (electric sutic discharge; referred to as ESD) iESD can be easily transmitted to the inside of the component through the input and output terminals and power lines to destroy the entire component. For example, it can be easily accessed by an individual and accidentally touched the IC. Pin and accidentally generate a high electric calendar. As a result, the gate oxide of the device collapses. Therefore, while manufacturing the MOS device, the ESD protection circuit is also manufactured as a priority. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, the structure of the source / drain also made of metal silicide and low doped drain (LDD) may damage the ESD pin closure. The performance of the polar oxide layer. This means that the silicide of the gold layer may invalidate the ESD protection circuit. Mr. Chen proposed in the reference materials of PrOceeding 〇f the EOS / ESD Symposium (1988) on page 2 12 · Shallower junctions and thicker salicide have 3 ——--- * 3 The paper size is common to the national standard of the country (CNS > A4 specification (210X297 mm) A7 411608 _B7___ 5. Explanation of the invention () negative impact on the ESD capability of a process '', such a concept.
Amerasekera 箄人在 IEDM Technical Digest (1 996)， 第893頁也討論了自偏壓侧向NPN電晶體（一在NM1 OS 電晶體之寄生的雙離子電晶體）電流增益P和ESD性能之 關係’ Amerasekera等人發現p值愈低則ESD的性能也將 愈低。進一步.又發現P值強烈的受到金層矽化物以下之 有效源/汲掻擴散深度的影響，而擴敢深度是可以藉由離 子佈植以及矽化反應消耗的掮散區的大小而加以調整的， 因此’發展一 salicide的製程同時，也一併製造一 ESD 防護電路並考慮上述的因素，將對ULSI元件製造有最小 的衝擊。 另一方面，當線寬小到次微米時，微影的製程也是一 個重要的因素。例如，光波的波長λ和增加光圈數 值的大小（Ν Α)都是可以^析度的。不過將會 減少聚焦景深（depth of focus ; 考 C,Y. Chang and S.M. Sze ”ULSI technology”，（McGraw-Hill Book Co.， (1996) p.270):如下方程式所示： Ζ)ί?^ = ±λ/2(ΝΑ)2 DOF對應最大之窗口（window)或者相當於光阻的高 度’因此當元仵尺寸滅少時，減少微影的次數或降低罩幕 的高度或在低溫形成另一可替代光阻的罩幕層以降低其厚 度是值得考慮的。一種液相沉積氧化層（liquid phase deposition; LPD-Si Ο」應是可以加以應用之最佳候選者之 4 本紙張尺度速用中國^家橾準（CNS ) A4说格(2丨0X297公釐） ---------裝--ΓΊΙ—,訂-----線 (請先閱讀背面之注意事項再填寫木頁) 經濟部智蒽財產局員工消費合作社印製 411608五、發明説明（ A7 B7 LPD技術可以參考Homma等人在；叫…心㈣s〇c （测）P.240所介紹的-種利用H2SiF^MM 為形成氧化層之來源。H_a等人冑LpD_Si〇2以選擇性 的化學氣相沉積於光阻圖案之間或者料線間的溝渠内且 不破壞光阻層。除此之外’形成LPD_Si〇2只需在低溫的 環境下操作。另-優㈣，t也具有比光阻曆更能防止灌 子穿透的特性。並且勿需另加額外的罩幕層。 經濟部智慧財產局員工消费合作社印製 發明目的及概述： 本發明之目的係提供一種可以同時形 和ESD防護電阻的方法。 本發明之再一目的係藉由桎短的通道 碎化物接觸區以獲得元件之高速性能的表 及熱载子效應也因有抗透穿區及低摻雜區 由於高的ESD防護電壓可以因為有〇〇〇 元件壽命可以更持久。 製程步驟如下：首先在一已有隔離區 和一 ESD昉護區之矽基扳上，以習知抆 少形成含有一第一閘極結構，ESD防護區 二閘極結構。其中第一閘極結構係用以形 閘極結構係用以形成ESD防護電阻；接 離子怖植，使用η型導電性雜質怖值所有 成金氧半電晶 並具有 現，短 而改善 接面而 ，隔龌 術在功 也至少 成電晶 著’施 表面， 自對 通遒 。其 獲得 ~功 能區 形成體， 以第 用以 本紙張尺度通用中國國家標準（CNS ) 格（2丨〇)<297公着） 經濟部智慧財產局員工消費合作社印製 JU608 五、發明説明（） 第一輕摻雜汲極區LDD及第二LDD區，分則於功能區内 於ESD防護區内）；隨後，以一斜角度約1〇_6〇。施以第二 次難子怖植，使用P型雜質怖植所有表面，用以形成第— 及第一袋狀抗透穿區於功能區内及ESD防護區内。接著 以光阻圖案罩幕於功能區上以做為第三攻離子佈植之罩幕 層。第二次離子佈植，侏以两種η型雜質之離子以斜角度 佈植於ESD防護區以形成一摻雜之區域，除用以補償之 前Ρ型蘿子的摻雜區外，並藉以產生雙港子擴散汲槿區 (DDD)。接著’以光阻圖案為罩幕，形成一 LPD_Si〇2層（液 相沉積氧化層）於ESD防護區。去除光阻後，在第—閘拯 的侧g形成間隙壁’再以自對準技術自對準的金厲矽化物 (包括全面的形成一層高溫金鹰層後，先以較低溫（35〇_ 700°C)的快速熱退火（RTp)以形成金麋矽化物再去除間 隙壁、隔SI區及LPD層之未反應的金屬層）。之後，再以 低能量神離子佈植於已形成之金屬矽物層之内以做為雜質 的擴散源，最後再以高溫（7〇〇_115〇 之第二次RTP製 程將雜質驅入，用以形成棰淺接面源/汲極區與具導電性 的襆晶閘極’ ESD防護區内的DDD接面也可藉以完成·» 另外金厲矽化物也可同時由介穩相轉成較低電阻而且較穩 定的金属矽化物相》 圖示簡單説明： 本發明的較佳實施例將於往後之説明文字中輔以下列 6 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） ---------上----^--訂 1 f請4-聞讀f·面之注意事項再填寫本頁) %1β〇8 Α7 Β7 五、發明説明（ 圖形丨故更詳Iff的Μ述 經濟部智慧財產局員工消費合作社印製 ^顯：依據習知技術，形成電晶㈣極绪構於两㈣ 功能區域，ESD防護區域的横载面視圖； ® 一顯不依據本發明技術，形成氡t 取矽# 叫氧氮矽化物層於閘極結赛 興"$基板之横截面視圖；圖二顯示依捸本發明技術，施以LDD Hi工I , ESD ^ ^ LDD灌子怖植功能區万 區的横截面視圖； 示依據本發明技術，施以袋狀抗透穿雜子怖植功能 區及ESD防護區的橫截面視圖； 圖五顯示稷蓋-光阻圖案於功能區，並以神和鱗同時怖相 ESD防竣區域的横截面視豳； 圖六顯示依據本㈣技#f H LPD氧化㈣ESD防 護區域的横裁面視圖； 顯示依據本發明技術 結構的横载面視圖； 圖八顯示依捸本發明技術，形成自對準金屬矽化物層功 區之後晶閘極、源/汲極之上表面上的橫截面視圖； 圖九顯示依據本發明技術，施以砷搫子佈植金屬矽化物 的横截面視圖；及 圖十顯示依據本發明技術，施以第二階段RTP製程以 成低電阻且穩定相的金厲矽化物層並形成極淺接面的3 汲極，以及ESD防蠖區之DDD接面的橫截面視圖。 形成側間隙壁於功能區之閘 本紙張尺度適用中國國家櫺準（CNS ) A4規格（2丨0X297公釐） ----------^---i — —^------1 ··- (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 _ 411608 五、發明説明（） 發明詳細説明： 本發明提供一以自我對準形成金屬矽化物之短通道 MOSFET ’並同時具有增進ESC)防護結構之製造方法。發 明的細節將描述如下： 圖一所示’係一具有兩個不同區域，功能區域 (functional region)20，ESD防護區域21的橫截面視圖。 每一區域至少有一已定義之钹晶矽閘極結構22形成於 <00 1>珊滲雜的矽晶圓上，以定義源/汲極區23的位置。Amerasekera 箄 in IEDM Technical Digest (1 996), p. 893 also discusses the relationship between the current gain P and the ESD performance of a self-biased lateral NPN transistor (a parasitic dual ion transistor in the NM1 OS transistor). Amerasekera et al. Found that the lower the p-value, the lower the ESD performance. Further, it was found that the P value is strongly affected by the effective source / drain diffusion depth below the gold silicide, and the expansion depth can be adjusted by the size of the diffusion region consumed by ion implantation and silicidation reaction. Therefore, while developing a process for salicide, it also manufactures an ESD protection circuit and considers the above factors, which will have the smallest impact on the manufacture of ULSI components. On the other hand, when the line width is as small as a sub-micron, the lithography process is also an important factor. For example, both the wavelength λ of the light wave and the magnitude of the increase in the aperture value (NA) can be resolved. However, it will reduce the depth of focus (see C, Y. Chang and SM Sze "ULSI technology", (McGraw-Hill Book Co., (1996) p.270): as shown in the following equation: ZZ) ί? ^ = ± λ / 2 (ΝΑ) 2 DOF corresponds to the largest window or the height of the photoresistor '. Therefore, when the size of the element is reduced, reduce the number of lithography or reduce the height of the mask or form at low temperature. Another alternative to the photoresist mask layer to reduce its thickness is worth considering. A liquid phase deposition oxide layer (LPD-Si 0) should be one of the best candidates that can be applied. 4 Paper Size Quick Use China ^ 家 橾 准 (CNS) A4 grid (2 丨 0X297 mm ) --------- install --ΓΊΙ—, order ----- line (please read the precautions on the back before filling in the wooden page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 411608 Description of the invention (A7 B7 LPD technology can refer to Homma et al .; called ... heart ㈣oc (test) P.240-a kind of using H2SiF ^ MM as the source to form the oxide layer. H_a et al. LpD_Si〇2 to Selective chemical vapor deposition in the trench between the photoresist pattern or the material line without damaging the photoresist layer. In addition, the formation of LPD_Si〇2 only needs to be operated in a low temperature environment. Another-excellent, t also has the property of preventing the penetration of the pot more than the photoresistive calendar. And no additional cover layer is required. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Purpose and summary of the invention: The purpose of the present invention is to provide a Method capable of simultaneously forming and ESD protection resistor. Another object of the present invention is to shorten The surface of the channel debris contact area to obtain the high-speed performance of the device and the hot carrier effect are also due to the anti-penetration region and the low-doped region. Due to the high ESD protection voltage, it can be more durable because of the life of the device. It is as follows: Firstly, a silicon gate having an isolation region and an ESD protection region is formed on the silicon substrate, and it is conventionally formed to contain a first gate structure and an ESD protection region with two gate structures. The first gate structure is The gate structure is used to form an ESD protection resistor; the ion implantation is performed, and the n-type conductive impurity is used to form all metal-oxygen semi-transistors with current, short and improved junctions. At least an electric crystal is deposited on the surface, and it is self-aligning. It obtains a ~ functional area forming body, which is based on the Chinese paper standard (CNS) grid (2 丨 〇) &297; published by the Ministry of Economic Affairs. JU608 printed by the Intellectual Property Bureau's consumer cooperative. V. Description of the invention () The first lightly doped drain region LDD and the second LDD region, divided into the functional area and the ESD protection area); 1〇_60. A second difficulty planting was applied, and all surfaces were planted with P-type impurities to form first and first pocket-like anti-penetration areas in the functional area and the ESD protection area. Then use a photoresist pattern to cover the functional area as a mask layer for the third attack ion implantation. In the second ion implantation, the ions of two η-type impurities are implanted in the ESD protection area at an oblique angle to form a doped area. In addition to compensating the doped area of the previous P-type seed, The Shuanggangzi Diffusion Divergent Area (DDD) was created. Next, using a photoresist pattern as a mask, an LPD_SiO2 layer (liquid-phase deposited oxide layer) is formed in the ESD protection area. After removing the photoresist, a gap wall is formed on the side of the first gate, and then the self-aligned gold silicide (including the comprehensive formation of a high-temperature golden eagle layer) is first formed at a lower temperature (35 ° _ 700 ° C) rapid thermal annealing (RTp) to form gold molybdenum silicide and then remove the unreacted metal layer of the spacer, the SI region and the LPD layer). After that, low-energy god ions are implanted in the formed metal silicon layer as a diffusion source of impurities, and finally the impurities are driven in by the second RTP process of high temperature (700-1150). It can be used to form the 棰 shallow junction source / drain region and the conductive 襆 thyristor's DDD junction in the ESD protection zone can also be completed. »In addition, the gold silicide can also be converted from metastable phase to relatively Low-resistance and relatively stable metal silicide phase "The diagram illustrates briefly: The preferred embodiment of the present invention will be supplemented by the following 6 texts. The paper size is applicable to China National Standard (CNS) A4 (210X297) (Mm) --------- Top ---- ^-Order 1 f, please 4-read the notes on f., Then fill out this page)% 1β〇8 Α7 Β7 V. Description of the invention ( Graphics 丨 More detailed description of Iff printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. ^ Display: According to the conventional technology, a crystal cross-section view is formed between two functional areas and ESD protection areas; ® A display is not based on the technology of the present invention, and the silicon is formed to take silicon # called an oxygen nitrogen silicide layer on the gate junction Saixing's substrate Cross-sectional view; Figure 2 shows a cross-sectional view of the LDD Hi-tech I, ESD ^ ^ LDD irrigation plant functional area according to the technology of the present invention; showing a bag-shaped anti-penetration according to the technology of the present invention Cross-sectional view of the functional area and the ESD protection area of heterozygous plants; Figure 5 shows the cross-sectional view of the cover-photoresist pattern on the functional area, and the ESD prevention area is simultaneously displayed with God and scales; Figure 6 shows the basis This technology #f H LPD A cross-sectional view of the ESD protection area; shows a cross-sectional view of the structure according to the technology of the present invention; FIG. 8 shows a crystal after forming the self-aligned metal silicide layer functional region according to the present technology A cross-sectional view on the upper surface of the gate and source / drain electrodes; FIG. 9 shows a cross-sectional view of a metal silicide implanted with arsenic and tritium according to the technology of the present invention; and FIG. The second stage of the RTP process is to form a low-resistance and stable phase gold silicide layer and form a 3-drain electrode with a very shallow junction, and a cross-sectional view of the DDD junction in the ESD anti-rust zone. Side gaps are formed in the functional area Zhaban Paper Standard Applies to China Standard (CNS) A4 (2 丨 0X297mm) ---------- ^ --- i — — ^ ------ 1 ··-(Please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _411608 V. Description of the invention () Detailed description of the invention: The present invention provides a short-channel MOSFET that forms a metal silicide by self-alignment and also has improved ESC) protection Manufacturing method of structure. The details of the invention will be described as follows: Figure 1 is a cross-sectional view of two different regions, a functional region 20 and an ESD protection region 21. Each region has at least one defined crystalline silicon gate structure 22 formed on a < 00 1 > silicon doped silicon wafer to define the location of the source / drain region 23.
一隔藏區24，隔絶功能區2〇與ESD防護區域21。ESD 防護區2 1的位置可以礞功能區2〇很逮也可以很靠近但必 須以隔陲區24隔絶，至於，形成後晶矽閘極結構22矽晶 圓上的技術已成習知抆術因此在此將不再多加赘述。 接著，如圖二所示，形成一絶緣層25於矽基板5之 源/汲極區23及第一及第二複晶閘極結構22的表面，這 層絶緣層25以氧氮矽化物（oxynitride)為佳，本發明之氧 氮夕化物的形成方法是以Ν〗〇以及/或的氣氛下形成， 當氣氮妙化物形成的同寺並具有使乾姓刻的損傷得以恢後 的效果。 參考圖三，為防止熱載子效應（hot carrier effect)，一 ldd (iow doped drain)怖植，以磷或砷薙子植入功能區π 及 0防護區21的所有區域内，以形成輕摻雜的區域29 怖植的條件係：能量和剤量分別為5 keV to 100 keV 及 5xl〇12-Ui〇i4 /cm2。 本紙張纽適用中CNS > A4規格（2ι〇χ297公產） ---------A-------^訂. - (請·先閲讀背面之'/£-意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 411608 A7 _'__B7______ 五、發明説明（） 參照圖四，為了克服nMOSFET的短通道效應（short-channel effect) ’以大角度的袋狀抗透穿（pocket anti_ punchthrough) BF/佈植（如圖示之箭頭方向植入）功能區及 ESD防護區21以形成抗透穿區3〇，以一較佳的實施例而 言，此離子怖植的能量和劑量分別為20-120 keV，和 5xl011至lxlO13 /cm2，佈植的角度則在10-60。範圍。 接著如圖五所示，在光阻圖案31經由微影製程形成 於功能區20之所有表面上之後，選自磷、砷、或録族笨， 其中之两種®子一起植入ESD防護區21，以便形成雙維 子擴散汲極接面32»此離子怖植的能置和劑量（例如怖植 砷難子而言為 5-150keV 和 5xl〇14 /cm2 至 5xl〇" /cm2。新 珅離子’對磷雜子而言則為5_丨50keV和2x 1〇l4 /cm2至 2xl015/cm2。由於在ESD防蠖區内，此時n型導電性雜 質的濃度高於先前佈植之大角度的袋狀抗透穿BF〆怖植， 因此在之後之高溫退火步驟將足以使p型導電性雜質的效 應可以被忽略而只考碟雙雄子擴散汲極區32(d〇uble diffusion drain)的效應即可。A compartment area 24 isolates the functional area 20 from the ESD protection area 21. The location of the ESD protection area 21 can be either the functional area 20 or it can be very close, but it must be isolated by the isolation area 24. As for the formation of the post-silicon gate structure 22, the technology on the silicon wafer has become a common practice. Therefore, I will not repeat them here. Next, as shown in FIG. 2, an insulating layer 25 is formed on the surface of the source / drain region 23 and the first and second complex gate structures 22 of the silicon substrate 5. oxynitride) is preferred. The method for forming an oxynitride according to the present invention is formed in an atmosphere of N〗 〇 and / or. When the oxynitride is formed in the same temple, it has the effect of recovering the damage caused by the dry name. . Referring to FIG. 3, in order to prevent a hot carrier effect, an ldd (iow doped drain) is implanted, and phosphorus or arsenic is implanted into all regions of the functional region π and the protection region 21 to form a light carrier. The conditions of the doped region 29 are: energy and mass are 5 keV to 100 keV and 5x1012-Ui〇i4 / cm2, respectively. CNS > A4 specification (2ι297 × 297 product) applicable to this paper New Zealand --------- A ------- ^ Order.-(Please read the '/ £ -Italian items on the back first] (Fill in this page again.) Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs. 411608 A7 _'__ B7______ 5. Description of the invention Pocket anti_ punchthrough BF / implanting (implanted in the direction of the arrow as shown) functional area and ESD protection area 21 to form an anti-penetration area 30. In a preferred embodiment, this ion The planting energy and dose are 20-120 keV, and 5xl011 to lxlO13 / cm2, and the implanting angle is 10-60. range. Then, as shown in FIG. 5, after the photoresist pattern 31 is formed on all surfaces of the functional area 20 through a lithography process, two kinds of ® are selected from phosphorus, arsenic, or Luzuben, and are implanted into the ESD protection area together. 21 in order to form a two-dimensional diffusive drain junction 32 »The energy and dose of this ion implant (for example, 5-150 keV and 5xl04 / cm2 to 5xl0 " / cm2 for arsenic ions). New For ions, the ions are 5_50keV and 2x1010 / cm2 to 2xl015 / cm2. Because of the ESD protection zone, the concentration of n-type conductive impurities is higher than that previously implanted The large-angle bag-shaped anti-penetration BF is planted, so the subsequent high-temperature annealing step will be sufficient to make the effect of p-type conductive impurities negligible and only consider the dipole diffusion region 32 (duoble diffusion). drain) effect.
接著，如圖六所示，-LPD氧化f 33，沉積於 防護區21的所有表面上，LPD氧化層33的形成溫度在 25-3〇0〇C，形成的厚度是5(M⑽nm。值得注意的是，LpD 氧化層33在以下的製程將扮演著蕈幕層的角色。因此可 以使製程步驟簡單化。 接下來請參考圖七，在去除功能區20之光阻圖案31 之後，在祓晶矽閘極結構22和矽基扳5的所有區域以cvd ί______—__— 9 本纸張尺度適用中國國家梂準（CNS ) Α4規格（21 Οχ297公釐） ---------.:¾---^-IIJtT------^ - -* (請先閲讀背面t注意事項再填寫本頁) Α7 Β7 4Π6〇8 -~~~—.___ 五、發明説明（ 法形成 氧化層’厚度約為50-200 nm，然後.以非箄向 性姓刻古+ 士 it β 万式在複晶矽閘極緒構2 2的兩惻形成間隙壁3 6。 .為形成一自對準的salicide接觸區（contact)，_選自 =Y C〇、Ni和W其中之一的一金麋層（未圖示）鍍在所有 '區域之上，沉積的方法可以是以CVD或者是以骤鍍的 ^ 並且’通常）几積的厚度約在10-100nm的厚度。然 後再施以第一階段的矽化物反應退火製程。如圖八所示， 金屬層和褸晶矽岡極結構22之祓晶矽反應以形成複晶金 屬玲化物同時金屬層和源/汲桎區23上之單晶较 = 屬较化物層3 8。 以—較佳的實施例而言’一在350-750 ^的氣氣氛 之快速熱退火（RTP)便可以形成所要的矽化物，部份未反 應的金屬層，例如在隔離區24，在間隙壁上 s i I __ 氧化 mag 參考圖九，高劑量低能量的砷或磷龌子（ 可以以NH4〇H' h2〇、h2〇2所組成_刻液， 為最佳）’選擇其中之一植入所有的金層矽仆 ^ θ 7 物層 38， 含祓晶閘極結構22及源/汲極區23之上）， ) 以一較佳的赏 經濟部智慧財產局員工消費合作社印^ 施例而言，此齷子佈植的能董和劑量（例如怖植 、 子）分別為，5-100keV和5xl014 /cm2至5x1nu碟或神離 土 ；>x1〇u /ctn2。，射 較重質量的砷雞子施以較低能置怖植，隔齷pNext, as shown in FIG. 6, -LPD oxide f 33 is deposited on all surfaces of the protection region 21. The formation temperature of the LPD oxide layer 33 is 25 to 300 ° C, and the thickness is 5 (M⑽nm. It is worth noting The LpD oxide layer 33 will play the role of a curtain layer in the following processes. Therefore, the process steps can be simplified. Please refer to FIG. 7. After removing the photoresist pattern 31 in the functional area 20, All regions of the silicon gate structure 22 and silicon base plate 5 are cvd ί ______—__— 9 This paper size is applicable to China National Standard (CNS) Α4 specification (21 〇 × 297 mm) ---------. : ¾ --- ^-IIJtT ------ ^--* (Please read the precautions on the back before filling this page) Α7 Β7 4Π6〇8-~~~ —.___ V. Description of the invention The thickness of the oxide layer is about 50-200 nm, and then the non-orientated surname Cargo + Shi it β Wanshi forms a partition wall 3 6 on the two sides of the complex crystal gate structure 2 2. A self-aligned salicide contact (contact), a gold molybdenum layer (not shown) selected from one of YCO, Ni, and W is plated on all the regions. The deposition method can be CVD or The thickness of ^ and 'usually' several layers is about 10-100nm, and then the first stage silicide reaction annealing process is performed. As shown in FIG. The crystalline silicon of structure 22 reacts to form a complex crystalline metal oxide, and the metal layer and the single crystal on the source / drain region 23 are equal to the compound layer 38. In the preferred embodiment, one is 350 -750 ^ rapid thermal annealing (RTP) in the gas atmosphere can form the desired silicide, part of the unreacted metal layer, such as in the isolation zone 24, on the gap si I __ oxidation mag. Refer to Figure 9, high dose Low-energy arsenic or phosphine (can be composed of NH4OH'h2O, h2O2_etching solution, the best) 'choose one of them to implant all gold silicon silicon ^ θ 7 physical layer 38 , Including the tritium thyristor structure 22 and the source / drain region 23),) In a better case, it is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The doses (for example, plant and seed) are 5-100 keV and 5xl014 / cm2 to 5x1nu dish or Shenli soil; > x10u / ctn2, respectively. , Heavier quality arsenic chickens are treated with lower energy,
區 2 4和L P D 氧化層32都是有效罩幕層足以阻擋離子棺 入妙基极5。 4直入上述區域進 如圖十所示，接著一厚的並連續的CVD电 ^VD氧化層40沉 本紙張尺度適用t固國家揉準（CNS 洗格（210X297公釐） A7 B7 411608 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 積在ESD防護區21和功能區2〇的表面，以一較佳的實 施例而言，CVD氧化層40的厚度約為1〇〇_8〇〇 nm，沉積 的溫度約為500-800。(：，隨後再苑以第二階段的熱處理。 此時在金屬矽化物的雜質將扮演—擴散源的角色，將雜赏 引入妙基板5與褸晶妙層之内，並且形成一源/汲極區23 以形成淺接面。源/汲極區23的接面的深度由雜質重分佈 的丨木度而定’亦即熱處理的條件而定。另外，在第一階段 就形成的金屬矽化物也將轉變成較穩定相的金屬矽化物。The regions 24 and the L P D oxide layer 32 are both effective masking layers sufficient to block the ion coffin from entering the base 5. 4 Straight into the above area, as shown in Figure 10, followed by a thick and continuous CVD electrical ^ VD oxide layer 40, the size of this paper is applicable to the national standard (CNS washing grid (210X297 mm) A7 B7 411608 V. Invention Explanation () (Please read the precautions on the back before filling this page) The surface of the ESD protection area 21 and the functional area 20 is accumulated. In a preferred embodiment, the thickness of the CVD oxide layer 40 is about 1〇 〇_80〇nm, the deposition temperature is about 500-800. (:, And then the second stage of heat treatment. At this time, the impurities in the metal silicide will play the role of a diffusion source, introducing miscellaneous rewards. Within the substrate 5 and the crystal layer, a source / drain region 23 is formed to form a shallow junction. The depth of the junction of the source / drain region 23 is determined by the degree of redistribution of impurities, that is, heat treatment In addition, the metal silicide formed in the first stage will also be transformed into a more stable phase metal silicide.
以TiSiz金屬矽化物為例，第—階段的RTp的溫度約在 550-650°C 而第一階段的熱處理溫度則要比75〇。(：高，第二階段 的RTP將介穩相的C_49TiSi2轉變成低電阻的c· 54TiSi2(正方晶格orth〇g〇nal phase)，在此同£SD防護區 21之DDD的接面也同時形成’另外怖植於矽基板$和 複晶第一及第二閘極結構22的雜質也可以活化，雎子佈 植的缺陷損傷也得以消除，以一較佳的實施例而言，第二 階段的退火是以RTP的方式，溫度約在700-U50 "C，約 5 · 1 8 0 秒 〇 本發明的優點包括： 經濟部智慧財產局=貝工消費合作社印製 (1) 極短^通道並具有自對準的矽化物接觸 區可以以陳闘_酬_擴散源來獲得； (2) 元件的操作速度和短通道效應都可以明 顯的獲得改善，並旦 (3) 髙的ESD防護電壓可以因為有DDD接 11 本紙張尺度適用中國圏家標準（CNS ) A4*t格（210X297公釐） 411£〇8 at B7 五、發明説明（） 面而獲得 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脱雜本發明所揭示之 精神下所完成之箄效改變或修飾，均應包含在下述之申請 專利範圍内。例如本發明雖僅提到nMOSFET為例，以神 佈植以形成n + p接面，當然本發明之結構也同樣適用於 對pMOSFET，一如熟悉該镇域的人士所了解，通常就要 佈植以BF2 +雜子以形成p + n接面。 ^^pvr ^nf ^^^1 .i ^^^1 I .^i·— 1- 一B3 - t - _ (請先鬩讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印^ 12 本紙乐尺度適用中國國家標率（CNS ) A4規格（2!〇X297公釐）Taking TiSiz metal silicide as an example, the temperature of the RTp in the first stage is about 550-650 ° C and the heat treatment temperature in the first stage is higher than 75 °. (: High, the second stage of RTP will transform the metastable phase C_49TiSi2 into a low-resistance c · 54TiSi2 (square lattice orthogonal phase), which is also at the same time as the SDDD 21 DDD interface. The impurities that form the implanted silicon substrate and the first and second gate structures 22 of the complex crystal can also be activated, and the defects and damages of the implantation of the rafters can be eliminated. In a preferred embodiment, the second The annealing in the stage is RTP, the temperature is about 700-U50 " C, about 5.180 seconds. The advantages of the present invention include: Intellectual Property Bureau of the Ministry of Economic Affairs = Printed by Bayer Consumer Cooperative (1) Very short ^ The silicide contact area with a channel and self-alignment can be obtained with a sintered source; (2) the operating speed of the device and the short channel effect can be significantly improved, and (3) ESD of 髙The protection voltage can be obtained because the DDD is connected to 11. This paper size is applicable to the Chinese standard (CNS) A4 * t grid (210X297 mm) 411 £ 〇8 at B7 5. The description of the invention () and the above is only the present invention The preferred embodiments are not intended to limit the scope of patent application of the present invention; It does not decompose the effect changes or modifications completed under the spirit disclosed by the present invention, which should be included in the scope of the following patent applications. For example, although the present invention only mentions nMOSFET as an example, the gods are planted to form n + The p junction, of course, the structure of the present invention is also applicable to pMOSFET, as people familiar with the town know, it is usually necessary to plant BF2 + heterozygous to form a p + n junction. ^^ pvr ^ nf ^^^ 1 .i ^^^ 1 I. ^ I · — 1- One B3-t-_ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 12 sheets Music scale is applicable to China National Standard (CNS) A4 specification (2.0 × 297mm)