經濟部中央標準局負工消費合作社印製 .41.1584 A7 _____B7 五、發明説明（I ) 詳細說明： (一) 發明技術領域： 本發明是有關一種非揮發記憶體(non-volatile memory)中間隙壁(spacer)的形成方法，尤指使用離子摻 雜技術之氮化矽(Si3N4)間隙壁(spacer)的形成方法。 (二) 發明技術背景： 快閃記憶體(flash memory)的積體電路結構中，主要 包括有源極、汲極、控制閛極、浮動閘極等基本結構， 其中該閘極結構又可以分爲堆疊式閘極(Stack Gate)結構 與分離式閘極(Split Gate厕種結構。而堆疊式閘極結構與 分離式閘極結構相較之下，可以縮小每一記憶細胞元的 面積，具有提高積體電路元件密度的優點，但在抹除記 憶資料時卻有容易過度抹除之缺點，而分離式閘極結構 可以克服上述堆疊閘極結構的缺點。 製作分離式閘極結構可參考圖一所示之製程示意 圖，圖一中，形成在氧化層12上的浮動間極14(floating gate)和控制閘極22(C〇ntrd gate)之間包括複晶矽層間氧 化層16、氧化層18和氮化矽間隙壁20。氧化層18與 介電層19覆蓋住浮動閘極14，並形成於浮動閘極14兩 旁的矽基板10上。氮化矽間隙壁20形成在浮動閘極14 側壁，氧化層18上方》 其中所述之氮化矽間隙壁20的形成，其目的在於防 止在浮動閘極I4及氧化層12之尖角處100與控制閘極 22間產生天線效應(Antenna effect)的情況即尖端放電， ------------裝—^---Γ,--訂------線 (請先閱讀背面之注意事哼再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) :\4規格（2Ι0χ'297公釐） A7 B7 41.1584 五、發明説明（>) 造成漏電流(leakage)，而產生提早導通(tum-on)。 然而在形成氮化矽間隙壁20製造過程中所見結果並 非如前述完美，習知製程中，在製作氮化矽間隙壁20 時，係先沈積一層氮化矽於氧化層18之上，再触刻氮化 矽層，並控制蝕刻速率，以形成氮化矽間隙壁20，但由 於形成氮化矽間隙壁20之寬度僅有100至300A之間， 其蝕刻不易穩定地控制，而容易產生過度蝕刻或蝕刻不 完全的問題，若發生過度蝕刻，上述之間隙壁20會被侵 蝕，亦影響其下的氧化層18之可靠度。因此，在目前微 影、蝕刻等條件的限制下，爲避免間隙壁20過度蝕刻導 致場區臨界電壓(field threshold voltage)不穩定，本發明將 提供有效改進蝕刻終點的製程方法。 (三)發明簡要說明： 有鑑於上述習用技術之缺失，本發明人乃提出一種 新的自動對準接觸窗製程，可有效改善上述習用技術缺 失之本發明，即： 本發明之主要目的即在於提供一種有效避免因過度 蝕刻而遭受侵蝕的間隙壁之形成方法，即利甩離王施值 技術形成分離式快閃記惇體間隙壁的方法 本發明之次要目的即在於提供一種形成分離式快閃 記憶體間隙壁的方法，增加形成間隙壁之良率，降低生^ 產成本/ 爲了達成上述之目的，本發明主要係利用以下所述 之製程步驟而完成；首先，於一基底上依形成第一氧化 ------------裝 — ^-------訂------線 (請先閱讀背面之注意事巧再填寫本頁) 經濟部中央螓隼局員工消費合作.社印^ 國國家標準（〇阳）/\4規格（2!〇:< 297公釐 A7 B7 經濟部中央橾隼局員工消費合作社印装 面示意圖 12閘氧化層 16複晶矽層間氧化層 B介電層 22控制闊極 33氧化層 37多晶砂氧化層 41氮化矽層 411584 五、發明説明（J ) 層、第一多晶砂層與多晶砂氧化層(P〇〗y-〇xide)，定義出 浮動閘極，之後使用高溫形成第二氧化層於浮動閘極之 上，再覆蓋氮化矽層’並以離子植入法摻雜於氮化矽層 上部，以造成氮化矽層經離子佈值部份與未經離子佈值 之蝕刻速率不同後，再進行間隙壁蝕刻以形成側壁子， 接續沈積介電層後再形成第二多晶矽，並定義出控制閘 極，完成快閃記憶體之閘極製作。 爲使貴審查委員對於本發明案之特徵、目的與功 效能有更進-步之瞭解跑1識，細g合目^詳細画如 后： (四）圖式之簡要說明： 圖-係繪示習知技藝中分離式快_憶體之晒製程 剖面示意圖。 圖二八〜®二D f纖神獅實_中_讎技術 製作分離式朗_般麵製程剖 圖號說明： 10基底 14浮動閘極 18氧化層 20間隙壁 31基底 35浮動閘極 39氧化層 1 I I 1 I I I 裝— —i I *1 I 訂 I I I 線 {請先閱讀背面之注意事^為填寫本頁) 本紙浪尺度適用中國國家^7^7^7^^· 411584 A7 B7_ 五、發明説明（f) 43間隙壁 45控制閘極 47介電層 1〇〇尖角處 (五)發明詳細說明： 本發明係爲一種利用摻雜技術形成快閃記憶體中 間隙壁的方法，請參閱圖二A〜圖二D，其係繪示根據 本發明實施例之利用摻雜技術形成間隙壁的製程。以 下，參照圖面詳細說明本發明之利摻雜技術形成間隙壁 之方法的實施例。 如圖二A所繪示，於一半導體基底31上，依序形 成一氧化矽層33、一浮動閛極35及一多晶矽氧化層 37，並微影、定義出浮動閘極極結構。其中，氧化矽層 33之組成係爲氧化矽，係使用熱氧化法所形成，直接將 基板加熱以形成之，當進行資料”1”的寫入時，熱電子 將”穿隧(tunnel)”過所述之氧化層33而進入，其氧化層 33其係含穿隧氧化層(tunnel oxide)及閘氧化層(gate oxide)所組成[圖中未示]，而其穿隧氧化層於源極與汲極 處較薄；浮動閘極35之組成係可爲非晶矽 '複晶矽或 複晶矽化金屬(Polycide)係使用化學氣相沈積方式 (chemical vapor deposition ; CVD)形成·，多晶矽氧化層 37之組成係爲浮動閘極35之上方經熱氧化反應所形 成。 接著，在定義第一閘極結構之圖形後，於多晶砂氧 化層37上方、浮動閘極35和其半導體基底31兩旁上， 使用高溫形成一主要用於抹消動作之氧化層39，目卩$卩 ---„---,----裝--1---..--訂------線 (請先閱讀背面之注意事'U-再填寫本頁) 經濟部中央標準局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS ) A4规格（210:<2<Π公釐） A7 B7 411584 五、發明説明（，） 圖二B所示。 接續，進入本發明之重點，沈積氮化矽層41 ’如 圖二所示，係先使用化學氣相沈積方式(CVD)形成厚度 介於100至300A之間之氮化矽層41，再對所述之氮化 矽層41進行離子佈植(ion implanting)，將硼(B)或氟化 ®0(BF2)之離子源(ion source)以離子佈植方式植入覆蓋 氧化層39上之氮化矽層41內，其中所述之離子佈植能 量介於20keV至50keV之間，由於經佈植過之氮化矽層 41a中，由於使用之離子佈值方式採取垂直方式佈值入 氮化矽層41，如圖二C所示，因此，離子不易植入位 於浮動閘極35側壁上之氮化矽41，由於含有硼(B)離子 的氮化矽層41a部份(斜線部份)與未經離子佈植部份之 材料特性己不园_，所以會造成蝕刻速率的不同。其中， 蝕刻氮化砂層41係採用非均向性電獎蝕刻(isotropic plasma etching)方式。氮化矽層41a中斜線有離子植入的 部份，_定的共價鍵鍵結被j直入乏離壬 速率較未經離子佈植部份的蝕刻速率爲高，因此經過離 子佈值後之氮化矽餓刻速率較快’不需任何蝕刻終止層 便能有效率地控制蝕刻終止時間，在進行氮化矽層41a 的間隙壁蝕刻時，便容易得到即如圖二D所示之間隙壁 43的結構。 接續，如圖二D所示，沈積介電層47，其組成可 爲氧化層或多層介電層結構：氧化矽/氮化砂/氧化砍 (Oxide-Nitride-Oxide ; ΟΝΟ)結構，當使用氧化層時，Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 41.1584 A7 _____B7 V. Description of the Invention (I) Detailed Description: (I) Technical Field of the Invention: The present invention relates to a partition wall in a non-volatile memory A method for forming a spacer, especially a method for forming a silicon nitride (Si3N4) spacer using an ion doping technology. (II) Technical background of the invention: The integrated circuit structure of a flash memory mainly includes basic structures such as a source electrode, a drain electrode, a control gate, and a floating gate. The gate structure can be divided into It is a stack gate structure and a split gate structure. Compared with the split gate structure, the stack gate structure can reduce the area of each memory cell and has The advantage of increasing the density of integrated circuit components is that it has the disadvantage of being easily over-erased when erasing memory data, and the separated gate structure can overcome the shortcomings of the stacked gate structure described above. Refer to the figure for making the separated gate structure A schematic diagram of the process shown in FIG. 1. In FIG. 1, a floating silicon interlayer oxide layer 16 and an oxide layer are formed between a floating gate 14 and a control gate 22 formed on the oxide layer 12. 18 and silicon nitride spacer 20. The oxide layer 18 and dielectric layer 19 cover the floating gate 14 and are formed on the silicon substrate 10 on both sides of the floating gate 14. The silicon nitride spacer 20 is formed on the floating gate 14. Side wall, above oxide layer 18》 The purpose of the formation of the silicon nitride spacer 20 is to prevent tip discharge when the antenna effect (Antenna effect) occurs between the tip 100 of the floating gate I4 and the oxide layer 12 and the control gate 22. ------------ Installation — ^ --- Γ,-Order ------ line (please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS): \ 4 specifications (2Ι0χ'297 mm) A7 B7 41.1584 5. Description of the invention (>) Causes leakage current and early turn-on (tum-on). However, the silicon nitride gap is formed The results seen in the manufacturing process of the wall 20 are not as perfect as described above. In the conventional manufacturing process, when the silicon nitride spacer 20 is manufactured, a layer of silicon nitride is first deposited on the oxide layer 18, and then the silicon nitride layer is etched, and The etching rate is controlled to form the silicon nitride spacer 20, but since the width of the silicon nitride spacer 20 is only between 100 and 300A, the etching is not easy to control stably, and the problem of over-etching or incomplete etching is easy to occur. If excessive etching occurs, the above-mentioned spacer 20 will be eroded, which will also affect the availability of the oxide layer 18 below it. Therefore, under the constraints of current lithography, etching and other conditions, in order to avoid the instability of the field threshold voltage caused by the over-etching of the spacer 20, the present invention will provide a method for effectively improving the end point of the etching. 3) Brief description of the invention: In view of the lack of the conventional technology, the present inventor proposes a new automatic alignment contact window manufacturing process, which can effectively improve the invention lacking the conventional technology, that is, the main purpose of the invention is to provide A method for forming a partition wall that can effectively avoid erosion due to over-etching, that is, a method for forming a separate type flash memory carcass partition wall by using the technology of Wang Shi value, and a secondary object of the present invention is to provide a method for forming a separate type flash memory The method of the memory gap wall increases the yield rate of the gap wall and reduces the production cost / In order to achieve the above purpose, the present invention is mainly completed by using the process steps described below. First, a first step is formed on a substrate. Oxidation ------------ install — ^ ------- order ------ line (please read the notes on the back before filling in this page) economy Ministry of Economic Affairs, Central Government Bureau, Consumer Consumption Cooperatives. National Seal of China (〇 阳) / \ 4 specifications (2! 〇: < 297 mm A7 B7, schematic diagram of the printed surface of the Central Government Bureau of the Ministry of Economic Affairs, Consumer Council of Employees) Oxide layer 16 polycrystalline silicon interlayer oxide layer B dielectric layer 22 control wide pole 33 oxide layer 37 polycrystalline sand oxide layer 41 silicon nitride layer 411584 V. Description of the invention (J) layer, first polycrystalline sand layer and polycrystalline sand An oxide layer (P〇〗 y-〇xide), defines a floating gate, and then uses a high temperature to form a second oxide layer on top of the floating gate, and then covers the silicon nitride layer 'and is doped with nitrogen by ion implantation. After siliconizing the upper part of the silicon layer to make the etching rate of the silicon nitride layer different from that of the ion-distribution value and the value of the ion-undistribution value, the spacer is etched to form a sidewall, and then a second layer is formed after the dielectric layer is deposited. Crystal silicon, and define the control gate to complete the gate fabrication of flash memory. In order for your reviewing committee to have a better understanding of the features, purposes, and effects of the present invention, a detailed understanding of each item is shown below. (Details are as follows: (4) Brief description of the drawings: Figure-Department drawing Shows a schematic cross-sectional view of the drying process of the separate fast-memory body in the learning technique. Figure 28 ~ ® Two D f fiber lion real _ _ _ _ technology to produce a separate Lang _ general surface process sectional number description: 10 substrate 14 floating gate 18 oxide layer 20 spacer 31 substrate 35 floating gate 39 oxidation Tier 1 II 1 III Packing — i I * 1 I order III line {Please read the notes on the back ^ to fill out this page) The scale of this paper is applicable to Chinese countries ^ 7 ^ 7 ^ 7 ^^ · 411584 A7 B7_ V. Explanation of the invention (f) 43 The gap wall 45 controls the sharp angle of the gate 47 dielectric layer 100 (e) Detailed description of the invention: The present invention is a method for forming a spacer wall in a flash memory by using a doping technique. Referring to FIG. 2A to FIG. 2D, a process for forming a spacer wall by using a doping technique according to an embodiment of the present invention is shown. Hereinafter, an embodiment of a method for forming a spacer by the favorable doping technique of the present invention will be described in detail with reference to the drawings. As shown in FIG. 2A, a silicon oxide layer 33, a floating gate electrode 35, and a polycrystalline silicon oxide layer 37 are sequentially formed on a semiconductor substrate 31, and a floating gate structure is defined by lithography. Among them, the composition of the silicon oxide layer 33 is silicon oxide, which is formed using a thermal oxidation method, and the substrate is directly heated to form it. When the data “1” is written, the hot electrons will “tunnel” It enters through the above-mentioned oxide layer 33. The oxide layer 33 is composed of a tunnel oxide layer and a gate oxide layer [not shown], and the tunnel oxide layer is formed from a source. The electrode and drain are thinner; the composition of the floating gate 35 can be amorphous silicon, polycrystalline silicon or polycide, which is formed using chemical vapor deposition (CVD). Polycrystalline silicon The composition of the oxide layer 37 is formed by a thermal oxidation reaction above the floating gate 35. Next, after defining the pattern of the first gate structure, an oxide layer 39 mainly used for erasing is formed on the polycrystalline sand oxide layer 37, on both sides of the floating gate 35 and its semiconductor substrate 31, using high temperature. $ 卩 --- „---, ---- install--1 ---..-- order ------ line (please read the note on the back 'U- before filling this page) Economy The paper standard printed by the Consumer Standards Cooperative of the Ministry of Standards and Standards of the Ministry of China applies the Chinese National Standard (CNS) A4 specification (210: < 2 < Πmm) A7 B7 411584 V. Description of the invention (,) Figure 2B. Continued, Entering the focus of the present invention, as shown in FIG. 2, a silicon nitride layer 41 is deposited. First, a chemical vapor deposition (CVD) method is used to form a silicon nitride layer 41 with a thickness between 100 and 300A. The silicon nitride layer 41 is ion implanted, and an ion source of boron (B) or fluorinated 0 (BF2) is implanted into the nitride layer over the oxide layer 39 by ion implantation. In the silicon layer 41, the ion implantation energy is between 20 keV and 50 keV. Because of the implanted silicon nitride layer 41a, the ion implantation method is adopted. The silicon nitride layer 41 is distributed in a vertical manner, as shown in FIG. 2C. Therefore, ions are not easily implanted on the silicon nitride 41 on the side wall of the floating gate 35. Because the silicon nitride layer 41a contains boron (B) ions, The material characteristics of the part (slashed part) and the part not implanted with ions are different. Therefore, the etching rate will be different. Among them, the etching of the nitrided sand layer 41 uses isotropic plasma etching (isotropic plasma). etching) method. The oblique line in the silicon nitride layer 41a has an ion implanted portion, and the fixed covalent bond is directly penetrated by the ionization rate. The etching rate is higher than that of the non-ion implanted portion. After the ion distribution, the silicon nitride has a faster etching rate. It can effectively control the etching termination time without any etching termination layer. When the spacer of silicon nitride layer 41a is etched, it is easy to obtain, as shown in Figure 2. The structure of the partition wall 43 shown in D. Next, as shown in FIG. Nitride-Oxide; 〇ΝΟ) structure, when using an oxide layer,
---^---r----裝--r--.--訂------線 (請先閱讀背面之注意事V為填寫本頁J 經濟部中央樣準局員工消費合作社印製 本紙婊尺度適用中國國家標準（CNS)A4規格（210X297公釐） 411584 Α7 _ Β7 經濟部中夬標準局負工消費合作社印製 五、發明説明（b) 其形成方式如同製作氧化層39，當使用多層介電層結 構[氧化矽/氮化矽/氧化矽(ΟΝΟ)]時，通常係以低壓化學 氣相沈積法(low pressure chemical vapor deposition ; LPCVD)形成此多層介電層結構，採用上述多層介電層 是爲了增加介電層47之絕緣性質。 最後，再如圖二D所繪示，以化學氣相沉積法(CVD) 沈積多晶矽層後定義出控制閘極45，即完成分離式快 閃記憶體之閘極製作。 由於本發明中利用離子佈值方式對後續形成間隙 壁43之氮化矽層41進行慘雜，故造成不同的飯刻速 率。因此，可有效將過度蝕刻而導致間隙壁被侵触的可 能性降低。 本發明之利用摻雜技術形成間隙壁的方法，可避免 — ^—. 於蝕刻時，間滕壁容易被敏刻之步_驟所侵蝕，而導致電 子向下穿隧的情形發生；因此本發明可有效提高產品的 良率，進而減低生產成本。 上述利用摻雜技術形成間隙壁的方法充分顯示出 本發明目的及功效上均深富實施之進歩性，極具產業之 利用價值’且爲目前市面上前所未見之新發明，完全符 合發明專利之要件，爰依法提出申請。 唯以上所述者，僅爲本發明之較佳實施例而已，當 不能以限定本發明所實施之範圍。即大凡依本發明申請 專利範圍所作之均等變化與修飾，皆應仍屬於本發明專 利涵蓋之範圍內’謹請貴審查委員明鑑，並祈惠准， ---^-------裝-- (請先閱讀背面之注意事項Κ填寫本頁) -" 線_ 本紙掁尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公爱） 411584 五、發明説明（/?)是所至禱。 ----—^----裝— (請先閱讀背面之注意事境<填寫本頁) 丁 4° 線 經濟部中央標準局工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A#見格（210 X 297公釐）--- ^ --- r ---- install --r --.-- order ------ line (please read the notes on the back first. V is for filling out this page. The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 411584 Α7 _ Β7 Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economy Layer 39. When a multilayer dielectric layer structure is used [silicon oxide / silicon nitride / silicon oxide (ΟΝΟ)], the multilayer dielectric layer is usually formed by a low pressure chemical vapor deposition (LPCVD) method. The structure uses the above-mentioned multi-layer dielectric layer to increase the insulation properties of the dielectric layer 47. Finally, as shown in FIG. 2D, the control gate 45 is defined after depositing a polycrystalline silicon layer by chemical vapor deposition (CVD). That is, the production of the gate of the separated flash memory is completed. Since the silicon nitride layer 41 that subsequently forms the partition wall 43 is miscellaneously formed in the present invention by using the ion cloth value method, it results in different meal rates. Therefore, it is effective Over-etching will reduce the possibility of the wall being invaded. The invention uses the doping technique to form the spacer wall, which can avoid — ^ —. During the etching, the spacer wall is easily eroded by the step of engraving, which causes the electrons to tunnel downward; therefore, the invention The method can effectively improve the yield of the product, thereby reducing the production cost. The method for forming the partition wall by using the doping technology fully shows the advanced implementation of the purpose and efficacy of the present invention, which has great industrial use value. New inventions not seen on the market completely meet the requirements of invention patents, and apply in accordance with the law. However, the above are only preferred embodiments of the present invention, and the scope of implementation of the present invention cannot be limited. That is to say, all equal changes and modifications made in accordance with the scope of the patent application of the present invention should still fall within the scope of the patent of the present invention. Equipment-(Please read the precautions on the back first to fill out this page)-" Thread _ The size of this paper is applicable to the Chinese National Standard (CNS) Α4 specification (210 × 297 public love) 411584 V. Description of the invention (/?) Prayer. ----— ^ ---- Equipment— (Please read the note on the back & fill in this page first) Ding 4 ° Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives This paper is in accordance with Chinese national standards (CNS) A # see grid (210 X 297 mm)