411557 2815twf1/002 第87107569號說明書修正頁 'VA7 B7 ΐ像:'_刁 1 %正“日期;8S/4/18 '··.' 卜 ,-rW； 18 :多晶矽層 24，34 ·虛置圖案 42 :多晶矽圖案 50 :第一·圖案區 60 *虛置圖案兀 五、發明說明（t ) Π :閘氧化層 20, 22, 30, 32 :金屬線 40 :主動區圖案 44 :井區圖案 52 :第二圖案區 實施例 請參照第3圖，其繪示依照本發明一較佳實施例的一 種具有移位虛置圖案之主動區圖案的設計方法示意圖。如 第3圖所示，金屬線30, 32係覆蓋於不同之虛置圖案34 上方。然，由於虛置圖案34均經過移位，例如相鄰不同 之虛置圖案34均以一定之位移排列於主動區圖案間，故 而使得金屬線30所覆蓋之虛置圖案34與金屬線32所覆 .蓋之虛置圖案，有相當之寄生電容。因此，對於金屬線32 與30而言，在實際電路之應用上，具有較佳之效能表現， 而無不同的RC延遲問題產生。 第4圖是本發明實施例之設計方法所使用的原始圖 案，在積體電路佈局（Layout)之原始圖案中，例如包括有 所需之主動區圖案40，多晶矽圖案42，與井區（Well)圖案 44 = 第5圖係由第4圖所示之原始圖案與選擇之參數a， 所得之反轉圖案。如第5圖所示，先將主動區圖案40與 多晶矽圖案向外擴張一參數a的線寬，參數a例如爲 1.4μπι :並將井區圖案44的邊界向內兩側各擴張一參數b 的線寬，參數b例如爲0.9μηι。若上述之擴張範圍有互爲 請先閱讀背面之注意事項再填寫本頁) ---I--- I 訂·--I----- 梦 ί 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中园國家標準（CNS)A4規格（210 X 297公釐） 43.1557 26l5twf.doc/006 A7 經濟部中央標準局貝工消费合作社印製 五、發明説明（/ ) 本發明是有關於一種具有移位虛置圖案（Shift Dummy Pattern)之主動區圖案的設計方法，且特別是有關於一種在 淺溝渠隔離（Shallow Trench Isolation)製程中，對主動區圖 案之設計加入移位虛置圖案，以使得後續之化學機械硏磨 (CMP)等製程，可得到較佳之平坦化結果，並大大地改善 金屬線間不同寄生電容所產生的電路問題。 隨著積體電路設計趨於複雜，在製程中將線寬減少到 Ιμπι以下，已使CMOS的溝渠隔離（Trench Isolation)發展 有所限制。因爲習知利用化學機械硏磨技術來達成平坦化 的過程中，如果在底層(Under Layer)的圖案有元件間距超 過ΙΟμηι以上，經硏磨後會在此無元件區域產生碟形的凹 槽，而無法達到此全面平坦化的要求，此即所謂的碟形效 應(Dishing Effect)。請參照第1Α〜1D圖所示，爲傳統利用 化學機械硏磨技術的淺溝渠隔絕製程的剖面圖，此習知的 方法詳述如下： 請參照第1A圖，在一半導體基底，例如是矽基底10 表面形成一墊氧化層11，接著形成一介電層12覆蓋在墊 氧化層11上，例如是一氮化矽層，隨後上光阻並以光學 微影和蝕刻程序而形成元件區Π，再利用此元件區上的光 阻(未顯示）爲罩幕，在矽基底10上以非等向性蝕刻一定的 深度而形成複數個溝渠。請參照第1B圖，在該矽基底1〇 表面利用化學氣相沈積法(CVD)沈積一氧化層14，接著， 利用化學機械硏磨法硏磨氧化層I4並以第一介電層12之 表面爲硏磨終止層，而形成複數個溝渠隔離區15，16，如 3 ---^------------IT------'線 C請先閲贫背面之注意事項再填寫本頁) 本紙張尺度適用中困國家標準（CNS ) A4規格（2!0X297公釐） 如557 經濟部中央標李局員工消費合作社印製 五、發明説明（丄） 第1C圖所示。接著去掉元件區介電層的殘留部份’而在 矽基底10表面形成閘氧化層17及多晶矽層18,而完成了 溝渠隔絕製程。 然而，並非每一個溝渠隔絕區都等寬度，其間具有相 當顯著的差異，如圖示，溝渠隔離區16就比溝渠隔離區W 大，於是，在平坦化的製程中，多晶矽層18塡充於溝渠 隔絕區15的部份就可得到相當平坦的表面，而塡充於溝 渠隔絕區16的部份則呈現一平緩下凹的表面。因此，傳 統的淺溝渠隔離技術，祇能達到局部平坦化（Locai Planarization)的效果，卻無法獲致全面平坦化（Global Planarization)的目的。 故而，傳統更以將虛置圖案加入於主動區圖案的設計 方法來改善CMP製程的均勻性，然而卻又產生了增加寄 生電容的問題，而影響元件的效能表現。由於覆蓋於不同 虛置圖案上方之金屬線，會因不同的寄生電容而導致不同 的時間延遲，而導致電路問題。請參照第2圖，其繪示依 照傳統具有虛置圖案之主動區圖案的設計方法示意圖。如 第2圖所示，金屬線20, 22係覆蓋於不同之虛置圖案24 上方，例如金屬線20覆蓋於一行的虛置圖案24上方，但 金屬線22覆蓋於二行的虛置圖案間，故而對於金屬線22 與24而言，會有不同的寄生電容’在實際電路之應用上’ 會產生不同時序的困擾，例如RC(電阻電容)延遲的問題° 因此本發明的主要目的，在於提供一種具有移位虛置 圖案之主動區圖案的設計方法，將欲加入於原始圖案之虛 4 ：------—择------訂------ '威 f (請先閲诜背面之注意事項再填寫本頁) 本紙張尺度適用中囷固家揉準（CNS} A4規格（210X297公嫠） 411557 28l5twf.doc/〇06 A7 B7 經濟部中央標牟局貝工消費合作杜印裝 五、發明説明（i ) 置圖案，經過移位之後再加入於原始圖案中，使得其後製 程所得覆蓋於虛置圖案上方之各金屬線，具有相當之寄生 電容，而得到相當之RC時間延遲。 根據本發明的目的，提出一種具有移位虛置圖案之主 動區圖案的設計方法，用以在具有一主動區圖案、一多晶 矽圖案與一井區圖案之一積體電路製程上完成。首先，對 該主動區圖案向外擴張一第一參數之線寬，而得到一第一 圖案區，並對多晶矽圖案向外擴張第一參數之線寬而得到 一第二圖案區，同時並對并區圖案向兩側擴張第二參數之 線寬而得到一第三圖案區。然後’對第一圖案區' 第二圖 案區與第三圖案區作NOR邏輯運算而得到一第四圖案區。 接著，提供包括有複數個虛置圖案元之一虛置陣列圖案， 並對虛置圖案元作一第一等距縱向移位與一第二等距橫向 之移位而得到一移位虛置陣列圖案°之後’對第四圖案區 與移位虛置陣列圖案作AND邏輯運算而得到一共有圖案。 再對共有圖案向外擴張第三參數之線寬’而得到一虛置圖 案。最後，對第一圖案區與虛置圖案作OR邏輯運算而得 到本發明具有移位虛置圖案之主動區圖案。藉由本發明提 供之具有移位虛置圖案之主動區圖案的設計方法，用以改 善全面平坦化之製程的均勻性，同時並得以大大地改善金 屬線間之不同寄生電容所產生的電路問題。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂’ 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 5 I ϋ^— - I II I 士·- I . < <:#先閲•讀背面之注意事項再填寫本頁) 訂 線 本紙張尺度適用十國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央橾準局貝工消費合作社印装 411557 28i5twf,doc/〇〇^ A7 五、發明説明t半） 圖式之簡單說明： 第1A〜1D圖所示乃傳統淺溝渠隔離之製程中’利用化 學機械硏磨技術平坦化的製程剖面圖； 第2圖繪示依照傳統具有虛置圖案之主動區圖案的設 計方法示意圖； ^ 第3圖繪示依照本發明一較佳實施例的一種具有移位 虛置圖案之主動區圖案的設計方法示意圖； 第4圖繪示依照本發明實施例之設計方法所使用的原 始圖案； 第5圖繪示依照第4圖所示之原始圖案與選擇之參數 a與b所得之反轉圖案； 第6A圖繪示依照本發明實施例之設計方法所使用的 一虛置陣列圖案； 第6B圖繪示依照第6A圖所示之虛置陣列圖案移位後 之移位虛置陣列圖案； 第7A圖繪示依照第5圖及第6B圖所得之共有圖案； 第7B圖繪示依照第7A圖所示之共有圖案所得之虛置 圖案；以及 第8圖繪示依照第4圖與第7B圖所得之本發明具有 移位虛置圖案之主動區圖案。 標號說明： 10 :矽基底 11 :墊氧化層 12 :介電層 13 :元件區 14 :氧化層 15，16 :溝渠隔離區 6 本紙張尺度逍用中國國家梂準{CNS) M规格（210x297公楚） ---^-------裝------ΪΤ-----d. c锖先閲#背面之注意事項存填寫本頁) 411557 2815twf1/002 第87107569號說明書修正頁 'VA7 B7 ΐ像:'_刁 1 %正“日期;8S/4/18 '··.' 卜 ,-rW； 18 :多晶矽層 24，34 ·虛置圖案 42 :多晶矽圖案 50 :第一·圖案區 60 *虛置圖案兀 五、發明說明（t ) Π :閘氧化層 20, 22, 30, 32 :金屬線 40 :主動區圖案 44 :井區圖案 52 :第二圖案區 實施例 請參照第3圖，其繪示依照本發明一較佳實施例的一 種具有移位虛置圖案之主動區圖案的設計方法示意圖。如 第3圖所示，金屬線30, 32係覆蓋於不同之虛置圖案34 上方。然，由於虛置圖案34均經過移位，例如相鄰不同 之虛置圖案34均以一定之位移排列於主動區圖案間，故 而使得金屬線30所覆蓋之虛置圖案34與金屬線32所覆 .蓋之虛置圖案，有相當之寄生電容。因此，對於金屬線32 與30而言，在實際電路之應用上，具有較佳之效能表現， 而無不同的RC延遲問題產生。 第4圖是本發明實施例之設計方法所使用的原始圖 案，在積體電路佈局（Layout)之原始圖案中，例如包括有 所需之主動區圖案40，多晶矽圖案42，與井區（Well)圖案 44 = 第5圖係由第4圖所示之原始圖案與選擇之參數a， 所得之反轉圖案。如第5圖所示，先將主動區圖案40與 多晶矽圖案向外擴張一參數a的線寬，參數a例如爲 1.4μπι :並將井區圖案44的邊界向內兩側各擴張一參數b 的線寬，參數b例如爲0.9μηι。若上述之擴張範圍有互爲 請先閱讀背面之注意事項再填寫本頁) ---I--- I 訂·--I----- 梦 ί 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中园國家標準（CNS)A4規格（210 X 297公釐） 經濟部中央標準局員工消費合作社印餐 28l5twf.doc/006 Λ7 B7 五、發明説明（厶） 重疊，則予以合倂成同一區域，擴張後之圖案爲一第一圖 案區50。然後，將第一圖案區50以反相邏輯運算，例如 是以色調反轉處理（Reverse Tone)後，得到一第二圖案區 52，故而第二圖案區52係對主動區圖案40 '多晶矽圖案 42與井區（Well)圖案44擴張後之圖案再作NOR邏輯運算 而得。 第6A圖係本發明實施例之設計方法所使用的一虛置 陣列圖案，此虛置陣列圖案具有複數個虛置圖案元60，且 呈陣列（array)形式排列，而虛置圖案元60間互以一參數d 的距離相隔，並各具有一參數e的寬度和參數f的長度， 其中，參數d例如爲1.8μηι、參數e例如爲0.2μπι、參數f 例如爲2.2μιη。 請參照第6Β圖，其繪示係根據第6Α圖移位後之移位 虛置陣列圖案，係對第6Α圖中將相鄰之虛置圖案元60各 作一例如爲〇.#m等距縱向與一例如亦爲0.2μιη等距橫向 之移位。 請參照第7Α圖，其繪示根據第5圖及第6Β圖二者所 得之共有圖案。第7Α圖所示之共有圖案，例如是對第5 圖之第二圖案區52與第6Β圖所示之移位陣列圖案作AND 邏輯運算而得，故而包括所有第5圖之第二圖案區52與 第6B圖所示之移位陣列圖案中的共同部份。 接著，對第7A圖所示之共有圖案，向外擴張一參數c 的線寬，而得到如第7B圖所示之虛置圖案。由於第7B圖 所示之虛置圖案係由第7A圖所示之共有圖案轉換而來， S 本紙張尺度適用中國國家標f<CNsiA4&格（210X297公釐) ---^------—t------IT------.^ .(請先Μ讀背面之注意事項再填寫本頁) 411557 2 8 15 twf - doc /0 06 a7 B7 經濟部中央椋準局負工消費合作社印掣 五、發明説明（7) 故而包括有相同數目之圖案區塊，所不同者乃在於虛置圖 案係沿著共有圖案週邊向外延伸一參數C的線寬所得，此 參數C例如爲0·4μιη。 最後，請參照第S圖，其繪示根據第4圖所示之主動 區圖案40與第7Β圖所示之虛置圖案所得之具有移位虛置 圖案之主動區圖案。第8圖所示之具有移位虛置圖案之主 動區圖案包括有第4圖所示之主動區圖案40與第7Β圖所 示之虛置圖案的所有面積。然後，再利用此一具有移位虛 置圖案的主動區圖案來完成後續淺溝渠隔離製程之步驟。 因此，本發明的特徵之一是在原有之主動區圖案中加 入虛置圖案以利後續半導體之平坦化製程。 本發明的特徵之二是加入之虛置圖案係經移位後之結 果，故而在後續製程中，加入於主動區圖案上方之各金屬 線，具有相當之寄生電容。 本發明的特徵之三是由於後續各金屬線具有相當之寄 生電容，因而具有相當之RC時間延遲，增加電路結構之 效能表現。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 9 本紙張尺度適用Ί1國國家梂準（CNS ) A4洗格（210X297公釐） --1------- 1^.------11------.^ (诗先閲讀背面之注意事項再填寫本頁)411557 2815twf1 / 002 No. 87107569 Revised Sheet 'VA7 B7 Image:' _ Diao 1% Positive 'Date; 8S / 4/18' ··. 'Bu, -rW; 18: Polycrystalline silicon layer 24, 34 · Void Pattern 42: polycrystalline silicon pattern 50: first pattern region 60 * dummy pattern V. invention description (t) Π: gate oxide layer 20, 22, 30, 32: metal line 40: active region pattern 44: well region pattern 52: Embodiment of the second pattern area Please refer to FIG. 3, which illustrates a schematic diagram of a method for designing an active area pattern with a shifted dummy pattern according to a preferred embodiment of the present invention. As shown in FIG. The lines 30 and 32 cover different dummy patterns 34. However, since the dummy patterns 34 are all shifted, for example, the adjacent different dummy patterns 34 are arranged between the active area patterns with a certain displacement, so that The dummy pattern 34 covered by the metal line 30 and the metal line 32 are covered. The dummy pattern covered has considerable parasitic capacitance. Therefore, for the metal lines 32 and 30, it has a better effect on the actual circuit application. Performance without different RC delay problems. Figure 4 shows the design of the embodiment of the present invention. The original pattern used in the design method includes the required active area pattern 40, polycrystalline silicon pattern 42, and well pattern 44 in the original pattern of the integrated circuit layout (Figure 5). The original pattern shown in Figure 4 and the selected parameter a, the resulting inverted pattern. As shown in Figure 5, the active area pattern 40 and the polycrystalline silicon pattern are expanded outward by a parameter a line width, and the parameter a is, for example, 1.4μπι: Expand the boundary of the well pattern 44 inwardly on both sides by a line width of the parameter b, for example, the parameter b is 0.9μηι. If the above expansion ranges are mutually exclusive, please read the precautions on the back before filling this page ) --- I --- I order · --I ----- Meng ί Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives This paper is printed in accordance with the National Park Standard (CNS) A4 (210 X 297 mm) ) 43.1557 26l5twf.doc / 006 A7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) The present invention relates to a method for designing an active area pattern with a shift dummy pattern , And especially about a kind of isolation in shallow trenches In the Shallow Trench Isolation process, a shift dummy pattern is added to the design of the active area pattern, so that subsequent processes such as chemical mechanical honing (CMP) can obtain better planarization results and greatly improve the difference between metal lines. Circuit problems caused by parasitic capacitance. As integrated circuit designs become more complex, reducing the line width to less than 1 μm in the manufacturing process has limited the development of trench isolation in CMOS. Because it is known to use chemical mechanical honing technology to achieve the flattening process, if the pattern of the underlying layer has an element pitch of more than 10 μηι, a dish-shaped groove will be generated in this element-free area after honing. However, this comprehensive flattening requirement cannot be achieved, which is the so-called dishing effect. Please refer to Figs. 1A to 1D, which are cross-sectional views of a conventional shallow trench isolation process using chemical mechanical honing technology. This conventional method is described in detail below. Please refer to Fig. 1A, a semiconductor substrate, such as silicon A pad oxide layer 11 is formed on the surface of the substrate 10, and then a dielectric layer 12 is formed on the pad oxide layer 11 to cover the pad oxide layer 11, such as a silicon nitride layer. Then, a photoresist is formed and an element area is formed by an optical lithography and etching process. Then, a photoresist (not shown) on the element region is used as a mask to form a plurality of trenches on the silicon substrate 10 by anisotropic etching to a certain depth. Referring to FIG. 1B, an oxide layer 14 is deposited on the surface of the silicon substrate 10 by a chemical vapor deposition (CVD) method. Then, the oxide layer I4 is honed by a chemical mechanical honing method and the first dielectric layer 12 is formed. The surface is a honing stop layer, and a plurality of trench isolation areas 15, 16 are formed, such as 3 --- ^ ------------ IT ------ 'Line C, please read Note on the back, please fill in this page again.) This paper size is applicable to the National Standard for Difficulties (CNS) A4 (2! 0X297 mm). For example, 557 Printed by the Central Consumer Bureau of the Ministry of Economic Affairs. Figure 1C. Then, the residual portion of the dielectric layer in the device region is removed, and a gate oxide layer 17 and a polycrystalline silicon layer 18 are formed on the surface of the silicon substrate 10, and the trench isolation process is completed. However, not every trench isolation area has the same width, and there are quite significant differences. As shown in the figure, the trench isolation area 16 is larger than the trench isolation area W. Therefore, during the planarization process, the polycrystalline silicon layer 18 is filled with A part of the trench isolation area 15 can obtain a fairly flat surface, while a part of the trench isolation area 16 presents a gently concave surface. Therefore, the conventional shallow trench isolation technology can only achieve the effect of Locai Planarization, but cannot achieve the purpose of Global Planarization. Therefore, traditionally, the design method of adding dummy patterns to the active area pattern is used to improve the uniformity of the CMP process. However, the problem of increasing the parasitic capacitance has been generated, which affects the performance of the device. Due to the metal lines covering the different dummy patterns, different time delays due to different parasitic capacitances will cause circuit problems. Please refer to FIG. 2, which illustrates a schematic diagram of a design method of an active area pattern having a dummy pattern according to a conventional method. As shown in FIG. 2, the metal lines 20 and 22 cover the different dummy patterns 24. For example, the metal lines 20 cover the dummy patterns 24 on one line, but the metal lines 22 cover the dummy patterns on the second line. Therefore, for the metal lines 22 and 24, there will be different parasitic capacitances 'in practical circuit applications' which will cause different timing problems, such as the problem of RC (resistance-capacitance) delay. Therefore, the main purpose of the present invention is to Provide a design method of active area pattern with shifted dummy pattern, which will be added to the original pattern of the imaginary 4 (Please read the notes on the back of the card before filling out this page.) This paper size is applicable to the standard of Chinese paper (CNS) A4 (210X297) 411557 28l5twf.doc / 〇06 A7 B7 Industrial and consumer cooperation Du Yinzhuang 5. Description of the invention (i) Place the pattern, add it to the original pattern after shifting, so that the subsequent process covers the metal lines above the dummy pattern, and has considerable parasitic capacitance, and A comparable RC time delay is obtained. A method for designing an active area pattern with a shifted dummy pattern is proposed to be completed on an integrated circuit process having an active area pattern, a polycrystalline silicon pattern, and a well area pattern. First, the active area pattern Expand a line width of a first parameter outward to obtain a first pattern region, and expand a line width of a first parameter to a polysilicon pattern to obtain a second pattern region, and expand the pattern of the parallel region to both sides A third pattern area is obtained by using the line width of the second parameter. Then, a NOR logic operation is performed on the second pattern area and the third pattern area to obtain a fourth pattern area. Next, a plurality of One of the dummy pattern elements is a dummy array pattern, and a first equidistant vertical shift and a second equidistant lateral shift are performed on the dummy pattern element to obtain a shifted dummy array pattern. The four pattern areas and the shifted dummy array pattern are ANDed together to obtain a common pattern. Then, the common pattern is expanded outward by the third parameter's line width 'to obtain a dummy pattern. Finally, the first pattern area and the dummy pattern are obtained. Set pattern An OR logic operation is performed to obtain the active area pattern with a shifted dummy pattern of the present invention. The design method of the active area pattern with a shifted dummy pattern provided by the present invention is used to improve the uniformity of the overall planarization process, At the same time, the circuit problems caused by the different parasitic capacitances between the metal lines can be greatly improved. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is given below, in conjunction with the attached The drawings are described in detail as follows: 5 I — ^ —-I II I 士 ·-I. ≪ <:# Read the notes on the back before filling this page) Alignment This paper size is applicable to ten countries Standard (CNS) A4 specification (210X297 mm) Printed by the Central Bureau of Quasi-Ministry of Economy, Ministry of Economic Affairs, Printed Paper Cooperative, 411557 28i5twf, doc / 〇〇 ^ A7 5. Brief description of the invention: Brief description of the drawings: Figures 1A ~ 1D Shown is a cross-sectional view of a process using a chemical mechanical honing technique to planarize a conventional shallow trench isolation process; FIG. 2 shows a schematic diagram of a design method according to a conventional active area pattern with a dummy pattern; ^ FIG. 3 shows A schematic diagram of a design method of an active area pattern with a shifted dummy pattern according to a preferred embodiment of the present invention; FIG. 4 shows the original pattern used in the design method according to the embodiment of the present invention; The original pattern shown in FIG. 4 and the inverted pattern obtained from the selected parameters a and b; FIG. 6A shows a dummy array pattern used in the design method according to the embodiment of the present invention; The shifted dummy array pattern shown in FIG. 6A is shifted. The shifted dummy array pattern shown in FIG. 6A shows the common pattern obtained according to FIGS. 5 and 6B. The graph of FIG. 7B shows the common pattern obtained according to FIG. 7A. The dummy pattern obtained by sharing the patterns; and FIG. 8 shows the active area pattern with the shifted dummy pattern of the present invention obtained according to FIGS. 4 and 7B. DESCRIPTION OF SYMBOLS: 10: silicon substrate 11: pad oxide layer 12: dielectric layer 13: element area 14: oxide layer 15, 16: trench isolation area 6 This paper is based on the Chinese National Standard {CNS) M size (210x297mm) (Chu) --- ^ ------- install ------ ΪΤ ----- d. C 锖 Read first #Notes on the back and fill in this page) 411557 2815twf1 / 002 Manual No. 87107569 Correction page 'VA7 B7 Artifact:' _ Diao 1% positive 'date; 8S / 4/18' ··. 'Bu, -rW; 18: Polycrystalline silicon layer 24, 34 · Dummy pattern 42: Polycrystalline silicon pattern 50: No. I. Pattern area 60 * Dummy pattern V. Invention description (t) Π: Gate oxide layer 20, 22, 30, 32: Metal line 40: Active area pattern 44: Well area pattern 52: Second pattern area Example Please refer to FIG. 3, which illustrates a schematic diagram of a method for designing an active area pattern with a shifted dummy pattern according to a preferred embodiment of the present invention. As shown in FIG. 3, the metal lines 30 and 32 cover different Above the dummy pattern 34. However, since the dummy patterns 34 are all shifted, for example, adjacent dummy patterns 34 are arranged between the active area patterns with a certain displacement, so that the metal line 30 The covered dummy pattern 34 and the metal line 32 are covered. The covered dummy pattern has considerable parasitic capacitance. Therefore, for the metal lines 32 and 30, it has better performance in practical circuit applications, and No different RC delay problems occur. Figure 4 is the original pattern used in the design method of the embodiment of the present invention. The original pattern of the integrated circuit layout (Layout) includes, for example, the required active area pattern 40, polycrystalline silicon Pattern 42, and Well pattern 44 = Figure 5 is the inverted pattern obtained from the original pattern shown in Figure 4 and the selected parameter a. As shown in Figure 5, the active area pattern 40 is first Expand the line width of parameter a with the polycrystalline silicon pattern outward, for example, parameter a is 1.4 μm: and expand the boundary of the well pattern 44 to the inner side and the line width of parameter b, and the parameter b is, for example, 0.9 μm. The scope of expansion is mutual, please read the notes on the back before filling this page) --- I --- I Order --- I ----- Dream Standards apply to China National Park Standard (CNS) A4 (210 X 297 male) (%) Employees of the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, printed meals 28l5twf.doc / 006 Λ7 B7 V. Description of the Invention (厶) If they overlap, they are combined into the same area. The expanded pattern is a first pattern area 50. Then, The first pattern region 50 is operated in reverse logic, for example, after a tone reverse process (Reverse Tone) to obtain a second pattern region 52. Therefore, the second pattern region 52 is an active region pattern 40 'polycrystalline silicon pattern 42 and The expanded pattern of the well pattern 44 is obtained by performing a NOR logic operation. FIG. 6A is a dummy array pattern used in the design method of the embodiment of the present invention. The dummy array pattern has a plurality of dummy pattern elements 60 and is arranged in an array. There are 60 dummy pattern elements. They are separated from each other by a distance of a parameter d, and each has a width of a parameter e and a length of a parameter f, where the parameter d is, for example, 1.8 μm, the parameter e is, for example, 0.2 μm, and the parameter f is, for example, 2.2 μm. Please refer to FIG. 6B, which shows a shifted dummy array pattern after shifting according to FIG. 6A, and each of adjacent dummy pattern elements 60 in FIG. Displacement from the longitudinal direction to an equidistant transverse direction, for example, 0.2 μm. Please refer to Fig. 7A, which shows a common pattern obtained from both Figs. 5 and 6B. The common pattern shown in FIG. 7A is obtained by performing an AND logic operation on the second pattern area 52 in FIG. 5 and the shift array pattern shown in FIG. 6B, and therefore includes all the second pattern areas in FIG. 5 52 and a common portion in the shift array pattern shown in FIG. 6B. Next, for the common pattern shown in FIG. 7A, a line width of a parameter c is expanded outward to obtain a dummy pattern as shown in FIG. 7B. Since the dummy pattern shown in Fig. 7B is converted from the common pattern shown in Fig. 7A, the paper size of this paper applies the Chinese national standard f < CNsiA4 & grid (210X297 mm) --- ^ ---- --- t ------ IT ------. ^. (Please read the notes on the back before filling this page) 411557 2 8 15 twf-doc / 0 06 a7 B7 Central Ministry of Economic Affairs 椋Printed by the quasi-office consumer cooperatives V. Description of the invention (7) Therefore, the same number of pattern blocks are included, the difference is that the dummy pattern is obtained by extending the line width of the parameter C along the periphery of the common pattern. This parameter C is, for example, 0.4 μm. Finally, please refer to FIG. S, which shows an active area pattern having a shifted dummy pattern obtained from the active area pattern 40 shown in FIG. 4 and the dummy pattern shown in FIG. 7B. The active area pattern with the shifted dummy pattern shown in FIG. 8 includes all areas of the active area pattern 40 shown in FIG. 4 and the dummy pattern shown in FIG. 7B. Then, the active area pattern with the shifted dummy pattern is used to complete the subsequent shallow trench isolation process steps. Therefore, one of the features of the present invention is to add a dummy pattern to the original active area pattern to facilitate the subsequent planarization process of the semiconductor. The second feature of the present invention is that the added dummy pattern is the result of displacement. Therefore, in the subsequent process, each metal line added above the active area pattern has a considerable parasitic capacitance. The third feature of the present invention is that since the subsequent metal lines have equivalent parasitic capacitances, they have considerable RC time delays and increase the performance of the circuit structure. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 9 The size of this paper is applicable to the national standard of one country (CNS) A4 washing grid (210X297 mm) --1 ------- 1 ^ .------ 11 ------. ^ ( (Read the notes on the back of the poem before filling out this page)