TW410416B

TW410416B - Method for forming fuse in DRAM

Info

Publication number: TW410416B
Application number: TW88109980A
Authority: TW
Inventors: Wan-Yi Lian
Original assignee: Vanguard Int Semiconduct Corp
Priority date: 1999-06-15
Filing date: 1999-06-15
Publication date: 2000-11-01

Abstract

The invention provides a method for forming improved fuse structure by removing excessive components in a DRAM circuit. The method includes the following steps. (a) Form a fuse in a second poly-silicide layer with silicon nitride and insulating spacer. (b) After forming a capacitor node and interconnecting the first metal layer (M1), the first metal layer (M1) is etched to define via holes, and also define a fuse opening on top of the fuse. Tungsten plugs are provided as metal interconnection in the via holes and a patterned second metal layer (M2) are used to protect the via holes form over-etching when the fuse opening is completed. (c) Next, a silicon nitride layer and a poly-silicide layer are deposited for being used as the passivation layer of the DRAM. The present method is able to reduce the number of required photo-masks, and avoid a short circuit problem caused by residual metal in the fuse region. (d) HDP chemical vapor deposition is utilized to form an USG layer, so as to prevent moisture from entering neighboring circuits and increase the reliability of the chip.

Description

410416 五 '發明說明（1) 本發明係有關於一種積體電路（integration circuit ，1C)之製造方法，特別有關於一種在半導體積體電路上-形成改良之保險絲構造的方法，例如是動態隨機記憶體（410416 Five 'invention description (1) The present invention relates to a method for manufacturing an integrated circuit (1C), in particular to a method for forming an improved fuse structure on a semiconductor integrated circuit, such as dynamic random Memory(

Dynami.c Random Access Memory，其後以DRAM 簡稱之）。這個方法係使用單一光罩步驟以於一保護層中敍刻該保險絲之開口，其中，在該DRAM晶片上並同時形成開口作為焊接墊（bonding pad)。半導體製程技術之進步，如高解析度的光學微影技術 (photolithography)與非等向性電藥敍刻，降低了半導體元件之特徵大小，而增加其積集度。不幸的，由於該半導〇體元件之積集度上升，且晶片上分離的元件數目增加，許多IC元件之產品良率（晶片良率）遂下降；例如，一種積集度上升而良率下降之電路元件係為DRAM，在一晶月上一般具有64M位元；在西元2000年之後，記憶體單元的數目相信會增加至超過卜4G位元，且沒有利用剩餘的單元及修理產物之方法，將更難以達到高的最後產物良率。克服在DRAM元件上之低良率的一個辦法係為提供額外的記憶體單元的列（row)，並將各單元的每一列融合在一起，一般’係於多個Μ位元之DRAM中使用雷射來連結（融合 )’以無法損壞記憶體單元的列，並修正該位置解^器，P 以致能夠選擇取而代之記憶體單元剩餘的列。這些保險絲構造需要額外的製程步驟因而增加產品之成本；通常所需之步驟係為三個光罩步驟：第二個光^步驟係用於打開在該保險絲上之絕緣層，第二個光罩則用於Dynami.c Random Access Memory, hereinafter abbreviated as DRAM). This method uses a single mask step to engrave the opening of the fuse in a protective layer, wherein an opening is simultaneously formed on the DRAM wafer as a bonding pad. Advances in semiconductor process technology, such as high-resolution photolithography and anisotropic electro-pharmaceutical engraving, have reduced the feature size of semiconductor devices and increased their accumulation. Unfortunately, the product yield (wafer yield) of many IC components has decreased due to the increase in the integration level of the semiconductor components and the increase in the number of separated components on the wafer; for example, an increase in the integration level and a yield The falling circuit element is DRAM, which generally has 64M bits on a crystal moon; after 2000 AD, the number of memory cells is believed to increase to more than 4G bits, and the remaining units and repair products are not used Method, it will be more difficult to achieve high final product yields. One way to overcome the low yield on DRAM devices is to provide additional rows of memory cells and fuse each column of each cell together. It is generally used in DRAMs with multiple M bits. The laser is used to link (fusion) the row of the memory unit so as not to damage it, and correct the position resolver P so that the remaining row of the memory unit can be selected instead. These fuse constructions require additional process steps and thus increase the cost of the product; the steps usually required are three photomask steps: the second photo ^ step is used to open the insulating layer on the fuse, and the second photomask Is used

第First

410416 五、發明說明（2) ' 打開在焊接墊上的氮化矽層’以及第三個光罩係用於蝕刻在聚亞醯胺保護層中的開口。減少製程費用的一個辦法係為將位於保險絲上方的保護層中形成開口的製程步驟結合，並同時在DRAM晶片上的其他電路元件產生開口，包括焊接墊開口。410416 V. Description of the invention (2) 'Open the silicon nitride layer on the solder pad' and the third photomask is used to etch the opening in the polyurethane protective layer. One way to reduce process costs is to combine the process steps of forming an opening in the protective layer above the fuse, while creating openings in other circuit components on the DRAM chip, including solder pad openings.

為了能夠更加認識與形成保險絲及介層洞開口之整合製程步驟有關之問題，一概略的保險絲結構之剖面圖以及經過疋義其圖案之第一金屬層及其開口係示於第i圖中，第1圖顯示一基板10 ^ 一般此基板1〇係有一部份徹底具有擴散之半導體裝置，如具有定義過圖案之第一複晶矽化金，層（未顯示）以作為閘電極之場效電晶體。一絕緣層i 2 接著形成於該基板上以電子式地隔絕元件（這些元件並未詳述於圖示中）；第1圖顯示一經定義圖形的第二複晶矽化金屬層14’其用於形成電子式之内連接點，如DRAM元件之位元線。通常這些定義過圖形之複晶矽化金屬層14包括部女用以作為保險絲的部分，在此亦標號為14 ;接下來，沈積一第二絕緣層1 6 ’且在形成介層洞（未顯示）之後，係沈積一第一金屬（Ml)層18 ’並定義其圖案以作為下一層電子内連接點。一般，金屬層18係為鋁、銅之合金，且當mi層係利用光學微影術及電漿蝕刻製程來定義其圖案時，在其表面具有作為抗反射塗料（antireflective coating, ARC )之氮化鈦層20。接著，沈積一第三絕緣層22以絕緣該圖案化之具有ARC層20之Μ1層；現在，要钱刻該位於保險絲 14上方之絕緣層22與16以提供雷射光接近亦且擦過的機會In order to be able to better understand the problems related to the integration process steps of forming fuses and interstitial hole openings, a schematic cross-sectional view of the fuse structure and the first metal layer and its opening through the pattern are shown in Figure i. Figure 1 shows a substrate 10 ^ Generally, the substrate 10 is a part of a semiconductor device with complete diffusion, such as a first polycrystalline gold silicide with a defined pattern, and a layer (not shown) is used as the field effect of the gate electrode. Crystal. An insulating layer i 2 is then formed on the substrate to electrically isolate the components (the components are not detailed in the illustration); FIG. 1 shows a second pattern of a polycrystalline silicided metal layer 14 ′ with a defined pattern, which is used for Form electronic interconnection points, such as bit lines for DRAM devices. Generally, the patterned polycrystalline silicided metal layer 14 includes a part for a fuse, which is also designated as 14 here. Next, a second insulating layer 16 'is deposited and a via hole (not shown) is formed. ) After that, a first metal (Ml) layer 18 ′ is deposited and its pattern is defined as the next-level electron interconnection point. Generally, the metal layer 18 is an alloy of aluminum and copper, and when the mi layer is defined by an optical lithography and plasma etching process, the surface has nitrogen as an antireflective coating (ARC). Of titanium layer 20. Next, a third insulating layer 22 is deposited to insulate the patterned M1 layer with the ARC layer 20; now, the insulating layers 22 and 16 above the fuse 14 are required to be engraved to provide the opportunity for the laser light to approach and wipe away

410416 五、發明說明（3) -- ，並同時蝕刻該絕緣層22至該M1層丨8以作為開口 4，而與下一層的第二金屬（M2)做接觸。於此習知之方法中，係使用單一光罩來蝕刻開口 2與4，而減低製程之費用。但是很不幸的，當蝕刻保險絲丨4上方之開口 2時，作為接觸的開口4之過度蝕刻對其下方的^層18會造成損傷，而相對地影響到該介層洞接觸電阻（Rc)以及金屬的電致遷移 (eleCti*oraigration)時間。更甚於此，由於過度的蝕刻，介層洞的形狀會降級；當M2層沈積並定義其圖案時，則會造成其他的問題；當非等向性地蝕刻該位於保險絲丨4上之開口2中之M2層24，因為其階梯的高度高（高縱橫比），因此要完全的移除殘留於保險絲丨4之絕緣侧壁上的金屬2 4，是困難的。曾經有人提出各種在1C上製作保險絲的辦法，例如， Okazaki ’美國專利第5753539號，其教導了一個在與一接觸塾相同的平面上製作一保險絲結構的方法，因此 Okazak 1能夠使用單一光罩於絕緣層中蝕刻保險絲之開口與接觸塾之開口。由於保險絲元件的開口要比接觸墊的開口小付夕’在钱刻過程間之微負載效應（m i cr〇 1 〇ad丨ng e f f e c t)會造成保險絲上之钱刻速率較慢，且因此該絕緣層之薄的部分維持於該保險絲之上方以保護該保險絲，防止水氣進入’而該接觸墊-則暴露於該接觸墊開口。 Fukahara et al.，於美國專利第5650355號係使用不同的方法以形成保險絲及焊接墊，其中，當蝕刻該焊接墊之開口時’該保險絲係由一氮氧化層所保護e Chen，美國專第7頁 4Ϊ0416 五、發明說明（4) 利第5712206號與5538924號則分別說明製造水氣透不過的防護罩以及水氣阻障層的方法；此方法包括環繞著保險絲開口形成一阻住水氣防護罩或層以預防該半導體電路之水氣殘留在保險絲之區域。Takayania et al，β國寄利第 45 3 6 949號，說明了一種不需增加費用，而藉由每一次絕緣層係形成於IC導線之上方，在保險絲上方餘刻而能更精確地形成保險絲開口的方法。Board man et al. 於美國專利第52 9 0 734號則說明了一種形成可靠的防止融化之連結 ’其中，一高電阻物質（1〜2G Ω )，例如是非晶石夕，能利用電壓穿過該非晶矽鍵結而改變，因此其電阻降低至大約 2 0 0 Ω。這個方法取代了鈦及鎢化鈦保險絲，且於丨c上佔據了較少的空間。在半導體產業中仍舊十分需要改善製造保險絲結構之有效生產費用的方式。因此，本發明的一個主要目的在於提供一種在IC上經改良之保險絲構造，係利用單一光罩以同時蝕刻出保險絲開口作為因雷射加熱以燒掉保險絲，與蝕刻出用以於保護層中作為焊接墊接觸之開口。本發明之其他目的在於使用鎢栓塞於介層洞中以避免當介層洞與部分被触刻之保險絲開口同時利用單一光阻餘刻罩幕而埠行蝕刻時，第一金屬層過度之過蝕刻。本發明之其他目的在於當形成該dram元件之焊接塾開口時’利用單一光罩以完成於聚亞醯胺/氩化矽保護層中之保險絲開口，並因此提供一更有效的製造程序。410416 V. Description of the invention (3)-, and simultaneously etch the insulating layer 22 to the M1 layer 8 as the opening 4 and make contact with the second metal (M2) of the next layer. In this conventional method, a single photomask is used to etch the openings 2 and 4, thereby reducing the cost of the process. Unfortunately, when the opening 2 above the fuse 4 is etched, the over-etching of the opening 4 as a contact will cause damage to the ^ layer 18 below it, and will relatively affect the via hole contact resistance (Rc) and Electromigration (eleCti * oraigration) time of metal. What's more, the shape of the via hole will be degraded due to excessive etching; when the M2 layer is deposited and its pattern is defined, other problems will be caused; when the opening on the fuse 4 is anisotropically etched Since the M2 layer 24 in 2 has a high step height (high aspect ratio), it is difficult to completely remove the metal 2 4 remaining on the insulating sidewall of the fuse 4. Various methods have been proposed for making fuses on 1C. For example, Okazaki 'U.S. Patent No. 5,753,539 teaches a method of making a fuse structure on the same plane as a contact pad, so Okazak 1 can use a single mask. The opening of the fuse and the opening of the contact are etched in the insulating layer. Since the opening of the fuse element is smaller than the opening of the contact pad, the micro load effect (mi cr0 1 〇ad 丨 ng effect) during the money engraving process will cause the money engraving rate on the fuse to be slow, and therefore the insulation The thin part of the layer is maintained above the fuse to protect the fuse from moisture ingress and the contact pad is exposed to the contact pad opening. Fukahara et al., U.S. Patent No. 5,650,355 uses different methods to form fuses and solder pads, wherein when the openings of the solder pads are etched, the fuse is protected by a nitrogen oxide layer. Chen, United States Page 7 4Ϊ0416 V. Description of the Invention (4) Li Nos. 5712206 and 5538924 respectively explain the method of manufacturing a water-vapor-impermeable protective cover and a water-vapor barrier; this method includes forming a water vapor barrier around the fuse opening. A protective cover or layer to prevent moisture in the semiconductor circuit from remaining in the area of the fuse. Takayania et al, β Country Maili No. 45 3 6 949, explains that a type of fuse can be formed more accurately without any additional cost by forming an insulation layer on top of the IC wire and leaving a moment above the fuse. Method of opening. Board man et al. In U.S. Patent No. 52 9 0 734 describes a reliable connection to prevent melting. Among them, a high-resistance substance (1 ~ 2G Ω), such as amorphous stone, can be passed through by voltage. The amorphous silicon bond changes, so its resistance is reduced to about 200 Ω. This method replaces titanium and titanium tungsten fuses, and takes up less space on the c. There is still a great need in the semiconductor industry for ways to improve the efficient production costs of manufacturing fuse structures. Therefore, a main object of the present invention is to provide an improved fuse structure on an IC, which utilizes a single photomask to simultaneously etch the fuse opening as laser heating to burn out the fuse, and etched out for use in the protective layer. As an opening for solder pad contact. Another object of the present invention is to use a tungsten plug in a via hole to avoid excessive passivation of the first metal layer when the via hole and a part of the etched fuse opening are simultaneously etched using a single photoresist mask. Etching. Another object of the present invention is to use a single photomask to complete the fuse opening in the polyimide / silicon argon protective layer when forming the solder opening of the dram element, and thus provide a more efficient manufacturing process.

第8頁 410416____— 五、發明說明（5) 這個在DRAM元件（晶片）上形成保險絲結構的方法在保險絲之開口係蝕刻至該機板上之複晶矽化金屬保險絲時，-不會過度地腐蝕該第一金屬内連接點；且此方法係於介層洞中利用鎢栓塞以保護先前完成保險絲之開口蝕刻的第一金屬。這個方法亦使得其一係使用單一光罩以完成該保險絲之開口，且同時银刻焊接墊之開口。這個方法首先係提供一半導體基板，通常為具有輕微摻雜的單晶矽；場氧化層（field oxide，F0X)區域則形成於環繞該半導體基板之表面以電子式地隔絕出元件區β I 導體元件，如用於1C之場效電晶體，係形成於元件區且用於製造DRAM晶片·，由一第一複晶石夕化金屬層，形成該場效電晶體之閘電極。具有這些1C之刪除部分改良之保險絲# 造之DRAM或於一DRAM中之記憶體單元受損害的列係藉由、尤積·一第一絕緣層’如·—氧化妙於該基板上以電子式地隔離該元件。接著，要平坦化第一絕緣層，如利用化學機械研磨法（chemical mechanical polishing, CMP);再沈積第二複晶碎化金屬層’並於該第二複晶珍化金屬層上形成一氮化矽覆蓋層，而此覆蓋層與該第二複晶矽化金屬層^ 定義其圖案之後遂於該DRAM之記憶體單元内形成位元、線/ 並形成用於保險絲之一部分的局部内連接《氮化石夕絕$ ’ 壁層係形成於此經定義圖案之第二複晶矽化金屬層之你丨 ;在該圖案化之第二複晶矽化金屬層上則沈積—第二層壁且經平坦化以於該位元線上方形成一内層介電層 * (inter 1 eve 1 dielectric layer, ILD)。接著姓刻該第 _Page 8 410416____ — V. Description of the invention (5) This method of forming a fuse structure on a DRAM element (wafer) does not corrode excessively when the opening of the fuse is etched to a polycrystalline silicon silicide fuse on the board. The first metal internal connection point; and this method is to use a tungsten plug in a via hole to protect the first metal that has previously etched the opening of the fuse. This method also enables one to use a single photomask to complete the opening of the fuse, and at the same time the opening of the silver engraved solder pad. This method first provides a semiconductor substrate, usually a single-crystal silicon with a slight doping; a field oxide (F0X) region is formed on the surface surrounding the semiconductor substrate to electronically isolate the element region β I conductor The element, such as a field-effect transistor for 1C, is formed in the element area and used to manufacture a DRAM wafer. A gate electrode of the field-effect transistor is formed by a first polycrystalline silicon metallization layer. Improved fuses with these 1C deleted parts # The DRAM made or the memory cell in a DRAM is damaged by a special insulating layer such as a first insulation layer The component is isolated in a conventional manner. Next, the first insulating layer is to be planarized, for example, by chemical mechanical polishing (CMP); a second polycrystalline shredded metal layer is deposited and a nitrogen is formed on the second polycrystalline shredded metal layer. A silicon cover layer is formed, and the cover layer and the second polycrystalline silicon silicide layer ^ define a pattern, and then form bits, lines, and form local interconnections for a part of the fuse in the memory cell of the DRAM. The nitride layer is formed on the second polycrystalline silicided metal layer in this defined pattern; on the patterned second polycrystalline silicided metal layer, a second layer of walls is formed and flat Forming an interlayer dielectric layer (ILD) * above the bit line. Then the last name carved the first _

410416 五、發明說明（6) 與第一絕緣元區域内延開口。接下開口，並於置’能夠形層，係沈積化該第三絕之粗糙。於一金屬層，此第一金屬子内連線。 intermetal 該位於第一刻在該用作層，以作為刻進入該第過度姓刻。屬層，且回在此蝕刻過之後沈積一義其圖案以墊。在該蝕屬層係被移造成於該保層至該基板以形成接觸開口，並於該記情體μ 伸該位元線以形成電容器之自我對準節^ 單郝趨觸來沈積一經摻雜的複晶矽層以填滿該節點啊該節點接觸開口上定義其圖案β藉由習知之觸成DRAM電容；一第三絕緣層，一般係指—敦於該第二絕緣層與節點電容之上方；接著平D 緣層以降低起因於節點電容所造成的表垣該第三絕緣層中形成介層洞之後’係沈積— 如鋁/銅，並於該第一金屬層上沈積—Ai?C 第層與ARC層係經定義其圖案以形成下一屬 ’ _ 胃的雷再沈積一第四絕緣層，亦指内層金屬介電層包 dielectric, IMD)，並蝕刻該第四絕緣廣（金屬層上方之ARC層以形成介層洞，並同至保險絲之第二複晶矽化金屬層上方之第四麵更開闊之保險絲開口。此保險絲開口亦部$緣三絕緣層’而該ARC層係預防該第一金屬層力匈接著沈積一氮化飲黏著層，並沈積一撝耐< 钱刻至該黏著層以於介層洞形成金屬轉板塞金程十’金屬鶴係移除至該保險絲開口之底主’ 第二金屬層’如鋁/銅，並利用電漿蝕刻~法^。形成下一層之金屬内連接點，其包括金屬定刻之過程中’位於該保險絲開口底部之第，接除；並使用過度蝕刻法以移除該黏著層，〜金險絲開口中之保險絲上方之第三絕緣屠而更410416 V. Description of the invention (6) The opening is extended in the area of the first insulator. The opening is closed, and the layer can be formed to deposit the third absolute roughness. In a metal layer, the first metal is interconnected. The intermetal should be located at the first moment in the layer used as the moment to enter the first excessive surname. It is a layer, and the pattern is deposited to pad after this etching. After the eroded layer system is moved from the protective layer to the substrate to form a contact opening, the bit line is extended in the memory to form a self-alignment node of the capacitor. Miscellaneous polycrystalline silicon layer to fill the node ah The pattern defined on the contact opening of the node β touches a DRAM capacitor by a conventional method; a third insulating layer generally refers to the second insulating layer and the node capacitor Above; then flattening the D edge layer to reduce the surface gap caused by the node capacitance. After the formation of a via hole in the third insulating layer, a series of deposits-such as aluminum / copper, and deposited on the first metal layer-Ai The? C layer and the ARC layer are defined by their patterns to form the next genus. _ Wei Lei of the stomach then deposits a fourth insulating layer, also referred to as the inner metal dielectric layer (dielectric, IMD), and etches the fourth insulating layer. (The ARC layer above the metal layer forms a via hole, and it is the same as the fuse opening on the fourth face above the second polycrystalline silicon silicide metal layer of the fuse. This fuse opening also includes a three-edge insulation layer and the ARC Layer system prevents subsequent deposition of the first metal layer Nitrided drink adhesion layer, and deposited a layer of << qin resistant to this adhesion layer to form a metal transfer plate plug in the interposer hole. Gold process X 'metal crane system is removed to the bottom of the fuse opening' main 'second metal layer' Such as aluminum / copper, and plasma etching method is used to form the next layer of metal internal connection points, which includes the process of metal setting 'located at the bottom of the fuse opening, then removed; and over-etched to remove This adhesive layer is ~ the third insulation layer above the fuse in the gold wire opening and more

第10頁 — 41041ft______ 五、發明說明（7) 。接下來’沈積一保護層；此保護層係藉由順應性沈積一氮化矽層而形成’隨之而形成的是更厚的聚亞醯胺；藉由本發明之方法，係使用一單一光罩與非等向性蝕刻法蝕刻至該第二金屬層以在保護層中作為焊接塾之開口；並餘刻該保護層至該保險絲開口中殘留的第三絕緣層。且光阻光罩係位於適當之位置，該剩下的第三絕緣層與第二絕緣層係移除至該位於保險絲上方之氮化矽覆蓋層；上述之絕緣層係利用具有二氧化矽與氮化矽之高蝕刻選擇率之方法蝕刻之。這形成了在DRAM上做為雷射檫過（abras i on)之保險絲，造；而此方法避免了金屬殘餘在可能造成短路的保險（絲區域’且該氮化矽絕緣側壁層與覆蓋層防止在晶圓製造及測試期間因水氣所造成的損害。 , 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：之簡單說afl : 、第1圖為習知之概要剖面圖，顯示在使用單一光罩步蝕刻出開口時，習知之於介層洞接觸中具有構與過飯刻金屬之半導體基板的一部分；以及争α 、、第2〜7圖顯示依據本發明之形成保險絲接觸開口之方 :觸2 :鎢ί S以避免形▲介層 '洞㈣蝕刻之較佳保險絲，觸、、、》構之製程步驟概要剖面流程圖。符號 1 〇〜基板；1 2〜絕緣層；1 4 ~第二複晶矽化金屬層；i 6〜Page 10 — 41041ft______ 5. Description of the Invention (7). Next 'deposit a protective layer; this protective layer is formed by compliant deposition of a silicon nitride layer' followed by thicker polyimide; by the method of the present invention, a single light is used The cover and anisotropic etching are etched to the second metal layer to serve as an opening for a soldering tin in the protective layer; and a third insulating layer remaining from the protective layer to the fuse opening is etched. Moreover, the photoresist mask is located at an appropriate position, and the remaining third insulating layer and the second insulating layer are removed to the silicon nitride cover layer above the fuse; the above-mentioned insulating layer uses silicon dioxide and Etching of silicon nitride with high etching selectivity. This forms a fuse made on the DRAM as an abras i on; and this method avoids the metal residue in the fuse (wire area) that may cause a short circuit, and the silicon nitride insulating sidewall layer and the cover layer Prevent damage caused by water and gas during wafer manufacturing and testing. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings A detailed description is as follows: Briefly, afl:, Figure 1 is a conventional outline cross-sectional view, which shows that when a single photomask is used to etch an opening, it is known that there is a structure and metal engraved metal in the via hole contact. A part of the semiconductor substrate; and Figures 2 to 7 show the method of forming a fuse contact opening according to the present invention: contact 2: tungsten 钨 S to avoid the shape ▲ interlayer 'hole etched better fuse, contact, The process flow diagram of the outline of the process steps of the structure. Symbol 1 0 ~ substrate; 1 2 ~ insulating layer; 1 4 ~ second polycrystalline silicon silicide layer; i 6 ~

第11頁 410416 五、發明說明（8) 第二絕緣層；1 8〜笛 .„ „ 铱一姐以a ·第一金屬層；2〜開口； 20~氮化鈇層；22 〜第二絕緣層，24、盆-人超ia 第一金屬層；24’〜金屬；4〜開口；30〜複日日石夕層，3 2〜妙仏么思& n «〇 A , - . 金屬層，3 3〜第二複晶矽化金屬層； _凡'，’ ’ δ'保險絲；34〜覆蓋層；36~絕緣側壁層；一絕緣層’ 4 0〜複晶矽層；1〜電容接觸節點；42〜第二浥]緣層’ 44〜第—金屬層；46~反反光層；48〜第四絕緣二，，〜保險絲開口； 50〜氮化鈦黏著層；52〜金屬鎢層；3〜二層洞’54〜第一金屬層；56〜氮化矽層；58一亞醯胺。實施例本發明係有關於一種形成積體電路（Integrated C1 rcu 11)之較佳保險絲接觸結構的方法。而該方法係在形成保險絲接觸開口時，於介層洞中利用鎢栓塞（tungsi：en Pjiig)，以避免下層金屬間連線之過蝕刻。此方法亦允許單一光罩的使用以钱刻該聚亞醯胺保護層，作為該保險絲開口與焊接墊開口；其中，一氮化層覆蓋層與絕緣間隙壁係保護此複晶矽化金屬層以防止其受水氣的損害。接下係詳細說明這個用於製造出此保險絲構造的方&以於DR 電路上形成保險絲；這個方法藉由燒掉保險絲並移除疵的記憶體單元之行或是列’並使用所備用完好之^ 瑕單元的行或列。然而’由習知之技藝應該很容易能^ ^ = 此方法一般係適用於製造積體電路。 b 嗓解本發明首先係提供/半導體基板1 0，如第2圖所八該種普遍用於半導體工業之基板係由單晶矽所組成，w 格排列方向係為<1 〇〇>，且其中摻雜了 P型離子，如L二晶 1夕U如是蝴 4104^6 五、發明說明（9) 。該半導體元件之詳細構造係由場效電晶體（Field Effect Transistor，FET)所形成，但未詳示於圖中，以簡化該圖示及其後之說明，但一般係於矽基板上形成場氧化層（field oxide，F0X)以包圍並電子式地隔離各元件區域在元件區域表面係成長一薄氧化層，並定義一第一複晶矽化金屬層之圖案，以形成該場效電晶體之閘電極。此場效電晶體係於在閘電極之侧，例如，施行離子植入法形成源/汲極區域而完成。仍舊請參考第2圖’將要詳細說明利用此改良的保險絲構造以製造動態隨機記憶體之方法；在形成場效電晶體之後，一第一絕緣層12係沈積於該半導體基板1〇上以呈元件之電性隔離；其中，上述之絕緣層丨2最好為二氧化矽，利用化學氣相沈積法（Chemical Vapor Deposition，CVD) ’以四乙氧基矽酸鹽（TE0S)為反應氣體沈積而成。該第一絕緣層12之厚度約介於8 0 0 0〜1 2 0 〇〇埃之間，並利用例如 CMP以進行平坦化。繼續參考第2圖’係沈積一經摻雜的複晶；5夕層3〇與_ 高溫之梦化金屬層32以形成一第二複晶石夕化金屬層33。一般複晶矽層3 0的沈積方法係為利用低壓物理氣相沈積法（ low-pressure chemical vapor deposition， LPCVD)，以例如是矽曱烷（s i 1 ane )為反應氣體，並利用離子植入法或是隨著沈積的反應摻植（in situ)磷離子至其濃度約在 2E20〜5E20原子數/立方公分之間。複晶石夕層30所沈積之厚度則約為5 0 0 ~ 1 0 0 0埃之間；該耐高溫之石夕化金屬層3 2之材Page 11 410416 V. Description of the invention (8) The second insulation layer; 1 8 ~ flute. „„ Sister iridium with a · first metal layer; 2 ~ opening; 20 ~ hafnium nitride layer; 22 ~ second insulation Layer, 24, basin-human super ia first metal layer; 24 '~ metal; 4 ~ opening; 30 ~ day-day Shixi layer, 3 2 ~ Mysticism & n «〇A,-. Metal layer , 3 3 ~ Second polycrystalline silicon silicide layer; _ Fan ',' 'δ' fuse; 34 ~ cover layer; 36 ~ insulating sidewall layer; 1 insulating layer '4 0 ~ polycrystalline silicon layer; 1 ~ capacitor contact node 42 ~ Second 浥] edge layer '44 ~ first-metal layer; 46 ~ reflective layer; 48 ~ fourth insulation layer, ~~ fuse opening; 50 ~ titanium nitride adhesion layer; 52 ~ metal tungsten layer; 3 ~ Two-layer hole '54 ~ first metal layer; 56 ~ silicon nitride layer; 58-imide. Example The present invention relates to a method for forming a better fuse contact structure of an integrated circuit (Integrated C1 rcu 11). In this method, when a fuse contact opening is formed, a tungsten plug (tungsi: en Pjiig) is used in the via hole to avoid over-etching of the underlying metal-to-metal connection. This method also allows the use of a single photomask to engrav the polyurethane protective layer as the fuse opening and solder pad opening; wherein a nitride layer cover layer and an insulating spacer wall protect the polycrystalline silicided metal layer to Protect it from moisture damage. The following is a detailed description of the method used to fabricate this fuse structure to form a fuse on the DR circuit; this method uses the fuses and removes defective rows or rows of memory cells and uses the spares. Intact rows or columns of defective cells. However, ‘from the know-how should be easy to implement ^ ^ = This method is generally suitable for manufacturing integrated circuits. b. The present invention first provides the semiconductor substrate 10, as shown in Figure 2. The substrate commonly used in the semiconductor industry is composed of single crystal silicon, and the w-grid arrangement direction is < 1 〇〇 > , And it is doped with P-type ions, such as L two crystals and U 4 is 4104 ^ 6 5. Description of the invention (9). The detailed structure of the semiconductor element is formed by a field effect transistor (FET), but it is not shown in detail in the figure to simplify the illustration and the following description, but it is generally formed on a silicon substrate to form a field oxide. A layer oxide (F0X) surrounds and electrically isolates each element area. A thin oxide layer is grown on the surface of the element area, and a pattern of a first polycrystalline silicon silicide layer is defined to form a gate of the field effect transistor. electrode. This field effect transistor system is completed on the side of the gate electrode, for example, by performing ion implantation to form a source / drain region. Still referring to FIG. 2 ', a method for manufacturing a dynamic random access memory using this improved fuse structure will be described in detail. After forming a field effect transistor, a first insulating layer 12 is deposited on the semiconductor substrate 10 to present Electrical isolation of components; among them, the above-mentioned insulating layer 2 is preferably silicon dioxide, which is deposited by using a chemical vapor deposition method (Chemical Vapor Deposition (CVD)) using tetraethoxy silicate (TE0S) as a reactive gas. Made. The thickness of the first insulating layer 12 is between 80 and 120 Angstroms, and planarization is performed using, for example, CMP. Continuing to refer to FIG. 2 ', a doped polycrystal is deposited; the 30th layer 30 and the high-temperature dream metallization layer 32 are formed to form a second polycrystallized metallization layer 33. A general method for depositing a polycrystalline silicon layer 30 is to use low-pressure chemical vapor deposition (LPCVD), for example, using si 1 ane as a reactive gas, and using ion implantation. In addition, the phosphorous ions are implanted in situ with the reaction of deposition to a concentration of about 2E20-5E20 atomic number / cubic centimeter. The polycrystalline stone layer 30 is deposited to a thickness of about 500 to 100 angstroms; the high-temperature-resistant petrified metal layer 32 is made of a material

第13頁 410416 五、發明說明（ίο) --- 質最好為石夕化鎢（ffSix)並利用CVD法，將氟化鎢與矽甲烧作為反應氣體沈積而成，而此矽化金屬層32所沈積之較理想之厚度約在1〇〇〇〜2〇〇〇埃之間。接下來’一覆蓋層（cap lay er)34係形成於該第二複晶矽化金屬層33上，覆蓋層34 之材質最好為氮化矽’係由LPCVD法’利用二氣矽甲燒 (S1ClaH2)與氨氣（NHs)混和氣體反應而成，且其厚度約在 1500~2500埃之間。此氮化矽覆蓋層34與第二複晶矽化金屬層33係經定義其圖案以形成動態隨機記憶體單元之記憶體區域之位元線33A，如第2圖中之區域A所示，並形成具有保險絲區域之局部内連接點33B，如第2圖中之區域b所示。習知之光學微影技術（photolithographic technique)與非等向性電漿蝕刻法（anisotropic plasflla etching)係用於定義該覆蓋層34與該第二複晶矽化金屬層 3 3之圖案；此非等向性電漿蝕刻之施行係於，例如，使用活性離子蝕刻法（Reactive Ion Etching，RIE)，將氟乙烷（C2F6)、氟丁烯（C4F8)、氟曱烷（CH3F)、與氬氣（Argon) 的混和作為蝕刻氣體’用於蝕刻該覆蓋層34，以及將三氯化硼（BC13)與氣氣之混和用以蝕刻該複晶矽化金屬層33。接下來，係順應性（001^00^1)沈積一毯覆式（1)131^6〇氮化矽層36，例如，以LPCVD法形成，再非等向性回蝕刻 (etch back)該氮化矽層以於該經定義過圖形之第二複晶矽化金屬層3 3之侧壁（s i dewa 11)上形成一絕緣側壁層3 6，其寬度約在400- 1 0 00埃之間。請參看第3圖，一第二絕緣層38係沈積於該圖案化之Page 13 410416 V. Description of the invention (ίο) --- It is best to use tungsten oxide (ffSix) and use CVD method to deposit tungsten fluoride and silicic acid as the reaction gas, and this silicided metal layer The more ideal thickness of 32 is between 1000 and 2000 Angstroms. Next, a cap layer 34 is formed on the second polycrystalline silicon silicide metal layer 33. The material of the capping layer 34 is preferably silicon nitride. S1ClaH2) is reacted with a mixed gas of ammonia (NHs), and its thickness is between 1500 ~ 2500 Angstroms. The silicon nitride cover layer 34 and the second polycrystalline silicon silicide layer 33 are bit lines 33A that define a pattern to form a memory region of a dynamic random access memory cell, as shown by region A in FIG. 2, and A partial internal connection point 33B having a fuse area is formed, as shown by area b in FIG. 2. The conventional photolithographic technique and anisotropic plasflla etching are used to define the pattern of the cover layer 34 and the second polycrystalline silicided metal layer 33; this non-isotropic The plasma etching is performed, for example, by using reactive ion etching (Reactive Ion Etching, RIE), using fluoroethane (C2F6), fluorobutene (C4F8), fluorofluorane (CH3F), and argon ( A mixture of Argon) is used as an etching gas to etch the cover layer 34, and a mixture of boron trichloride (BC13) and gas is used to etch the polycrystalline silicon silicide layer 33. Next, a blanket (001 ^ 00 ^ 1) silicon nitride layer 36 is deposited (001 ^ 00 ^ 1), for example, formed by LPCVD, and then anisotropically etched back. The silicon nitride layer forms an insulating sidewall layer 3 6 on the sidewall (si dewa 11) of the second polycrystalline silicon silicide layer 3 3 with a defined pattern, and has a width of about 400-1000 Angstroms. . Referring to FIG. 3, a second insulating layer 38 is deposited on the patterned layer.

IHI 第14頁 410416 _ 五、發明說明（11) 第二複晶矽化金屬層33之上；而此第二絕緣層38為USG層，係以HDP CVD之方式沈積，由於其具有不吸收水氣之特性，因此能夠於深次微米之MAM製程中’在相距狹窄的位元線33 A間提供良好的填溝能力（gap f i 1 1 i ng)。此第二絕緣層38係利用矽甲烷（SiH4)、氧（02)、或是氬（Ar)作為反應氣體而形成；且此第二絕緣層3 8，一般係指I LD，係沈積於該定義過圖形之第二複晶矽化金屬層上，並利用CMP 進行平坦化製程，以具有厚度約在4 000〜8000埃之間。仍舊請參考第3圖，係蝕刻該第二與第一絕緣層38與 12至該半導體基板表面，以形成DRAM元件之電容接觸節點開口 1。此節點接觸開口 1係於位元線33A之間蝕刻，並於位元線間延伸以於該記憶體單元區域形成一電容器之自我對準（self-a 1 igned)節點接觸開口，如第3圖中之區域A所示。例如’該節點接觸開口 1係使用RIE法，且蝕刻之氣體係為例如是氟丁烯（C4F8)、氟曱烷（CH2F2)、或是氬（Ar)，而選擇性地蝕刻該第二絕緣層3 8，以避免傷害該氮化矽覆蓋層34與氮化矽絕緣侧壁層36。接著，一經摻雜的複晶矽層4 0係沈積以填滿該節點接觸開口1 ;而上述之複晶矽層 40係使用矽曱烷為反應氣體，利用LPCVD法沈積而成，並隨著沈積的反應摻雜磷離子，其濃度約在2E20到5E 20原子數/立方公分之間。如今，利用習知之裝置能夠形成dram 電容，但無法詳示於圖中；例如，具有圓柱狀，臂狀，或類似之形狀之電容可藉由額外之製程步驟，以形成一内電極介電層（inter-electrode dielectric layer)與一表面IHI Page 14 410416 _ V. Description of the invention (11) The second polycrystalline silicon silicide layer 33; the second insulating layer 38 is a USG layer, which is deposited by HDP CVD, because it does not absorb moisture Due to its characteristics, it can provide good trench filling capability (gap fi 1 1 in ng) between the narrow bit lines 33 A in the deep sub-micron MAM process. The second insulating layer 38 is formed by using silicon methane (SiH4), oxygen (02), or argon (Ar) as a reaction gas; and the second insulating layer 38, generally referred to as I LD, is deposited on the A second polycrystalline silicon silicide layer having a pattern is defined, and a planarization process is performed by using CMP so as to have a thickness of about 4 to 8000 angstroms. Still referring to FIG. 3, the second and first insulating layers 38 and 12 are etched to the surface of the semiconductor substrate to form the capacitor contact node opening 1 of the DRAM element. This node contact opening 1 is etched between the bit lines 33A, and extends between the bit lines to form a self-a 1 igned node contact opening of the capacitor in the memory cell area, as shown in the third Area A in the figure. For example, 'the node contact opening 1 uses the RIE method, and the etching gas system is, for example, fluorobutene (C4F8), fluoromethane (CH2F2), or argon (Ar), and the second insulation is selectively etched. Layer 38 to avoid damage to the silicon nitride cover layer 34 and the silicon nitride insulating sidewall layer 36. Next, a doped polycrystalline silicon layer 40 is deposited to fill the contact opening 1 of the node; and the above-mentioned polycrystalline silicon layer 40 is deposited using siloxane as a reactive gas by LPCVD method, and follows The deposited reaction is doped with phosphorus ions at a concentration between about 2E20 and 5E 20 atoms / cm3. Nowadays, a conventional device can be used to form a dram capacitor, but it cannot be shown in detail in the figure; for example, a capacitor with a cylindrical shape, an arm shape, or a similar shape can be formed into an inner electrode dielectric layer by additional process steps. (Inter-electrode dielectric layer) and a surface

第15頁 410416 五、發明說明（12) 電極；第3圖以標號40大略顯示此電容。請參考第4圖，一第三絕緣層42，一般係指ILD，係沈積於該第二絕緣層38表面，且於該節點電容40之上；第三絕緣層42係為HDP-CVD法所形成的USG二氧化矽，且其厚度約在1 2 00 0〜1 600 0埃之間》第三絕緣層42接著係利用CMP，進行全面性平坦化製程，以降低該記憶體單元區域與DRAM 晶片之周圍間之階梯高度。依舊參考第4圖，用於連接各層間之介層洞（未顯示於圖中）係形成於該第三絕緣層42中，且一第一金屬層44係沈積於其内；該金屬層4 4最好係為鋁或銅，且係利用物理（氣相沈積法（physical vapor deposition，PVD)，例如藏鍍沈積’至其厚度約介於3000~5000埃之間。接下來，一 ARC層46係沈積在該第一金屬層44之上；其中，上述之ARC 層最好為氮化鈦（T i N )，且係利用，例如，於充滿氮氣之腔室中進行鈦靶之濺擊而沈積。此ARC層46所沈積之厚度約在大約1 00 0~ 1 50 0埃之間；該ARC層46與該第一金屬層44 係利用習知之光學微影術與非等向性電漿蝕刻而定義其圖案’以形成下一層的電子内連線《例如，該電漿蝕刻係利用RIE法’利用如三氯化硼（BCl3)、氯氣（Cl2)、與三氟甲炫（CHF3)作為蝕刻之反應混和氣體，以蝕刻該ARC層46，且以三氣化硼（BCI3)、氯氣（Cl2)、三氟甲烷（CHF3)、與氮氣（化）作為蝕刻之反應混和氣體，以蝕刻該金屬層44。請參考第5圖’係沈積一第四絕緣層4 8，亦即I MD層；此第四絕緣層48係為二氧化矽，由PECVD法所沈積，且具Page 15 410416 V. Description of the invention (12) Electrode; Figure 3 roughly shows this capacitor with reference number 40. Please refer to FIG. 4. A third insulating layer 42 generally refers to ILD, which is deposited on the surface of the second insulating layer 38 and above the node capacitor 40. The third insulating layer 42 is a HDP-CVD method. The formed USG silicon dioxide has a thickness of about 12000 to 1600 Angstroms. The third insulating layer 42 is then subjected to a comprehensive planarization process using CMP to reduce the memory cell area and DRAM. The height of the steps between the wafers. Still referring to FIG. 4, a via hole (not shown) for connecting the layers is formed in the third insulating layer 42, and a first metal layer 44 is deposited therein; the metal layer 4 4 is preferably aluminum or copper, and uses physical (physical vapor deposition (PVD), such as Tibetan plating deposition) to a thickness of about 3000 to 5000 angstroms. Next, an ARC layer The 46 series is deposited on the first metal layer 44; among them, the ARC layer is preferably titanium nitride (TiN), and the titanium target is sputtered in, for example, a nitrogen-filled chamber. And deposited. The thickness of the ARC layer 46 is about 1000-1500 Angstroms; the ARC layer 46 and the first metal layer 44 are formed by conventional optical lithography and anisotropic electricity. The plasma etching defines its pattern 'to form the next level of electronic interconnects.' For example, this plasma etching system uses the RIE method 'to use, for example, boron trichloride (BCl3), chlorine (Cl2), and trifluoromethane (CHF3). ) As a reaction mixture gas for etching to etch the ARC layer 46, and boron trichloride (BCI3), chlorine (Cl2), trifluoromethane Alkane (CHF3), mixed gas with nitrogen (chemical) as an etching reaction to etch the metal layer 44. Please refer to FIG. 5 'to deposit a fourth insulating layer 48, which is an I MD layer; this fourth insulation Layer 48 is silicon dioxide, which is deposited by PECVD and has

第16頁有厚度在6000到12000埃之間。Page 16 has a thickness between 6000 and 12000 Angstroms.

繼續參考第5圓’本發明之關鍵特徵，介層洞3係由蚀刻該第四絕緣層48至該位於圖案化之第一金屬層44上方之 ARC層4 6所形成’且更寬闊之保險絲開口 5係利用蝕刻在該作為保險絲3 3 B之第二複晶石夕化金屬層上方之該第四絕緣層48所形成。此相關厚度ARC層4 6使得該保險絲開口 5在控制該保險絲開口之蝕刻深度下，能夠被過度蝕刻；這使得被蝕刻之保險絲開口 5可延伸至部分的保險絲3 3 B上方之第三絕緣層42，以控制該保險絲上方之絕緣層厚度。Continuing to refer to the fifth circle, the key feature of the present invention, the via hole 3 is formed by etching the fourth insulating layer 48 to the ARC layer 46 above the patterned first metal layer 44 and a wider fuse The opening 5 is formed by using the fourth insulating layer 48 etched over the second poly-sparite metalized layer as the fuse 3 3 B. The related thickness ARC layer 46 allows the fuse opening 5 to be over-etched while controlling the etch depth of the fuse opening; this allows the etched fuse opening 5 to extend to a third insulating layer above a portion of the fuse 3 3 B 42 to control the thickness of the insulating layer above the fuse.

依舊請參考第5圖，將要形成本發明之其他關鍵特點，亦即於該介層洞3中形成一金屬栓塞；此金屬栓塞可避免該介層洞中的第一金屬層在接下來的步驟中被蝕刻。欲形成此金屬栓塞首先要先沈積一氤化鈦黏著層5〇 ’接著沈積一耐高溫的金屬層52 ;此氮化鈦層50最好是於充滿氮氣之腔室中’濺擊鈦靶而產生之濺鍍沈積，且沈積的厚度在 600~1200埃之間。此耐高溫之金屬層52最好是鶴，並以 CVD法’利用六氟化鎢作為反應氣體沈積而成。此金屬層 5 2所沈積的厚度要夠厚，以填滿該次微米介層洞3，並且要夠薄’以順應性沈積於該較寬之黏著窗開口 5。接下來 ’係利用非等向性姓刻法進行此金屬層5 2之毯覆式回银刻製程’钱刻至該黏著層50，而於該介層洞3中形成鎢金屬栓塞52。例如，以RIE法，並將六氟化矽、氮氣、氦氣之混和作為蝕刻反應氣體，回蝕刻該金屬層52。在蝕刻期間 ’係移除該鎢金屬至該保險絲開口 5之底部，但在該保險Still referring to FIG. 5, another key feature of the present invention is to be formed, that is, a metal plug is formed in the via hole 3; this metal plug can prevent the first metal layer in the via hole from being in the next step. Was etched. To form this metal plug, first deposit a titanium halide adhesion layer 50 ′ and then deposit a high temperature resistant metal layer 52; this titanium nitride layer 50 is preferably 'sputtered on a titanium target in a nitrogen-filled chamber and The resulting sputter deposition has a thickness between 600 and 1200 angstroms. The high-temperature-resistant metal layer 52 is preferably a crane and is deposited by a CVD method using tungsten hexafluoride as a reaction gas. The thickness of the metal layer 5 2 should be thick enough to fill the sub-micron via 3 and thin enough to be deposited on the wider adhesive window opening 5 compliantly. The next step is to perform the blanket oversilver engraving process of the metal layer 52 using an anisotropic surname engraving process to the adhesive layer 50 to form a tungsten metal plug 52 in the interlayer hole 3. For example, the metal layer 52 is etched back by an RIE method using a mixture of silicon hexafluoride, nitrogen, and helium as an etching reaction gas. During the etching process, the tungsten metal is removed to the bottom of the fuse opening 5, but in the fuse

第17頁 ——4-104-^------ 五、發明說明（14) 絲開口 5之侧壁上則殘留部分的金屬鎢。广、) 參考第6圖，一第二金屬層54係沈積於該黏著層5〇之-上’且位於該鶴栓塞5 2上方’並順應性沈積於該保險絲開口5内。此第二金屬（M2)層54之材質最好為鋁或銅，且利用P VD法，例如是濺鍍法沈積而成，且具有厚度約為6 〇〇〇〜1 0 0 0 0埃。在此’係使用習知之光學微影技術與非等向性電漿姓刻之方法，定義該M2層54之圖案，以形成下一層的金屬内連接線，如第6圖中之鎢栓塞52上方的金屬線54所示。而當定義該第二金屬層的圖案時，此氮化鈦黏著層同時蝕刻至該第四絕緣層48之表面；在定義該第二金屬層的圖案時’亦形成録塾（未顯示於圖中）。一般而言，電漿蝕刻係利用RIE法，且使用三氯化硼（Bey、氣氣（cl2)、三氟甲燒（CHF3)、與氮氣（N2)作為蝕刻之反應混和氣體。此第二金屬層在#刻的過程中被移除至該保險絲開口 5之底部，但於該保險絲開口 5之側壁上仍殘留部分的第二金屬54。在該第一金屬層54的過钱刻過程中，移除了黏著層 50，而位於該保險絲開口 5中的第三絕緣層42更因此而減少了 2 0 0 0埃。現在請參考第7圖，一氮化矽層5 6係順應性沈積於該經定義過圖形的第二金屬層之上，以作為保護層的一部分而用以保護在該基板上的元件，避免其受離子與水氣的侵害°此氮化矽層56最好係藉由電漿加強CV])法，於3〇〇 °C之相對低溫下使用如石夕甲院與氨氣的混和氣體反應而成；且該氮化矽層56所沈積的厚度約在4〇〇〇〜8〇〇〇埃之間。再沈Page 17 ——4-104-^ ------ V. Description of the invention (14) On the side wall of the wire opening 5, a part of metal tungsten remains. (2) With reference to FIG. 6, a second metal layer 54 is deposited on-of the adhesive layer 50 and is located above the crane plug 52 and is conformably deposited in the fuse opening 5. The material of the second metal (M2) layer 54 is preferably aluminum or copper, and is deposited by using a P VD method, for example, sputtering, and has a thickness of about 600 to 100 angstroms. Here 'is the method of using the conventional optical lithography technology and the anisotropic plasma engraving method to define the pattern of the M2 layer 54 to form the next metal interconnection line, such as the tungsten plug 52 in FIG. 6 The upper metal line 54 is shown. When the pattern of the second metal layer is defined, the titanium nitride adhesive layer is simultaneously etched to the surface of the fourth insulating layer 48; when the pattern of the second metal layer is defined, a recording is also formed (not shown in the figure) in). In general, plasma etching uses RIE, and uses boron trichloride (Bey, gas (cl2), trifluoromethane (CHF3), and nitrogen (N2) as the reaction mixed gas for etching. This second The metal layer was removed to the bottom of the fuse opening 5 during the #etching process, but a portion of the second metal 54 remained on the side wall of the fuse opening 5. During the money engraving process of the first metal layer 54 , The adhesive layer 50 is removed, and the third insulating layer 42 located in the fuse opening 5 is reduced by 2000 angstroms. Now refer to FIG. 7, a silicon nitride layer 56 is conformally deposited. On the second metal layer with a defined pattern, as a part of the protective layer, it is used to protect the components on the substrate from being attacked by ions and water. This silicon nitride layer 56 is preferably By plasma enhanced CV]) method, a mixed gas such as Shixi Jiayuan and ammonia is reacted at a relatively low temperature of 300 ° C; and the thickness of the silicon nitride layer 56 is about 4 〇〇〇～ 80〇〇 angstroms. Sink again

第18頁 410416Page 410 410416

五、發明說明（15) 積厚的聚亞醯如屠58 ’例如使用旋塗法（Spin coating )，並固化而得該保護層；且此聚亞醯胺層5 8所沈積的厚度約在70000〜90 00 0埃之間。仍舊請參考第7圖’本發明之其他關鍵特徵，係使用單一光阻罩幕（未顯示於圖中）與非等向性蝕刻法以蝕刻在該氮化矽層56中之開口至該由M2層54所形成之銲墊（未顯示於圖中），同時，此氮化矽層56係被蝕刻至該保險絲開口 5之底σ卩而向下至該第二絕緣層42。而該聚亞醯胺光阻仍適當地殘留於該第三絕緣層4 2，且係選擇性地蝕刻該第二絕緣層38至位於複晶矽化金屬保險絲（33B層）之該氮化矽，蓋層34。此絕緣層42與38係利用一二氧化矽與氮化矽之高姓刻速率選擇性（select ivity)而移除；例如，係使用RIE方法來進行蝕刻，且蝕刻反應氣體係為諸如丁烯、一氟f烷、氬等混和氣體，其具有氧化物對氮化物之蝕刻選擇性至少為20 :1。這完成了在DRAM上因為雷射加轨以燒掉保險絲的保險絲構造；同時，這個方法避免在保險絲之區域上有剩餘的金屬而造成短路，如同於第丨圖之習知糸 2中所發生的現象-般，且氮化梦絕緣側壁層36與覆蓋 :34防止了在晶圓製作與測試期間水氣可能造成的損傷。 ίί近此氧化層第二與第三絕緣層避免水氣進人其鄰近之電路中因此而改善了該晶片之可靠度。雖然本發明已以較佳實施例揭露如上，ς其並 nr月，任何熟習此項技藝者，☆不脫離本發明之精神和範心，當可作更動與潤飾，因此本發明之保護範圍V. Description of the invention (15) The thick polyimide Rutu 58 'uses, for example, a spin coating method and curing to obtain the protective layer; and the polyimide layer 5 8 has a thickness of about Between 70,000 and 90,000 Angstroms. Still refer to FIG. 7 for other key features of the present invention, which use a single photoresist mask (not shown) and anisotropic etching to etch the opening in the silicon nitride layer 56 to the substrate. The pad (not shown) formed by the M2 layer 54, and the silicon nitride layer 56 is etched to the bottom of the fuse opening 5 σ5 and down to the second insulating layer 42. The polyimide photoresist still properly remains in the third insulating layer 42, and the second insulating layer 38 is selectively etched to the silicon nitride located in the polycrystalline silicon silicide fuse (layer 33B),盖层 34。 Cover layer 34. The insulating layers 42 and 38 are removed by using the high selectivity of silicon dioxide and silicon nitride; for example, the RIE method is used for etching, and the etching reaction gas system is such as butene. A mixed gas such as trifluoromethane, argon, argon, etc. has an etching selectivity of oxide to nitride of at least 20: 1. This completes the fuse structure on the DRAM because the laser is added to the rail to burn the fuse; at the same time, this method avoids the short circuit caused by the remaining metal on the fuse area, as occurs in the conventional figure 2 in Figure 丨The phenomenon is the same, and the nitrided insulating sidewall layer 36 and the cover: 34 prevent possible damage caused by moisture during wafer fabrication and testing. Recently, the second and third insulating layers of the oxide layer prevent moisture from entering the nearby circuits, thereby improving the reliability of the chip. Although the present invention has been disclosed in the preferred embodiment as above, it is nr months, anyone skilled in this art, ☆ without departing from the spirit and fan heart of the present invention, it can be modified and retouched, so the scope of protection of the present invention

410416 五、發明說明（16) 當視後附之申請專利範圍所界定者為準 ΙΒΪ410416 V. Description of the invention (16) It shall be subject to the definition in the appended claims. ΙΒΪ

Claims

_41Π4|^_ 六、申請專利範圍 1. 一種在動態隨機接達記憶體電路中形成保險絲的方法，包括下列步驟：提供一半導體基板，且於其上具有元件，其元件區係由場氧化層區隔出來，而上述之元件一部份係由一經定義圖案之第一複晶矽化金屬層所形成；於該半導體基板上之該元件上方形成一平坦化的第一絕緣層；沈積一第二複晶矽化金屬層與一覆蓋層於該第一絕緣層上方；定義該覆蓋層與該第二複晶矽化金屬層之圖案以於該ί DRAM上之記憶體單元區域形成位元線，並形成局部的具有部分作為保險絲之内連接線，且於該定義過圖案之第二複晶矽化金屬層之侧壁上形成絕緣侧壁層；沈積一第二絕緣層於該定義圖案之第二複晶矽化金屬層上，並平坦化該第二絕緣層；蝕刻出一接觸開口於該位於該位元線上方之該第二絕緣層與該第一絕緣層至該半導體基板以於該記憶體單元區域中做為自我對準節點電容；沈積一經摻雜的複晶矽層於該第二絕緣層上與該接觸開口中；定義該複晶矽層的圖案以於該接觸開口形成自我對準接觸節點，並形成該節點電容，係與上述兩者接觸；沈積一第三絕緣層於該第二絕緣層與該節點電容上，並平坦化該第三絕緣層；_41Π4 | ^ _ 6. Scope of Patent Application 1. A method for forming a fuse in a dynamic random access memory circuit, including the following steps: Provide a semiconductor substrate with components thereon, and the component area is formed by a field oxide layer Isolate it, and a part of the above-mentioned element is formed by a first polycrystalline silicon silicide layer with a defined pattern; a planarized first insulating layer is formed over the element on the semiconductor substrate; a second is deposited A polycrystalline silicon silicide layer and a cover layer over the first insulating layer; defining a pattern of the cover layer and the second polycrystalline silicon silicide layer to form bit lines in the memory cell region on the DRAM, and forming Partially has a part as the inner connecting line of the fuse, and an insulating sidewall layer is formed on the sidewall of the second polycrystalline silicided metal layer of the defined pattern; a second insulating layer is deposited on the second polycrystalline of the defined pattern Silicide the metal layer and planarize the second insulating layer; etch a contact opening over the second insulating layer and the first insulating layer to the half above the bit line; The body substrate uses the memory cell region as a self-aligned node capacitor; a doped polycrystalline silicon layer is deposited on the second insulating layer and in the contact opening; a pattern of the polycrystalline silicon layer is defined to The contact opening forms a self-aligned contact node and forms the node capacitance, which is in contact with the two; a third insulating layer is deposited on the second insulating layer and the node capacitance, and the third insulating layer is planarized;

_440416-- 六、申請專利範圍圖案以形成電子式沈積一第一金屬層與一反反光層，定義該第一金屬層與該反反光層之金屬内連線；沈積一第四絕緣層；蝕刻該第四絕緣層至該位於該第一金屬層上方之反反光層以形成介層洞，同時於用做保險絲之該部分的第二複晶石夕化金屬層上餘刻更寬之保險絲開口，真該保險絲開口係由蝕刻該第四絕緣層及部分之該第三絕緣層所形成，而上述之反反光層係防止了該第一金屬層的過度蝕刻；_440416-- 6. Apply for a patent scope pattern to form an electronically deposited first metal layer and a reflective layer, define the metal interconnects of the first metal layer and the reflective layer; deposit a fourth insulating layer; etch The fourth insulating layer to the reflective layer over the first metal layer forms a via hole, and at the same time, a wider fuse opening is etched on the second polycrystalline siliconized metal layer used as the part of the fuse. It is true that the fuse opening is formed by etching the fourth insulating layer and a part of the third insulating layer, and the above-mentioned reflective layer prevents the first metal layer from being over-etched;

沈積一黏著層，並沈積一耐高溫金屬層’當.移除在該保險絲開口中之該耐高溫金屬時，回蝕刻該耐高溫金屬層以於該介層洞中形成一耐高溫金屬栓；沈積一第二金屬層，並定義該第二金屬層的圖案以形成包括金屬焊接墊之金屬内連接線，且移除位於該保險絲開口之該第二金屬層，更蝕刻該在該保險絲開口中之保險絲上方之該第三絕緣層；以餘刻該保護層至該 ’並蝕刻該保險絲開沈積一保護層於該半導體基板上使用單一光罩與非等向性蝕刻法第二金屬層以形成開口作為該焊接墊口至該第三絕緣層；以及絕緣層與該第二絕緣層至位於該之該覆蓋層以完成該保險絲之該選擇性地蝕刻該第三第二複晶硬化金屬層上方保險絲開口。 2·如申請專利範圍第項所述之方法’其中，該複晶Depositing an adhesive layer and depositing a high-temperature-resistant metal layer; when the high-temperature-resistant metal in the fuse opening is removed, the high-temperature-resistant metal layer is etched back to form a high-temperature-resistant metal plug in the via hole; A second metal layer is deposited, and a pattern of the second metal layer is defined to form a metal interconnection line including a metal bonding pad, and the second metal layer located at the fuse opening is removed, and the second metal layer is etched into the fuse opening. The third insulating layer above the fuse; the protective layer is etched into the fuse and the protective layer is etched to deposit a protective layer on the semiconductor substrate using a single photomask and a second metal layer with anisotropic etching to form The opening serves as the solder pad opening to the third insulating layer; and the insulating layer and the second insulating layer are located above the cover layer to complete the selective etching of the third second polycrystalline hardened metal layer. Fuse opening. 2. The method according to item 1 of the scope of patent application, wherein the compound crystal

第22頁 410416_ 六、申請專利範園矽化金屬層係為一經摻雜的複晶矽層，其間之厚度約在 500~ 1 0 00埃間，且上層之鎢化矽層厚度約在1〇〇〇〜2 0 0 0埃之間。 3. 如申請專利範圍第1項所述之方法，其中，該覆蓋層係為氮化矽層，其沈積之厚度約在1 5 0 0〜2 5 0 0埃間。 4. 如申請專利範圍第1項所述之方法，其中，該絕緣間隙壁係藉由沈積一氮化矽層再非等向性回蝕刻以形成該絕緣間隙壁，其厚度約在4 0 〇〜1 〇〇〇埃之間。 5. 如申請專利範圍第1項所述之方法，其中，該第二絕緣層係為氧化矽層’係利用高密度電漿化學氣相沈積法沈積而成’且其厚度約在4000〜8000埃之間。 6 ·如申請專利範圍第1項所述之方法，其中，該經摻雜的複晶矽層係沈積至一過填滿該接觸開口之厚度，並同時摻雜一 N型傳導摻雜物至其濃度在1〇Ε19ι1()Ε21原子數/立方公分之間。 7·如申請專利範圍第1項所述之方法，其中，該第三絕緣層係為氧化矽層，係由化學氣相沈積法沈積而成，且其厚度約在1 200 0〜1 6000埃之間。 8. 如申請專利範圍第1項所述之方法，其中，該第一金屬層係為鋁/銅，且所沈積之厚度約在3〇〇〇〜5〇〇〇埃之間〇 9. 如申請專利範圍第1項所述之方法’其中，該反反光層係為氮化鈦層，且所沈積之厚度約在丨0001 5〇〇埃之間。Page 22 410416_ VI. The patent application Fanyuan silicided metal layer is a doped polycrystalline silicon layer with a thickness of about 500 ~ 1000 Angstroms, and the thickness of the upper siliconized tungsten layer is about 100. 〇 ~ 2 0 0 0 Angstroms. 3. The method according to item 1 of the scope of the patent application, wherein the covering layer is a silicon nitride layer, and the deposited thickness thereof is between about 15 and 50 Angstroms. 4. The method according to item 1 of the scope of patent application, wherein the insulating spacer is formed by depositing a silicon nitride layer and then anisotropically etched back to form the insulating spacer, the thickness of which is about 400. ~ 100 Angstroms. 5. The method according to item 1 of the scope of patent application, wherein the second insulating layer is a silicon oxide layer 'deposited by a high-density plasma chemical vapor deposition method' and has a thickness of about 4000 to 8000 Between Egypt. 6. The method as described in item 1 of the scope of the patent application, wherein the doped polycrystalline silicon layer is deposited to a thickness that fills the contact opening and is simultaneously doped with an N-type conductive dopant to Its concentration is between 10〇19ι1 () E21 atoms / cm3. 7. The method according to item 1 of the scope of patent application, wherein the third insulating layer is a silicon oxide layer, which is deposited by a chemical vapor deposition method, and has a thickness of about 1 200 to 1 6000 angstroms. between. 8. The method according to item 1 of the scope of patent application, wherein the first metal layer is aluminum / copper, and the deposited thickness is between about 3000 and 5000 angstroms. The method described in item 1 of the scope of the patent application, wherein the retroreflective layer is a titanium nitride layer and the deposited thickness is between about 0001 and 500 angstroms.

IH 第23頁 41041β 六、申請專利範圍 1 0.如申請專利範圍第1項所述之方法，其中’該第四絕緣層係為氧化矽層，係由電漿加強化學氣相沈積法所沈積而成’且所沈積之厚度約在60 00〜12000埃之間。 11·如申請專利範圍第1項所述之方法，其中，該黏著層係為氮化鈦層，且所沈積之厚度約在600〜1 20 0埃之間。 12·如申請專利範圍第1項所述之方法，其中，該耐高溫金屬層係為鎢，且所沈積之厚度約在5 〇〇〇〜丨〇〇〇 0埃之間 c 13‘如申請專利範圍第1項所述之方法，其中，該第二屬層係為鋁/銅’且所沈積之厚度約在6〇〇〇〜1〇〇〇〇埃之間〇層包如申請專利範圍第1項所述之方法，其中，該保護以^上氣化石夕層’所沈積之厚度約在40〇〇~800 0埃之間， ~9ηίΐ“層之複晶5夕化金屬層’且所沈積之厚度約在 υϋ0埃之間。方法種在動態隨機接達記憶體電路中形成保險絲的 β包括下列步驟：由場— 導體基板，且於其上具有元件，其元件區係圖案之笛層區隔出來，而上述之元件一部份係由一經定義於=Γ複晶矽化金屬層所形成；絕緣層Y半導體基板上之該元件上方形成一平坦化的第I 洗積—笛一沐 —絕緣層上方一複晶矽化金屬層與一氮化矽覆蓋層於該第IH, page 23, 41041β VI. Patent application scope 10. The method described in item 1 of the patent application scope, wherein 'the fourth insulating layer is a silicon oxide layer and is deposited by a plasma enhanced chemical vapor deposition method And the deposited thickness is about 60 00 ~ 12000 angstroms. 11. The method according to item 1 of the scope of the patent application, wherein the adhesive layer is a titanium nitride layer, and the deposited thickness is between 600 and 120 angstroms. 12. The method according to item 1 of the scope of patent application, wherein the high-temperature-resistant metal layer is tungsten, and the deposited thickness is between about 50000 ~ 丨 000000 angstroms c 13 'as applied The method described in item 1 of the patent scope, wherein the second metal layer is aluminum / copper 'and the deposited thickness is about 600-1000 Angstroms. The method according to item 1, wherein the protective layer is deposited with a thickness of about 40,000 to 800 angstroms, and the thickness of the layer is about 9 ΐ "the polycrystalline layer of the crystalline layer" and The deposited thickness is between υϋ0 angstroms. The method of forming a fuse in a dynamic random access memory circuit includes the following steps: Field-conductor substrate with components on it, the flutes of the pattern of the component area Layer is separated, and a part of the above-mentioned element is formed by a polycrystalline silicon silicide layer defined by Γ; an insulating layer Y semiconductor substrate forms a flattened first washout-Di Yimu —A polycrystalline silicon silicide layer and a silicon nitride layer over the insulation layer In the first

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-—ilOilfi 六、申請專利範圍 Ϊ義該覆蓋層與該第二複晶梦化金屬層之圖案以於該之6己憶體單元區域形成位元線，並形成局部的具^ ，分作為保險絲之内連接線，且於該定義過圖案之日曰矽化金屬層之側壁上形成絕緣側壁層； —複沈積一第二絕緣層於該定義圖案之第二複晶矽化層上，並平坦化該第二絕緣層；屬钱刻出一接觸開口於該位於該位元線上方之該第二絕、與該第一絕緣層至該半導體基板以於該記憶體單元區域中做為自我對準節點電容；沈積一經推雜的複晶矽層於該第二絕緣層上與該接觸開口中；定義該複晶硬層的圖案以於該接觸開口形成自我對準接觸節點’並形成該節點電容，係與上述兩者接觸；沈積一第二絕緣層於該第二絕緣層與該節點電容上，並平坦化該第三絕緣層；，積一第一金屬層與一反反光層；定義該第一金屬層與該反反光層之圖案以形成電子式金屬内連線；沈積一第四絕緣層； #刻該第四絕緣層至該位於該第一金屬層上方之反反光層以形成介層洞’同時於用做保險絲之該部分的第二複晶矽化金屬層上蝕刻更寬之保險絲開口，真該保險絲開口係由蚀刻該第四絕緣層及部分之該第三絕緣層所形成’而上述之反反光層係防止了該第一金屬層的過度餘刻；--- ilOilfi 6. The scope of the patent application means that the pattern of the cover layer and the second polycrystalline dream metal layer is to form a bit line in the 6 memory cell unit area, and to form a local design, which is divided into fuses. Connecting lines, and forming an insulating sidewall layer on the sidewall of the silicided metal layer on the day of the defined pattern;-depositing a second insulating layer on the second polycrystalline silicided layer of the defined pattern, and planarizing the A second insulating layer; a contact opening is carved into the second insulation above the bit line and the first insulating layer to the semiconductor substrate as a self-aligned node in the memory cell area Capacitor; depositing a doped polycrystalline silicon layer on the second insulating layer and the contact opening; defining a pattern of the polycrystalline hard layer to form a self-aligned contact node 'at the contact opening and forming the node capacitance, It is in contact with the above two; a second insulating layer is deposited on the second insulating layer and the node capacitor, and the third insulating layer is planarized; a first metal layer and a reflective layer are stacked; defining the first One gold Layer and the retroreflective layer to form an electronic metal interconnect; deposit a fourth insulating layer; #etch the fourth insulating layer to the retroreflective layer above the first metal layer to form a via hole At the same time, a wider fuse opening is etched on the second polycrystalline silicon silicide layer used as the part of the fuse. The fuse opening is formed by etching the fourth insulating layer and a portion of the third insulating layer. The retro-reflective layer prevents excessive etch of the first metal layer;

第25頁 --4lQ41fi ____ 六、中請專利範圍 " ' '—' 沈積一氮化鈦黏著層’並沈積一耐高溫鎢金屬層，當移除在該保險絲開口中之該耐高溫鎢金屬時，回钱刻該咐兩溫鶴金屬層以於該介層洞中形成一耐高溫金屬栓；沈積一第一金屬層’並定義該第二金屬層的圖案以形成包括金屬焊接墊之金屬内連接線，且移除位於該保險絲開口之該第一金屬層’更飯刻該在該保險絲開口中之保險絲上方之該第三絕緣層；沈積一保護層於該半導體基板上，而該保護層係由氣化矽層與其上之複晶矽化金屬層所組成；使用單一光罩與非等向性餘刻法以餘刻該保護層至該第二金屬層以形成開口作為該焊接墊’並钱刻該保險絲開口至該第三絕緣層；以及選擇性地蝕刻該第三絕緣層與該第二絕緣層至位於該第二複晶矽化金屬層上方之該覆蓋層以完成該保險絲之該保險絲開口。 — 16. 如申請專利範圍第15項所述之方法，其中，該複晶矽化金屬層係為一經摻雜的複晶矽層，其間之厚度約在 500〜1 0 0 0埃間，且上層之鎢化矽層厚度約在1 00 0〜2 000埃之間。 17. 如申請專利範圍第15項所述之方法，其中，該氮一化矽覆蓋層所沈積之厚度約在15〇〇〜2 50 〇埃間。 18.如申請專利範圍第1 5項所述之方法’其中，該絕緣間隙壁係藉由沈積一氣化梦層再非等向性回鍅刻以形成該絕緣間隙壁，其厚度約在4 0 0〜1 〇〇〇埃之間。Page 25--4lQ41fi ____ Sixth, the scope of the patent claim " '-' Deposition of a titanium nitride adhesion layer 'and deposition of a high temperature resistant tungsten metal layer, when the high temperature resistant tungsten metal in the fuse opening is removed At the time, when the money is returned, the two temperature crane metal layers should be ordered to form a high temperature resistant metal plug in the interlayer hole; a first metal layer is deposited and the pattern of the second metal layer is defined to form a metal including a metal welding pad Interconnect the wires, and remove the first metal layer located at the fuse opening; moreover, the third insulating layer above the fuse in the fuse opening; deposit a protective layer on the semiconductor substrate, and the protection The layer consists of a vaporized silicon layer and a polycrystalline silicon silicide layer thereon; a single photomask and an anisotropic epitaxial method are used to leave the protective layer to the second metal layer to form an opening as the solder pad ' And engraving the fuse opening to the third insulating layer; and selectively etching the third insulating layer and the second insulating layer to the cover layer above the second polycrystalline silicon silicide layer to complete the fuse. Insurance Wire opening. — 16. The method according to item 15 of the scope of the patent application, wherein the polycrystalline silicon silicide layer is a doped polycrystalline silicon layer with a thickness between about 500 and 100 angstroms, and an upper layer The thickness of the tungsten silicon layer is between 1000 and 2000 angstroms. 17. The method according to item 15 of the scope of patent application, wherein the thickness of the silicon nitride oxide coating layer is between about 15,000 and 2500 angstroms. 18. The method according to item 15 of the scope of the patent application, wherein the insulating spacer is formed by depositing a gasification dream layer and then anisotropically etched to form the insulating spacer, and the thickness is about 40. 0 ~ 100 Angstroms.

第26頁 410416 —----- —___________ 六、申請專利範圍 1 9 如申請專利範圍第1 5項所述之方法’其中’該第二絕緣層係為氧化矽層，係利用高密度電漿化學氣相沈積法沈積而成’且其厚度約在4〇〇〇~80〇〇埃之間。 20. 如申請專利範圍第15項所述之方法’其中，該經摻雜的複晶矽層係沈積至一過填滿該接觸開口之厚度，並同時摻雜一N型傳導摻雜物至其濃度在1.0E19至1.0E21原子數/立方公分之間。 21. 如申請專利範圍第15項所述之方法’其中，該第三絕緣層係為氧化矽層，係由化學氣相沈積法沈積而成，且其厚度約在12000〜16000埃之間。 22. 如申請專利範園第15項所述之方法，其中，該第一金屬層係為鋁/銅，且所沈積之厚度约在3〇〇〇〜5〇〇〇埃之間。、 23. 如申請專利範圍第15項所述之方法，其中，該反反光層係為氮化鈦層，且所沈積之厚度約在丨Q00M 5〇〇埃之間。、 24. 如申請專利範圍第1 5項所述之方法，其中，該第四絕緣層係為氧化矽層，係由電漿加強化學氣相沈積法所沈積而成，且所沈積之厚度約在60〇〇〜1 200 0埃之間。 25 ^如申請專利範圍第1 5項所述之方法，其中，該氣化鈦黏著層所沈積之厚度約在60 0〜1 20 0埃之間。 26. 如申請專利範圍第15項所述之方法，其中該耐高溫鶴金屬層所沈積之厚度約在5000〜10000埃之間。、 27, 如申請專利範圍第1 5項所述之方法，其中，該第Page 26 410416 —----- — ___________ VI. Application scope of patent 1 9 The method described in item 15 of the scope of patent application 'wherein' the second insulation layer is a silicon oxide layer, which uses high-density electricity It is deposited by the slurry chemical vapor deposition method, and its thickness is between 4,000 and 80,000 angstroms. 20. The method according to item 15 of the scope of the patent application, wherein the doped polycrystalline silicon layer is deposited to a thickness that fills the contact opening and is simultaneously doped with an N-type conductive dopant to Its concentration is between 1.0E19 and 1.0E21 atoms / cm3. 21. The method according to item 15 of the scope of patent application, wherein the third insulating layer is a silicon oxide layer, which is deposited by a chemical vapor deposition method, and has a thickness between about 12,000 and 16,000 angstroms. 22. The method according to item 15 of the patent application park, wherein the first metal layer is aluminum / copper, and the deposited thickness is between about 3000 and 5000 angstroms. 23. The method according to item 15 of the scope of patent application, wherein the reflective layer is a titanium nitride layer, and the deposited thickness is between Q00M and 500 angstroms. 24. The method according to item 15 of the scope of the patent application, wherein the fourth insulating layer is a silicon oxide layer, which is deposited by a plasma enhanced chemical vapor deposition method, and the deposited thickness is about Between 60 and 120 Angstroms. 25 ^ The method according to item 15 of the scope of the patent application, wherein the thickness of the deposited titanium oxide adhesive layer is between about 60 and 120 angstroms. 26. The method according to item 15 of the scope of patent application, wherein the high-temperature resistant crane metal layer is deposited to a thickness of about 5000 to 10,000 angstroms. 27. The method as described in item 15 of the scope of patent application, wherein

第27頁 _410416_ 六、申請專利範圍二金屬層係為鋁/銅，且所沈積之厚度約在6000~10000埃之間。 28,如申請專利範圍第15項所述之方法，其中，該保護層之氮化矽部分所沈積之厚度約在4000〜80 0 0埃之間，且該複晶矽化金屬層所沈積之厚度約在700 00〜9 000 0埃之間。Page 27 _410416_ VI. Scope of patent application The second metal layer is aluminum / copper, and the deposited thickness is about 6000 ~ 10000 Angstroms. 28. The method according to item 15 of the scope of the patent application, wherein the thickness of the silicon nitride portion of the protective layer is between about 4000 and 80,000 angstroms, and the thickness of the polycrystalline silicon silicide layer is It is between 700,000 and 9,000 Angstroms.

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