TW400671B

TW400671B - Method and apparatus for clock recovery

Info

Publication number: TW400671B
Application number: TW83112167A
Authority: TW
Inventors: Walter M Pitto; Donald D Shugard
Original assignee: At & T Corp
Priority date: 1994-06-30
Filing date: 1994-12-24
Publication date: 2000-08-01

Abstract

A method and apparatus for recovering the time base of signals which change at periodic intervals is disclosed. The apparatus comprises gated voltage controlled oscillators (GVCO) that are alternated or exchanged, to reduce phase and frequency deviations in the recovered time base signal, such as the deviations induced by inherent GVCO differences. Each GVCO is stabilized by a respective phase locked loop. The respective GVCOs are gated only in response to a chosen polarity transition in the input signal, to make the circuit more tolerant of waveform distortions. More than two GVCOs may be used to provide improved frequency drift resistance. The circuit uses resynchronization control signals, such as the time slot signal in synchronous switching systems, to indicate resynchronization or reassignment the GVCO in gaps in the data transmission. Automatic reassignment is insured when there are periods of non-transitioning data that last longer then the stability of the GVCOs to prevent frequency drift in the recovered clock.

Description

五、發明説明:（1 ) 本發明的領域本發明是關於提供具有相關於一個輸入訊號，例如， —個恢復的時脈的一個定義的相位關係的同步化訊號的電路。尤其是，本發明關於提供這些訊號的訊號處理電路。相關技術之討論在數十億位元的光學資料網路中，有效率的接收器必須能夠在十億分之二十秒以內取得位元級同步化，保持同步十億分之5 0 0秒，然後在一些應用之中能夠在相同的短時間內取得與另一個訊號源的同步。在這些速度上，現有最先進的數位技術中，超量取樣並不是確保持脈準確性的一個實際方法。時脈恢復電路是必要的。美國專利第5，2 3 7，2 9 0號（> 2 9 0專利）發表了使用相符的可變頻率電壓控制振盪器（VC〇s ) 的一個時脈恢復電路。/ 2 9 0專利的內容在此被使用做爲參考。經濟部中央標準局員工消費合作社印製尤其是，/ 2 9 Q專利的圖8之中所示的相位鎖定迴圏時脈恢復電路是依據可能使用積體電路生產技術的多數振盪器電路物理和電氣特性的精確的回應而作用。因爲這些電路只被"間接地調整'，該電路的振盪器以略爲不同的頻率操作。振盪器之間頻率差値將被强調，使得當輸入的訊號如它是在1或0的未破斷的串列之中一樣而未轉變時在恢復的時脈和輸入的資料之間產生頻率漂移和可能的對不準現象。當輸入訊號長時間沒有轉變而恢復的時脈漂本紙張尺度適用中國國家標準（匸吣）八4規格（210/297公釐）—4 經濟部中央樣準局員工消費合作社印製 A7 B7 五、發明説明（2 ) 移時，當重新轉變時恢復時脈的柑位將會偏移，因而造成錯誤，直到振盪器可以再次被同步化爲止。另外一個可能的錯誤來源是由於資料輸入訊號的扭曲失眞所引起。失眞的主原因是傳輸媒介的電抗和類似的渦流效應扭曲了類比資料訊號所造成。由於在數位化門檻上所造成的不確定性，偵測的數位資料脈衝的有效寬度將會被大爲減小。這些扭曲失眞的資料訊號也在> 2 9 0電路中造成了一些問題。一個失眞的資料輸入將造成後續的時脈訊號失眞，使其脈衝寬度變得很窄小。當這些脈衝寬度變得太窄小時，它們將無法被可靠地使用於資料恢復電路之中。本發明之概要. 本發明產生用以對一個輸入資料訊號取樣的一個同步訊號，並且克服原有技術需要輸入資料流的最小作業循環和轉變密度的限制。本發明使用一個多數的振盪訊號，各自被調整爲一個參考的週期訊號。任何一個時刻的一個振盪訊號被連接至該同步化訊號，由於輸入資料的一個選定的轉變，一個新的振盪訊號被送出，相位對準輸入資料脈衝並且被連接至同步化訊號。當振盪訊號未連接於輸出時，它們將可以被暫停其作用或是被與一個參考時脈衝訊號重新同步化。這將產生— 個可靠的，容許失眞的，同步化訊號。這個同步化訊號具有與輸入訊號經過定義的相位關係，並且被用以恢復輸入本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐）V. Description of the invention: (1) Field of the present invention The present invention relates to a circuit for providing a synchronization signal having a defined phase relationship with respect to an input signal, for example, a recovered clock. More particularly, the present invention relates to a signal processing circuit for providing these signals. Discussion of related technologies In a multi-gigabit optical data network, an efficient receiver must be able to achieve bit-level synchronization within 20 billionths of a second and maintain synchronization at 500ths of a billionth of a second. , And then in some applications can be synchronized with another signal source in the same short time. At these speeds, over state-of-the-art digital technology is available, oversampling is not a practical way to ensure pulse hold accuracy. A clock recovery circuit is necessary. U.S. Patent No. 5,237,290 (> 290 patent) has published a clock recovery circuit using a matching variable frequency voltage controlled oscillator (VC0s). The contents of the / 290 patent are hereby incorporated by reference. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. In particular, the phase-locked loop-back clock recovery circuit shown in Figure 8 of the / 2 9 Q patent is based on most oscillator circuits that may use integrated circuit production technology. The precise response of the electrical characteristics works. Because these circuits are only "indirectly adjusted", the circuit's oscillator operates at a slightly different frequency. The frequency difference between the oscillators will be emphasized, so that when the input signal is in the unbroken string of 1 or 0 without being transformed, it is generated between the recovered clock and the input data Frequency drift and possible misalignment. The clock drifts when the input signal is restored without change for a long time. The paper size is in accordance with Chinese National Standard (匸吣) 8 4 Specifications (210/297 mm)-4 Printed by the Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs A7 B7 5 2. Description of the invention (2) When shifting, the citrus bit of the recovered clock will be shifted when re-transformed, thus causing an error until the oscillator can be synchronized again. Another possible source of error is caused by distortion and loss of data input signals. The main cause of the failure is that the reactance of the transmission medium and similar eddy current effects distort the analog data signal. Due to the uncertainty caused by the digitization threshold, the effective width of the detected digital data pulse will be greatly reduced. These distorted data signals also cause problems in the > 290 circuit. A missed data input will cause subsequent clock signals to be lost, making its pulse width very narrow. When these pulse widths become too narrow, they cannot be reliably used in data recovery circuits. SUMMARY OF THE INVENTION The present invention generates a synchronization signal for sampling an input data signal, and overcomes the limitation of the minimum operation cycle and transition density of the input data stream required by the prior art. The present invention uses a plurality of oscillating signals, each adjusted to a reference periodic signal. An oscillating signal at any time is connected to the synchronization signal. As a result of a selected transition of the input data, a new oscillating signal is sent out, phase-aligned with the input data pulse and connected to the synchronization signal. When oscillating signals are not connected to the output, they can be suspended or resynchronized with a reference pulse signal. This will produce a reliable, tolerant, synchronized signal. This synchronized signal has a defined phase relationship with the input signal and is used to recover the input. The paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm)

經濟部中央標準局員工消費合作社印製 A7 _B7 五、發明説明（3) 訊號上所收到的資料位元。本發明在數化偏碼的資料必須在沒有轉變資料時脈的狀況下被恢復時非常有用。尤其是，它相當適用於重新產生不穩定的轉變資料。本發明的一個實施例假定輸入資料流包含作用週期，在其間有效的資料被傳輸，以下被稱爲作用資料，中間以待機週期加以區隔，其間沒有任何有效資料被傳輸，稱爲間隙。這些間隙的時間不被用以同步化振盪訊號與已知和輸入資料訊號有相當接近的頻率同步化的一個參考訊號的頻率。振盪訊號必須穩定地保持頻率上與輸入資料訊號相當同步化，持續等於或大於最大作用週期的一段時間。利用原有技術已知的部份間隙的長度必須足以使振盪訊號能夠與參考訊號词步化。在本實施例之中，只需要兩個振盪訊號。在間隙期間，兩個振盪訊號均被與一個參考訊號的頻率同步化。在作用資料期間，兩個振盪凱號將反應具有一個已知極性的輸入訊號之中的轉變而交替地被送出並且連接至同步化訊號。在這些作用週期間，這些振盪訊號的頻率是利用在上一個間隙時所決定的偏壓訊號値所保持。本發明非常適用於資料間隙被有意地或以統計方式加以定位的系統。這些系統包括能夠完全決定地以一個每時間區劃方式捜尋定位作用資料和間隙的同步切換設備。相對於同步切換設備所需的時間鎖定間隙，資料網路系統可以以統計方式提供一個資料流中的間隙的一個確定的最小本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公瘦） (諳先聞讀背面之注意事填寫本頁) H— 填寫. 訂經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明.（4 ) 頻率，分佈和週期。這些系統提供可以啓動指示何時將發生這樣的以統計方式定位的間隙的一個傳輸監控訊號的碼或一些其它訊號，例如資料標題區塊或資料結尾區塊。例如衛星資料連結通訊設備和中控室框架中繼或 A TM切換設備系系統的高穩定性的要求必須使用反應一個週期訊號而在一個資料流中心以決定論方式定位的間隙，確保間隙的最小需求週期和頻率。傳輸和接收使用於光網路和交換機中的資料框格的）資料集模式通訊連結可以定址各個框格內的間隙，因而確保以每一框格爲基準的正確的同步化。在另一個可取的實施例之中，兩個振盪訊號被交替地提供至輸出端，而第三個則可以在其相位鎖定迴圈的控制下被執行而重新同步化。另外的這個振盪訊號將被提供，使得總是有一個振盪訊號在重新同步化模式下操作。在一個已知的時刻，重新同步化的振盪訊號被重新設定以便交替地產生一個輸出同步化訊號，而原先用以產生同步化訊號的一個振盪訊號被重新設定以便重新同步化。這些新的設定將對所有的三個振盪訊號有系統地實施，使得各自可以在相對於參考訊號產生顯著的漂移前輪替地重新同步化 0Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 _B7 V. Description of the invention (3) Data bits received on the signal. The present invention is very useful when the digitized partial code data must be recovered without changing the data clock. In particular, it is quite suitable for regenerating unstable transition data. An embodiment of the present invention assumes that the input data stream includes a period of action, during which valid data is transmitted, which is hereinafter referred to as the action data, and is separated by a standby period in the middle, during which no valid data is transmitted, called a gap. These gap times are not used to synchronize the frequency of a reference signal that synchronizes the oscillating signal with a frequency that is fairly close to the known and input data signals. The oscillating signal must be stably kept in synchronization with the frequency of the input data signal for a period of time equal to or greater than the maximum action period. The length of the partial gap known by the prior art must be sufficient to enable the oscillating signal to be stepped from the reference signal. In this embodiment, only two oscillation signals are required. During the gap, both oscillating signals are synchronized with the frequency of a reference signal. During the use of data, the two oscillating cels will be sent out alternately in response to a transition in an input signal with a known polarity and connected to a synchronization signal. During these cycles, the frequency of these oscillating signals is maintained using the bias signal 讯 determined during the previous gap. The present invention is very suitable for systems where data gaps are intentionally or statistically located. These systems include synchronous switching equipment that can completely locate positioning data and gaps in a time-zoned manner. Relative to the time lock gap required for synchronously switching devices, the data network system can statistically provide a determined minimum gap in a data stream. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 male thin) (谙 First read the notes on the back and fill in this page) H—Fill in. Order the A7 B7 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention. (4) Frequency, distribution and period. These systems provide a code or some other signal that can initiate a transmission monitoring signal indicating when such a statistically located gap will occur, such as a data header block or a data end block. For example, satellite data link communication equipment and central control room frame relays or ATM switching equipment systems require high stability. A gap that reflects a periodic signal and is located deterministically in a data flow center must be used to ensure the minimum demand for the gap. Period and frequency. The data set mode communication link used for transmitting and receiving data frames in optical networks and switches can address the gaps in each frame, thus ensuring correct synchronization based on each frame. In another preferred embodiment, two oscillating signals are alternately provided to the output, while the third can be resynchronized by being executed under the control of its phase locked loop. An additional oscillating signal will be provided so that there is always an oscillating signal operating in resynchronization mode. At a known time, the re-synchronized oscillating signal is reset to alternately generate an output synchronization signal, and an oscillating signal originally used to generate the synchronization signal is reset to re-synchronize. These new settings will be systematically implemented for all three oscillating signals, allowing each to alternately resynchronize before generating significant drift relative to the reference signal. 0

這個可取實施例在輸入資料流中沒有間隙的狀況下產生一個被可靠地相位同步化而且頻率調整同步化的輸出訊號。這對於資料流中沒有間隙或是不能以決定論方式產生間隙的系統，例如使用某些標準通訊協定，如S ONET 本紙張尺度適用中國國家標隼（CNS ) Λ4規格（210X 297公釐）—7 丨——I丨丨丨^^------、玎----- (請t閲讀背面之注意事^^填寫本頁) A7 _ B7 五、發明説明（5 ) 或T 3，或是無法忍受間隙的費用的系統而言，相當有利 0 這個可取實施例依賴輸入資料的正方向或負方向轉變 ’而不是兩個方向並行，因爲已知其輸入資料訊號作業循環所欠缺的對稱性是資料處理錯誤的一個原因。使用相位利用在輸入訊號中的一個特定的改變被同步化而且頻率被同步化爲一個穩定的參考値的閘流電壓控制振盪器提供一個穗定的重新產生的時脈訊號，使串聯的通訊訊號能夠快速地進行位元値同步化。本發明可以達到即使是資料流中的一個轉變那麼小的同步，使其能夠被使用於資料集模式或是連續的點對點應用之中。本發明可需要其主時脈恢復方式之中爲了超量取樣所使用的高速時脈，使得電路能夠被設計爲以任何已知的技術使資料傳送率最大化。本發明提供了一個健全的時脈恢復電路，比較不容易受到由於資料訊號遺失和漂移所產生的失眞所導致的資料錯誤的影響。經濟部中央標準局員工消費合作社印裝圖面的簡要說明配合提供的圖面硏讀以下的可取實施例的詳細說明將會更瞭解本發明的功能和優點，其中：圖1是一個閘流電壓控制振盪器（G V C 0 )時脈恢復電路的一個電路圖，依據> 2 9 0專利的圖8之中所示的電路；圖2是一個時間圖，顯示圖1中的電路沒有閘延遲的本紙悵尺度適用中國國家標準（CNS ) Λ4規格（2 ΙΟ X 297公釐） A7 _ B7____ 五、發明説明（6) 小型時脈之產生，更清楚地顯示訊號之間的因果關係：圖3是多重G V C 0等時脈恢復設備的一個高階概略方塊圖：圖4是依據本發明一個目前可取的實施例的一個雙 GVCO時脈恢復電路的一個概略圖；圖5是圖4並聯電路的一個概略圖；圖6是依據本發明的另一個目前可取的實施例的一個三個GVCO時脈恢復電路的一個概略圖；在這個圖面中，相同的參考數字標示相同的元件。 g.取實施例的詳細說明經濟部中央標準局員工消費合作社印製如> 2 9 0專利的圖8之中，在圖1的時脈恢復電路 1 〇之中，第一個和第二個GVC01 1，1 2經由轉換器1 6的作用而接收出現於輸入端1 4的非常完整的資料信號1 4 a。在它們被轉換器1 6使其極性反向之後，第 —個GVC0 1 1將被訊號1 4 a往負方向的轉變啓動其作用：而第二個GVC01 2將被資料訊號1 4 a往負方向的轉變啓動其作用。第一個和第二個GVC01 1 ， 1 2的頻率利用包括例如連接於參考訊號"f "的一個、相位偵測器'的相位鎖定迴圈元件的配合的控制電路的~ 個第三個相符的G V C 0 1 8被加以調整。各自的 GVCQ訊號1 1 a ，1 2 a被N〇R閘元件1 7以同步化訊號1 7 a的形式輸出。圖1中的原有技術的時脈恢復電路1 0有其傻點，但本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐）—9 _ A7 B7 五、發明説明（7) 是並非完全沒有問題。因爲GVCOs11 ，12是由數位的1和0資料値之間的轉變而啓動作用，當發生數位的 1或0的未破斷半列時，各別的啓動的GVCO的精確頻率變得非常重要。交替地被啓動作用的GVCOs 1 1和 1 2的頻率並不是依據它們實際的，各自的頻率被加以調整，而是依據一個控制電路GVC Ο 1 8的頻率。這個電路設計假定GVCOs 1 1 ，1 2 ，和1 8很類似，因而如果它們被相同的訊號所控制時可以在彼此具有可忽略的頻率差異的狀況下操作。然而，如果發生夠長的數位的1 或0的未破斷半列時，這三個GVC 0 s將不相同而導致頻率差異將造成G V C 0 s漂移。當轉變再次發生於資料訊號中時，將造成使用恢復的時脈的接收器中的資料錯誤 0 .這個原有技術的電路1 0的訊號波形失眞的問題更加嚴重。例如，在圖2之中，具有相同的時脈週期、t"的一個8稱的〃時脈訊號S 1和一個數位資料訊號5 2 在訊號於一個已知的網路中被傳輸時產生可對稱地扭曲失其的訊號'"S A 〃。圖2也顯示一個接收裝置偵測到該裝置用以產生數位化輸入訊號S D的輸入訊號中的轉變時的時檻値。失眞的資料脈衝的前和後綠造成數位化輸入訊號S D中相對於訊號S 2的原始的脈衝寬度、t " 相當窄小的脈衝寬度a w "。施加具有其減小的脈衝寬度、w 〃的訊號S d做爲圖 1的電路1 0中的輸入訊號1 4產生訊號1 1 2!和1 2 a 本纸張尺度適用中國國家標隼（CNS )八4規格（210X297公釐）_ (請先閲讀背面之注意事_This preferred embodiment produces an output signal that is reliably phase-synchronized and frequency-synchronized without gaps in the input data stream. This is for systems that have no gaps in the data stream or cannot generate gaps in a deterministic manner, such as using certain standard communication protocols, such as SONET. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) — 7 丨 ——I 丨丨丨 ^^ ------, 玎 ----- (Please read the notes on the back ^^ Fill this page) A7 _ B7 V. Description of the invention (5) or T 3 , Or a system that cannot tolerate the cost of the gap, it is quite advantageous. This preferred embodiment relies on a positive or negative transition of the input data, rather than two directions in parallel, because it is known that the input data signal cycle is lacking. Symmetry is a cause of data processing errors. The phase is synchronized using a specific change in the input signal and the frequency is synchronized to a stable reference. The thyristor voltage-controlled oscillator provides a fixed regenerated clock signal, making the serial communication signal It is possible to quickly synchronize bits. The invention can achieve even a small synchronization in the data stream, so that it can be used in data set mode or continuous point-to-point applications. The present invention may require the high-speed clock used in its main clock recovery method for oversampling, so that the circuit can be designed to maximize the data transfer rate by any known technique. The present invention provides a robust clock recovery circuit, which is relatively less susceptible to data errors caused by data loss due to data signal loss and drift. Brief description of the printed drawings of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs in conjunction with the drawings provided. Reading the following detailed description of the preferred embodiments will better understand the functions and advantages of the present invention, where: Figure 1 is a thyristor voltage A circuit diagram of the clock recovery circuit for controlling the oscillator (GVC 0), according to the circuit shown in Figure 8 of the > 2 0 0 patent; Figure 2 is a time chart showing the circuit of Figure 1 without gate delay The 怅 scale applies the Chinese National Standard (CNS) Λ4 specification (2 ΙΟ X 297 mm) A7 _ B7____ V. Description of the invention (6) The generation of small clocks more clearly shows the causal relationship between signals: Figure 3 is multiple A high-level schematic block diagram of a GVC 0 isoclock recovery device: FIG. 4 is a schematic view of a dual GVCO clock recovery circuit according to a presently preferred embodiment of the present invention; FIG. 5 is a schematic view of a parallel circuit of FIG. 4 Figure 6 is a schematic diagram of a three GVCO clock recovery circuit according to another presently preferred embodiment of the present invention; in this figure, the same reference numerals indicate phase Elements. g. Take a detailed description of the embodiment. In Figure 8 of the Consumer Cooperatives printed by the Central Standards Bureau of the Ministry of Economic Affairs, such as > 2 0 0 patents, among the clock recovery circuit 10 in FIG. 1, the first and second Each GVC01 1, 12 receives a very complete data signal 1 4 a appearing at the input terminal 14 through the action of the converter 16. After they are reversed in polarity by converter 16, the first GVC0 1 1 will be activated by the transition of signal 1 4 a to the negative direction: and the second GVC01 2 will be negative by the data signal 1 4 a The change of direction starts its effect. The frequency of the first and second GVC01 1, 1 2 utilizes, for example, a third control circuit including a phase detector 'phase lock loop element connected to a reference signal " f " A matching GVC 0 1 8 was adjusted. The respective GVCQ signals 1 1 a and 12 a are output by the NOR gate element 17 in the form of a synchronized signal 17 a. The original technology clock recovery circuit 10 in Figure 1 has its stupidity, but this paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) —9 _ A7 B7 V. Description of the invention (7 ) Isn't it perfectly fine. Because GVCOs 11 and 12 are activated by the transition between the digital 1 and 0 data frames, when the unbroken half-columns of the digital 1 or 0 occur, the precise frequency of the respective activated GVCO becomes very important. The frequencies of the GVCOs 1 1 and 12 that are activated alternately are not based on their actual, the respective frequencies are adjusted, but on the frequency of a control circuit GVC 0 18. This circuit design assumes that GVCOs 1 1, 1 2, and 18 are very similar, so they can operate with negligible frequency differences from each other if they are controlled by the same signal. However, if a sufficiently long unbroken half-column of 1 or 0 digits occurs, the three GVC 0 s will be different and the frequency difference will cause G V C 0 s to drift. When the transition occurs again in the data signal, it will cause a data error in the receiver using the recovered clock 0. The problem of signal waveform loss in this prior art circuit 10 is even more serious. For example, in Fig. 2, an 8-clock clock signal S 1 and a digital data signal 5 2 with the same clock cycle, t " are generated when the signal is transmitted in a known network. Distort the missing signal symmetrically " SA 〃. Figure 2 also shows the time threshold when a receiving device detects a transition in the input signal used by the device to generate the digitized input signal SD. Digitization of the front and back green of the missing data pulse results in digitization. The original pulse width of the input signal SD relative to the signal S 2, t " a relatively narrow pulse width a w ". The signal S d with its reduced pulse width, w 做 is applied as the input signal 1 4 in the circuit 10 of FIG. 1 to generate the signals 1 1 2! And 1 2 a. ) 8 4 specifications (210X297 mm) _ (Please read the notes on the back _

-訂經濟部中央橾準局負工消費合作社印製 10 - 經濟部中央標準局負工消費合作社印製五、發明説明（8 ) 。以N 0 R閘元 N 〇 R處理產生重的問題，即訊時脈不是一個完整的時脈寬度脈衝寬度爲"r '。如果小脈衝件1 7對訊號1 l a和1 2 a施以邏輯的訊號1 7 a。產生的訊號1 7 a有一個嚴號1 4 a的第一個正方向轉變後的第一個 / 這個小脈衝的具有一效時脈。因而保持與率同步的寬度脈將產效頻率圖統的一 1 0 2 路1 0 的一個個同步 1 0 0 料位元訊號，電被視爲一個5 0 %作業循環的時脈，它將個有效的時脈週期a e 〃。這些小脈衝、r 〃的有週期'e 〃顯著地比正常的資料時脈週期't"短接收器必_須能夠操作得比資料時脈的頻率快，以便這些失眞的訊號的顯著地較短的時脈寬度的有效頻。理論上，由具有正好資料的實際時脈週期、t " 的5 0 %的一個寬度的數位化資料脈衝所產生的時生有效地具有一個。脈衝寬度，和一個無限快的有的輸出時脈。 3顯示依據本發明的一個多重G.V C 0時脈恢復系個高階方塊圖。電路1 0 0與由局部時脈產生器局部地產生的一個參考時脈一起接收資料輸入。電〇的輸出是具有與輸入資料的一個定義的相位關係同步化訊號。經由產生相位上與輸入資料同步的一化訊號，一個資料處理電路可以使用來自電路的同步化輸出訊號定義接收的輸入資料訊號上的資。爲了消除不穩定，資料處理也必須接收參考時脈或者交替地具有其本身的內部時脈產生器電路。路1 0 0包含多重電壓控制的振盪器區塊1 1 〇和請先聞讀背之注意事項本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）_ 11 A 7 _____B7 五、發明説明（9 ) Ϊ· 1 1。不能有各種實施例，各自.處理兩個或更多的振盪器電路。各個電壓控制振盪器包括有由OUTPUT — εν訊號控制的一個輸出啓動電路，使輸出能夠被選擇性地啓動或解除作用。各個電壓控制振盪器可以反應V C 0 一εν輸入訊號被選擇性地啓動而執行或進行閘流，而當被啓動時，各個振盪器的相位將與啓動訊號對齊。因而這些區塊中的振盪器被稱爲閘流電壓控制振盪器GV c Ο S 。各個振盪器區塊中的振盪器被稱爲閘流電壓控制振盪器 GVCOs。各個振盪器區塊也包括能夠使振盪器的頻率與一個參考的時脈輸入訊號R E F — C L K同步的一個同歩化電路，例如一個相位鎖定迴圈。當SYNC_CE訊號被聲明時，振盪器區塊將被設定爲同步化模式。電路101控制送至所有GVCOs的所有啓動訊號。電路101控制GVCOs使得當輸入訊號上接收到有效的資料的任何時刻，一個GVCO將提供被用以產生電路1 0 0的DATA — CLOCK輸出訊號的VCO__ 經濟部中央標準局員工消費合作社印裝〇U T訊號。電路1 〇〇也必須切換提供用以產生 DATA — C LOCK以避免GUCO漂移的VCO — OUT訊號的GVC〇。每次GVCO s被切換而啓動訊號反應輸入訊號的轉變被聲明和解除聲明時，被啓動的GVCO的相位將對齊輸入訊號。另外，電路101必須使各個GVCO的頻率經常地與參考時脈訊號同步化以避免G V C Ο的頻率漂移超出一個可容許的範圍。本紙張尺度適用中國國'^標準（（:奶）/\4規格（210父2(;7公釐）_1<7- " 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（10) G V C Ο s的輸出被結合爲電路1 2 0中的一個單一的資料輸出時脈。電路1 2 0也可以經由電路1 0 1所產生的OUT_EN訊號被選擇性地解除作用。如果所有的 G V C Ο s被重新同步化確定glitches或錯誤的同步化訊號未被輸出於DATA — C LOCK訊號上，則這項功能有其潛在的必要性。電路1 3 0可以是各種不同的資料處理電路其中之一。常具的例子包括一個資料並聯化電路，一個串聯通道重覆器，供不連續訊號源使用的一個連續的週期性時脈訊號產生器，等。電路1 3 0接收電路1 0 0的DATA_ C LOCK輸出訊號並且用以定義輸入訊號上的資料位元。依據系統需求，電路1 3 0可能也需要接收局部的參考時脈訊號。本發明特別適用於產生一個資料時脈以便由一個不穩定傳輸訊號恢復其資料。這是由圖5的去不穩定化資料並聯化電路所表示。在一個特定的實施例中，它也非常適用於其中一個連續時脈必須由一個非連續的或大量的時脈源產生的系統。本發明只要在輸入訊號接收大量的時脈源便可以執行此功能，而同步化輸出訊號將產生連續時脈。圖4顯示依據本發明的一個第一個可取實施例的一個時脈恢復電路3 0。兩個GVCOs 3 1 ，3 2分別是由一個雙穗定的正反器3 4的，Q+ 〃和'"Q— 〃輸出啓動其作用。因爲這個電路中的GVCOs 3 1 ，3 2的輸入本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公麓） 13 C請先閱讀背面之注意事填寫本頁) 一-----------IT----------f------ 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（u) 是以正反器的'輸出所啓動，它們只對訊號3 6 a中的正方向的轉變加以反應。此外’ GVCOs 3 1 ，3 2經由產生於雙穩定的正反器3 4的和"Q —，輸出的訊號3 4 a和3 4 b的控制而被那些正方向的轉變交替地啓動。 —個極性選擇器3 6也被提供於這個實施例之中。由 'P 0 L_S E L"輸入控制的極性選擇器連接訊號 1 4 a或其反向的1 6 a於雙穩定的正反器3 4。當傳輸的訊號的失眞相當不對稱時，資料輸入訊號1 4 a的極性反轉將有幫助。明確地說，當極性被選擇而使較短的作業循環脈衝的前緣啓動G V C 0 s時，電路性能將被改善。各個G V C 0的頻率利用以虛線表示的各個相位鎖定迴圏（P L L ) 4 1 ，4 2被同步化。各個P L L具有以原有技術中已知的任何適合的方式提供一個訊號4 1 a， 4 2 a至一個各自的GVC04 1 ，4 2的頻率控制輸入 "F "的一個相位偵測器和一個^取樣並且保存〃濾波器。各個相位偵測器被提供以一個參考頻率訊號"f "。參考頻率是由'REF — CLK 〃輸入訊號上的一個局部訊號源所供應。然而，當一個傳輸監控訊號*SYNC_ PERIOD" 54a作用，表示資料並未由輸入訊號 1 4 a提供時，參考頻率* f '將經由A N D閘元件 45a，45b被供應至PLLs41 ，42。同時，由各個G V C Ο輸出的各個訊號·^ A g "和"B g "利用本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐）-14 (請先閲讀背面之注意事填寫本頁)-Order Printed by the Offshore Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 10-Printed by the Offshore Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (8). Processing with N 0 R gate element N 〇 R produces a serious problem, that is, the clock is not a complete clock width, and the pulse width is " r '. If the small pulse element 17 applies a logical signal 1 7 a to the signals 1 l a and 1 2 a. The generated signal 1 7 a has a strict signal 1 4 a. The first / this small pulse has a valid clock. Therefore, the width pulse that is synchronized with the rate will synchronize the output frequency signals of the 1 2 0 1 1 0 0 level signal. Electricity is regarded as the clock of a 50% duty cycle. A valid clock cycle ae 〃. These small pulses, r 〃 have a period 'e 〃 significantly longer than the normal data clock period' t " the short receiver must be able to operate faster than the frequency of the data clock so that these missing signals are significantly Effective frequency with shorter clock width. Theoretically, the time generated by a digitized data pulse with a width of 50% of t " with the actual clock period of exactly the data effectively has one. Pulse width, and an infinitely fast output clock. 3 shows a high-level block diagram of a multiple G.V C 0 clock recovery system according to the present invention. The circuit 100 receives data input together with a reference clock locally generated by the local clock generator. The output of the electric signal is a synchronized signal with a defined phase relationship with the input data. By generating a normalized signal that is synchronized in phase with the input data, a data processing circuit can use the synchronized output signal from the circuit to define the data on the received input data signal. To eliminate instability, the data processing must also receive a reference clock or alternatively have its own internal clock generator circuit. Road 1 0 0 contains multiple voltage-controlled oscillator blocks 1 1 〇 and notes for reading and reading. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) _ 11 A 7 _____B7 V. Invention Description (9) Ϊ · 1 1 There cannot be various embodiments, each dealing with two or more oscillator circuits. Each voltage-controlled oscillator includes an output enable circuit controlled by the OUTPUT — εν signal, enabling the output to be selectively enabled or disabled. Each voltage-controlled oscillator can respond to the V C 0 -εν input signal to be selectively activated for execution or thyristor, and when activated, the phase of each oscillator will be aligned with the activation signal. Therefore, the oscillators in these blocks are called thyristor voltage controlled oscillators GV c 0 S. The oscillators in each oscillator block are called thyristor voltage controlled oscillators (GVCOs). Each oscillator block also includes an synchronization circuit, such as a phase locked loop, that synchronizes the frequency of the oscillator with a reference clock input signal R E F — C L K. When the SYNC_CE signal is asserted, the oscillator block will be set to synchronization mode. The circuit 101 controls all activation signals sent to all GVCOs. Circuit 101 controls the GVCOs so that any time a valid data is received on the input signal, a GVCO will provide a VCO__ which is used to generate the DATA — CLOCK output signal of the circuit 1 0__ Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy Signal. The circuit 1 00 must also switch the GVC 0 that provides the VCO — OUT signal used to generate DATA — C LOCK to avoid GUCO drift. Each time the GVCO s is switched and the activation signal responds to the transition of the input signal is declared and de-asserted, the phase of the activated GVCO will be aligned with the input signal. In addition, the circuit 101 must frequently synchronize the frequency of each GVCO with the reference clock signal to prevent the frequency shift of G V C 0 from exceeding an allowable range. This paper size applies to China's standard ((: milk) / \ 4 size (210 father 2 (; 7 mm) _1 &7; " printed by A7 B7, Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs) V. Description of the invention (10) The output of GVC 0 s is combined into a single data output clock in circuit 120. Circuit 1 2 0 can also be selectively deactivated via the OUT_EN signal generated by circuit 1 0 1. If all GVC 0 s is resynchronized to determine that glitches or incorrect synchronization signals have not been output on the DATA — C LOCK signal, then this function has its potential necessity. Circuit 1 3 0 can be a variety of different data processing circuits One of them. Common examples include a data parallelization circuit, a series channel repeater, a continuous periodic clock signal generator for discontinuous signal sources, etc. Circuit 1 3 0 Receive circuit 1 0 The DATA_C LOCK output signal of 0 is used to define the data bits on the input signal. Depending on the system requirements, the circuit 130 may also need to receive a local reference clock signal. The invention is particularly suitable for generating a data The clock in order to recover its data by an unstable transmission signal. This is represented by the destabilizing data parallelization circuit of Fig. 5. In a specific embodiment, it is also very suitable for a continuous clock where A non-continuous or a large number of clock source generation system. The present invention can perform this function as long as the input signal receives a large number of clock sources, and the synchronized output signal will generate a continuous clock. Figure 4 shows the A clock-recovery circuit 30 of a first preferred embodiment. The two GVCOs 3 1 and 3 2 are respectively set by a double-swapped flip-flop 3 4, Q + 〃 and '" Q— 〃 output start Its role. Because the input of GVCOs 3 1 and 3 2 in this circuit is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 male foot) 13 C, please read the notes on the back first and fill in this page) 1 --- -------- IT ---------- f ------ Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Invention Description (u) is a flip-flop '' Outputs are activated, they only apply to positive direction transitions in signal 3 6 a In addition, GVCOs 3 1, 3 2 are alternately activated by those positive direction transitions by controlling the output signals 3 4 a and 3 4 b generated by the sum of the bistable flip-flops 3 4 " Q —. A polarity selector 36 is also provided in this embodiment. The polarity selector controlled by the 'P 0 L_S E L " input connects the signal 1 4 a or its reverse 1 6 a to the bi-stable positive Inverter 3 4. When the loss of the transmitted signal is quite asymmetric, the polarity reversal of the data input signal 14a will help. Specifically, when the polarity is selected so that the leading edge of the short duty cycle pulse starts G V C 0 s, the circuit performance will be improved. The frequency of each G V C 0 is synchronized with each phase lock loop (P L L) 4 1, 4 2 indicated by a dotted line. Each PLL has a phase detector " F " that provides a signal 4 1 a, 4 2 a to a respective GVC04 1, 4 2 frequency control input in any suitable manner known in the art, and A ^ sample and save the 〃 filter. Each phase detector is provided with a reference frequency signal " f ". The reference frequency is supplied by a local signal source on the 'REF — CLK' input signal. However, when a transmission monitoring signal * SYNC_PERIOD " 54a is applied, indicating that data is not provided by the input signal 1 4a, the reference frequency * f 'will be supplied to the PLLs 41, 42 via the AN gate devices 45a, 45b. At the same time, each signal output by each GVC 〇 ^ A g " and " B g " Use this paper size to apply Chinese National Standard (CNS) Λ4 specification (210X297 mm) -14 (Please read the note on the back first (Fill in this page)

-5 A7 B7 五、發明説明（l2) AND閘元件4 6，4 7被供應至P 1 1 4 1，4 2 ’而兩個GVCOs 3 1 , 3 2均反應控制訊號5 4 a，經由 NOR閛元件56，57被啓動。針對GVCOs ，由它們各自的相位鎖定迴圈4 1 ， 4 2所產生的VCO偏壓控制訊號41a，42a保持於閘隙被P L L s中的·各個^取樣並保存"> 電路終止之前便存在的値。因而，當輸入1 4沒有資料時，""SYNC — P E R 1 0 D，輸入訊號可以使GVCOs利用PLL 4 1，4 2直接與參考頻率'同步化。當GVCOs重新同步化時，>SYNC_ PER 1 0D 〃訊號也被用以解除輸出閘元件5 2的同步化訊號的作用。危險防止經濟部中央檁準局員工消費合作社印製在本發明的一個特定的可取實，施例之中存在有在原有技術中大家所熟知的一個典型的邏輯危險。該危險是來自於GVCOs 3 1和3 2的兩個時脈啓動N〇R閘元件是由NOR閘元件5 3以邏輯的NOR加以處理。該電路中的時序可能是當GVCOs反應輸入訊號1 4 a切換時一個錯誤的小脈衝在輸出5 2 a產生。依據此項技術，一個 NOR閘元件9 0被增加於電路以避免邏輯上的危險。然而，由於GVCOs 3 1 ，3 2輸出的訊號Ag ，-5 A7 B7 V. Description of the invention (l2) AND gate elements 4 6, 4 7 are supplied to P 1 1 4 1, 4 2 'and the two GVCOs 3 1, 3 2 both respond to the control signal 5 4 a, via NOR The thorium elements 56, 57 are activated. For GVCOs, the VCO bias control signals 41a, 42a generated by their respective phase-locked loops 4 1, 4 2 are held in the gate gap and sampled and saved by the PLL s before each circuit is terminated. Existing puppet. Therefore, when input 1 4 has no data, " " SYNC — P E R 1 0 D, the input signal can make GVCOs use PLL 4 1, 4 2 to synchronize directly with the reference frequency. When the GVCOs are resynchronized, the > SYNC_PER 1 0D 〃 signal is also used to deactivate the synchronization signal of the output gate element 52. Prevention of dangers Printed by the Consumer Cooperatives of the Central Bureau of Quasi-Ministry of the Ministry of Economic Affairs In a particular desirable embodiment of the present invention, there is a typical logical danger that is well known in the prior art. The danger comes from the two clock-activated NOR gate elements of GVCOs 31 and 32, which are handled by the NOR gate element 53 in a logical NOR. The timing in this circuit may be that an incorrect small pulse is generated at the output 5 2 a when the GVCOs respond to the input signal 1 4 a switching. According to this technology, a NOR gate element 90 is added to the circuit to avoid logical danger. However, due to the signal Ag output by GVCOs 3 1, 3 2,

Bg被閘流，GVCO輸出Ag ，Bg並不適合做爲傳統的·"第三個N 0 R '閘元件9 0的輸入。爲了解決這個問本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ 五、發明説明（l3) 題，在啓動訊號E —與訊號A和Βι被加以NOR處理之前，用於手閘流的振盪器輸出A，B的內部停止訊號被提供於依據本發明的這個功能的G V C 0 s 3 1 ，3 2內。資料#聯化時脈恢復電路3 0利用反應一串列的資料輸入位元產生一串列的時脈而操作。當資料出現時，同步化訊號 5 2 a利用輸出邏輯，此處爲一個NOR閘5 2被連接至資料並聯化電路5 0的輸入"R 〃。經由使用同步化訊號 5 2 a，並聯化電路5 0可以消除輸入資料中發現的不穩定，因爲GVCOs 3 1和3 2在每一次一定極性的資料請閲讀背之注意事 i 經濟部中央標準局員工消費合作社印裝輸入轉位將與由於輸出號1 4 路6 0 5 0的產生時償，使的轉變必要的 6 0 a 而，當變時相位其相對應於伴隨同訊號5 2 a上。資延遲，使設定和保脈。另外得造成的。要正確。經由此和同步化彼此對應將與資料對齊。產生的同步化脈步化訊號電路的 a之前，輸入資料轉變' d "利得延遲的資料位存時間，就好像，延遲電路必須時脈完全配合產地消除電路5 0 項技術，當由外訊號5 2 a看起地觀察時，它們 —個輸入位元"d "的相衝' C 〃對齊。延遲，在脈衝"C 〃發生料位元’d "將發生於訊用原有技術中已知者被電元完全對齊以符合電路它是以同步化脈衝"C " 針對傳播延遲被正確地補生它的資料輸入訊號之中之中的不穩定的話，這是部觀察時，資料訊號來可能仍然不太穩定：然的不穩定將被同步化，而 16 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）經濟部中央標準局員工消費合作社印製 A7 _____B7_________ 五、發明説明（l4) 訊號6 0 a和5 2 a之間的相位關.係可以被保持於一個常數。圖5較詳細地說明將延遲的輸入訊號6 0 a處理成爲 •8位元字元的過程。延遲訊號6 0 a的8個序列時脈週期利用恢復的訊號5 2 a被以時脈方式送入正反器6 4 A至 6 4 H。起始字元偵測電路在正反器6 4 A至6 4 Η之中發現一個符合的起始字元模式，而且它將產生一個 '"字元對齊偵測訊號'脈衝6 5 a。訊號6 5 a被用以啓動時脈分隔器6 6 ，使其以5 2 a的速度的八分之一速度開始產生時脈訊號6 6 a，訊號6 6 a的相位直接對齊訊號 5 2 a而且與訊號6 6 a擁有相同數目的不穩，即使現在該不穗定由於時脈被劃分爲較小的間隔而包含較小比例的同步化訊號週期。時脈訊號6 6 a被用以由正反器6 4A 至6 4H傳送資料的8個位元至暫存器6 7內。訊號6 5 A a也可以被外部電路用以使用原有技術中已知者決定一個接收到的資料集的開端。訊號6 6 a是由產生頻率與訊號6 6 a同步但是沒有任何不穩定的一個乾淨的無不穩定的時脈訊號6 9 a的時脈產生器電路6 9所接收。訊號6 9 a並非自由地流動，而是由訊號6 6 a予以閘流，所以由電路6 9產生於訊號 6 9 a上的脈衝數目正好等於電路6 9在訊號6 6 a上接收的脈衝數目。這個電路可以使用原有技術中已知的一個閘流的相位鎖定迴圈或其它技術。訊號6 9 a被用以將資料暫存器6 7傳送至輸出暫存器6 8內。暫存器6 8產生本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-I? ''装-- J (請先閲讀背面之注意事'^蛾寫本頁) 訂 A7 B7 五、發明説明（15) 整個被稱爲5 0 a的資料字元輸出.訊號W0至W 7。訊號 6 9 a也被提供於外部電路。訊號6 9 a和資料輸出字元 5 0 a均是完全沒有不穩定現象，因爲它們在頻率和相位上均與完全沒有不穩定現象的同步。訊號5 4 a指示沒有作用資料出現於輸入訊號1 4 a 上。在這個間隙間距期間，同步化訊號電路執行重新同步化，而沒有任何同步化訊號被提供於訊號5 2 a上而進入電路5 0內。當訊號5 4 a被聲明時將啓動起始字元偵測器6 5。爲作用資料出現於訊號14 a上而訊號5 4 a被解除聲明時，起始字元偵測器6 5將開始搜尋下一個符合的起始字元模式。由於電路5 0的輸出5 0 a在輸入資料中的間隙期間被解除作用，而且直到在輸入資料流中發現一個新的起始字元模式才恢復，電路5 0的輸出只包含有效的作用資料 0 使用多重GVCOs 圖6顯示本發明的另一個可取實施例，電路7 0 ，其中三個GVC〇s 3 1 ，3 2 ，3 3提供同步化訊號。本實施例的功能原則上類似於圖4之中說明者；因此圖6是一個簡化的圖，省略了兩個實施例中相同的許多電路細節而强調其電路不同的部份。明確地說，圖4之中執行極性選擇功能，危險防止，及並聯化功能的電路並出現於圖6 之中。任何熟悉此項技術的人士顯然應該知道如何修改圖 6之中的電路實施例使其包含圖4之中另外的電路，以及本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0 X 297公釐）-18 - ^^^1 1^1 In ml (請先閲讀背面之注意事填寫本頁) ---------、«τ----- 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（l6) /或者修改圖6之中的3 GVCO. s實施例爲使用4個或更多GVCOs的一個電路。經濟部中央標準局員工消費合作社印製Bg is gated and GVCO outputs Ag. Bg is not suitable as the input of the third " N0R 'gate element 90. In order to solve this problem, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 5. Description of the invention (l3), before starting the signal E — and the signals A and Bι are NOR processed, it is used for manual operation. The internal stop signals of the oscillating oscillator outputs A, B are provided in GVC 0 s 3 1, 3 2 according to this function of the present invention. The data #linking clock recovery circuit 30 operates by generating a series of clocks by responding to a series of data input bits. When the data appears, the synchronization signal 5 2 a uses the output logic, here a NOR gate 5 2 is connected to the input of the data parallelization circuit 50 0 " R 〃. By using the synchronization signal 5 2 a, the parallelization circuit 50 can eliminate the instability found in the input data, because GVCOs 3 1 and 3 2 read the data of a certain polarity each time. Please read the note below. Central Bureau of Standards, Ministry of Economic Affairs Employee consumer cooperatives ’printed input indexing will be compensated for the necessary change due to the production of output number 1 4 6 0 5 0, and the phase of the change will correspond to the accompanying signal 5 2 a . The information delays the setting and the pulse. In addition must be caused. Be right. After this and synchronization, they correspond to each other and will be aligned with the data. Before the a of the synchronized pulsed signal circuit is generated, the input data is transformed 'd " to obtain the delayed data bit storage time. It is as if the delay circuit must fully cooperate with the origin elimination circuit 50 clock technology, when the external signal 5 2 a When looking up from the ground, they—the collision of the input bits " d " C 〃 are aligned. The delay occurs in the pulse " C 料 material level 'd " will occur when the signal is known in the prior art and is completely aligned by the electronics to conform to the circuit. It is based on the synchronization pulse " C " for the propagation delay If the instability in its data input signal is correctly regenerated, this is an observation, the data signal may still be unstable: of course, the instability will be synchronized, and the 16 paper standards are applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 _____B7_________ V. Description of the invention (14) The phase relationship between the signals 6 0 a and 5 2 a. It can be determined by Keep it constant. Fig. 5 illustrates the process of processing the delayed input signal 60a into an 8-bit character in more detail. The eight sequential clock cycles of the delayed signal 60 a are clocked into the flip-flops 6 4 A to 6 4 H using the recovered signal 5 2 a. The start character detection circuit finds a matching start character pattern in the flip-flops 6 4 A to 6 4 Η, and it will generate a '" character alignment detection signal' pulse 6 5 a. The signal 6 5 a is used to activate the clock divider 6 6 to start generating the clock signal 6 6 a at a one-eighth speed of the speed of 5 2 a, and the phase of the signal 6 6 a is directly aligned with the signal 5 2 a Moreover, it has the same number of instabilities as the signal 6 6 a, even though the frequency of the signal is now divided into smaller intervals and the synchronization signal period is smaller. The clock signal 6 6 a is used to transfer 8 bits of data from the flip-flops 6 4A to 6 4H to the register 6 7. The signal 6 5 A a can also be used by an external circuit to determine the start of a received data set using a person known in the art. The signal 6 6 a is received by a clean clock generator circuit 6 9 generating a frequency that is synchronized with the signal 6 6 a but without any instability. Signal 6 9 a does not flow freely, but is blocked by signal 6 6 a, so the number of pulses generated by circuit 6 9 on signal 6 9 a is exactly equal to the number of pulses received by circuit 6 9 on signal 6 6 a . This circuit can use a thyristor phase-locked loop known in the art or other techniques. The signal 6 9 a is used to transfer the data register 6 7 to the output register 6 8. Register 6 8 produced This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -I? '' Pack-J (Please read the note on the back first '^ Moth write this page) Order A7 B7 V. Description of the invention (15) The entire data character output called 50a. Signals W0 to W7. The signal 6 9 a is also provided to the external circuit. The signal 6 9 a and the data output character 5 0 a are completely free of instability, because they are synchronized in frequency and phase with no instability. Signal 5 4 a indicates that no effect data appears on input signal 1 4 a. During this gap interval, the synchronization signal circuit performs resynchronization, and no synchronization signal is provided on the signal 5 2 a and enters the circuit 50. When signal 5 4 a is asserted, the start character detector 6 5 is activated. When the function data appears on signal 14a and signal 5 4a is undeclared, the start character detector 65 will start searching for the next matching start character pattern. Since the output 50 a of circuit 50 is deactivated during the gap in the input data, and it is not restored until a new starting character pattern is found in the input data stream, the output of circuit 50 contains only valid data 0 Using Multiple GVCOs FIG. 6 shows another preferred embodiment of the present invention, a circuit 70, in which three GVCs 3 1, 3 2, 3 3 provide synchronization signals. The function of this embodiment is similar to that illustrated in FIG. 4 in principle; therefore, FIG. 6 is a simplified diagram, omitting many of the same circuit details in the two embodiments and emphasizing the different parts of the circuit. Specifically, the circuit for performing the polarity selection function, the danger prevention, and the parallelization function shown in FIG. 4 is shown in FIG. 6. Anyone familiar with this technology should obviously know how to modify the circuit embodiment in Fig. 6 to include the other circuit in Fig. 4 and that this paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 Mm) -18-^^^ 1 1 ^ 1 In ml (Please read the notes on the back and fill out this page first) ---------, «τ ----- Staff of the Central Bureau of Standards, Ministry of Economic Affairs The consumer cooperative prints A7 B7 V. Description of the invention (16) / or the 3 GVCO.s embodiment shown in FIG. 6 is a circuit using 4 or more GVCOs. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs

本實施例的目的是消除對GVCO s在其間可以與~ 個參考値同步化的輸入資料流中的間隙的需求。由於當接收到作用資料時兩個G V C 0 s必須提供同步化脈衝，這個實施例提供一個另外的GVCO，因而在另外兩個 GV C 0 s提供同步化訊號時使得任何一個GV C 0能夠被重新同步化。GVCO的閘流輸出Ag，Bg ，Cg可以利用其各別相對應的P L L 4 1 ，4 2，4 3各自被加以調整。各個G V C 0的輸出在電路8 0的控制下經由一個A N D閘元件7 4 ，76和7 8被啓動。各個 GVCOE —輸入是由一個邏輯電路.8 1 ，8 2 ，8 3所驅動。邏輯電路8 1 ，8 2和8 3爲其各自的GVCO針對E — G V C 0啓動訊號選擇以下三個操作模式其中之一 ;所有時刻均啓動作用，當訊號3 4 a低時啓動作用，當訊號3 4b低時啓動作用。電路8 0產生控制訊號EN__ POS和EN — NEG。在圖6之中，三組控制訊號被標示爲控制電路8 1的EN — POSa，EN_NEGa，控制電路8 2的EN_P〇S，EN_NEGb，以及控制電路8 3的EN — P〇Sc ，EN_NEGc 。三個啓動重新同步化訊號分別針對GVCOs 3 1 ，3 2 ，和 3 3 被標示爲 EN_SYNCa，EN_SYNCb，以及EN_SYNCc。電路8 0產生控制各個PLLs的啓動重新同步化訊號EN — SYNC。當EN_SYNC 本紙張尺度適用中關家標準（CNS ) A4規格（210X297公#)_ 19 _— 經濟部中央標準局負工消費合作社印製 A7 _______B7___ 五、發明説明（l7) 訊號髙時，P L L S將執行它們柑對應的GVCO的輸出與週期性的參考訊號4 4 a之間的相位比較。當EN_ SYNC訊號低時，PLLs將被解除作用而PLL的頻率控制輸出訊號F將被保持於當EN_SYNC訊號高時的原有狀態。當EN_SYNC訊號由低轉變爲高時，使用原有技術中已知的方法和技術啓動它們的內部相位比較器，以便消除GVCO的輸出和參考訊號4 4 a之間的起始相位差，對於P L L s來說是有利的。這使得整個同步化週期被用以調整GVCO的頻率，而不是重新獲得相位 •同步。訊號3 4 a和3 4 b是正反器3 4的輸出而且永遠互補。正反器3 4是由輸入訊號1 4 a提供時脈訊號而其功能是每一次訊號14a正方向轉變時交替改變訊號 3 4 a和3 4 b的狀態。在電路7 0操作時的任何時刻，控制電路8 0選擇將被稱爲GVCO s 'X "和'的一對GVCO s並且利用設定其相對應的GVCO s的輸出啓動控制訊號0E爲高而啓動它們的輸出。在圖6之中，三個輸出啓動電路分別相對應於GVCOs 3 1 ’ 3 2 和3 3被標示爲〇Ea，OEb，和〇Ec °將被稱爲 GVCO 〃的第三個GVCO在電路8 0的控制下利用使其相對應的輸出啓動控制訊號設定爲低而使其輸出被解除作用。同時，電路8 0選擇所有三個GVCO s的 E _輸入所使用的操作模式。利用設定G V C Ο ' Z 〃的相對應EN — P 0 S和ΕΝ — NE G訊號爲低而將其置於、所有時刻均啓動"的狀態。電路8 〇選擇GVC0 "x 本紙張又度適用中國國家標準（CNS ) Λ4規格（210X_297公釐）_ 20 - (請先閱讀背面之注意事^Sp%寫本頁) ------~.--.---y#—-----IT----- 五、發明説明（18) '爲當訊號3 4 a變低時啓 POS訊號設定爲高，而其對於GVCO，電路動。該GVCO使其ΕΝ__ EN__NEG訊號設定爲低。 8 0也設定訊號EN — POS 爲低，而EN — NEG爲高，因而使其在訊號3 4 b變低對應於GVCO 的EN 外兩個GVCOs的EN_ 經濟部中央標準局員工消費合作社印製時被啓 _ S Y S Y N 所 P L L 連續地作用以隨正方向啓動。被進行入的正個將產期性訊一直持動。電 N C爲 C訊號得的架 s調整啓動。避免其著訊號轉變時它們的 0 R處方向轉生相位號4 4 續到輸The purpose of this embodiment is to eliminate the need for gaps in the input data stream during which the GVCO s can be synchronized with ~ reference frames. Since two GVC 0 s must provide synchronization pulses when receiving the action data, this embodiment provides an additional GVCO, so that any two GV C 0 can be re-enabled when the other two GV C 0 s provide synchronization signals. Synchronization. The thyristor outputs Ag, Bg, and Cg of the GVCO can be adjusted by using their respective corresponding P L L 4 1, 4 2, and 4 3. The output of each G V C 0 is activated by an A N D gate element 7 4, 76 and 78 under the control of the circuit 80. Each GVCOE — the input is driven by a logic circuit 8 1, 8 2, 8 3. Logic circuits 8 1, 8 2 and 8 3 select one of the following three operating modes for their respective GVCOs for the E-GVC 0 start signal; the function is activated at all times, when the signal 3 4 a is low, when the signal 3 Starts when 4b is low. Circuit 80 generates control signals EN__POS and EN — NEG. In FIG. 6, three sets of control signals are marked as EN_POSa, EN_NEGa of the control circuit 81, EN_POS, EN_NEGb of the control circuit 82, and EN_POS, EN_NEGc of the control circuit 82. The three start resynchronization signals are labeled EN_SYNCa, EN_SYNCb, and EN_SYNCc for GVCOs 3 1, 3 2, and 3 3 respectively. Circuit 80 generates the start resynchronization signal EN — SYNC that controls each PLLs. When EN_SYNC This paper standard is applicable to the Zhongguanjia Standard (CNS) A4 specification (210X297 公 #) _ 19 _— printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _______B7___ V. Description of the invention (l7) The signal will be issued by PLLS. Perform a phase comparison between the output of their corresponding GVCO and the periodic reference signal 4 4 a. When the EN_SYNC signal is low, the PLLs will be deactivated and the frequency control output signal F of the PLL will be maintained at the original state when the EN_SYNC signal is high. When the EN_SYNC signal changes from low to high, start their internal phase comparators using methods and techniques known in the prior art in order to eliminate the initial phase difference between the output of the GVCO and the reference signal 4 4 a. For PLL s is advantageous. This allows the entire synchronization cycle to be used to adjust the frequency of the GVCO, rather than regaining phase. The signals 3 4 a and 3 4 b are the outputs of the flip-flop 34 and are always complementary. The flip-flop 34 is provided with a clock signal by the input signal 1 4 a and its function is to change the state of the signals 3 4 a and 3 4 b alternately each time the signal 14a changes in the forward direction. At any time when the circuit 70 is operating, the control circuit 80 selects a pair of GVCOs to be called GVCO s 'X " and' and sets the output of the corresponding GVCO s to activate the control signal 0E to be high and Start their output. In Figure 6, the three output start-up circuits corresponding to GVCOs 3 1 '3 2 and 3 3 are labeled as 0Ea, OEb, and 0Ec °. The third GVCO will be referred to as GVCO in circuit 8. Under the control of 0, the corresponding output start control signal is set to low, and its output is deactivated. At the same time, the circuit 80 selects the operating mode used by the E_ inputs of all three GVCOs. By setting the corresponding EN — P 0 S and EN — NE G signals of G V C Ο 'Z 〃 to be low, they are placed in a state of being activated at all times. Circuit 8 〇 Select GVC0 " x This paper is again applicable to the Chinese National Standard (CNS) Λ4 specification (210X_297mm) _ 20-(Please read the notes on the back first ^ Sp% write this page) ------ ~ .--.--- y # —----- IT ----- V. Description of the invention (18) 'is to set the POS signal to high when the signal 3 4 a goes low, and it is important for GVCO The circuit moves. The GVCO sets its EN__EN__NEG signal to low. 8 0 also sets the signal EN — POS to low and EN — NEG to high, so that it becomes low at signal 3 4 b corresponding to the EN of the two GVCOs outside the EN of the GVCO. The PLL activated by _SYSYN is continuously applied to start in the positive direction. The entrants have been kept informed of the interim news. The signal N C is adjusted by the C signal. Avoid the direction transition phase of their 0 R direction when the signal changes.

G V C 0 s 的，而且解除先當作資料 4之中的G V ，各個G V C 路8 0設定相高，而設定另爲低。構使得G V C 其頻率以符合在這段期間，造成任何資料 3 4 a 和 3 4 改變狀態，其輸出被啓動，理以產生恢復變時，該對G 對齊輸入資料 A a同步的同入訊號的下一另一個G V C 前被啓動的G 出現於輸入時 C 0 S所執行 0訊號的頻率 0 ' Z 周期性 G V C 錯誤。 b在每它兩個然後經的時脈 V C 0 轉變，步化脈個正方 0被啓 V C 0 ，這對的功能被在以 #在其相對應的的參考訊號4 4 a時被 0 的輸出被解除 —次輸入 G V C 0 由0 R閘輸出訊號，X '或而頻率幾衝。這些向轉變。動，因而的作用。 G V C 0 訊號1 s將被元件7 R。每^ γ ^ 乎與參同步化這使得產生週 4 a往交替地 2 —起一次輸任何一與的週脈衝將該對期脈衝的功能與圖相同。在這些作用期間 —次各個GVCO被設本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）—21 請聞讀背意事項再寫本頁 A 7 B7 五、發明説明（19) 定爲與輸出斷路而被容許與參考頻率同步化的—個單位期間所決定的偏壓訊號値加以維持。輪替/重新設定圖6中的實施例經由對稱地重新設定那些GV C 0 s 爲、X"和'"對，何者爲'Z"而操作。由控制電路 8 0所控制的重新設定必須符合兩個要求：三個G V C 0 各自均須在其G V C 0漂移相對於參考的週期性訊號超過一個容許量之前被設定爲"z" G V C 0而使其能夠重新同步化，而GVCO在下一個重新設定之前必須被提供足夠的時間以進行同步化。經濟部中央標準局員工消費合作社印製原有技術中大家熟知的一個效應是非常穩定的振盪器可以容許相當長的時間才會漂移；然而，這些相同的振盪器重新同步化通常也需要相當長的時間。另一方面，穩定性低的振盪器可以快速地被重新同步化，但是它們也在很短的時間後便會源移。選擇所需的振盪器穩定性和相對應的重新設定的時間間隔是一項標準的工程最佳化的作業，依據技術和應用二者有所不同，而且任何熟悉此項技術之人士均瞭解。最簡單的重新設定策略是週期性地轉換所有三個 GVCO，依次設定每一個爲GVCO。其它重新設定模式，例如虛擬.隨機，只要符合上述的要求，也可以被使用。具有三個以上的G V C〇s的實施例可以得到更多的重新設定模式。本紙張尺度適用中國國家標準（CNS ) Λ4規格（2ΐ〇χ 297公釐）-22 Α7 Β7 五、發明説明（20) 圖6之中的電路的可取實施例.使用一個外部的時脈參考訊號4 4 a建立用於重新設定的一個時序基準而執行一個輪替的重新設定。在電路8 0內部，參考訊號4 4 a被向下區劃而以重新設定頻率產生一個週期性的重新設定時脈訊號。時脈週期的長度必須足以容許一個GV C Ο重新同步化爲參考的週期性訊號，而且必須短到足以使各個 GV C Ο在漂移超過容許値之前可以進行一次重新同步化作業。每一次這個重新設定時脈由低轉變爲高時，監控被連接於電路7 0之中的訊號3 4 b的輸入訊號Q —的狀態的電路8 0內部將啓動一個重新設定排序器，而一個暫停計數器將被啓動而計數訊號4 4 a上一個預定數目的脈衝。重新設定排序器知道哪些GVCOs執行"X"和〃的功能而娜一個G V C 0是、Z 〃的功能。下一個重新同步化的GVC0被稱爲目標GVC0。電路8 0也知道或、丫次GVC0是目標GVC0而將變成下一個 GVC 0。重新設定排序器等待直到目標GV c〇被啓動而後等待訊號3 4 b的下一個轉變，指示目標 GVC0被解除作用。當3 4 b轉變時，重新設定設定排序器設定目標GVC0的功能，無論是'"X"或'’ 於目前爲、Z，GVC0的GVC0，而且設定方功能於目標GV C〇。當進行這個重新設定時，第三個 GV C 0同時提供同步化訊號。當重新設定完成時’暫停計數器將被啓動，而重新設定排序器將被置於等待重新設定時脈下一個由低至高的轉變的狀態。本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐）—23 - (請先閲讀背面之注意事填寫本頁) 經濟部中央標準局員工消費合作社印製 ... ------訂-----—unM,----^--- ____B7 五、發明説明（21) 由於重新設定排序器的正確操作是依據本身是由輸入訊號1 4 a所導出的訊號3 4 b的轉變，必須提供—個機構使得即使較長的資料間隙存在於輸入上，電路也能夠正確地發揮功能。如果未進行此項工作，則輸入中的長間隙將延遲重新設定，而使得GVC 0 s可能漂移超過它們的容許値。當資料重新啓動時，GVCOs將一直等到所有三個G V C〇s均同步化之後才能夠以正確的頻率提供— 個同步化訊號。爲了克服這個潛在的問題，電路8 0具有一個暫停計數器，使得當計數器達到一個預定的値時，無論訊號3 4 a的狀態爲何，重新設定排序器都將啓動重新設定作業。如果事實上輸入訊號包含並無含有任何轉變的有效資料，這將可能造成一個單位元錯誤。因此，如果可能容許任何位元錯誤的話，必須在輸入資料保存一定的轉變密度。經濟部中央標隼局員工消費合作社印製最後，任何一個實施例均可以在其中一個單一的振盪器提供同步化訊號而一個或更多的振盪器進行同步化的一個模式下作業。該振盪器將提供同步化訊號一段時間，使得在另一個振盪器被啓動而提供同步化訊號之前，其相位相對於輸入訊號不會漂移超過一個容許値。振盪器的切換受到前述實施例中所討論的類似的限制。請注意振盪器的相位在它們被啓動時是對齊於輸入訊號。熟悉此項技術的人士將瞭解在本發明的精神和範圍之內將可能對發表的設備進行各種變化和修改。上述的®施例是提供用以說明製作和使用本發明的目前可取的方 '法° 24 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） A7 _ B7 五、發明説明（22) 本發明由以下所附的申請專利範圍.所定義。明確地說，’DeMorgan’s Theorem 和其它 Boolean邏輯技術可以被熟悉此項技術的人士用以修改整個電路說明中所使用的閘元件的種類爲邏輯上和/或功能上相等的元件0 (請先閲讀背面之注意事填寫本頁) •裝· 訂經濟部中央標準局員工消費合作社印製本紙張尺度適用中國國家標準（〇呢）八4規格（210乂 297公釐）-25-G V C 0 s, and the release is regarded as G V in data 4, each G V C channel 8 0 setting is high, and the setting is low. The structure makes GVC its frequency in accordance with this period, causing any data 3 4 a and 3 4 to change state, and its output is activated to generate a recovery change when the pair of G aligns the input data A a with the same incoming signal. The G that was started before the next GVC appears at the frequency of the 0 signal executed by C 0 S at the time of input. 0 'Z Periodic GVC error. b changes at every two clocks VC 0, and the pulses are squared to 0. VC 0 is turned on. The function of this pair is output by 0 at # in its corresponding reference signal 4 4 a. Canceled—The secondary input GVC 0 is output by the 0 R gate, X 'or while the frequency is a few punches. These are turning. Motion, and thus the role. G V C 0 signal 1 s will be replaced by element 7 R. Every ^ γ ^ is synchronized with the reference. This makes the cycle 4 a to alternately 2-from once to input any one of the week pulses. The function of the pair of pulses is the same as the figure. During these periods—each time the GVCO is set, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) —21 Please read the notes and write this page A 7 B7 V. Description of the invention (19) The bias signal 値, which is allowed to be synchronized with the reference frequency for a unit disconnection from the reference frequency, is maintained. Alternate / Reset The embodiment in FIG. 6 operates by resetting those GV C 0 s symmetrically, X " and '", whichever is' Z ". The resetting controlled by the control circuit 80 must meet two requirements: each of the three GVC 0s must be set to " z " GVC 0 before its GVC 0 drift relative to the reference periodic signal exceeds an allowable amount To enable it to resynchronize, the GVCO must be provided with sufficient time for synchronization before the next reset. One of the well-known effects of the original technology printed by the staff of the Central Standards Bureau's Consumer Cooperatives in the Ministry of Economics is that very stable oscillators can tolerate considerable time to drift; however, resynchronization of these same oscillators usually also requires considerable time time. On the other hand, low-stability oscillators can be resynchronized quickly, but they also shift sources after a short period of time. Choosing the required oscillator stability and the corresponding reset time interval is a standard engineering optimization operation, which differs depending on the technology and application, and anyone familiar with the technology will understand. The simplest reset strategy is to periodically switch all three GVCOs and set each one in turn as a GVCO. Other reset modes, such as virtual and random, can also be used as long as they meet the above requirements. Embodiments with more than three G V Cos can get more reset modes. This paper size applies the Chinese National Standard (CNS) Λ4 specification (2ΐ〇χ 297mm) -22 Α7 Β7 V. Description of the invention (20) The preferred embodiment of the circuit in Figure 6 uses an external clock reference signal 4 4 a Establishes a timing reference for resetting and performs an alternate reset. Inside the circuit 80, the reference signal 4a is divided downward to generate a periodic reset clock signal at the reset frequency. The length of the clock cycle must be sufficient to allow a GV C 0 to be resynchronized as a reference periodic signal, and it must be short enough to allow each GV C 0 to perform a resynchronization operation before the drift exceeds the allowable threshold. Each time the reset clock changes from low to high, the circuit monitoring the status of the input signal Q — connected to the signal 3 4 b in the circuit 7 0 will start a reset sequencer, and a The pause counter will be started to count a predetermined number of pulses on the signal 4 4 a. The reset sequencer knows which GVCOs perform the functions of " X " and 〃 and that a GV C 0 is a function of Z 〃. The next GVC0 to be resynchronized is called the target GVC0. Circuit 8 0 also knows that or, the next time GVC0 is the target GVC0 and will become the next GVC 0. The reset sequencer waits until the target GV c0 is activated and then waits for the next transition of the signal 3 4 b, indicating that the target GVC0 is deactivated. When 3 4 b changes, reset the setting sequencer to set the function of the target GVC0, whether it is' " X " or '' is currently GVC0 of Z, GVC0, and the setting function is the target GV C. When performing this reset, the third GV C 0 also provides a synchronization signal. When the reset is complete, the 'pause counter will be started and the reset sequencer will be placed in a state waiting for the next low-to-high transition of the reset clock. This paper size applies to Chinese National Standard (CNS) Λ4 specification (210X 297 mm) —23-(Please read the notes on the back first and fill in this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ... ---- --Order ------- unM, ---- ^ --- ____B7 V. Description of the invention (21) Because the correct operation of resetting the sequencer is based on the signal that is derived from the input signal 1 4 a 3 For the 4 b transition, a mechanism must be provided so that the circuit can function correctly even if a longer data gap exists on the input. If this is not done, the long gaps in the inputs will be delayed for resetting, causing GVC 0 s to drift beyond their allowable threshold. When the data is restarted, the GVCOs will wait until all three G V Cos are synchronized before being able to provide a synchronization signal at the correct frequency. To overcome this potential problem, the circuit 80 has a pause counter so that when the counter reaches a predetermined threshold, the reset sequencer will start a reset operation regardless of the state of the signal 3 4 a. If the input signal actually contains valid data without any transitions, this may cause a unit error. Therefore, if any bit error can be tolerated, a certain transition density must be stored in the input data. Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Finally, any embodiment can operate in a mode in which a single oscillator provides a synchronized signal and one or more oscillators are synchronized. This oscillator will provide the synchronization signal for a period of time so that its phase will not drift by more than a permissible phase relative to the input signal before another oscillator is started to provide the synchronization signal. Switching of the oscillator is similarly restricted as discussed in the foregoing embodiments. Please note that the phases of the oscillators are aligned with the input signal when they are activated. Those skilled in the art will appreciate that various changes and modifications to the published device are possible within the spirit and scope of the invention. The above-mentioned ® examples are provided to illustrate the currently preferred methods for making and using the present invention. 24 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 _ B7 V. Description of the invention ( 22) The present invention is defined by the scope of patents attached below. Specifically, 'DeMorgan's Theorem and other Boolean logic technologies can be used by those familiar with this technology to modify the type of gate components used in the entire circuit description to be logically and / or functionally equivalent. 0 (Please read first (Notes on the back fill in this page) • Binding and binding Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives The paper is printed in accordance with Chinese National Standards (〇呢) 8-4 (210 乂 297 mm) -25-

Claims

·.' :L I附件一:第83112167號專利申請案中文申請專利範圍修正本民國89年5月呈申請專利範圍種產生一個同步定的轉位關係利盪訊號選擇性 2 驟：選的週期其提供 3 驟：利而反應變具有，該方用反應其中之地啓動如申擇性地性訊號同步化 •如申用邊動輸入訊相對於一個輸法包含以下的輸入訊號的一一而產一個不生同步同的振範圍第盪訊號振盪訊化訊號的方法，同入訊號的轉變的一步驟：個選定的轉變啓動化訊號，反應各個盪訊號以便提供同 1項的方法，另外使它們本身同.步化號在同步化其本身步化訊號選個定義的相至少兩個振選定的轉變步化訊號。包含以下步請專利啓動振，而當訊號。請專利範圍第1項的方法，另外包含以下步至少兩號的僅爲一個參考時，將避免個振盪訊號其中之一產生同步化訊號有的一個單一的選定的極性的一個轉 (請先閲讀背面之注意寧項再賃頁) -裝. 訂· 變而提供該 4 ·如步驟：選擇 5 .如 I 驟：決定間盪訊號以便 6 .如驟：產生控盪訊號被選訊號和一個控制訊號，同步化訊號申請專利範輸入訊號的申請專利範隙是否存在在間隙期間申請專利範制振璗訊號擇性地啓動參考的週期當振盪訊號圍第3 選定的圍第2 輸入訊將它們圍第2 的頻率而使其性訊號被選擇項的方法，極性爲正或項的方法，號中而啓動本身同步化項的方法，的一個頻率本身同步化之間的相位性地解除作另外包含以下的者是負。另外包含以下步一個或更多的振〇另外包含以下步控制訊號，當振時*將反應振盪差異而產生頻率用而使其本身同線_ 經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準H CNS ) A4規格（210X297公釐） ·.' :L I附件一:第83112167號專利申請案中文申請專利範圍修正本民國89年5月呈申請專利範圍種產生一個同步定的轉位關係利盪訊號選擇性 2 驟：選的週期其提供 3 驟：利而反應變具有，該方用反應其中之地啓動如申擇性地性訊號同步化 •如申用邊動輸入訊相對於一個輸法包含以下的輸入訊號的一一而產一個不生同步同的振範圍第盪訊號振盪訊化訊號的方法，同入訊號的轉變的一步驟：個選定的轉變啓動化訊號，反應各個盪訊號以便提供同 1項的方法，另外使它們本身同.步化號在同步化其本身步化訊號選個定義的相至少兩個振選定的轉變步化訊號。包含以下步請專利啓動振，而當訊號。請專利範圍第1項的方法，另外包含以下步至少兩號的僅爲一個參考時，將避免個振盪訊號其中之一產生同步化訊號有的一個單一的選定的極性的一個轉 (請先閲讀背面之注意寧項再賃頁) -裝. 訂· 變而提供該 4 ·如步驟：選擇 5 .如 I 驟：決定間盪訊號以便 6 .如驟：產生控盪訊號被選訊號和一個控制訊號，同步化訊號申請專利範輸入訊號的申請專利範隙是否存在在間隙期間申請專利範制振璗訊號擇性地啓動參考的週期當振盪訊號圍第3 選定的圍第2 輸入訊將它們圍第2 的頻率而使其性訊號被選擇項的方法，極性爲正或項的方法，號中而啓動本身同步化項的方法，的一個頻率本身同步化之間的相位性地解除作另外包含以下的者是負。另外包含以下步一個或更多的振〇另外包含以下步控制訊號，當振時*將反應振盪差異而產生頻率用而使其本身同線_ 經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準H CNS ) A4規格（210X297公釐） A8 B8 C8 ______D8 _ 六、申請專利範圍步化時，頻率控制訊號將被保持於上一次振盪訊號被啓動而同步化其本身時所產生的上一個值。 7 .如申請專利範圍第6項的方法，另外包含以下步驟：當振盪訊號被啓動而同步化其本身時送出參考的週期性訊號和振盪.訊號之間的相位差。而僅使用後續的相位差產生頻率控制訊號，因而避免由於起始的相位偏移所造成的任何錯誤的頻率調整。 8. 如申請專利範圍第1項的方法，另外包含以下步驟：以邏輯方式結合所有振盪訊號爲一個單一的同步化訊號。 9. 如申請專利範圍第5項或第8項的方法，另外包含以下步-驟：當所有振盪訊號被重新同步化之後，解除同步化訊號的作用。 1 0 .如申請專利範圍第1項的方法，另外包含以下步驟：修改輸入訊號和同步訊號之間的相位關係。 1 1 .如申請專利範圍第1 0項的方法，另外包含以下步驟：轉換串聯的輸入訊號爲一個並聯的字元寬輸出而 t 且產生具有與字元寬輸出的一個定義的相位關係的一個新的同步化訊號。 1 2 .如申請專利範圍第1 1項的方法，另外包含以下步驟：在輸入訊號中捜尋定義一個傳輸的起始和/或資料字元的對齊的一個定義的模式，當發現該模式時’來自輸入訊號的兩個或更多的資料位元組被轉換爲並聯的字元寬資料訊號，一個訊號產生器提供其頻率爲申請專利範圍良紙張尺度適用中國國家標準'(CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再壙D頁) .裝· 、11 Θ 線經濟部智慧財產局員工消費合作社印製 -2 _ A8 B8 C8 D8 々、申請專利範圍第1項之中的同步化訊號的頻率除以一個資料字元之中的位元數目的一個完全沒有不穩定現象的字元同步化訊號，字元寬資料訊號被對齊爲與字元同步化訊的選定的轉變成一個定義的相位關係。 1 3 .如申請專利範圍第1 0項的方法，另外包含以下步驟：產生完全沒有不穩定現象而且被同步化爲申請專利範圍第1項的同步化訊號的一個第二個同步化訊號，並且對齊輸入資料訊號使其具有與第二個同步化訊號的選定的轉變的一個定義的相位關係。 1 4 .如申請專利範圍第1 0項的方法，另外包含以下步驟：使同步化訊號的特定的脈衝與它們的相位被對齊的特定的肩入訊號轉變相互關連。 1 5 .如申請專利範圍第2項的方法，關於有3個或更多的振盪訊號的狀況，另外包含以下步驟：選定一對振盪訊號交替提供同步化訊號，該對振盪訊號反應輸入訊號的一個選定的轉變而交替地提供同步化訊號，選擇一個或更多的剩下的振盪訊號進行重新同步化。 t 1 6 ·如申請專利範圍第1 5項的方法，另外包含以下步驟：改變三個或更多的振盪訊號其中哪些被選定爲交替地提供同步化訊號的一對，而哪些被選定進行重新同步化。 17.如申請專利範圍第16項的方法，另外包含以下步驟：反應在上一次改變選擇之後的一個重一個定義的時間間隔之後的輸入訊號的一個選定的轉變而改變選擇方本紙張尺度適用中國國家揉準'(CNS ) Λ4規格（210X297公釐） _---^----^-- (請先閲讀背面之注f項再填頁) 訂 -線· 經濟部智慧財產局員工消費合作社印製 -3 - A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製六、申請專利範圍 I 式 Ο 1 1 1 8 • 如串請專利範圍第 1 7 項的方法另外包含以 1 1 下步驟 ; 選擇上 — 次改變選擇方式之後的第 — 個時間間隔請 1 先 1 9 使得各個振 m 訊號均能在其頻率漂移超過 _. 個容許值之閲讀背刖被重新同步化〇之 1 £ 1 9 如串請專利範圍第 1 8 項的方法另外包含以意事 1 下步驟如果在上次改變選擇方式後第一個定義的時間間項再 4 1 1 隔之後以及第二個定義的時間間隔之前沒有發生輸入的任頁 )A 何選定的轉變時則不管任何輸入訊號轉變而直接改變選 1 I 擇方式其中第二個定義的時間間隔比第一個長〇 1 1 I 2 0 如串請專利範圍第 1 9 項的方法另外包含以 1 1 第訂下步驟 Μ 擇上 — 次改變選擇方式後的二個時間間隔 > 1 使得各個振盪訊號在其頻率漂移超 iia 迥 —* 個容許值之 -\八刖被重 1 1 新同步化〇 1 1 2 1 如串請專利範圍第 1 7 項的方法 > 另外包含以 1 〉个 I 下步驟 : 選擇上 — 次改變選擇方式後第 —. 個時間間隔使得將被重新同步化的 — 個或更多的振盪訊號可以進行重 t^r* m - 1 1 I 同步化至少達成與參考的週期性訊號頻率同步所需的最少 1 量時間〇 1 1 2 2 • 如串請專利範圍第 2 項的方法 * 另外包含以下 1 1 步驟 ; 選擇一個振盪訊號提供同步化訊號並且選擇 — 個 1 或更多的剩下的振蠻訊號進行重 m 同步化〇 1 I 2 3 * 如串請專利範圍第 2 2 項的方法另外包含以 1 1 1 下步驟 : 改變兩個或更多的振盪訊號中何者將被選定爲提 1 1 本紙張尺度適用中國國家標準'(CNS ) A4規格（210X297公釐） -4 - 經濟部智慧財產局員工消費合作杜印製 A8 B8 C8 D8 __六、申請專利範園供同步化訊號者，而何者將被選定以進行同步化。 2 4 _如申請專利範圍第2 3項的方法，另外包含以下步驟：在上一次改變選擇方式後的第一個定義的時間間隔後反應輸入訊號的一個選定的轉變而進行選擇方式的改變〇 2 5 ·如申請專利範圍第2 4項的方法’另外包含以下步驟：選擇上一次改變選擇方式後的第一個時間間隔，使得各個振盪訊號都能在其頻率漂移超過一個容許值之前被重新同步化。 2 6 ·如申請專利範圍第2 4項的方法’另外包含以下步驟：選擇上一次改變選擇方式後的時間間隔，使得在目前提供-同步化訊的振盪訊號相對於輸入訊號相位漂移超過一個容許值之前選定另一個振盪訊號以便提供同步化訊號。 2 7 .如申請專利範圍第2 3項的方.法，另外包含以下步驟：在上一次改變選擇方式後的第一個定義的時間間隔之後以及第二個定義的時間間隔之前如果沒有發生任何輸入訊號的選定的轉變，則不管任何輸入訊號轉變直接改變選擇方式，其中第二個定義的時間間隔比第一個長。 2 8 ·如申請專利範圍第2 7項的方法，另外包含以下步驟：選擇上一次改變選擇方式的一個第二個時間間隔，使得各個振盪訊號在其頻率漂移超過一個容許值之前都可以被重新同步化。 29.如申請專利範圍第24項的方法，另外包含以 (請先閲讀背面之注意事項再填ΪΚ·) -裝- -*tr. 線本紙張尺度逋用中國國家標準、（CNS ) A4規格（210X297公釐） 5 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製六、申請專利範圍 1 下步驟 : 選擇上 —^ 次改變選擇方式後的第 -* 個時間間隔 » 1 1 使得正被重新同步化的 *~~* 個或更多的振憑訊號可以進行重 1 I 新同步化至少達成 • fhrt 與參考的週期性訊號頻率同步所需的最 S 請 1 先 1 少量時間 0 閲 3 0 • —· 種在 —* 個輸出產生一個週期性訊號的方法 9 背之 1 注該週期性訊號具有相關於具有 _. 個已知極性的輸入訊號轉意本 1 項 I 變的 —- 個定義的相位關係 » 該方法包含以下步驟再填 1 1 反應具有已知極性的輸入訊號轉變而啓動一個振盪訊頁號所以未被啓動的振盪訊疏將是下一個將被啓動的振盪 1 I 訊號以及 1 1 I 提供該第一個或第二個振盪訊號至輸出 t 因而在輸出 1 1 訂 1 產生 — 個-健全的相位同步化的容許失真的週期性訊疏〇 3 1 • 如串請專利範圍第 3 0 項的方法另外包含以 1 1 下步驟 : 苔田 m 整各個振盪訊號的頻率爲 -~~* 個參考的週期性訊 1 | 號的頻率因而在輸出產生一個被可靠地調整的健全的 1 厂線相位被同步化的容許失真的週期性訊號〇 I I 3 2 \ 如串請專利範圍第 3 1 項的方法另外包含以 • 1 1 下步驟：反應一個傳輸監控訊號而 sm m 整所有振盪訊號的頻 1 1 率 0 I 3 3 • 如串請專利範圍第 3 1 項的方法另外包含以 1 I 下步驟 ; 在柑對於輸入訊號的 —. 個已知時刻調整所有振盪 1 1 I 訊號的頻率 0 1 1 3 4 如串請專利範圍第 3 1 項的方法另外包含以 1 1 下步驟；提供一個第三個振盪訊號其中在 —> 個時刻至少 1 1 本紙張尺度適用中國國家標準’（CNS ) A4規格（210X297公釐）一 6 - A8 Βδ C8 D8_ 六、申請專利範圍有一個振盪訊號的頻率被加以調整。 3 5 .如申請專利範圍第3 4項的方法’其中當該振盪訊號的頻率被調整時各個該振盪訊號將被解除與輸出的連接。 3 6 .如申請專利範圍第3 4項的方法’另外包含以下步驟：設定一個振盪訊號爲頻率經過調整而且重新設定頻率被調整的一個振盪訊號爲提供一個振盪訊號至輸出的振盪訊號其中之一，該各自的訊號反應一個傳輸監控訊號而被設定，使得在多重設定上的輸出的訊號頻率有效地成 .爲所有該振盪訊號的頻率的一個平均值。 37. 如申請專利範圍第36項的方法，其中當一定的時間內-沒有發生傳輸監控訊號時，振盪訊號反應輸入訊號中的一個轉變而被設定，該轉變具有已知的極性，因而可以確保輸出上振盪訊號持續地互換。 38. 如申請專利範圍第34項的方法，另外包含以下步驟：設定正提供振盪訊號至輸出的一個振盪訊號爲頻率已被調整而且重新設定頻率正被調整的一個振盪訊號爲 \ 提供一個振盪訊號至輸出的振盪訊號其中之一，該各個訊號反應一個週期性的參考訊號而被設定和重新設定，使得在多重設定上的輸出的訊號頻率有效地成爲所有該振盪器的頻率的一個平均值。 39. —種在一個輸出產生一個週期性訊號的方法，該週期性訊號具有相關於具有一個已知極性的輸入訊號轉變的一個定義的相位關係，該方法包含以下步驟：本紙張尺度逋用中國國家標準·（ CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填|||^頁) .裝. 線經濟部智慧財產局員工消費合作社印製 7 A8 B8 C8 D8 六、申請專利範圍反應具有已知極性的一個輸入訊號轉變而解除來自輸出的一個第一個振盪訊號的連接而且調整該第一個振盪訊號的頻率爲一個參考週期性訊號的頻率；反應具有已知極性的該輸入訊號轉變而啓動一個第二個振盪訊號，使得將被啓動的振盪訊號是原先未被啓動的一個振盪訊號；以及提供該第二個振盪訊號至輸出，因而在輸出產生一個被可靠地調整，健全地相位同步化的可容.忍失真的週期性訊號。 4 0 .—種用以產生一個同步化訊號的裝置，同步化訊號的選定的轉變具有相關於一個輸入訊號的轉變的一個定義的相位關係，該裝置包含：含有用以產生同步化訊號的至少兩個振盪器裝置的一個同步化訊號產生裝置，用以反應输入訊號的一個選定的轉變而啓動另一個振盪器裝置的一個控制裝置，以邏輯方式組合由所有的振盪器裝置產生的振盪訊號爲一個單一的同步化訊號的一個訊號多工處理裝置。 4 1 .如申請專利範圍第4 0項的裝置，另外包含：當被啓動時重新同步化各個振盪器裝置爲一個參考的週期性訊號的一個重新同步化裝置，選擇性地啓動振盪裝置進行重新同步化的一個啓動裝置，以及避免振盪器裝置在它們被啓動進行重新同步化時提供同步化訊號的一個分離裝置。 42.如申請專利範圍第40項的裝置，另外包含：本紙張尺度適用中國國家橾準’（CNS ) Α4規格（2丨0><297公釐） ^ ^----^-- (請先閲讀背面之注意事項再填頁) 訂· 線· 經濟部智慧財產局員工消費合作社印製 8 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8、申請專利範園反應輸入訊號的僅有的一個單一的選定的極性的轉變而啓動至少兩個振盪裝置其中之一的一個啓動裝置。 4 3 .如申請專利範圍第4 2項的裝置，另外包含：選擇輸入訊號的單一的極性爲正或負的一個選擇裝置。 4 4 .如申請專利範圍第4 1項的裝置，另外包含：決定間隙是否存在於輸入訊號中而啓動一個或更多的振盪器裝置使它們在間隙期間對其本身重新同步化的一個輸入訊號間隙決定裝置。 4 5 .如申請專利範圍第4 1項的裝置，另外包含：產生控制振盪器裝置的頻率的一個頻率控制訊號的一個頻率控制裝置。 4 6~.如申請專利範圍第4 5項的裝置，另外包含：利用比較由振盪器裝置產生的振盪訊號的相位與參考的週期性訊號而產生一個相位偏差訊號的一個相位偵測器裝置，用以依據目前或先前產生並保存的相位偏差訊號產生頻率控制訊號的一個取樣和保存裝置，當振盪器裝置被啓動而重新同步化其本身時*該取樣和保存裝置依據目前的相 I 位偏差訊號產生頻率控制訊號，當振盪器裝置被解除將其本身重新同步化的作用時，該取樣和保存裝置依據上一次振盪器裝置被啓動而重新同步化其本身時所產生的上一個相位偏差訊號而維持其頻率控制訊號。 4 7 .如申請專利範圍第4 6項的裝置，其中相位偵測器裝置，另外包含：反應重新同步化啓動訊號而送出由振盪器裝置產生的振盪訊號和週期性的參考訊號之間的相請先閲讀背之注意事項再裝頁訂線本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ297公釐） -9 - A8 B8 C8 __ D8 六、申請專利範圍位差，使得相位偵測器裝置永遠都偵測到一個起始的〇相位偏差的一個起始裝置。 48.如申請專利範圍第44項的裝置，另外包含：當所有的振盪器裝置均被重新同步化時解除同步化訊號的作用的一個同.步化訊號作用解除裝置》 4 9 .如申請專利範圍第4 0項的裝置，另外包含：修正輸入訊號和同步化訊號之間的相位關係的一個相位調整裝置。 50.如申請專利範圍第49項的裝置，另外包含：轉換串聯的輸入訊號爲一個並聯的字元寬輸出並且產生具有與字元寬輸出的一個定義的相位關係的一個新的同步化訊號的一~個訊號並聯化裝置。 5 1 .如申請專利範圍第5 0項的裝置，另外包含：搜尋輸入訊號中表示一個傳輸的開始和/或資料字元的對齊的一個定義的模式並且產生一個起始字元偵測訊號的一個起始字元偵測裝置，將來自輸入訊號的兩個或更多的資料字元組合成爲反應起始字元偵測訊號而被對齊串聯輸入 I 的並聯字元寬資料訊號的一個串聯至並聯轉換裝置，產生其頻率爲如申請專利範圍第4 0項的同步化訊號的頻率除以並聯資料字元中的位元數的一個完全沒有不穩定現象的字元同步化訊號的一個字元同步訊號產生裝置，對齊字元寬輸出訊號爲與字元同步化訊號的選定的轉變的一個定義的相位關係的一個字對齊裝置。 5 2 .如申請專利範圍第4 9項的裝置，另外包含： i張尺度適用中國國家標準’（CNS ) A4規格（210X297公釐）^ ·. _ 10 - (請先閲讀背面之注意事項再頁) -裝· 訂- 線經濟部智慧財產局員工消費合作社印製經濟部智慧財產局員工消費合作社印製 A8 B8 C8 _ _D8、申請專利範圍產生完全沒有不穩定現象而且被同步化爲申 4 0項的同步化訊號的一個第二個同步化訊同步化訊號產生裝置，對齊輸入資料訊號使個同步化訊號的選定的轉變的一個定義的相資料訊號對齊裝置。 53. 如申請專利範圍第49項的裝置使同步化訊號的特定的脈衝與它們的相位與的輸入訊號轉變之間產生關連的一個關連.化 54. 如申請專利範圍第41項的裝置個或更多的振盪器裝置，另外包含：選擇一對振盪器裝置交替地提供同步化一個或更名的剩下的振盪器進行重新同步化制裝置，反應輸入訊號的一個選定的轉變而的一對振盪器裝置其中該提供同步化訊號者請專利範圍第號的一個串聯其具有與第二位關係的一個，另外包含：之對齊的特定 u-f- «χα 裝置。，其中關於三訊號並且選擇的一個選擇控交替變換選定的一'個輸入轉請先閲背之注 I 頁裝訂變監控 5 改變三供同步個選擇 5 反應上 .訊號的變監控間間隔裝置。 5 .如個或更化訊號的一對，改變裝申請專利多的振盪範圍第5 4 器裝置中何而何者被選項的裝置，另外包含：者被選定成爲交替地提定進行重新同步化的一置。 6 .如申請專利範圍第5 5 一次選擇方式改變後一段定 —個選定的轉變而改變選擇裝置，控制上一次選擇方式使各個振盪器裝置在其頻率項的裝置*另義的時間間隔方式的一個選改變後的一個漂移超過一個外包含：之後輸入擇改變轉定義的時容許值之線本紙張尺度適用中國國家揉準’（CNS ) Α4規格（210X297公釐） -11 - A8 BS C8 ___D8 申請專利範園前被重新同步化的一個內部時序裝置。 5 7 .如申請專利範圍第5 5項的裝置，另外包含：用以當上一次選擇方式改變後的一個第一個定義的時間間隔之後以及一個第二個定義的時間間隔結束之前沒有發生任何輸入的選定的轉變時不管任何輸入訊轉變而直接改變其選擇的一個暫停裝置。 5 8 .如申請專利範圍第4 1項的裝置，另外包含：選擇一個振盪器裝置提供同步化訊號並旦選擇一個或更多的剩下的振盪器裝置進行重新同步化的一個選擇控制裝置請先閲讀背之注 I 裝頁經濟部智慧財產局員工消費合作社印製 59.如申請專利範圍第58項的裝置，改變兩個-或更多的振盪器裝置之中何者被選定步化訊號者而何者被選定進行重新同步化的一裝置。 6 0 .如申請專利範圍第5 9項的裝置，另外包含：反應上一次選擇方式改變後一段定義的一個時間間隔之後的輸入訊號的一個選定的轉變而改變選擇方式的一個轉變 V 監控裝置》另外包含：成爲提供同個選擇改變訂線 6 1 在上一次以及一段號的任何擇方式的 6 2 另外包含：改變後一段第一個定義的時間間隔之後發生輸入訊直接改變選 .如申請專利範圍第59項的裝置選擇方式第二個定義的時間間隔之前如果沒有選定的轉變時不管任何輸入訊號轉變一個選擇控制暫停裝置。 .一種從一對閘可變頻率振盪器提供一振盪訊號表紙張尺度適用中國國家標準，（CNS ) A4規格（210)<297公瘦） -12 - A8 B8 C8 D8 六、申請專利範圍之電路，該對閘可變頻率振盪器具有—輸出以連接至一邏輯危險避免電路，該邏輯危險避免電路包含一 N 0 R電路以接收該閘可變頻率振盪器之輸出，和回應該輸入以提供一輸出。 63. —種用以在輸出產生一個週期性訊號的裝置，該週期性訊號具有相關於具有一個已知極性的輸入訊號轉變的一個定義的相位關係，該裝置包含：用以反應具有已知極性的輸入訊號轉變而選擇性地提供第一個或第二個振盪器訊號，使得原先未被提供的一個 .振盪訊號是下一個將被提供的振盪訊號的第一個和第二個裝置；以及用以•提供該第一個或第二個振盪訊號至輸出，因而在輸出產生一個健全地相位同步化的容許失真的週期性訊號的第三個裝置。 64. 如申請專利範圍第63項的裝置，另外包含：用以分別調整該第一個和第二個振盪訊號的頻率爲一個參考的週期性訊號的頻率，因而在輸出產生一個被可靠地調整的，健全地相位同步化的失真容許的週期性訊號的第四個和第五個裝置。 6 5 ·如申請專利範圍第6 4項的裝置，其中該第四個和第五個裝置也包括：反應一個傳輸監控訊號用以反應該傳輸監控訊號調整該振盪訊號的頻率的控制裝置。 6 6 ·如申請專利範圍第6 4項的裝置，其中該第四本紙張尺度適用中國國家標準'(CNS ) A4規格（210X297公釐） ^-- . - - (請先閏讀背面之注意事項再填〇頁) 訂線. 經濟部智慧財產局員工消費合作社印製 -13 - A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製六、申請專利範圍個和第五個裝置也包括：用以在相對於輸入訊號的一個已知時刻調整該振盪訊號的頻率的控制裝置。 67.如申請專利範圍第64項的裝置，另外包含：用以分別產生一個第三個振盪訊號及調整該第三個振盪訊號的頻率的第六個和第七個裝置，其中該第三個裝置包括用以每次設定至少一個振盪訊號被調整的控制裝置。 6 8 .如申請專利範圍第6 7項的裝置，其中該第三個裝置包括用以在該振盪訊號被調整時解除各個振盪訊號與輸出的連接的裝置。 6 9 .如申請專利範圍第6 7項的裝置，其中該第三個裝置包·鹿反應一個傳輸監控訊號用以反應該傳輸監控訊號設定待調整的一個振盪訊號，使得多重設定上的輸出的訊號的頻率有效地成爲所有該振盪器訊號的頻率的一個平均值的控制裝置。 70.如申請專利範圍第69項的裝置，其中該控制反應具有已知極性的一個輸入訊號轉變，當一個預定的時間內未發生該傳輸監控訊號時，該控制裝置反應該轉變設定待調整的一個振盪訊號，因而確保輸出端振盪訊號持續地交換。 7 1 .如申請專利範圍第6 7項的裝置，其中該第三個裝置包括用以設定原來提供一個振盪訊號至輸出的一個振盪訊號被進行調整並且重新設定已被調整的一個振盪訊號爲一個提供一個振盪訊號至輸出的振盪訊號的控制裝置 ----；-------^-- (請先閲讀背面之注意事項再填頁) Φ 訂· 線- 本紙張尺度適用中國國家標準'(CNS ) A4規格（210X297公釐） -14 - 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 ____ D8六、申請專利範圍，該各個訊號反應一個週期性的參考訊號被設定和重新設定’使得多重設定上的輸出的訊號的頻率有效地成爲所有該振盪器訊號的頻率的一個平均值。 7 2 · —種用以在一個輸出產生一個週期性訊號的裝置，該週期性訊號焉有相關於具有一個已知極性的輸入訊號轉變的一個定義的相位關係，該方法包含以下步驟：用以反應具有已知的極性的一個輸入訊號轉變而解除一個第一個振盪訊號與輸出的連接以及諷整該第一個振盪訊號的頻率爲一個參考的週期性訊號的頻率的裝置；用以反應具有已知極性的該輸入訊號轉變而啓動一個第二個振盪訊號，使得被啓動的振盪訊號是原先未被啓動的一個振..盪訊號的裝置；以及用以提供該第二個振盪訊號至輸出，用而在輸出產生一個被可靠地調整的，健全地相位同步化的容許失真的週期性訊號的裝置。 7 3 .—種在其輸出提供一個週期性訊號的一個電路，該週期性訊號具有相關於一個已知極性的輸入訊號轉變的一個定義的相位關係，該電路包含：用以接收輸入訊號的一個雙穩定裝置，該雙穩定裝置具有第一個和第二個輸出，該雙穩定裝置反應具有已知極性的輸入訊號轉變交替地在該第一個和第二個輸出提供一個訊號；以及第一個和第二個可變頻率振盪器，各個振盪器具有一個啓動輸出，一個頻率控制輸入，及一個閘流輸出，各個諳先閲讀背面之注意事項再填 G頁裝· -訂· 線本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） -15 - 經濟部智慧財產局員工消費合作社印製 A8 Βδ C8 D8、申請專利範圍啓動輸入被連接系該雙穩定的裝置的一個各自的輸出使得當另一個可變頻率振盪器的閘流輸出未被啓動時該可變頻率振盪器其中之一的閘流輸出被啓動，因而在電路的輸出產生一個健全地相位同步化的容許失真的週期性訊號。 7 4 .如申請專利範圍第7 3項的電路，另外包含：第一個和第二個相位鎖定迴圈，各個迴圈具有連接於一個各自的閘流輸出的一個第一個輸入，連接於一個參考的週期性訊號的一個第二個輸入以及連接.於一個各自的可變頻率振盪器的頻率控制輸入的一個輸出，因而在輸出產生一個被可靠地調整的健全地相位同步化的容許失真的週期性訊號。 7 5 ~.如申請專利範圍第7 4項的電路，另外包含：被連接以反應一個傳輸監控訊號而岔斷一個各自的相位鎖定迴圈的操作的一個控制閘元件，該控制閘元件具有連接於一個傳輸監控訊號的一個第一個輸入以及被連接於一個各自的相位偵測器的一個輸出。 76. 如申請專利範圍第75項的電路，其中該閘元件的一個第二個輸入被連接於一個參考頻率。 77. 如申請專利範圍第75項的電路，其中該閘元件的一個第二個輸入被連接於一個各自的可變頻率的振盪器的該閘流輸出。 7 8 .如申請專利範圍第7 3項的電路，另外包含：被連接以便選擇性地連接各個可變頻率的振盪器的該閘流輸出於電路的輸出使得一次只有一個閘流輸出被連接本紙張尺度逋用中國國家標準' (CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填 •裝· 頁) ㊣線 ^ 16 - A8 B8 C8 D8 六、申請專利範園至電路的輸出，因而提供一個健全地可靠的容許失真的週期性訊號的輸出邏輯。 7 9·如申請專利範圍第78項的，其中該輸出邏輯包括提供該閘流輸出的一個Boolean OR的一個閘元件。 80.如申請專利範圍第78項的電路，其中輸出邏輯包括ίΐ供該閘流輸出的一個Boolean N0R的一個閘元件請先閲讀背 1¾ 之注意事項再頁裝 8 1 .如申請專利範圍第8 0項的電路，其中各個可變頻率振盪器具有被連接於一個危險防止閘元件的一個輸入的一個未閘流的振盪訊號分接點，該危險防止閘元件提供該未閘.i輸入的一個Boolean N0R ，而該危險防止閘一個輸出被連接於該輸出邏輯N O R閘元件的一個個健全地可靠的可容許失真的週期性訊元件的輸入，號。 8 因而提供 2 ·—種訂經濟部智慧財產局員工消費合作社印製，該週期性訊號 \ 的一個定義的相用以接收輸裝置具有第一個知極性的輸入訊第一個和第二個振盪器入，及各個振個閘流在其輸具有相位關係入訊號和第二號轉變輸出；盪器具輸出；出提供一個關於一個已，該電路包的一個雙穩個輸出，該而交替地提第一個，第有一個啓動第一個，第週期性訊號的一個電路知極性的輸入訊號轉變含：定的裝置，該雙穩定的雙穩定裝置反應具有已供地提供一個訊號於該二個和第三個可變頻率輸入，一個頻率控制輸二個和第三個相位鎖定 ❿ 線本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -17 - 經濟部智慧財產局員工消費合作社印製 A8 Βδ C8 ______D8 六、申請專利範圍迴圈’各個迴圈具有連接於一個各自的閘流輸出的—個第一個輸入’連接於一個參考的週期性訊號的一個第二個輸入及連接於一個各自的可變頻率振盪器的該頻率控制輸入的一個輸出；以及被連接於該雙穩定裝置的該輸出及該可變頻率振盪器的該啓動輸入的選擇邏輯，使得該雙穩定裝置的該各自的輸出經由該選擇邏輯被選擇性地連接至該第一個，第二個和第三個可變頻率振盪器，該選擇邏輯選擇性地設定該雙穩定裝置的各個輸出於一對該可變頻率振盪器的各個啓動輸入。 83:如申請專利範圍第82項的電路，其中該選擇邏輯也被-連接至一個傳輸監控訊號以便重新設定一個可變頻率振盪器的閘流輸出以反應該傳輸監控訊號而提供一個訊號至電路輸出並且解除另一個可變頻率振盪器的閘流輸出與電路的輸出的連接，所以在多重設定上的電路輸出的訊號的頻率有效地成爲該可變頻率振盪器的頻率的一個平均值。 t 84.如申請專利範圍第83項的電路，其中該選擇邏輯也被連接於參考的週期性訊號，使得當一個預定的時間內未發生該傳輸監控訊號.時一個可變頻率振盪器反應已知極性的一個轉變而被重新設定，因而確保在電路的輸出上振盪訊號持續的互換。 8 5 .如申請專利範圍第8 2項的電路，其中該選擇邏輯也被連接於參考的週期性訊號’使得當該參考的週期本紙張尺度適用中國國家標準（CNS ) 格（210X297公釐） ------^----I---裝------訂----：--線 (請先閱讀背面之注意事項再填ίβ頁) -18 - 々、申請專利範圍 (請先閲讀背面之注意事項再填ίΒ頁) 性訊號指示已經過了一段預定的時間時一個可變頻率的振盪器反應輸入訊號中的已知極性的一個轉變而被重新設定，所以在多重重新設定的電路輸出上的訊號的頻率有效地成爲該可變頻率振盪器的頻率的一個平均值》 8 6.種在其輸出產生一個週期性訊號的一個電路，該週期性訊號具有相關於具有一個已知極性的輸入訊號轉變的一個定義的相位關係，該電路包含：用以接收器輸入訊號的一個雙穩定裝置*該雙穩定裝置具有第一個和第二輸出，該雙穩定裝置反應具有己知極 .性的輸入訊號轉變而交替地提供一個訊號於該第一個和第二個輸出； ;〆第一-個和第二個可變頻率振盪器，各個振盪器具有一 /個啓動輸入、一個頻率控制輸入，以及提供一個各自的閘 ;流振盪訊號的一個閘流輸出； .............- ....... # I連接於各個可變頻率振盪器的輸出和電路的輸出之間的一個閘元件；經濟部智慧財產局員工消費合作社印製被連接以便選擇性地連接該雙穩定裝置的該輸出於該可變頻率振盪器的該啓動輸入，而且被連接於該閘元件以便反應具有已知極性的一個輸入訊號轉變而解除一個可變頻率振盪器的該啓動輸入與該雙穩定裝置的一個輸出的連接以及解除一個各自的第一個振盪訊號與電路輸出的連接，而反應該輸入訊號轉變連接另一個可變頻率振盪器的該啓動輸入於該雙穩定裝置的一個輸出並且連接一個各自的第二個振盪訊號於電路的輸出，使得當另一個可變頻率振本紙張尺度適用中國國家橾準（CNS ) Α4規格（210X297公釐） -19 - A8 B8 C8 D8 六、申請專利範圍盪器被解除與電路輸出的連接時一個可變頻率振盪器被連接至該電路輸出的選擇邏輯；以及被連接於各個可變頻率振盪器的該頻率控制輸入及該選擇邏輯以便在該各個可變頻率振盪器被解除連接時調整各個可變頻率振盪器的頻率爲一個參考的.週期性訊號的頻率，因而在輸出產生一個被可靠地調整，健全地相位同步化的容許失真的週期性訊號的一個各自的相位鎖定迴圈。 ^-- t 一 (請先閲讀背面之注意事項再填1頁) 4· 線經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準’（CNS ) A4規格（210X297公釐） -20 -· .: LI Annex 1: Patent Application No. 83112167 Chinese Application for Patent Scope Amendment The Republic of China filed a patent application in May 89 to generate a synchronous transposition relationship. The singularity signal is optional 2 steps: the cycle of selection Provide 3 steps: the reaction becomes beneficial, and the party uses the response to start the synchronization of the signal selectively. For example, the application of the edge input signal with respect to an input method includes the following input signals. A method that oscillates the signal without synchronizing the first signal in the same vibration range, a step of the same transition as the incoming signal: a selected transition initiates the signal, reflects each signal to provide the same method, and makes them It is the same as the .step signal in synchronizing its own step signal with at least two selected transition phase signals. Contains the following steps please patent start vibration, and when the signal. Please use the method in the first item of the patent scope, in addition to the following steps. At least two of the following steps are for reference only. One of the oscillating signals will be prevented from generating a single signal of the selected polarity. (Please read first.) Note on the back of the page (repurchase page)-Installation. Order · Change and provide the 4 · Steps: Select 5. Step I: Decide on the signal for 6. In order to generate a control signal, select the signal and a control Signal, synchronization signal, patent application, input signal, whether the patent application gap exists, during the gap, the patent application, the vibration signal, and the signal selectively starts the reference cycle. When the oscillating signal surrounds the 3rd selected range, the 2nd input signal surrounds them. The method of the second frequency to make its sexual signal the selected item, the method of the polarity is positive or the term, the method of starting the self-synchronized item in the signal, and the phase between the synchronization of the frequency itself is removed to include otherwise The following are negative. Includes one or more vibrations in the following steps. In addition, the control signals in the following steps are included. When vibrating *, it will reflect the difference in oscillations and generate frequencies to make it itself on the same line. Applicable to Chinese National Standard H CNS) A4 specification (210X297 mm) ·. ': LI Annex 1: Patent Application No. 83112167 Chinese Application for Patent Scope Amendment The Republic of China applied for a patent scope in May of 89 to generate a synchronized transfer Bit-response signal selectivity 2 steps: the cycle of the selection provides 3 steps: the benefit of the reaction becomes, the party uses the reaction to start the synchronization of the signal as optional • if the input signal is applied side by side A method of oscillating an oscillating signal with the following input signals in an output method that includes one by one of the following input signals, a step of the same transformation as the incoming signal: a selected transformation initiates the chemistry signal, reacts Each signal is provided in order to provide the same method, and in addition, they are the same. The step number is synchronizing its own steps. Definition signal selected from at least two transducers with a selected transition of the step signal. Contains the following steps please patent start vibration, and when the signal. Please use the method in the first item of the patent scope, in addition to the following steps. At least two of the following steps are for reference only. One of the oscillating signals will be prevented from generating a single signal of the selected polarity. (Please read first.) Note on the back of the page (repurchase page)-Installation. Order · Change and provide the 4 · Steps: Select 5. Step I: Decide on the signal for 6. In order to generate a control signal, select the signal and a control Signal, synchronization signal, patent application, input signal, whether the patent application gap exists, during the gap, the patent application, the vibration signal, and the signal selectively starts the reference cycle. When the oscillating signal surrounds the 3rd selected range, the 2nd input signal surrounds them. The method of the second frequency to make its sexual signal the selected item, the method of the polarity is positive or the term, the method of starting the self-synchronized item in the signal, and the phase between the synchronization of the frequency itself is removed to include otherwise The following are negative. Includes one or more vibrations in the following steps. In addition, the control signals in the following steps are included. When vibrating *, it will reflect the difference in oscillations and generate frequencies to make it itself on the same line. Applicable to Chinese National Standard H CNS) A4 specification (210X297 mm) A8 B8 C8 ______D8 _ VI. When the scope of patent application is stepped, the frequency control signal will be maintained at the time when the last oscillating signal was activated to synchronize itself Previous value. 7. The method according to item 6 of the patent application, further comprising the step of sending a phase difference between the reference periodic signal and the oscillating signal when the oscillating signal is activated to synchronize itself. Only the subsequent phase difference is used to generate the frequency control signal, thus avoiding any erroneous frequency adjustment caused by the initial phase offset. 8. If the method of applying for the first item of the patent scope, further includes the following steps: logically combine all the oscillating signals into a single synchronized signal. 9. If the method of applying for the scope of item 5 or item 8 of the patent, it additionally includes the following steps: after all the oscillating signals are resynchronized, the effect of the synchronization signal is cancelled. 10. The method according to item 1 of the patent application scope further includes the following steps: modifying the phase relationship between the input signal and the synchronization signal. 1 1. The method according to item 10 of the scope of patent application, further comprising the steps of: converting a serial input signal into a parallel character-width output and t and generating one having a defined phase relationship with the character-width output New synchronization signal. 1 2. The method according to item 11 of the patent application scope, further comprising the following steps: searching for a defined pattern in the input signal defining the start of a transmission and / or the alignment of the data characters, when the pattern is found 'Two or more data bytes from the input signal are converted into parallel character-wide data signals, and a signal generator provides its frequency for patent application. Good paper size applies to Chinese National Standards' (CNS) A4 specifications (210X297mm) (please read the precautions on the back first, and then read page D). Packing, 11 Θ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-2 _ A8 B8 C8 D8 々, Item 1 of the scope of patent application The frequency of the synchronization signal is divided by the number of bits in a data character. A character synchronization signal with no instability at all. The character-wide data signal is aligned to the selection of the character synchronization signal. Into a defined phase relationship. 1 3. The method as claimed in item 10 of the scope of patent application, further comprising the steps of generating a second synchronization signal which is completely free from instability and synchronized to the synchronization signal of item 1 of the patent application scope, and The input data signal is aligned such that it has a defined phase relationship with a selected transition of the second synchronization signal. 14. The method according to item 10 of the scope of patent application, further comprising the steps of correlating specific pulses of the synchronization signals with specific shoulder signal transitions whose phases are aligned. 15. As for the method in the second item of the scope of patent application, regarding the condition of three or more oscillating signals, the method further includes the following steps: selecting a pair of oscillating signals to alternately provide a synchronization signal, and the pair of oscillating signals reflecting the input signal A selected transition alternately provides a synchronization signal, and one or more of the remaining oscillating signals are selected for resynchronization. t 1 6 · The method according to item 15 of the scope of patent application, further comprising the steps of changing which of three or more oscillating signals are selected as a pair that alternately provides synchronization signals, and which are selected for re-selection Synchronization. 17. The method according to item 16 of the patent application scope, further comprising the following steps: changing the selection method in response to a selected change of the input signal after a redefined time interval after the last change selection National Standards (CNS) Λ4 specification (210X297 mm) _--- ^ ---- ^-(Please read the note f on the back before filling in the page) Order-line · Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative -3-A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application I Formula 0 1 1 1 8 • If the method of item 17 of the patent scope is stringed, it includes 1 1 below Step; select the first time interval after the last change of the selection method, please 1 first 1 9 so that each vibration m signal can drift more than _ at its frequency. The readback of the allowable value is resynchronized. 0 1 £ 1 9 If the method of item 18 in the patent scope is included, it also contains the following steps: 1 If the first time interval after the last change of the selection method is 4 1 1 and the second time is defined No input page has occurred before the time interval) A When the selected transition is made, the selection is changed directly regardless of any input signal transition. The first defined time interval is longer than the first. 0 1 1 I 2 0 The method of claiming item 19 of the patent scope additionally includes the step 1 of the first order M, which is selected-two time intervals after changing the selection method > 1 so that each oscillating signal has a frequency shift that exceeds iia by-* Permissible value-\ 八刖 was weighted 1 1 New synchronization 0 1 1 2 1 If the method of the 17th item in the patent scope is stringed> In addition, 1> I Next step: Select the previous one. The time interval after changing the selection mode makes the re-synchronization of one or more oscillating signals can be re-t ^ r * m-1 1 I Synchronization is achieved at least with reference The minimum amount of time required for the periodic signal frequency synchronization. 〇1 1 2 2 • If the method of the second item in the patent scope is requested * In addition, it includes the following 1 1 steps; select an oscillating signal to provide the synchronization signal and select — 1 Or more of the remaining vibration signals are re-m-synchronized. 0 1 I 2 3 * If the method of item 2 of the patent range is stringed, the method further includes 1 1 1 and the following steps: change two or more oscillating signals Which one will be selected to mention 1 1 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -4-Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperation Du printed A8 B8 C8 D8 __ VI. Application Patent model For synchronization signal who will be selected and how to synchronize. 2 4 _If the method in the scope of patent application No. 23, additionally includes the following steps: after the first defined time interval after the last change of the selection method, the selection method is changed in response to a selected transition of the input signal. 25 · The method according to item 24 of the scope of patent application 'additionally includes the following steps: selecting the first time interval after the last change of the selection method, so that each oscillating signal can be restarted before its frequency drift exceeds an allowable value Synchronization. 2 6 · The method according to item 24 of the scope of patent application 'additionally includes the following steps: selecting the time interval after the last change of the selection method, so that the phase shift of the oscillating signal currently provided-synchronized with respect to the input signal is more than an allowable Select another oscillating signal before the value to provide a synchronized signal. 27. The method of item 23 of the scope of patent application, further including the following steps: after the first defined time interval after the last change of the selection method and before the second defined time interval, if nothing happens The selected transition of the input signal directly changes the selection method regardless of any input signal transition. The second defined time interval is longer than the first. 2 8 · The method according to item 27 of the scope of patent application, further including the following steps: selecting a second time interval for the last change of the selection method, so that each oscillating signal can be restarted before its frequency drift exceeds an allowable value Synchronization. 29. If you apply for the method in item 24 of the scope of patent application, it also includes (Please read the precautions on the back before filling Ϊ ··) -pack--* tr. Chinese paper standard, (CNS) A4 specification (210X297 mm) 5 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for patent scope 1 Next steps: Select the top- ^ th time interval after changing the selection method-1st time interval »1 1 makes positive * ~~ * or more resynchronized signals can be re-synchronized 1 I New synchronization is achieved at least • fhrt Minimum S required for frequency synchronization with the reference periodic signal Please 1 first 1 small time 0 read 3 0 • — · A way to generate a periodic signal at — * outputs 9 Back to 1 Note This periodic signal has a correlation with an input signal with _. Known polarities. 1 The term I changes—a defined phase relationship »The method includes the following steps and then fills in 1 1 Responds to an input signal with a known polarity to start an oscillating signal page, so the oscillating signal that has not been activated will be the next one. The activated oscillating 1 I signal and 1 1 I provide the first or second oscillating signal to the output t and thus produce an order 1 at the output 1 1-a robust phase synchronizing tolerant distortion periodic signal. 3 1 • If the method of claiming item 30 of the patent range is included, the following steps are further included: 1 The moss m sets the frequency of each oscillation signal to-~~ * the reference periodic signal 1 | Generates a robust 1-line phase signal that can be reliably adjusted and synchronized tolerant distortion periodic signal 〇II 3 2 \ If string please patent scope The method of item 3 1 additionally includes the following steps: • 1 1 The following steps: respond to a transmission monitoring signal and sm m sets the frequency of all oscillating signals 1 1 rate 0 I 3 3 1 I next step; adjust all the oscillations at the known time of the input signal. 1 1 I frequency of the signal 0 1 1 3 4 If the method of string item 31 of the patent range is included, the method further includes the following steps: 1 1 Provide a third oscillating signal, which is at least 1 at the time of 1 1 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 6-A8 Βδ C8 D8_ VI. There is an oscillation in the scope of patent application The frequency of the signal is adjusted. 35. The method according to item 34 of the scope of patent application, wherein when the frequency of the oscillating signal is adjusted, each of the oscillating signals will be disconnected from the output. 36. The method according to item 34 of the scope of patent application 'additionally includes the following steps: setting an oscillating signal as one of the oscillating signals whose frequency is adjusted and resetting the frequency being adjusted as providing one of the oscillating signals to the output oscillating signal The respective signals are set in response to a transmission monitoring signal, so that the output signal frequency at multiple settings is effectively an average value of the frequencies of all the oscillating signals. 37. For example, the method in the 36th aspect of the patent application, wherein when a monitoring signal is not transmitted for a certain period of time, the oscillating signal is set in response to a transition in the input signal, the transition has a known polarity, thus ensuring that Oscillation signals on the output are continuously interchanged. 38. For the method of applying for the item 34 of the patent scope, the method further includes the following steps: setting an oscillating signal which is providing an oscillating signal to the output as the frequency has been adjusted and resetting an oscillating signal which is being adjusted in the frequency as \ providing an oscillating signal To one of the output oscillating signals, each signal is set and reset in response to a periodic reference signal, so that the output signal frequency at multiple settings effectively becomes an average of the frequencies of all the oscillators. 39. A method of generating a periodic signal at an output, the periodic signal having a defined phase relationship with respect to an input signal transition having a known polarity, the method includes the following steps: This paper uses China National Standards (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling ||| ^ pages). Packing. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 A8 B8 C8 D8 The scope of the patent application responds to the transition of an input signal with a known polarity and disconnects a first oscillating signal from the output and adjusts the frequency of the first oscillating signal to a frequency of a reference periodic signal; the reaction has a known polarity The input signal is changed to start a second oscillating signal, so that the oscillating signal to be started is an oscillating signal that was not originally started; and the second oscillating signal is provided to the output, thereby generating a reliably Adjustable, robust phase synchronization. Tolerant to distortion of periodic signals. 40. A device for generating a synchronization signal, a selected transition of the synchronization signal having a defined phase relationship with respect to a transition of an input signal, the device comprising: A synchronized signal generating device of two oscillator devices is used to start a control device of another oscillator device in response to a selected transition of an input signal, and logically combines the oscillation signals generated by all the oscillator devices as A signal multiplexing device for a single synchronized signal. 41. The device according to item 40 of the scope of patent application, further comprising: a resynchronizing device that resynchronizes each oscillator device as a reference periodic signal when activated, selectively starts the oscillating device to resynchronize A synchronizing start-up device, and a separate device that prevents the oscillator devices from providing a synchronizing signal when they are started for re-synchronization. 42. The device according to item 40 of the scope of patent application, further comprising: This paper size is applicable to China National Standards (CNS) A4 specification (2 丨 0 > < 297 mm) ^ ^ ---- ^-(Please read the notes on the back before filling in the page) Order · Line · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8, B8, C8 and D8 are printed, and the patent application range responds to a single selected polarity change of the input signal to activate one of at least two oscillators. 4 3. The device according to item 42 of the scope of patent application, further comprising: a selection device for selecting a single polarity of the input signal to be positive or negative. 4 4. The device according to item 41 of the scope of patent application, further comprising: an input signal that determines whether a gap exists in the input signal and activates one or more oscillator devices so that they resynchronize themselves during the gap The gap determines the device. 4 5. The device according to item 41 of the patent application scope, further comprising: a frequency control device for generating a frequency control signal for controlling the frequency of the oscillator device. 4 6 ~. The device according to item 45 of the scope of patent application, further comprising: a phase detector device that generates a phase deviation signal by comparing the phase of the oscillation signal generated by the oscillator device with a reference periodic signal, A sampling and holding device for generating a frequency control signal based on a current or previously generated and saved phase deviation signal, when the oscillator device is activated to resynchronize itself * the sampling and holding device is based on the current phase I bit deviation The signal generates a frequency control signal. When the oscillator device is de-synchronized, the sampling and holding device re-synchronizes itself according to the last phase deviation signal generated when the oscillator device was started. While maintaining its frequency control signal. 47. The device according to item 46 of the patent application scope, wherein the phase detector device further includes: a phase between the oscillation signal generated by the oscillator device and the periodic reference signal in response to the resynchronization start signal. Please read the precautions on the back first, and then bind the page. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm) -9-A8 B8 C8 __ D8 6. The difference in the scope of patent application makes phase detection The detector device always detects a starting device with an initial phase shift of zero. 48. The device in the 44th scope of the patent application, further comprising: a device that cancels the effect of the synchronization signal when all the oscillator devices are re-synchronized. 4-9. The device in the range of item 40 additionally includes: a phase adjustment device for correcting a phase relationship between an input signal and a synchronization signal. 50. The device of claim 49, further comprising: converting a serial input signal into a parallel character wide output and generating a new synchronized signal having a defined phase relationship with the character wide output One to one signal parallelization device. 51. The device as claimed in claim 50, further comprising: searching for a defined pattern in the input signal indicating the start of a transmission and / or the alignment of data characters and generating a start character detection signal A start character detection device that combines two or more data characters from an input signal into a parallel character wide data signal that is aligned in series with the input I in response to the start character detection signal and is connected in series to A parallel conversion device generates a character of the synchronization signal whose frequency is the frequency of the synchronization signal such as the 40th patent application range divided by the number of bits in the parallel data character without any instability. A synchronization signal generating device that aligns a character wide output signal to a word alignment device having a defined phase relationship with a selected transition of a character synchronization signal. 5 2. If the device in the scope of patent application No. 49 is included, it also contains: i-size is applicable to Chinese National Standards (CNS) A4 specification (210X297 mm) ^ ·. _ 10-(Please read the precautions on the back before (Page)-Binding · Ordering-Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by A8 B8 C8 _ _D8. There is no instability at all in the scope of patent application and it is synchronized as application 4 A synchronizing signal of 0 items, a second synchronizing signal synchronizing signal generating device, aligning the input data signal with a defined phase data signal aligning device for a selected transition of the synchronizing signal. 53. If the device under the scope of patent application 49 makes a correlation between the specific pulses of the synchronization signals and their phase and the input signal transition. 54. If the device under the scope of patent application 41 or More oscillator devices, additionally including: selecting a pair of oscillator devices to alternately provide synchronization of one or more remaining oscillators for resynchronization, a pair of oscillations in response to a selected transition of the input signal The device that provides the synchronization signal requests the patented scope number one in series which has a relationship with the second bit, and further includes: a specific uf- «χα device aligned. Among them, there is a selection control for three signals and the selection alternately changes the selected one of the input switches. Please read the note on the back page I. Binding and change monitoring. 5. As a pair of signals or more, a device that changes the number of patent applications for the oscillation range of the device. Which device is selected, and additionally includes: The device is selected to be alternately designated for resynchronization. One home. 6. If the scope of the patent application is 5th, the selection mode is changed after a selection mode is changed-a selected transition changes the selection device, and the last selection mode is controlled so that each oscillator device is in its frequency term. One drift after one selection change is more than one inclusion: Then enter the line of the allowable value when the selection is changed. The paper size is applicable to Chinese National Standards (CNS) A4 specification (210X297 mm) -11-A8 BS C8 ___D8 An internal timing device that was resynchronized before applying for a patent. 57. The device according to item 5 of the scope of patent application, further comprising: used to change nothing after a first defined time interval after the previous selection mode change and before a second defined time interval ends The selected transition of input is a pause device that directly changes its selection regardless of any input signal transition. 5 8. The device according to item 41 of the scope of patent application, further comprising: a selection control device that selects an oscillator device to provide a synchronization signal and selects one or more of the remaining oscillator devices for resynchronization. First read the back note I. Page printing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 59. If the device under the scope of patent application is 58, change which of the two or more oscillator devices is selected to be a step signal. Whichever device is selected for resynchronization. 60. The device according to item 59 of the scope of patent application, further comprising: a transition V monitoring device that changes the selection mode in response to a selected transition of an input signal after a time interval defined after the last selection mode is changed " Including: Become the same choice to change the subscription line 6 1 in the last choice and 6 of any number of choices 6 2 In addition: Change the input signal directly after the first defined time interval after changing the paragraph. For example, apply for a patent The device selection mode of range 59 is before the second defined time interval. If there is no selected transition, a selection control pauses the device regardless of any input signal transition. A kind of oscillator signal is provided from a pair of gate variable frequency oscillators. The paper size is applicable to Chinese National Standards, (CNS) A4 Specification (210) < 297 male thin) -12-A8 B8 C8 D8 VI. Patent application circuit, the pair of gated variable frequency oscillator has-output to connect to a logical danger avoidance circuit, which contains a N 0 The R circuit receives the output of the gate variable frequency oscillator and responds to the input to provide an output. 63. A device for generating a periodic signal at an output, the periodic signal having a defined phase relationship with respect to an input signal transition having a known polarity, the device comprising: for reflecting a known polarity The input signal is switched to selectively provide the first or second oscillator signal such that the one that was not previously provided. The oscillator signal is the first and second device of the next oscillator signal to be provided; and A third device to provide the first or second oscillating signal to the output, thereby generating a robust phase-synchronized, tolerable periodic signal at the output. 64. For example, the device of the scope of patent application No. 63 further includes: used to adjust the frequency of the first and second oscillating signals as a reference periodic signal frequency, so that a reliable adjustment can be made at the output. The fourth and fifth devices of the periodic signal are tolerated by robust, phase-synchronized distortion. 65. The device according to item 64 of the patent application range, wherein the fourth and fifth devices also include: a control device that responds to a transmission monitoring signal to adjust the frequency of the oscillating signal in response to the transmission monitoring signal. 6 6 · If the device in the scope of patent application No. 64, the fourth paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ^-.--(Please read the notes on the back first Matters are re-filled on page 0) Threading. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -13-A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The scope of patent application and the fifth device also include: A control device for adjusting the frequency of the oscillating signal at a known time relative to the input signal. 67. The device according to item 64 of the patent application, further comprising: sixth and seventh devices for generating a third oscillating signal and adjusting the frequency of the third oscillating signal, respectively, wherein the third The device includes a control device for setting at least one oscillating signal to be adjusted each time. 68. The device according to item 67 of the patent application scope, wherein the third device includes a device for disconnecting each oscillation signal from the output when the oscillation signal is adjusted. 69. The device according to item 67 of the scope of patent application, wherein the third device package · deer reflects a transmission monitoring signal to reflect the transmission monitoring signal setting to an oscillating signal to be adjusted, so that the output of multiple settings The frequency of the signal effectively controls the average of the frequencies of all the oscillator signals. 70. The device according to item 69 of the patent application scope, wherein the control response responds to an input signal transition with a known polarity, and when the transmission monitoring signal does not occur within a predetermined time, the control device responds to the transition setting to be adjusted An oscillating signal, thus ensuring that the oscillating signal at the output is continuously exchanged. 71. The device according to item 67 of the scope of patent application, wherein the third device includes an oscillation signal for setting an original oscillation signal to be output to be adjusted and resetting an adjusted oscillation signal to one. Control device that provides an oscillating signal to the output oscillating signal ----; ------- ^-(Please read the precautions on the back before filling in the page) Φ Order · Line-This paper size applies to China Standard '(CNS) A4 specification (210X297 mm) -14-Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 ____ D8 6. The scope of patent application, each signal reflects a periodic reference signal is set and re-set Setting 'makes the frequency of the output signal on multiple settings effectively an average of the frequencies of all the oscillator signals. 7 2 · —A device for generating a periodic signal at an output, the periodic signal having a defined phase relationship with respect to an input signal transition having a known polarity, the method includes the following steps: A device that responds to an input signal transition having a known polarity to disconnect a first oscillating signal from an output, and to ridicule the frequency of the first oscillating signal as a reference periodic signal; The input signal of known polarity is switched to start a second oscillating signal, so that the oscillated signal being activated is a oscillating signal that has not been activated previously; and a device for providing the second oscillating signal to the output The device is used to generate a periodically adjusted signal with reliable distortion and sound phase synchronization that allows distortion. 7 3. A circuit that provides a periodic signal at its output, the periodic signal having a defined phase relationship with respect to an input signal transition of a known polarity, the circuit comprising: a circuit for receiving an input signal A bistable device having first and second outputs, the bistable device responding to an input signal transition having a known polarity to alternately provide a signal at the first and second outputs; and a first And second variable frequency oscillators, each oscillator has a start-up output, a frequency control input, and a thyristor output, each read the precautions on the back before filling in G pages Standards apply to China National Sample Standard (CNS) A4 specifications (210X297 mm) -15-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 Βδ C8 D8, the input range of the patent application start input is connected to each of the bistable devices The output of one of the variable frequency oscillators is Output stream is enabled, generation of a periodic sound signal to permit a distortion of the phase synchronization circuit is output. 74. The circuit according to item 73 of the scope of patent application, further comprising: a first and a second phase-locked loop, each loop having a first input connected to a respective thyristor output, connected to A second input and connection of a reference periodic signal. An output to the frequency control input of a respective variable frequency oscillator, thus producing a robustly phased tolerable distortion that is reliably adjusted at the output Periodic signal. 7 5 ~. The circuit according to item 74 of the scope of patent application, further comprising: a control brake element connected to respond to a transmission monitoring signal to switch off the operation of a respective phase locked loop, the control brake element having a connection A first input at a transmission monitoring signal and an output connected to a respective phase detector. 76. For a circuit in the scope of patent application No. 75, wherein a second input of the gate element is connected to a reference frequency. 77. The circuit of claim 75, wherein a second input of the thyristor element is connected to the thyristor output of a respective variable frequency oscillator. 7 8. The circuit according to item 73 of the scope of patent application, further comprising: the thyristor output which is connected to selectively connect each variable frequency oscillator to the output of the circuit so that only one thyristor output is connected to the circuit at a time. Paper size: Chinese National Standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling in the page) ㊣ Thread 16-A8 B8 C8 D8 VI. Apply for a patent Fanyuan to Circuit Output, thus providing a robust and reliable output logic that allows distortion of periodic signals. 7 9. As in the scope of patent application No. 78, wherein the output logic includes a gate element of a Boolean OR providing the thyristor output. 80. If the circuit of the scope of patent application No. 78, where the output logic includes a gate element of a Boolean N0R for the thyristor output, please read the precautions on the back 1¾ and then install 8 A circuit of term 0 in which each variable frequency oscillator has an un-latched oscillating signal tap connected to an input of a danger-prevention gate element, the danger-prevention gate element providing an Boolean N0R, and one output of the hazard prevention gate is connected to the input of each of the sound signal elements of the sound logic NOR gate element which is robust and tolerable distortion. 8 Therefore provide 2—Specified by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a defined phase of the periodic signal \ is used to receive the first and second input signals with the first known polarity of the input device. The oscillator input, and each oscillating thyristor has a phase relationship between its input signal and the second transition output; the oscillating device output; the output provides a bi-stable output of the circuit package, which alternately Mention the first, the first one activates the first, the first periodic signal of a circuit knows the polarity of the input signal transition includes: a fixed device, the bistable bistable device responds with a signal provided to the two And the third variable frequency input, one frequency control input two and the third phase locked ❿ The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -17-Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperatives A8 Βδ C8 ______D8 VI. Patent Application Circumstances' Each loop has a separate gate connected to it Output-a first input 'a second input connected to a reference periodic signal and an output of the frequency control input connected to a respective variable frequency oscillator; and connected to the bistable The selection logic of the output of the device and the start input of the variable frequency oscillator enables the respective outputs of the bistable device to be selectively connected to the first, second and third via the selection logic Variable frequency oscillators, the selection logic selectively sets each output of the bistable device to each start input of a pair of variable frequency oscillators. 83: The circuit according to item 82 of the patent application, wherein the selection logic is also connected to a transmission monitoring signal so as to reset the thyristor output of a variable frequency oscillator to reflect the transmission monitoring signal and provide a signal to the circuit. The thyristor output of another variable frequency oscillator is output and disconnected from the output of the circuit, so the frequency of the signal output by the circuit on multiple settings effectively becomes an average of the frequency of the variable frequency oscillator. t 84. The circuit of claim 83, wherein the selection logic is also connected to the reference periodic signal, so that when the transmission monitoring signal does not occur within a predetermined time, a variable frequency oscillator responds. A change in the polarity of the sensor is reset, thereby ensuring that the oscillation signals on the output of the circuit are continuously interchanged. 8 5. The circuit of item 82 in the scope of patent application, in which the selection logic is also connected to the reference periodic signal 'so that when the reference period, the paper size applies the Chinese National Standard (CNS) grid (210X297 mm) ------ ^ ---- I --- install ------ order ----:-line (please read the precautions on the reverse side and fill in the β page) -18-々, apply Patent scope (please read the precautions on the back before filling the page). The signal indicates that a variable frequency oscillator has been reset in response to a change in the known polarity of the input signal when a predetermined period of time has passed, so The frequency of the signal at the multiple reset circuit output effectively becomes an average value of the frequency of the variable frequency oscillator. 8 6. A circuit that produces a periodic signal at its output, the periodic signal having a correlation For a defined phase relationship of an input signal transition with a known polarity, the circuit includes: a bistable device for receiving the input signal of the receiver * the bistable device has first and second outputs, and the bistable device reaction The input signal has a known polarity and alternately provides a signal to the first and second outputs; 〆 The first and second variable frequency oscillators, each of which has one / one Start input, a frequency control input, and a respective thyristor; a thyristor output of current oscillation signal; .............- ....... # I connected to each A gate element between the output of the variable frequency oscillator and the output of the circuit; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and connected to selectively connect the output of the bistable device to the variable frequency oscillator. The start input is also connected to the gate element in order to respond to an input signal transition having a known polarity to disconnect the start input of a variable frequency oscillator from an output of the bistable device and to release a respective first The connection of an oscillating signal to the output of the circuit, and the response of the input signal changes to connect the start input of another variable frequency oscillator to an output of the bistable device and connect an The second oscillating signal is output from the circuit, so that when another variable frequency vibrating paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) -19-A8 B8 C8 D8 When the circuit breaker is disconnected from the circuit output, a variable frequency oscillator is connected to the selection logic of the circuit output; and the frequency control input and the selection logic are connected to the variable frequency oscillators so that When the rate oscillator is disconnected, the frequency of each variable frequency oscillator is adjusted as a reference. The frequency of the periodic signal, so that the output produces a periodic signal that is reliably adjusted and sound phase synchronized tolerant of distortion. A respective phase locked loop. ^-t one (please read the precautions on the back and then fill in one page) 4 · The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Online Economy applies the Chinese National Standards (CNS) A4 specification (210X297 mm)- 20-