TW399287B

TW399287B - Structure of bottle-shaped deep trench and its manufacturing method

Info

Publication number: TW399287B
Application number: TW087121263A
Authority: TW
Inventors: Luen Mei
Original assignee: Siemens Plc; Mosel Vitelic Inc; Promos Techvologies Inc
Priority date: 1998-12-19
Filing date: 1998-12-19
Publication date: 2000-07-21
Also published as: DE19938481B4; JP2000223563A; DE19938481A1; JP3561447B2

Abstract

There is disclosed a bottle-shaped deep trench method, which is suitable for the substrate with a pad structure. The method forms a trench deep into the substrate at a predetermined position. First, a first insulated layer is formed to cover the surface of the pad structure. Second, the first insulated layer is etched onto a predetermined depth of the trench trough so as to leave the bottom insulated layer in the trench. Then, one pad oxidation layer is grown at the substrate sidewall on the upper region of the bottom insulated layer. Then, a second insulated layer is formed to cover the pad the surface of the oxidation layer, the pad layer structure and the bottom insulated layer. Then, the second insulated layer is etched to forms an insulated spacer at the pad layer structure inside the trench and the pad oxidation layer. Subsequently, the bottom insulated layer is removed. A bottled-shaped oxide layer is grown at the sidewall of the substrate, which is exposed on the down region of the wall of the insulated gap. The interface of the bottle-shaped oxidation layer and the sidewall of the substrate is expanded outside the trench. Then, the insulated spacer, the pad oxidation layer and the bottle-shaped oxide layer are removed, thereby forming the bottle-shaped deep trench.

Description

^S__87121263 Λ η 曰修正五、發明說明（1) 本發明係有關於一種半導體積體電路製程，特別有關於一種瓶型深溝槽之結構及其製造方法。近年來’隨著積體電路集積度的增加，半導體製程設計亦朝向縮小半導體元件尺寸以提高密度之方向發展，以目前廣泛使用之動態隨機存取記憶體（DRAM : dynamic random access memory)為例 ’64M DRAM製程已從〇.35um 轉換至0.3um以下，而128M DRAM或2 56M DRAM則更朝向0.2 um以下發展。由於電谷器基本上是由隔著一絕緣物質之兩導電層表面（即電極板）構成，而電容器儲存電荷之能力係由三種物理特徵決定’即（1)絕緣物質之厚度；（2)電極板之表面積；及（3)絕緣物質之電氣性質。其中為了使記憶體電路能包含大量之記憶胞，記憶胞之基底面積必須不斷減少以提高密度，同時，記憶胞電容之電極板部份則仍必須有足夠之表面積以儲存充分之電荷一般而言，高密度記憶體係具有兩種不同的電容器形成技術’其中一種為三維(three-dimension )之堆疊式電容（STC : stacked capacitor cell)，另一種為溝槽式電容。例如皇冠狀（crown)堆疊電容結構，其利用矽晶圓中存取裝置之上方空間來形成電容電極板，而溝槽式電容則利用基底主動區（active region)中之深溝槽來形成電谷儲存區。本發明之技術則是溝槽式電容技術的延伸。然而’隨著D R A Μ製程的持續縮小化，深溝槽之孔徑大小亦隨之限縮’當溝槽之縱寬比（aSpect ratio)已超過35^ S__87121263 Λ η Revision V. Invention Description (1) The present invention relates to a semiconductor integrated circuit manufacturing process, and particularly relates to a bottle-shaped deep trench structure and a manufacturing method thereof. In recent years, with the increase of the integration degree of integrated circuits, the design of semiconductor processes has also developed toward reducing the size of semiconductor elements to increase the density. Take the currently used dynamic random access memory (DRAM: dynamic random access memory) as an example. '64M DRAM manufacturing process has been switched from 0.35um to 0.3um, while 128M DRAM or 2 56M DRAM is moving towards 0.2um. Because the valley device is basically composed of two conductive layer surfaces (ie, electrode plates) separated by an insulating material, and the capacity of the capacitor to store charge is determined by three physical characteristics, namely, (1) the thickness of the insulating material; (2) Surface area of the electrode plate; and (3) electrical properties of the insulating substance. In order for the memory circuit to contain a large number of memory cells, the base area of the memory cells must be continuously reduced to increase the density. At the same time, the electrode plate portion of the memory cell capacitor must still have sufficient surface area to store sufficient charge. High-density memory systems have two different capacitor formation technologies. One is a three-dimension stacked capacitor (STC), and the other is a trench capacitor. For example, a crown-shaped stacked capacitor structure uses a space above an access device in a silicon wafer to form a capacitor electrode plate, and a trench capacitor uses a deep trench in an active region of a substrate to form an electric valley. Storage area. The technology of the present invention is an extension of the trench capacitor technology. However, as the D R AM process continues to shrink, the aperture size of deep trenches will be reduced accordingly. When the trench ’s aSpect ratio exceeds 35,

第4頁五、發明說明（2) .1時’作為電容儲存區之深溝槽將因而受限，此外，由於電谷量係與電容電極板之表面積成正比，而溝槽電容之電極板表面積為溝槽之深度與溝槽圓周面積之乘積，溝槽圓周面積則又與溝槽之孔徑有關，換言之，當製程技術從 0. 2um縮小至0. 1 8um時，溝槽之孔徑隨之變小，連帶使溝槽電容難以得到足夠之電容表面積以使電容量維持於4 〇pF 左右。再者’欲形成具有較小臨界尺寸之深溝槽，便必須選擇南縱寬比之方式進行蝕刻，同時當溝槽臨界尺寸愈小 ’即愈難使溝槽保持垂直輪廓，一般溝槽之孔徑係愈趨於基底底部愈加窄化（如第1圖所示）’此亦為目前蝕刻技術所面臨之挑戰。以傳統製程為例’其係以乾蝕刻技術直接蝕刻基底底部以形成一深溝槽，然而由於乾蝕刻製程受溝槽表面孔徑大小和溝槽深度之限制，因此僅能形成錐形深溝槽，而無法形成可以擴大電容儲存區表面積之瓶型深溝槽，同時目前亦未有實例顯示可以乾蝕刻技術來形成瓶型深溝槽且也無法延用至0.15 um以下之製程。此外，一種傳統瓶形電容製程，係由T. 〇Zaki等人所提出’參見（ 0.2 28 um Trench Cell Technologies with Bottle Shaped Capacitor for 1Gbit DRAMs,by T.Ozaki ，et al， IEDM’ 95’ pp66卜664，1 995 )，其中，瓶形電容之製造方法如下所述，首先在溝槽上部形成—厚度約8〇 nm之環形氧化層（c〇nar oxide layer )，然後執行氧化罩幕和原生氧化層之去除等電容製程，此時，環形氧化層厍葭亦因此減少至約5〇nm左右，接著沈積一複晶矽層， ^_ __5. Description of the invention on page 4 (2). At 1st time, the deep trench as a capacitor storage area will be limited. In addition, since the amount of valley is proportional to the surface area of the capacitor electrode plate, the surface area of the electrode plate of the trench capacitor As the product of the depth of the trench and the circumferential area of the trench, the circumferential area of the trench is related to the aperture of the trench. In other words, when the process technology is reduced from 0.2um to 0.18um, the aperture of the trench changes accordingly. It is small, and it is difficult for the trench capacitor to obtain a sufficient surface area to maintain the capacitance at about 40 pF. Furthermore, 'to form a deep trench with a smaller critical dimension, it is necessary to choose a method of etching with a south aspect ratio, and at the same time, the smaller the critical dimension of the trench', the more difficult it is to maintain the vertical profile of the trench. The more the system tends to narrow the bottom of the substrate (as shown in Figure 1), this is also a challenge facing the current etching technology. Take the traditional process as an example. It uses dry etching technology to directly etch the bottom of the substrate to form a deep trench. However, because the dry etching process is limited by the surface diameter of the trench and the depth of the trench, it can only form a tapered deep trench. Bottle-shaped deep trenches that can increase the surface area of the capacitor storage area cannot be formed. At the same time, there are no examples showing that dry-etching technology can be used to form bottle-shaped deep trenches, and the process cannot be extended to less than 0.15 um. In addition, a traditional bottle-shaped capacitor manufacturing process was proposed by T. O. Zaki et al. 664, 1 995), where the manufacturing method of the bottle-shaped capacitor is as follows. First, a circular oxide layer with a thickness of about 80 nm is formed on the trench, and then an oxide mask and a primary oxidation are performed. In the process of removing capacitors and other capacitors, the ring oxide layer is reduced to about 50 nm, and then a polycrystalline silicon layer is deposited. ^ _ __

_案號 87121263 修正曰五、發明說明（3) 於同環境下摻雜磷離子，隨之藉由爐管之熱退火製程將碟離子摻雜入溝槽之電容部側壁，環狀氧化層則可阻止磷離子播雜入溝槽上部，然後利用化學性乾蝕刻去除複晶矽層 ’同時在環狀氧化層下方之溝槽直徑也因此而擴大。然而前述傳統技術之問題在於，矽基底與捧雜離子之複晶矽層的姓刻選擇比並未較其他材質例如氧化層等為佳，因此，在半導體裝置尺寸日益縮小的情形下，其精準度並不符求。有鐘於此’本發明之目的即為了解決上述問題，而提出一種瓶型深溝槽之結構及其製造方法，其主要係先藉由 ^化^以在深溝槽内之基底底部和側壁形成瓶型氧化物二备，之以濕蝕刻方式蝕刻去除前述之瓶型氧化物層，由於氧化過程中會消耗基底中大量之石夕材f，因此，溝槽内 $瓶型氧化物層與矽基底之介面會朝外側移動瓶槽因而向外擴張，並進而使圍繞溝槽之基底側壁加約50%至100%，因此，溝槽電容結構之日亦隨之增加。合埽存&面積故依據本發明之—實施例，一種瓶法，適用於一具有塾層結構之基底，且塾：：：：製= 次姓刻第-絕緣層至溝槽之一既定深 2溝槽切其底部絕緣層接著實施熱氧化製…在底留: 之基底側壁形成一墊氧化物層；献後，忐一、緣層_ Case No. 87121263 Amended fifth, description of the invention (3) Doping phosphorus ions in the same environment, and then doping the dish ions into the side wall of the capacitor portion of the trench by the thermal annealing process of the furnace tube, and the ring oxide layer Phosphorus ions can be prevented from being diffused into the upper part of the trench, and then the polycrystalline silicon layer is removed by chemical dry etching. At the same time, the diameter of the trench under the ring-shaped oxide layer is also enlarged accordingly. However, the problem with the aforementioned conventional technology is that the selection ratio of the silicon substrate and the polycrystalline silicon layer containing hetero ions is not better than that of other materials such as oxide layers. Therefore, the accuracy of semiconductor devices is decreasing as the size of semiconductor devices decreases. Degrees do not match. Herein, the purpose of the present invention is to solve the above-mentioned problems, and propose a bottle-shaped deep groove structure and a manufacturing method thereof, which are mainly formed by forming a bottle at the bottom and side walls of the substrate in the deep groove first. The second type oxide is prepared by wet etching to remove the aforementioned bottle type oxide layer. Since a large amount of stone material f in the substrate is consumed during the oxidation process, the $ bottle type oxide layer and the silicon substrate in the trench are consumed. The interface will move the bottle trough to the outside and expand outward, and then increase the side wall of the substrate surrounding the trench by about 50% to 100%. Therefore, the date of the trench capacitor structure also increases. According to the embodiment of the present invention, a bottle method is suitable for a substrate having a layer structure, and 塾 :::: system = second name inscribed-one of the insulation layer to the trench The deep 2 trench cuts the bottom insulating layer and then performs thermal oxidation ... On the bottom left: a pad oxide layer is formed on the side wall of the substrate;

’以順應性復蓋墊氧化物層、墊層社構 7第二絕緣層 ^ ----_構和底部絕緣層表面修正 Λ-_3_ 曰 _案號8712]2肋五、發明說明（4) 2 Ϊ ’蝕刻第二絕緣’，以在溝槽内之墊層結構及墊氧 ^ ^ 成絕緣間隙壁，隨之，去除底部絕緣層， :一施熱氧化製程以在絕緣間隙壁下方暴露之基底側壁形 ,瓶型氧化物層’其中瓶型氧化物層與基底側壁之介面 Ϊ向溝槽外側擴張，之冑，去除絕緣間隙壁、塾氧化物層和瓶型氧化物層以形成瓶型深溝槽。為讓本發明之上述和其他目的、特徵、和優點能更明顯易It，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：圖式簡單說明第1至10圖為一半導體結構剖面圖，其顯示本發明之一種瓶型深溝槽之製造方法實施例。 [符號說明] 100〜基底；120，120’〜墊氧化物層；14〇〜墊氮化物層 ;160〜氧化物層；160’〜底部氧化物層；18〇〜氮化物層； 180’〜氣化物間隙壁；150〜基底侧壁；17〇〜瓶型氧化物層 ;1 9 0〜瓶型深溝槽。實施例首先睛參閱第1至10圖，其顯示本發明之一實施例之製造流程。依據第1圖’其係顯示本發明之起始步驟。其中，基底100為一半導體材質，例如由矽材質（sil ic〇ri )組成為方便說明起見，在此以一石夕基底為例。首先’起始步驟為在基底100表面依序形成絕緣層120 和140 ’其中絕緣層120和140構成一塾廣結構ho。例如該'Cover pad oxide layer, pad layer structure 7 second insulating layer with compliance ^ ___ Structure and bottom insulating layer surface modification Λ-_3_ said _ case number 8712] 2 ribs 5. Description of the invention (4 ) 2 Ϊ 'Etching the second insulation' to form an insulation gap in the trench structure and oxygen ^ ^, and then remove the bottom insulation layer: a thermal oxidation process to expose the insulation gap below The shape of the substrate side wall, the bottle-shaped oxide layer, wherein the interface between the bottle-shaped oxide layer and the substrate side wall expands to the outside of the trench, and then, the insulating spacer, the oxide layer and the bottle-shaped oxide layer are removed to form a bottle. Deep groove. In order to make the above and other objects, features, and advantages of the present invention more obvious and easy, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: The drawings briefly illustrate Figures 1 to 10 A cross-sectional view of a semiconductor structure showing an embodiment of a method for manufacturing a bottle-shaped deep trench according to the present invention. [Description of symbols] 100 ~ substrate; 120, 120 '~ pad oxide layer; 14 ~~ pad nitride layer; 160 ~ oxide layer; 160' ~ bottom oxide layer; 18 ~~ nitride layer; 180 '~ Gas barrier wall; 150 ~ substrate sidewall; 170 ~ bottle type oxide layer; 190 ~ bottle type deep groove. Embodiments First, referring to Figs. 1 to 10, a manufacturing process of an embodiment of the present invention is shown. Figure 1 'shows the initial steps of the invention. The substrate 100 is made of a semiconductor material, for example, made of a silicon material (silicon). For convenience of explanation, a Shixi substrate is used as an example here. First, the initial step is to sequentially form the insulating layers 120 and 140 on the surface of the substrate 100. The insulating layers 120 and 140 form a wide structure ho. For example this

第7頁案號 87121263 月曰修正五、發明說明（5) 步驟可在矽基底100之主動區表面依序形成厚度約為50埃之塾氧化物層，和厚度約為2000埃之墊氮化物層。舉例而言’墊氧化物層120之材質可由二氧化矽組成，其採用一熱生長式（thermal oxide)製程；墊氮化物層丨4〇可藉沈積一氮化矽材質形成’例如以二氣矽甲烷SiH2Cl2、氨nh3為主反應物，並藉低壓化學氣相沈積（LPCVD)製程產生。其中氮化物材質在後續製程中可作為蝕刻氧化物材質時之蝕刻罩幕（etching mask)。其次’請參閱第2圖，該步驟為利用微影製程及蝕刻步驟來定義墊層結構11〇和基底1〇〇以形成一溝槽13〇。例如，先於矽基底1〇〇之主動區位置定義一光阻圖案（未顯示 )，接著以非等向性乾蝕刻，如以氟碳化物之三氟甲烷 (CHF3)電漿為主蝕刻反應氣體，而藉反應性離子蝕刻法 (RIE .reactive ion etch)依序蝕刻墊層結構11()至基底 100之一既定深度，以形成一溝槽13〇，在本實施例中，所蝕刻之溝槽深度約為7.5um，溝槽130表面開口尺寸約為〇 2um，而溝槽13〇内之基底100底部寬度則約為〇 lum。 —其次，清參閱第3圖，該步驟為形成一絕緣層16〇 ,以覆蓋墊層結構11 〇表面並填滿前述之深溝槽丨3 〇。例如可選擇以高密度電漿（HDP :high density pUsma)化學氣相沈積製程（CVD)來沈積一由二氧化矽材質組成之氧化物層i6〇，其厚度約為2000埃，用以覆蓋墊層結構11〇之墊i化物層140表面以及填滿溝槽13〇。 ii60至溝槽130之一既定深度，以於溝賴内留下ίΐCase No. 87121263 on page 7 Rev. V. Description of the invention (5) The step can sequentially form a samarium oxide layer with a thickness of about 50 angstroms and a pad nitride with a thickness of about 2000 angstroms on the surface of the active area of the silicon substrate 100 in order. Floor. For example, the material of the pad oxide layer 120 may be composed of silicon dioxide, which uses a thermal oxide process; the pad nitride layer may be formed by depositing a silicon nitride material. Silicon methane SiH2Cl2 and ammonia nh3 are the main reactants and are produced by the low pressure chemical vapor deposition (LPCVD) process. Among them, the nitride material can be used as an etching mask when etching the oxide material in subsequent processes. Secondly, please refer to FIG. 2. This step is to define a pad structure 11 and a substrate 100 using a lithography process and an etching step to form a trench 13. For example, a photoresist pattern (not shown) is defined before the active area of the silicon substrate 100, and then anisotropic dry etching, such as fluorocarbon trifluoromethane (CHF3) plasma as the main etching reaction Gas, and RIE (reactive ion etch) is used to sequentially etch the pad structure 11 () to a predetermined depth of the substrate 100 to form a trench 13. In this embodiment, the etched The depth of the trench is about 7.5um, the opening size of the surface of the trench 130 is about 0um, and the width of the bottom of the substrate 100 in the trench 13 is about 0lum. — Secondly, referring to FIG. 3, this step is to form an insulating layer 16o to cover the surface of the cushion structure 11o and fill the aforementioned deep trenches 3o. For example, a high-density plasma (HDP: high density pUsma) chemical vapor deposition (CVD) process can be used to deposit an oxide layer i60 made of silicon dioxide material, with a thickness of about 2000 Angstroms to cover the pad. The surface of the pad structure 140 of the layer structure 110 and the trench 13 are filled. ii60 to a predetermined depth of one of the grooves 130 so that ΐ is left in the groove

接續’請參閱第4圖’該步驟為 ____塞號87121263___年月日佟,不___ 五、發明說明（6) 絕緣層160’ ，其中此既定深度距離溝槽130表面約lum，其作用為標記所欲形成之瓶型溝槽的起點，亦即，在約丨以上之區域係作為與元件之接面，而在1 u[n以下之區域則用來製作電容器之電容儲存區。舉例而言，對二氧化石夕材質構成之氧化物層160實施之餘刻步驟，係選擇氧化物對矽材質和氮化矽材質具高蝕刻選擇比之濕式蝕刻製程進行 ’其中’選擇以氫氟酸緩衝液來進行濕式蝕刻步驟，可在室溫下與二氧化矽快速反應，而不會蝕刻由矽材質構成之基底。其次，請參閱第5圖，該步驟為先形成一墊氧化物層 120’ ，再形成一絕緣層18〇以順應性覆蓋墊層結構丨丨❹和底部絕緣層1 60 ’表面。例如，先實施一熱氧化製程以底部絕緣層160’上方之基底側壁形成一墊氧化物層12〇，，厚度約為50埃，至於絕緣層18〇則可藉沈積一氮化矽材質形成，例如以二氣矽甲烷SiH2Cl2、氨NH3為主反應物，並萨氣：备沈積(LPCVD)製程產生以順應性覆蓋塾層二構110:底部氧化物層16〇’表自，其厚度約為2〇〇埃。以在ΐ m6 @，接續之步料對絕緣層m進行餘刻，具有保護作用之之層結構n〇和墊氧化物層12〇,側壁形成化物層夕涛間隙壁1 8〇’ 。例如，以乾蝕刻製程去除氮化物層180之覆蓋在墊層結構u 化物層180位於溝楢1qn由夕鈦隹取囬町不卞0丨刀，留下虱 11。側壁之垂直ΐ :形内成Λ物層12◦，和塾層結構 i 8 0，。形成/、有保護作用之氮化物間隙壁Continue to 'Please refer to Figure 4' This step is __plug No. 87121263 date, no ___ V. Description of the invention (6) Insulating layer 160 ', where the predetermined depth is about lum from the surface of the trench 130, Its role is to mark the starting point of the bottle-shaped groove to be formed, that is, the area above about 丨 is used as the interface with the component, and the area below 1 u [n is used to make the capacitor storage area of the capacitor . For example, the remaining steps of the oxide layer 160 made of the dioxide dioxide material are selected by performing an oxide etching process on the silicon material and the silicon nitride material with a high etching selection ratio. Hydrofluoric acid buffer solution is used for wet etching step, which can quickly react with silicon dioxide at room temperature without etching the substrate made of silicon material. Secondly, referring to FIG. 5, this step is to first form a pad oxide layer 120 ′, and then form an insulating layer 180 to conformably cover the pad structure and the bottom insulating layer 1 60 ′ surface. For example, a thermal oxidation process is first performed to form a pad oxide layer 120 on the sidewall of the substrate above the bottom insulating layer 160 ', with a thickness of about 50 angstroms. As for the insulating layer 180, it can be formed by depositing a silicon nitride material. For example, the two-gas silicon methane SiH2Cl2 and ammonia NH3 are used as the main reactants, and the gas-gas-prepare-deposition (LPCVD) process produces a compliant covering of the tritium layer 110: the bottom oxide layer 16 ′, and its thickness is approximately 200 angstroms. The insulating layer m is etched at ΐ m6 @, followed by a step, the protective layer structure no and the pad oxide layer 12 are formed, and the sidewalls are formed with an oxide layer Xitao gap wall 180. For example, the dry-etching process is used to remove the nitride layer 180 overlying the underlayer structure. The oxide layer 180 is located in the trench 1qn and retrieved from the titanium alloy, leaving the lice 11 behind. The vertical ΐ of the side wall: a Λ layer 12◦, and a 形 layer structure i 8 0, are formed in the shape. Formation / protective nitride spacers

修正曰案號87〗91?的五、發明說明（7) J ^ #J ^150 ° ^ ^ ^ ^ ^ ^ ^ 利翻# a…間隙壁為蝕刻保護層，並藉由濕式蝕 /fin，甘全去除前述形成於溝槽130内之底部氧化物層古μ ’，、'、中可選擇二氧化矽材質對矽材質和氮化矽材質具南χ選擇比之氫氟酸緩衝液來進行氧化物去除步驟。依序，凊參閱第8圖，該步驟為實施氧化成長製程， J "'、式或乾式之熱氧化步驟（thermal oxide)，以在氮化物間隙壁180’下方暴露之基底側壁15〇形成一瓶型氧化物層170，成長之厚度約為1〇〇〇埃其中此厚度可視實際實施之製程需要改變。此外，由於熱氧化製程會消耗位於基底側壁之矽材質，因此瓶型氧化物層1 70與基底側壁丨50 之介面將向溝槽130之外側擴張，而所擴張之厚度約為整個漑型氧化物層厚度之一半，亦即大約5〇〇埃左右。請參閱第9圖，其為去除絕緣間隙壁丨8〇’之步驟，例如可利用濕蝕刻方式，以熱磷酸溶液來蝕刻去除氮化物間隙壁180 ，其中部分之墊氮化物層140亦被蝕刻去除而留下1 4 0 ’之部分。請參閱第10圖，其為去除墊氧化物層丨2〇,和瓶型氧化物層170以形成瓶型深溝槽190之步驟。例如可利用濕蝕刻方式，如以氫氟酸緩衝蝕刻液來蝕刻去除墊氧化物層12〇，和瓶型氧化物層170 ’以形成瓶型深溝槽190。依據前述實施例所形成之瓶型深溝槽結構係包括一半導體基底100 ’形成有一瓶形溝槽19〇，該瓶形溝槽具有一第一深度dl如約為7. 5um及一隨第一深度dl變化之溝槽寬度以。及一側壁s，由半導體基底1〇〇圍繞瓶形溝槽ι9〇8形成Revised case number 87 〖91? V. Description of the invention (7) J ^ #J ^ 150 ° ^ ^ ^ ^ ^ ^ ^ Turn over # a ... the spacer is an etching protection layer, and by wet etching / fin In order to completely remove the bottom oxide layer formed in the trench 130, the silicon dioxide material and the silicon nitride material may be selected from the hydrofluoric acid buffer solution with a ratio of χ to silicon material and silicon nitride material. An oxide removal step is performed. Sequentially, referring to FIG. 8, this step is to implement an oxidative growth process, J " ', or dry thermal oxidation step, to form the substrate sidewall 15 exposed under the nitride spacer 180'. The thickness of a bottle-shaped oxide layer 170 is about 1000 angstroms, and this thickness may be changed according to the actual implementation process. In addition, since the thermal oxidation process consumes the silicon material located on the substrate sidewall, the interface between the bottle-shaped oxide layer 1 70 and the substrate sidewall 丨 50 will expand to the outside of the trench 130, and the expanded thickness is about the entire 漑 -type oxidation. The thickness of the material layer is half, that is, about 500 angstroms. Please refer to FIG. 9, which is a step of removing the insulating spacer 丨 80 ′. For example, the nitride spacer 180 may be etched and removed with a hot phosphoric acid solution by wet etching, and a part of the pad nitride layer 140 is also etched. Remove and leave a part of 1 4 0 '. Please refer to FIG. 10, which is a step of removing the pad oxide layer 20 and the bottle type oxide layer 170 to form a bottle type deep trench 190. For example, a wet etching method, such as a hydrofluoric acid buffered etching solution, is used to etch and remove the pad oxide layer 120 and the bottle-shaped oxide layer 170 'to form a bottle-shaped deep trench 190. 5um 和一个随第一 The bottle-shaped deep trench structure formed in accordance with the previous embodiment includes a semiconductor substrate 100 'formed with a bottle-shaped trench 190, the bottle-shaped trench having a first depth dl such as approximately 7. 5um and a first The trench width varies with the depth dl. And a side wall s formed by a semiconductor substrate 100 around a bottle-shaped trench ι708

第10頁 _案號 87121263 五、發明說明（8) 年月曰修正Page 10 _ Case number 87121263 V. Description of the invention (8)

’其自一第二深度d2如約ium之位置，區分為一上部23〇和一底部250 ’其中，側壁上部230不包含環狀氧化層，而第二深度d2小於第一深度dl。此外’於第二深度d2位置處之侧壁周圍區域si，具有 —自上部230向底部250延伸之突然增加的溝槽寬度。而壁底部250於鄰近第二深度“位置處，其溝槽寬度約大於1 =壁上部230之鄰近第二深度心位置處30%以上，而於此例壁周圍區域s 1以下，溝槽侧壁底部2 50則具有一隨深戶1 蜮之溝槽寬度變化。又啊另前述基底表面之溝槽寬度約為〇25uin以下，則約為15以上。衣寬此完成前述實傳統半導體可藉此瓶型。而由於本槽之基底側電容儲存區明之瓶型溝溝槽電容結到達〇. 13um 結構可應用憶胞面積下中所應用之各種具恰當構空間亦不可接續之後的 ’舉例而言，之電容儲存區張’使圍繞溝槽電容結構之由於本發而以此形成之需求，甚至是本發明之電容其在有限之記同時，本發明述者’其能由且本發明之結製程’例如半導體元件之製作等深溝槽1 90來形成溝槽電容結構實施例之瓶型深溝槽190向外擴壁表面積増加約5〇%，因此，溝面積亦隨之增加約5〇%以上。槽製造方法可有效利用空間，構，亦可符合下一世代之記憶之兩個世代製程以上。因此，'It is distinguished from a position at a second depth d2 as about ium, which is divided into an upper part 23 and a bottom part 250', wherein the upper side wall 230 does not include a ring-shaped oxide layer, and the second depth d2 is smaller than the first depth dl. In addition, the area si around the sidewall at the position of the second depth d2 has a sudden increase in groove width extending from the upper portion 230 to the bottom portion 250. Where the wall bottom 250 is at a position near the second depth, the groove width is greater than 1 = 30% of the wall top 230 is near the second depth center, and in this example, the area around the wall is below s 1 and the groove side The bottom of the wall 2 50 has a groove width that varies with the depth of 1 户. Also, the width of the groove on the substrate surface is below 0.25uin or less, which is approximately 15 or more. This bottle type, and since the bottle type trench trench capacitor junction of the capacitor storage area on the base side of the tank reaches 0.13um structure, it can be applied in various cell structures with appropriate structure space in the memory cell area. In other words, the capacitor storage area is stretched to meet the requirements of the trench capacitor structure formed by the invention, and even the capacitor of the present invention is limited. Junction process, such as the fabrication of semiconductor devices, such as deep trenches 190 to form trench capacitor structures. The bottle-shaped deep trenches 190 of the embodiment increase the surface area of the wall by about 50%, so the trench area also increases. 5〇% or more. The method of manufacturing a tank space can be effectively utilized, the configuration can also meet the next generation memory of more than two generation process. Thus,

第11頁於動態隨機存取記憶體（DRAM)，，可大幅增加相當之電容容量。物質材料，並不限於實施例所特性之物質和形成方法所置換，限於實引用之尺寸大小。 _案號 87121263_年月日__ 五、發明說明（9) 雖然本發明已以一較佳實施例揭露如下，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可做些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Page 11 In dynamic random access memory (DRAM), can significantly increase the equivalent capacitance. The material materials are not limited to those replaced by the materials and forming methods characteristic of the embodiments, but are limited to the dimensions actually cited. _ Case number 87121263_ 年月日 __ V. Description of the invention (9) Although the present invention has been disclosed as a preferred embodiment as follows, it is not intended to limit the present invention. Any person skilled in the art will not depart from the present invention. Within the spirit and scope of the invention, some modifications and retouching can be done. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

第12頁Page 12

Claims

±_Η 案號 871212fi.S 、中請專利範圍 1其：種瓶型深溝槽之製造方法，適用於一具有势層社構之基底，該墊層結構之一既定位置且形溝槽，該方法包括下列步驟：未入基底之 (a) 形成一第一絕緣層，其覆蓋滿該溝槽；恐層…構表面並填 (b) 蝕刻該第一絕緣層至該溝槽之—既定該溝槽内留下底部絕緣層；又乂於 (c) 實施一熱氧化製程，以在該底部底侧壁形成一墊氧化物層；，《上方之基塾(層絕緣層，以順應性覆蓋該墊氧化物層、墊層結構和該底部絕緣層表面； (e )蝕刻該第二絕緣層，以在該溝槽該墊氧化物層側壁形成一絕緣間隙壁；層、，〇構及 (f )去除該底部絕緣層； (g)實施熱氧化製程以在該絕緣間底側壁形成-瓶型氧化物層，其中該瓶型氧化物暴層露與〜基基底側壁之介面係向該溝槽外侧擴張；及、〜 (h )依序去除該絕緣間隙壁、墊氧化物層和瓶型物層以形成該瓶型深溝槽。 2. 申請專利範圍第1項所述之方法，其中，於步驟 )’該第一絕緣層係由一氧化物材質形成。 3. 如申請專利範圍第2項所述之方法，其中，於步驟 (b )’該既定深度係用以標記所欲形成之瓶型深溝槽的起 Λ 4.如申請專利範圍第3項所述之方& ’其中’於步驟± _Η Case No. 871212fi.S, Chinese patent scope 1: The method for manufacturing a bottle-shaped deep groove is suitable for a substrate with a potential layer structure, and one of the cushion structure has a predetermined position and a groove. The method It includes the following steps: (a) forming a first insulating layer covering the trench without entering the substrate; forming a layer on the surface and filling (b) etching the first insulating layer to the trench—the trench is established The bottom insulation layer is left in the trench; and (c) a thermal oxidation process is performed to form a pad oxide layer on the bottom bottom side wall; "the upper substrate (layer insulation layer, covering the compliance with compliance) A pad oxide layer, a pad structure, and a surface of the bottom insulating layer; (e) etching the second insulating layer to form an insulating gap on a side wall of the pad oxide layer in the trench; ) Removing the bottom insulating layer; (g) performing a thermal oxidation process to form a bottle-shaped oxide layer on the side wall of the insulating compartment, wherein the interface between the bottle-shaped oxide layer and the sidewall of the base substrate is toward the trench Lateral expansion; and, ~ (h) sequentially remove the insulation gap , Pad oxide layer and the layer of bottles to form the bottle-type deep trench. 2. The method of application of the first item of the scope of the patent, wherein, in the step ') of the first insulating layer is formed of an oxide-based material. 3. The method as described in item 2 of the scope of patent application, wherein, in step (b) ', the predetermined depth is used to mark the start of the bottle-shaped deep groove to be formed. 4. As described in item 3 of the scope of patent application Fang Zhifang & 'where' in steps

第13頁修正Page 13 Correction

SS.J7121263 六、申請專利範圍形成。法’其中，於步驟底部絕緣層。法’其中，於步驟除該底部絕緣層》法’其中，於步驟絕緣間隙壁。法，其中’於步驟緣間隙壁。法’其中’於步驟除該瓶型氧化物層適用於電容儲存區 (d )該第—絕緣層係由一氮化物材質 5. 如申請專利範圍第4項所述之方 (f )，係以選擇性之濕蝕刻方式去除該 6. 如申睛專利範圍第5項所述之方 (g )，係以氫氟酸緩衝蝕刻液來蝕刻去 (h) 7’如申清專利範圍第5項所述之方，係以選擇性之濕蝕刻方式去除該 (h) 8. 如申請專利範圍第7項所述之方 ’係以熱磷酸溶液來蝕刻去除該絕 9. 如申請專利範圍第7項所述之方 (h) ’係以氬氟酸緩衝蝕刻液來蝕刻去及該塾氧化物層。 10. 一種瓶型深溝槽之製造方法，，包括下列步驟： (a) 提供一矽基底，其具有一主動區； (b) 依序在該矽基底表面形成一第一墊氧化物層及— 第一墊氮化物層’其用以構成一墊層結構； (c) 定義該墊層結構及該基底，以在該主動區中形成一溝槽； (d)形成一第二氧化物層，其覆蓋該堆疊層表面並填滿該溝槽； (e)蝕刻該第二氧化物層至該溝槽之一既定深度，以於該溝槽内留下底部氧化物層； (f )實施一熱氧化製程，以在該底部絕緣層上方之基底側壁形成一塾氧化物層；SS.J7121263 6. The scope of patent application is formed. Method 'wherein the step is at the bottom of the insulating layer. In the method, the step of removing the bottom insulating layer is performed in the step. In the method, the step is used to insulate the spacer. Method, in which the step margin wall. Method 'wherein' the step of removing the bottle-type oxide layer is suitable for the capacitor storage area (d), the first insulating layer is made of a nitride material 5. As described in item 4 of the scope of patent application (f), the system This is removed by selective wet etching. 6. The method (g) described in item 5 of Shen Jing's patent scope is etched with a hydrofluoric acid buffer etching solution (h) 7 'as described in patent scope 5 The method described in the item is to remove the (h) by a selective wet etching method. The method described in item 7 of the scope of the patent application is to remove the insulation with a hot phosphoric acid solution. The method (h) 'described in item 7 is that the hafnium oxide layer is etched away with a hydrofluoric acid buffer etching solution. 10. A method for manufacturing a bottle-shaped deep trench, comprising the following steps: (a) providing a silicon substrate having an active region; (b) sequentially forming a first pad oxide layer on the surface of the silicon substrate and- The first pad nitride layer is used to form a pad structure; (c) defining the pad structure and the substrate to form a trench in the active region; (d) forming a second oxide layer, It covers the surface of the stacked layer and fills the trench; (e) etching the second oxide layer to a predetermined depth of the trench to leave a bottom oxide layer in the trench; (f) implementing a A thermal oxidation process to form a hafnium oxide layer on a sidewall of the substrate above the bottom insulating layer;

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曰修正 (g)形成-第二氮化物層’以順應性覆蓋該塾氧化物層、墊層結構和該底部氧化物層表面；蝕刻該第二氮化物層，卩在該溝槽内之墊層結構 σ塾氧化物層側壁形成一氮化物間隙壁； (i )濕钱刻去除該底部氧化物層； (j )實施熱氧化製程以力今g & & 基底側壁之介面係向該溝槽外側擴張了第一氧化物層與該〇〇依序濕蝕刻去除該第三 χ，及該氮化物間隙壁以形成該用於—氧化物層、墊氧化州^ 11 -種瓶型深溝槽結構包Υ儲存區之瓶型深溝槽。一半導體基底，形成；^ 一& 一第一哽声爲陆兮枝有瑕形溝槽，該瓶形溝槽具有一:ί:第一深度變化之溝槽寬度；則L由該半導體基底圍繞該瓶形溝槽形成，其依區分為一上部和，其中該第二深度小於該第一深度；及邱第一冰度位置處之側壁周圍區域’具有-自該上突然增加的溝槽寬度，且該側壁上部不包其中該溝槽深寬比則約為其中該第二具申請專利範圍第11項所述之結構底表面之溝槽寬度約為0.25㈣以下’ 1 53以上。 13.如巾請專利範圍第η項所述之結構冰度為距該基底表面約丨ujn。其中該侧壁第"項所述之結構Correction (g) formation-the second nitride layer 'covers the surface of the hafnium oxide layer, the underlayer structure, and the bottom oxide layer with compliance; the second nitride layer is etched, and the pad in the trench is etched The layer structure σ 塾 side wall of the oxide layer forms a nitride spacer; (i) wet bottom is used to remove the bottom oxide layer; (j) a thermal oxidation process is performed to force the interface of the side wall of the substrate to the The first oxide layer and the 00 are sequentially wet-etched outside the trench to remove the third x, and the nitride spacers to form the oxide layer, pad oxidation state, and the bottle type deep trench. The trough structure includes a bottle-shaped deep groove in the storage area. A semiconductor substrate is formed; ^ a & a first squeak is a grooved groove of the Lu Xizhi branch, the bottle-shaped groove has a: 第一: the first depth of the groove width change; then L from the semiconductor substrate It is formed around the bottle-shaped groove, which is divided into an upper part and a lower part, wherein the second depth is smaller than the first depth; and the area around the side wall at the first ice degree position of Qiu has a groove that suddenly increases from there. Width, and the upper side of the side wall does not include the groove aspect ratio, which is about the groove width of the bottom surface of the structure described in item 11 of the second patent application, which is about 0.25 mm or less, and more than 1 53. 13. The structure described in item η of the patent claim, the ice degree is about ujn from the surface of the substrate. The structure of the side wall item "

wm 第15頁，部於鄰近該第二深度位置，其溝槽寬度約大於該側壁上部之鄰近該第二深度位置30%以上。 1 5.如申請專利範圍第丨丨項所述之結構，其中該溝槽側壁底部具有一隨深度漸減之溝槽寬度變化。 ^ 16·如申請專利範圍第11項所述之結構，其中該第一深度為距該基底表面約75un]。 7. —種瓶型深溝槽之製造方法，適用於一基底該法包括下列步驟 _ (a )提供能予以選擇性 (b)形成一深入該基底之溝槽，該溝槽具有=側^ (C)形成一由該第一絕緣材料組成之第一絕緣層，以填入該溝槽； (d )蝕刻該第一絕緣層至一既定深度，該既定深度之底部絕緣層；以形成-低於隙壁⑷於該溝槽侧壁形成一由該第二絕緣材料組成之間 (f )以該間隙壁為罩幕，去除該底部底部側壁；〇啄層以露出該 (g )對該底部側壁進行化學反應；及 (h)去除該底部側壁之產生化學反應該底部之溝槽寬度。丨刀以擴大 18. 如申請專利範圍第17項所述之方法，底部側壁進行之化學反應為熱氧化反應。、，〇 19. 如申請專利範圍第18所述之方法，材質’該第二絕緣材料為氮化：一 _案號87121263_年月曰修正_ 六、申請專利範圍〇 2 0 .如申請專利範圍第1 9所述之方法，其中，該間隙壁之形成方式，包括：使用化學氣相沈積製程沈積一氮化物層，並填入該溝槽；及使用非等向性蝕刻製程以於該溝槽側壁形成一氮化物間隙壁，其露出部分底部絕緣層表面。 21 ,如申請專利範圍第2 0所述之方法，其中，在沈積該氮化物層之前，更包括形成一墊氧化物層之步驟。 2 2 . —種瓶型深溝槽結構包括：一半導體基底，形成有一瓶形溝槽，該瓶形溝槽具有一第一深度及一隨該第一深度變化之溝槽寬度；一側壁，由該半導體基底圍繞該瓶形溝槽形成，其依據一第二深度區分為一上部和一底部，其中該第二深度小於該第一深度；及於該第二深度位置處之側壁周圍，具有一自該上部向底部延伸之突然增加的溝槽寬度。wm p.15, the portion adjacent to the second depth position has a groove width that is approximately 30% greater than the upper portion of the side wall adjacent to the second depth position. 1 5. The structure according to item 丨丨 in the scope of patent application, wherein the bottom of the sidewall of the trench has a width of the trench that decreases with depth. ^ 16. The structure described in item 11 of the scope of patent application, wherein the first depth is about 75un from the surface of the substrate]. 7. —A method for manufacturing a bottle-shaped deep groove, which is suitable for a substrate. The method includes the following steps_ (a) providing a selective (b) formation of a groove deep into the substrate, the groove having = lateral ^ ( C) forming a first insulating layer composed of the first insulating material to fill the trench; (d) etching the first insulating layer to a predetermined depth, a bottom insulating layer of the predetermined depth; to form-low A gap wall is formed on the side wall of the trench to form a gap composed of the second insulating material (f) with the gap wall as a cover, removing the bottom bottom side wall; pecking the layer to expose the (g) to the bottom The side wall undergoes a chemical reaction; and (h) removing the bottom side wall produces a chemical reaction at the bottom groove width.丨 Knife to expand 18. According to the method described in item 17 of the scope of patent application, the chemical reaction on the bottom side wall is a thermal oxidation reaction. 、〇19. According to the method described in the scope of patent application No. 18, the material 'The second insulating material is nitrided: _ Case No. 87121263_ year month and month amendments _ 6. Scope of patent application 〇 2 0. The method of claim 19, wherein the forming method of the spacer comprises: depositing a nitride layer using a chemical vapor deposition process and filling the trench; and using an anisotropic etching process to the A sidewall of the trench forms a nitride spacer, which exposes part of the bottom insulating layer surface. 21. The method as described in claim 20, wherein before depositing the nitride layer, a method of forming a pad oxide layer is further included. 2 2. A bottle-shaped deep trench structure includes: a semiconductor substrate formed with a bottle-shaped trench, the bottle-shaped trench having a first depth and a trench width that varies with the first depth; a side wall formed by The semiconductor substrate is formed around the bottle-shaped trench, and is divided into an upper portion and a bottom portion according to a second depth, wherein the second depth is smaller than the first depth; and around the side wall at the second depth position, there is a A sudden increase in groove width extending from the upper portion to the bottom.

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