五、發明說明（1) ----一~-- 3本發明是有關於一種提昇蝕刻一致性的半導體製程， ^是有關於一種利用蝕刻終止層來改善蝕刻厚度不均的製 程技術，可減少因為被蝕刻膜厚度不均所導致的蝕刻不一 ，特別適用在高深寬比（aspect rati〇>8)的接觸窗蝕 刻。 在一般的積體電路製程中，在晶圓上製作出M0S電晶 =，會先在基底上沈積一層介電材肖，然後再進行後續 、，屬層的沈積，這層用來隔離金屬線與M〇s元件的介電層 通常被稱為内層介電層（Inter_Layer Dielectrics ; θ I^LD)，内層介電層結構通常是由化學氣相沈積法所沈積的 虱化層所組成，例如PE_TE〇s、Bp_TE〇s等，有時更包括一 1 =旋轉，佈所形成之S0G層。由於這層内介電層並非完 全平坦而是隨著晶圓表面的圖案高低起伏，因此通常可藉 由化學機械研磨法（CMP)加以平坦化之後，再進行後續接 觸窗的蝕刻。 ' 接下來，則是以微影成像和蝕刻程序，在内層介電層 中疋義出接觸窗口的圖案，以便進行金屬層與M〇s源極/汲 極的接觸（contact)。在進行接觸窗的蝕刻時，為了使金 屬與M0S的接觸能夠完全，位於源極/汲極上方的氧化矽必 須被徹底的清除，然而，即使是經過化學機械研磨（CMp) 的介電層也很難達到完全的平坦化，平均而言，其在晶圓 上的厚度依然會有±3K埃的差異（最大的高低差可達到βκ 埃之譜）。因此，在習知技術中為了彌補介電層在晶圓上 的厚度差異，在蝕刻接觸窗時通常需加上約2〇%的過度蝕V. Description of the invention (1) ---- 1 ~-3 The present invention relates to a semiconductor process for improving etching uniformity, and ^ relates to a process technology using an etching stop layer to improve uneven etching thickness. It reduces the uneven etching caused by the uneven thickness of the etched film, and is especially suitable for contact window etching with high aspect ratio (aspect rati0> 8). In a general integrated circuit manufacturing process, a MOS transistor is produced on a wafer. A layer of a dielectric material is first deposited on the substrate, and then a subsequent, metal layer is deposited. This layer is used to isolate metal wires. The dielectric layer of the Mos element is usually called an inter-layer dielectric layer (Inter_Layer Dielectrics; θ I ^ LD). The structure of the inner dielectric layer is usually composed of a chemical layer deposited by chemical vapor deposition, such as PE_TE0s, Bp_TE〇s, etc., sometimes even include a SOG layer formed by 1 = rotation, cloth. Because this inner dielectric layer is not completely flat but fluctuates with the pattern on the wafer surface, it can usually be planarized by chemical mechanical polishing (CMP) before the subsequent contact window etching. 'Next, the pattern of the contact window is defined in the inner dielectric layer by the lithography imaging and etching process so as to make contact between the metal layer and the Mos source / drain. During the contact window etching, in order for the metal to contact the MOS completely, the silicon oxide above the source / drain must be completely removed. However, even the dielectric layer subjected to chemical mechanical polishing (CMp) is also It is difficult to achieve complete planarization. On average, the thickness on the wafer will still have a difference of ± 3K Angstroms (the largest difference in height can reach the spectrum of βκ Angstroms). Therefore, in order to compensate for the difference in the thickness of the dielectric layer on the wafer in the conventional technology, it is usually necessary to add about 20% overetching when etching the contact window.
五、發明說明（2) 刻’才能確保每個區城的接觸窗都能夠蝕刻完全。但過产 蝕刻的時間越長，蝕刻電漿對底層材料（矽化鈦或矽'^所^ 成的損失也就越大’不僅會影響到元件的電性，甚至造成 接合漏電流（junction leakage)。 有鑑於此，本發明的主要目的就是為了解決上述問 題，而提供一種以蝕刻終止層改善蝕刻厚度不均的半導體 製程，依據本發明方法可減少過度蝕刻的時間，降低蝕刻 電襞對底層材料的破壞。 在半導體積體電路的餘刻製程中，蝕刻終丘層（Etch Stop)是一種常被使用的技術，利用被蝕刻層與蝕刻終止 層之間明顯的敍刻選擇比，可確保敍刻程序的精確度、，並 可應用在自動對準接觸窗（SAC)製程中，具有放寬操作範 圍的功效。惟選㈣刻終止層時，除了考慮㈣選擇比之 二：m i下方材料層的性f ’以及事後去除時的方 便與否來作整體性考量’方不至於產生新的問題。 在本發明的方法中，係以一層氮化 矽（SiON)來取代内層介雷呙甘ώ & μ 乳乳化 PE-TE0S)作為#刻終止層I =八f f彳匕層（例如 ㈣卜第-階段_所^用：；；；===的 化石夕（或氮氧化石夕）呈有較古^ =體^頁對氧化石夕/氣 刻停留在此钮刻終較：：=，(>9) ’以便讓麵 電層有高有低，但是： ’儘管未餘刻之前的介 度差將可因為蝕刻終止居=而2刻進打完畢後，其厚 當氧化婦化石夕的=== 大降低。舉例來說， J比為10 .1時，原本厚度差達士 五、發明說明（3) 一 3 K埃的介f & 下±〇.3Κ埃。在ΐ第一階段蝕刻完畢後’其厚度差將只剩 穿透氮化石夕二階段的敍刻當中，可視需要選用容易 其下的介電層古化石夕）的製程氣冑’以巍穿麵刻終止層與 度差僅剩“本出基底為止、。由於此時介電層的厚 間也只需要原本的^之，因此進行過度蝕刻所需的時 — 2%)’可大大減少過度 詳而之，本發明的方法包括下列步驟： 止層、以及第半二導介體電^底.上依序形成第-介電層、蝕刻終 個開（口b 以在第二介電層中形成複數 選擇性，使餘刻停留刻終止層之間的餘刻 協钚馇- 、嶺蝕刻終止層；以及 與第-介電層，以飯形刻成步驟J沿上述開口蝕刻蝕刻終止層 其特徵在於步=)成;//上述基底之接觸窗。 之蝕刻步驟停留於蝕刻終止钱刻p止層，可使步驟⑶） 介電層完全去除為止，以 直到將所有開口下的第一 昇蝕刻均勻度。 3降低介電層的厚度差異、提V. Description of the invention (2) Engraving can ensure that the contact windows of each district can be completely etched. However, the longer the over-production etching time, the greater the loss of the underlying material (titanium silicide or silicon) caused by the etching plasma will not only affect the electrical properties of the device, but even cause junction leakage. In view of this, the main purpose of the present invention is to solve the above problems, and provide a semiconductor process with an etching stop layer to improve uneven etching thickness. According to the method of the present invention, the time of over-etching can be reduced, and the etch voltage on the underlying material In the remaining process of semiconductor integrated circuits, Etch Stop is a commonly used technology, which uses the obvious etch selection ratio between the etched layer and the etch stop layer to ensure the The accuracy of the engraving procedure can be used in the automatic alignment contact window (SAC) process, which has the effect of widening the operating range. However, when selecting the engraving termination layer, in addition to considering the ㈣ selection ratio: the material layer below the mi The f 'and the convenience of removing it afterwards as a whole should not be considered as a whole. In the method of the present invention, a layer of silicon nitride (S iON) to replace the inner layer of Leigangan & μ milk emulsified PE-TE0S) as the # 刻 止 层 I = eight ff 彳 层 layer (for example ㈣ 第 第 -stage_ used by: ;;; === 的Fossil eve (or oxynitride eve) shows a more ancient ^ = body ^ page on oxidized stone eve / gas engraving stays at the end of this button: ::, (> 9) 'in order to make the surface electric layer high Low, but: 'Although the difference in the degree of interstitial before the remaining time can be stopped because of etching, and the thickness of the oxide film is greatly reduced after the etching is completed. For example, the J ratio is At 10.1, the original thickness difference was Dashi V. Description of the invention (3)-3 K Angstrom f & under ± 0.3K Angstrom. After the first stage of etching, the thickness difference will only penetrate In the second-stage narrative of nitrided stone, if necessary, a process that can easily use a dielectric layer (an ancient fossil stone) can be selected. The process is to “cut through the surface and cut off the difference between the end layer and the degree.” When the thickness of the dielectric layer is only required, the time required for over-etching-2%) 'can greatly reduce the excessive detail. The method of the present invention includes the following steps: Stop layer, and the second semi-dielectric dielectric. The first-dielectric layer is sequentially formed, and the etching is finally opened (b to form a plurality of selectivity in the second dielectric layer, so that the rest of the stay is terminated. The etch stop layer between the layers and the etch stop layer; and the first dielectric layer are etched in a rice shape in step J. The etch stop layer is etched along the above-mentioned opening, which is characterized by step =) 成; // the above substrate The contact step of the etching step is to stop the etching and stop the p-stop layer, so that the dielectric layer can be completely removed in step (3) until the first liter of etching uniformity under all openings is reduced. 3 Reduce the thickness of the dielectric layer Difference, mention
為讓本發明之上述和A 顯易懂，下文特舉一較佳二1目的、特徵、和優點能更明 細說明如下： A $例’並配合所附圖式，作詳 圖式之簡單說明 第卜3圖為一系列剖面圖 用以說明本發明一較佳實In order to make the above and A of the present invention comprehensible, the following describes one of the objectives, features, and advantages of a better one as follows: A $ example 'and a simplified description of the detailed drawings in conjunction with the attached drawings Fig. 3 is a series of cross-sectional views for explaining a preferred embodiment of the present invention.
第6頁 五、發明說明（4) 施例形成内層介電層與蝕刻接觸窗的 符號說明 10〜半導體基底； 1 2 ~場氧化層； 1 4〜閘極氧化層； 1 6〜閘極導電層； 1 8〜源極/、;及極區； 2 0、2 2〜絕緣層； 30〜第一介電層； 3 2〜蝕刻終止層； 34〜第二介電層； 4 0〜接觸窗。 實施例 在本實施例中，係依本發明之上述方法來製作内層介 電層並在其中蝕刻出高深寬比（aspect rati〇>8)的接觸 窗。請參照第1圖’首先提供一半導體基底1〇，而在基底 上已开> 成有電晶體元件，包括閘極氧化層1 4，閘極導電層 1 6 ’以及源極/汲極區1 8，基底上有場氧化層1 2將此電晶 體與其他元件隔離’並有絕緣層2 0、2 2將閘極覆蓋以保護 此電晶體；其中閘極導電層1 6例如是石夕化鶴/複晶；g夕層， 絕緣層2 0、2 2的材質通常是氮化矽。 繼續參照第1圖，接著進行内層介電層（ILD )的沈積， 依本發明依序沈積第一介電層30、蝕刻終止層32、及第二 介電層3 4。根據本發明的方法，钮刻終止層的材質可為氮 第7頁~- " 五、發明說明（5) 氮氧1“夕’其厚度約在1 0 00〜2000埃之間，例如 第介電層與第二介電層的材質並無特殊限 如忠t㊉ί由化學氣相沈積法所沈積的氧化層所組成。舉 介電：可包厚:R6K埃的〇3-TEOS層’而第二 η闰由由&數層*PE_TE0S與⑽―1^08堆疊而成的結構 ΛΛί2 )。在本實施例中，由第一介電層別、钱 第埃二介電層34所賴 姓刻Si ΐ:第2圖/以一光阻圖案當作罩幕(未顯示） 在匕直到將所有開口底下的第 的高選擇比，在本實施中係選層與飯刻終止層 種氣體的蝕刻配方，其氧化矽=3CH2F2、CA、⑶等三 1，因此經過此崎驟T，夕殘 的㈣比可達: ±〇.3K埃。 殘餘介電層的厚度差異僅有 接下來晴參照第3圖，〉VL莫卩 刻’直到露出基底上的源極;汲：：、=績第二階段的蝕 使餘刻能夠容易穿透餘刻終止'用止。此時’為了 的餘刻配方，，列如可使用包含c曰可選用㈣選擇性較差 Ar等六種氣體的蝕刻配方，盆j 6 2 2、C4F8、CO、〇2、 2 :ι。待主蝕刻完畢之後，ςί化矽/氮化矽的蝕刻比約 的第一介電層蝕刻乾淨，由於=，度蝕刻以將接觸窗底下 於此時介電層的厚度差僅有士 第8頁 五、發明說明（6) '一- -------—一· 0. 3K ’只需進行〇· 3K的過度蝕刻即可。因此相較於之 本發明的製程能將過度蝕刻的時間縮短裏原本的十分 一’可大幅降低過度钱刻對底層材料所造成的破壞， 元件性能受到影響。 雖然本發明已以一較佳實施例揭露如上，麩立並 以限定本發明’任何熟習此技藝者，在不脫離本發明 神和範圍内’當可作各種之更動與潤飾，因此本發明 瘦範圍當視後附之申請專利範園所界定者為準。 下， 之 避免 非用 之精 之保Page 6 V. Description of the invention (4) Example of symbols for forming an inner dielectric layer and etching contact window 10 ~ semiconductor substrate; 1 ~ field oxide layer; 1 ~ gate oxide layer; 16 ~ gate conductivity Layers; 18 ~ source / ;; and electrode regions; 20, 2 2 ~ insulating layers; 30 ~ first dielectric layer; 3 ~ etch stop layer; 34 ~ second dielectric layer; 40 ~ contact window. EXAMPLES In this example, a contact window with a high aspect ratio (aspect rati0> 8) was fabricated by forming an inner dielectric layer according to the above method of the present invention. Please refer to FIG. 1 'a semiconductor substrate 10 is provided first, and a transistor element is formed on the substrate, including a gate oxide layer 14, a gate conductive layer 16', and a source / drain region 18, there is a field oxide layer on the substrate 1 2 to isolate this transistor from other components, and an insulating layer 2 0, 2 2 covers the gate to protect the transistor; the gate conductive layer 16 is, for example, Shi Xi Chemical crane / polycrystalline; g Xi layer, insulating layer 20, 22 is usually made of silicon nitride. Continuing to refer to FIG. 1, an inner dielectric layer (ILD) is deposited, and a first dielectric layer 30, an etch stop layer 32, and a second dielectric layer 34 are sequentially deposited according to the present invention. According to the method of the present invention, the material of the button stop layer may be nitrogen. Page 7 ~-" V. Description of the invention (5) Nitrogen oxide 1 "Xi ', its thickness is about 100 ~ 2000 Angstroms, for example The material of the dielectric layer and the second dielectric layer is not particularly limited. For example, it is composed of an oxide layer deposited by a chemical vapor deposition method. For example, a dielectric layer: a thickness of R6K angstrom of 〇3-TEOS 'and The second η 闰 is a structure ΛΛί2) formed by stacking & several layers of * PE_TE0S and ⑽-1 ^ 08. In this embodiment, the first dielectric layer and the second dielectric layer 34 depend on Surname engraved Si 第: Figure 2 / A photoresist pattern is used as a mask (not shown) The highest selection ratio at the bottom of the opening until the bottom of all openings, in this implementation, the layer selection and the end of the meal engraving layer gas The etching formula is silicon oxide = 3CH2F2, CA, ⑶ and so on. Therefore, after this step T, the ratio of the residual can reach: ± 0.3K angstrom. The thickness of the residual dielectric layer is only the next sunny. Referring to Fig. 3, "VL Mo engraved 'until the source on the substrate is exposed; draw ::, == the second stage of etch makes it easy to penetrate the remaining moment to terminate'. At this point 'For the rest of the recipe, you can use an etching recipe containing six kinds of gases, such as Ar, which has poor selectivity, such as Ar, pot j 6 2 2, C4F8, CO, 〇2, 2: ι. Wait for the main etch After completion, the first dielectric layer is etched cleaner than the silicon / silicon nitride etch, because the thickness of the dielectric layer under the contact window at this time is only about ± 5. Explanation of the invention (6) 'One ---------- One · 0.3K' only needs to perform overetching of 0.3K. Therefore, compared with the process of the present invention, the time of overetching can be shortened. The original tenth of the original can greatly reduce the damage to the underlying material caused by excessive money engraving, and the performance of the component is affected. Although the present invention has been disclosed as above with a preferred embodiment, the present invention is limited to limit the present invention. Those who do not depart from the spirit and scope of the present invention should be able to make various modifications and retouching. Therefore, the thin scope of the present invention shall be defined as defined in the attached patent application park. The next, the essence of avoiding non-use Guarantee
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