TW396321B - Lower-error fixed-width two's complement parallel multiplier - Google Patents

Abstract

The invention presents a low-error fixed-width two's complement parallel multiplier. Given two n-bit inputs, the fixed-width multiplier generates n-bit(instead of 2n-bit) product error, but uses only about half the area and less the delay of a standard two's complement parallel multiplier. Therefore, the proposed multiplier is useful in fixed-width data path architectures for multimedia and digital signal processing applications in which a unform word width is required.

Description

Λ7 Λ7 經濟部中央橾率局貝工«费合作社印製 五、發明説明（1 > ------ 產業上之應用領域 本發明触-_定寬度二補數平絲法器，它不 5但擁有極低的乘積誤差，而且它只需要標準平行乘法器 的一半面積與運算時間》 創作背景 10 乘法器疋一般多媒體和數位訊號處理晶片中最重要 的運算器之-’因為它主宰這些晶片的速度高低和面積 大小。為了獲得高速度，平行乘法器經常被使用而使得 所需的硬體面積相對增加。然而，在許多多媒體和數位 訊號處理應用中’乘法運算經常出現固定寬度（fixed_ I5 width)的特殊性質。也就是說，他們的輸入資料以及輸 出乘積有相同的η位元寬度⑽width) ^因此，原本2«位 元的乘積就必頦t接或以四捨五入的方法刪除《個最低 位位元（least-significant bits)，而只保留《個最高位位元 (most-significant bits )。例如··在無失真資料壓縮算數編 20 碼（arithmetic coding)晶片的設計中就需要一個八位元的 固定寬度乘法運算，以及小波（Wavelet)轉換晶片中則需 要一個十二位元的固定寬度乘法運算。此外，許多的數 位濾波器亦使用固定寬度之乘法運算。因此’設計一固 定寬度的低乘積誤差平行乘法器以節省大量的晶片面積 3 本纸張欠度逍用中國國家揉率（CNS )八4祕（210X297公釐1 (請先Μ讀背面之注意事項再填寫本頁) Γ訂 A7 ____________B7 五、發明説明.（2 )~~" ~ 及其運算時P枝絕對有必要的。本發明提丨_侧定寬 度二補數平行乘法器，它不但擁有極低的乘積誤差而 且它只需要標準平行乘法器的一半面積與運算時間。 5 乘法器是數位訊號處理系統中一個必要的基本運算 器’因此已有多篇文獻及中華民國專利1〇5918號， 23844〇號’ 247976號等專利公報提出以提高乘法器的 運算速度以及降低硬趙面積。然而，它們都沒有處理數 位訊號處理系統中固定寬度的問題，都不屬於固定寬度 ίο之類的乘法器。 在該等文獻中唯一相關設計為S. S. Kidarabi等 人於 1996 年 BEEE Trails. Circuits itod Systems—Π 第 43 卷第 2 期第 90,94 頁所發表之 Area-Efficient Multipliers for ϋ Signal Processing Applications，其中提出一種固定寬度平行 乘法器；主要特徵為直接捨棄樨準平行乘法器中產生„ 個最低位乘積的加法元件，然後再加上常數1到簡化的 電路中以降低乘積誤差〃此一固定寬度乘法器架構雖然 有簡單、面積小的優點，但是它無法根據輸入做適當的 20誤差修正使得乘積誤差仍然很大。 因此，一種低誤差固定寬度平行乘法器是迫切需要 _4__ 本紙張尺度適扣中困國家標準（CNS ) A4規格（2丨0X297公釐） (請先聞讀背面之注f項再填寫本頁) 訂 9. A7 _______________B7____ 五、發明説明（3 ) 的》又因為數位系統中經常以二補數表示法來表示數字， (請先閱讀背面之注意事項再填寫本頁) 所以本發明提出一稚低誤差固定寬度二補數平行乘法 器。 5 發明之目的 本發明提出一個低誤差（low^error)固定寬度（fixed-width)二補數平行乘法器，其係產生兩個”位元二補數表 示的乘數與被乘數之高《位元乘積，此一乘積等於或極 适似於標準二補數平行乘法器所產生乘積的高也元； 本低誤差固定寬度二補數平行乘法器的實體結構包括： (1) ”位元進位產生電路，其接收輸入兩數之部分乘 積項，且提供適當的進位輸出； (2) /ί位元高位區段乘積產生電路，其接收前迷”位 15 元進位產生電路之進位輸出以及輸入兩數之部分乘 積項’且提供等於或極近似於標準二補數手行乘法 莽所產生的高η位元乘積。 (3) «位元進位產生電路，其係包耠„·2個二輪入〇R 閘和一個二輸入NOR閘。 20 表列說明 表一 Θ之值與其他部分乘積項為；l的機率 表二固定寬度二補數平行乘法器乘積誤差比較結果Λ7 Λ7 Shellfish of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs «Printed by Fei Cooperatives V. Invention Description (1 > ------ Industry Application Fields The present invention touches a fixed-width two-complement flat-wire device, which Not only does 5 have a very low product error, and it only requires half the area and computing time of a standard parallel multiplier. Creative background 10 Multipliers 疋 One of the most important operators in general multimedia and digital signal processing chips-because it dominates The speed and area of these chips. In order to achieve high speed, parallel multipliers are often used to increase the required hardware area. However, in many multimedia and digital signal processing applications, 'multiplication operations often occur in fixed width ( fixed_ I5 width). In other words, their input data and output products have the same η-bit width (width) ^ Therefore, the original 2 «bit product must be connected or deleted by rounding off" Least-significant bits, and only the most-significant bits are reserved. For example, · In the design of distortion-free data compression arithmetic coding of 20-chip (arithmetic coding) chip, an 8-bit fixed-width multiplication operation is required, and in a wavelet (Wavelet) conversion chip, a 12-bit fixed-width is required Multiplication. In addition, many digital filters also use fixed-width multiplication. Therefore, 'design a parallel multiplier with a low product error of a fixed width to save a large amount of chip area. Please fill in this page again) Γ Order A7 ____________B7 V. Description of the invention. (2) ~~ " ~ and P branch is absolutely necessary for its operation. The present invention provides a __ side fixed width two's complement multiplier, which Not only has a very low product error, but it only requires half the area and operation time of a standard parallel multiplier. 5 A multiplier is a necessary basic operator in a digital signal processing system. Therefore, there have been many documents and ROC patents1. Patent publications such as No. 5918, No. 2384440 and No. 247976 propose to increase the operation speed of the multiplier and reduce the area of the hard Zhao. However, they do not deal with the problem of fixed width in the digital signal processing system, and they are not fixed width. The only relevant design in these documents is SS Kidarabi et al., 1996 BEEE Trails. Circuits itod Systems—Vol. 43, No. 2, Issue 90, 94 Page-Area-Efficient Multipliers for ϋ Signal Processing Applications, which proposes a fixed-width parallel multiplier; the main feature is to directly discard the 樨 quasi-parallel multiplier that generates the „lowest-order multiplication product, and then add the constant 1 To a simplified circuit to reduce the product error. Although this fixed-width multiplier architecture has the advantages of simplicity and small area, it cannot make proper 20-error correction based on the input, so the product error is still large. Therefore, a low-error fixed The width multiplier is urgently needed _4__ This paper size is suitable for the National Standard (CNS) A4 specification (2 丨 0X297 mm) (please read the note f on the back before filling this page) Order 9. A7 _______________B7____ V. Description of the invention (3) "Because digital systems often use two's complement representation to represent numbers, (please read the precautions on the back before filling this page), so the present invention proposes a childish low error fixed width two's complement Number of parallel multipliers. 5 Purpose of the invention The present invention proposes a low-error fixed-width dth) Two-complement parallel multiplier, which generates two “bit-wise multiplications of the multiplier represented by the two-complement and the multiplicand.” This product is equal to or very similar to the standard two-complement parallel multiplication. The physical structure of this low error fixed-width two-complement parallel multiplier includes: (1) a bit carry generation circuit that receives a partial product term of the input two numbers and provides appropriate carry Output; (2) / bit high-order segment product generation circuit, which receives the carry output of the first 15-bit carry generation circuit and inputs the partial product term of the two numbers' and provides an equal or close to the standard two's complement number High η-bit product produced by manual multiplication. (3) «Bit carry generation circuit, which includes: ·· 2 two-round R gate and one two-input NOR gate. 20 Tables indicate that the product of the value of Θ in Table 1 and other parts is; the probability table of l Product comparison results of two fixed-width two-complement parallel multipliers

Α7 Β7 圖示說明 五、發明説明（4) 圏一標準6* 6二補數平行乘法器 圖二 6位元乘法器MP， 囷三6位元進饵產生電路 圖四完整的6位元低誤差固定寬度二補數平行乘法 器 圓五η位元進位產生電路 圓六完整的η位元低誤差固定寬度二補數平行乘法器 10 (請先閱讀背面之注意事項再4寫本頁) 15 1··半加器 4-· ·輸入2 7, ·佘加器 1ί) · * LP 電路 圖號說明 2··半加器元件 5 ·.總和 8 ··全加器元件 11.，OR元件 發明之詳細敘述 3 · ·輸入1 6· ·進位 9··輸入3 *νβ Τ 1.二輔數乘法運算之介紹 根據 1973 年 IEEE Trans Computers，第 022 卷第 12 期第1〇45-1〇47頁中，c. R. Baugh等人所發表之 20 二補數平行陣列乘法演算法，若輸入兩個η位元數字方 和r’則標準二補數乘法實行以下的運算以獲得一個 位元乘積Ρ: 本紙張尺度適州中國國家榇準（CNS ) Α4規格（210X297公釐) A7 A7 (1) 22n~2 (3) 10 五、發明説明（5 P=XY = =Wm2㈠·Σ衫，〜艺乃2…〜艺2…⑺Α7 Β7 Graphic illustration V. Description of the invention (4) 标准 A standard 6 * 6 two's complement parallel multiplier Figure 2 6-bit multiplier MP, 囷 3 6-bit bait generation circuit diagram 4 Complete 6-bit low error Fixed-width two-complement parallel multiplier round five η-bit carry generation circuit round six complete η-bit low error fixed-width two-complement parallel multiplier 10 (Please read the precautions on the back before writing this page) 15 1 ·· Half-adder 4- ·· Input 2 7, · 佘 Adder 1ί) · * LP circuit diagram number description 2 ·· Half-adder element 5 ·. Sum 8 ·· Full adder element 11. OR of the invention of the OR element Detailed description 3 · · Input 1 6 · · Carry 9 · · Input 3 * νβ Τ 1. Introduction to the second-complement multiplication operation According to IEEE 1973, Vol. 022, Vol. 12, No. 12, pages 1045-1〇47 In the 20-complement parallel array multiplication algorithm published by c. R. Baugh et al., If two η-bit digital squares and r 'are input, the standard two-complement multiplication performs the following operations to obtain a bit product Ρ: This paper is in Chinese state standard (CNS) Α4 size (210X297 mm) A7 A7 (1) 22n ~ 2 (3) 10 Described invention (5 P = XY = = Wm2㈠ · Σ shirt, is the Yi ~ Yi ~ ... 2 ... 2 ⑺

㈣ ㈣ i=0 U 其中々’ h和&代表X，r和P的第i個位元。減一 個以二補數表示的數就孝於加上這個數的一補數再加丄， 因此（2)式中的第三項可以重寫為： -^-11^2^=-1^.^2^=(1-0)22^ +Σ〇-W,)2"*，+, +2-1 Σ(ζ^)2"~,+#+2Λ 類似（3)式’（2)式中的第四項可以重寫為 w = 2'|^)严+2“ (4) 將⑶式和⑷式代入(2)式中，乘積^的計算變為如下 (5) ρ:22〜㈣2〜 根據(5)式-個6*6二補數平行乘法器架構^圓一中畫 出又赛積Ρ可以表示為兩個區段的和，即高位區段邮 和低位區段π的和：〜研咖玄 /=« /=〇 i ⑹ 我們稱標準祕器巾產生低位區段〖p的電路為電路^。 圖一的陰影部份中的電路即為電路 LP。 2〇 2 ·低誤差©定寬度二槪平行乘法器 尺/1 則’關家辟^^\4祕（ (請先閲讀背面之注意事項再填寫本頁)㈣ ㈣ i = 0 U where 々 ′ h and & represent the i-th bit of X, r and P. Subtracting a number represented by two's complement is filial to adding the one's complement of this number and then adding 丄, so the third term in (2) can be rewritten as:-^-11 ^ 2 ^ =-1 ^ . ^ 2 ^ = (1-0) 22 ^ + Σ〇-W,) 2 " *, +, + 2-1 Σ (ζ ^) 2 " ~, + # + 2Λ is similar to the formula (3) '(2 The fourth term in) can be rewritten as w = 2 '| ^) strict +2 "(4) Substituting ⑶ and ⑷ into (2), the calculation of the product ^ becomes as follows (5) ρ: 22 ~ ㈣2 ~ According to formula (5)-a 6 * 6 two's complement parallel multiplier architecture ^ The circled product P drawn in circle one can be expressed as the sum of two sections, namely the high section post and the low section Sum of π: ~ Kan Ka Hyun / = «/ = 〇i ⑹ We call the circuit of the low-key section [p] that is produced by a standard secret towel as a circuit ^. The circuit in the shaded part of Figure 1 is the circuit LP. 2〇 2 · Low error © fixed width two parallel multiplier ruler / 1 rule 'guanjiapi ^^ \ 4 secret ((Please read the precautions on the back before filling in this page)

、1T %/—· 經濟部中央秫準而妁工消赍合作ij卬紫 A7 B7 五、發明説明（6 ) 最簡單的固定寬度二補數平行乘法器可以藉由直接刪 除標準二補數平行乘法器中的電路同時將剩餘電路 中的每個進位輸入飯給〇而得。這種固定寬度乘法器我 5們稱之為乘法器尬>，，一個6位元乘法器卿，的架構如 圓二所示。然而乘法器，所產生的乘積將與標準二補 數平行乘法器所產生的乘積之高位區段MP之間有可觀的 誤差。 10 15 經澉部中央榀苹^:::::工消费合作^卬製 20 為了降低固定寬度乘法器的乘積释差，本發明提出一 個非常簡潔的進位產生電路（ circuit» Cg)， 它能供給乘法器MP，適當的進位輸入使得乘積誤差降至 最低》事實上* Cg郎是要取代標準乘法器中的以電路β 因此，Cg所要產生的輸出即為電路ζρ所產生的進位輸 出。我們以6位元诨定寬度乘法器為例子說明Cg的設 計原貍和架構。令外，力代表LP電路中第i行第j列加 法元件所產生的進位輸出，α代表電路ip所產生的進位 輪出之和，即冷，»。則由圈__和⑸式分析可得〇;Sc^5 且or xsy〇 + x4yi +x3y2+ x2y3 + + + £c(/, ή /+/=5 > \{x5y〇+x^yi + x3y：+xiy3 + ^y4 + ^7ys) 本紙張尺度通用中囷國家標準（CNS > A4規格（2丨0x297公嫠） --------ΗΉ-- -. -.·.. (請先閲讀背面之注意事項再填寫本頁)、 1T% / — · The central ministry of the Ministry of Economic Affairs and the Ministry of Economic Cooperation and Cooperation ij 卬 Purple A7 B7 V. Description of the invention (6) The simplest fixed-width two's complement parallel multiplier can be deleted by directly deleting the standard two's complement parallel The circuit in the multiplier simultaneously inputs each carry in the remaining circuit to 0. This kind of fixed-width multiplier is called a multiplier, and the structure of a 6-bit multiplier is shown in circle 2. However, the multiplier produces a considerable error between the high-order section MP of the product produced by the standard two-complement parallel multiplier. 10 15 Central Ministry of Economic Affairs ^ ::::: Industrial-consumer cooperation ^ system 20 In order to reduce the product release difference of fixed-width multipliers, the present invention proposes a very simple carry generation circuit (circuit »Cg), which can Supply the multiplier MP with the appropriate carry input to minimize the product error. "In fact * Cg Lang is to replace the circuit β in the standard multiplier. Therefore, the output produced by Cg is the carry output produced by the circuit ζρ. We take a 6-bit fixed-width multiplier as an example to illustrate the design of the original raccoon and architecture of Cg. In addition, the force represents the carry output generated by the i-th row and j-th column of the LP circuit, and α represents the sum of the carry rounds generated by the circuit ip, that is, cold, ». Then by circle __ and 分析 analysis, we can get 〇; Sc ^ 5 and or xsy〇 + x4yi + x3y2 + x2y3 + + + £ c (/, valent / + / = 5 > \ {x5y〇 + x ^ yi + x3y: + xiy3 + ^ y4 + ^ 7ys) This paper has a common Chinese national standard (CNS > A4 specification (2 丨 0x297 male)) -------- ΗΉ---. -.... (Please read the notes on the back before filling this page)

、1T A7 ——---------B7____ 五、發明説明（7 ] ' + +xsyj +^2 +xjy3 +^)+^(^〇 +x2yi +x〇ys).1 / . 1 . 、 ⑺ 16 (xiy〇+^iyi + W2)+~(xi^〇 +x〇^i) 於此b」表不大於x之表大整數p 由⑺式可知α之值受、jc山和 這六個部分乘積項的影響最大《而且 •^5=1-％少5 ’因此我們稱jc5y0、〜乃、j^y2、七少3、巧义 和這六項為主要進位輸入項。接下來，只要找出《與 妾要進位輸入項之間的W係，命即可獲得。為了找 10與這六項之間的關係，（7)式被重新表示為\xsy〇 +\x^yj +\x3y2 +\Xiy4 +\x〇ys +>^其中 Ay =;^少〇+，··+▲_。又： \^^(i-x5y〇h-^y^P〇 5 ^ +|f^I〇 (9) (8) 其中=1 15 經M·部中央標準而只工消费合作ii卬絮 2 2 =*仍+沁，其中馬: if x4yi = 0 0.5, \ΐχ3γ2=\ 〇, ifx3y2 = 〇 〇, ifx2y3-〇 0.5，if父山=1 0, ifxJy4=〇 (10) (11) (12) (13) ^%v7=^{i-^)=-W5+^ * ifx〇^0 (14> 9 本紙張尺度適用中國國家橾準（CNS > A4規格（21〇X297公釐） (請先閲讀背面之注意事項再填寫本頁)、 1T A7 ------------- B7____ V. Description of the invention (7) '+ + xsyj + ^ 2 + xjy3 + ^) + ^ (^ 〇 + x2yi + x〇ys). 1 /. 1. ⑺ ⑺ 16 (xiy〇 + ^ iyi + W2) + ~ (xi ^ 〇 + x〇 ^ i) Here b "is a large integer p not greater than x. From the formula, we can know that the value of α is And these six partial product terms have the greatest effect, and • ^ 5 = 1-% less 5 'so we call jc5y0, ~ Nai, j ^ y2, Qishao3, Qiaoyi and these six terms as the main carry inputs. Next, as long as you find the W system between 与 and 输入 to carry the input, fate can be obtained. In order to find the relationship between 10 and these six terms, formula (7) is re-expressed as \ xsy〇 + \ x ^ yj + \ x3y2 + \ Xiy4 + \ x〇ys + > ^ where Ay =; ^ less. +, ·· + ▲ _. Also: \ ^^ (i-x5y〇h- ^ y ^ P〇5 ^ + | f ^ I〇 (9) (8) where = 1 15 only works in accordance with the central standard of the Ministry of Work and Consumer Cooperation ii. 2 2 = * still + Qin, where horse: if x4yi = 0 0.5, \ ΐχ3γ2 = \ 〇, ifx3y2 = 〇〇, ifx2y3-〇0.5, if father mountain = 1 0, ifxJy4 = 〇 (10) (11) (12) ) (13) ^% v7 = ^ {i-^) =-W5 + ^ * ifx〇 ^ 0 (14 > 9 This paper size applies to China National Standards (CNS > A4 size (21〇X297mm) (Please (Read the notes on the back before filling out this page)

A7 A7 5 10 20 五、發明説明（8 ; 由（9)式〜（Ί4)式，（8)式可改寫為如下（15)式 卿々，，爲+ /?/+心 =L(咖糾州♦/?」=(，+奶，+他)制 其中户-⑽-⑽+鳥+岛+馬+馬+馬+办+外。 (15)式的户中仍有爲這一項與主要進位輸入項之間的關係尚 不明確。為了解決此問題，我們定義一個數〆 ^ = x5y〇++ x$yi+ x2y3+ xiy^+x〇ys 〇6) 0代表主要進位輸入項中等於1的項的數目。表一列出0 之值與其他部分乘積項為1的機率。例如：若0=2表示 這六項中有兩項為1其他四項為〇。因此；c5~々以及心〜八 這十二個輸入位元中最多有8個為1、最少有4個為1 , 所以每一個位元為1的機率為ί^±£1Η1=〇. 5，所以其他 2 部分乘積項為1的機率為0 3*0.5=0.25。 15 由表一和（9)式〜（14)式即可推得#與主要進位輸 入項之間的關係》根據實際分析，我們獲得α下重要結 論：當θ=0 *則1<々<2 ;當0>〇，則(^户<1。板據此一 結論，當θ=〇時|/」=1，當0>〇時[^1=0。因此 α * j (^7 + ^2+^5+^) + 1, if^ = 0 (17) 1 X4yi+x3y2+x2y3+x}y4, if 0 > ο 根據（17)式，我們設計一個6位元進位產生電路印如囷 三所示。 _10___ (請.先閲讀背面之注$項再填寫本頁)A7 A7 5 10 20 V. Description of the invention (8; From (9) to (Ί4), (8) can be rewritten as the following (15), which is + /? / + 心 = L (Coffee Jiaozhou ♦ /? ”= (, + Milk, + other) system in which households -⑽-⑽ + birds + islands + horses + horses + horses + horses + office + outside. (15) type of households still have this item The relationship with the main carry input is not clear. To solve this problem, we define a number 〆 ^ = x5y〇 ++ x $ yi + x2y3 + xiy ^ + x〇ys 〇6) 0 means equal to the main carry input The number of items in Table 1. Table 1 lists the probability that the value of 0 and the product of other parts are 1. For example: if 0 = 2, two of the six items are 1 and the other four are 0. Therefore; c5 ~ 々 And there are at most 8 of the twelve input bits of heart to eight as 1, and at least 4 as 1, so the probability of each bit being 1 is ί ± £ 1Η1 = 0.5, so the other 2 parts The probability that the product term is 1 is 0 3 * 0.5 = 0.25. 15 The relationship between # and the main carry input term can be deduced from Tables 1 and (9) ~ (14). According to the actual analysis, we obtain α An important conclusion: when θ = 0 * then 1 < 々 <2; when 0 > 〇, then (^ 户 < 1 According to this conclusion, when θ = 〇 | / ″ = 1, when 0 > 〇 [^ 1 = 0. Therefore α * j (^ 7 + ^ 2 + ^ 5 + ^) + 1, if ^ = 0 (17) 1 X4yi + x3y2 + x2y3 + x} y4, if 0 > ο According to formula (17), we design a 6-bit carry generation circuit as shown in Figure 3. _10___ (Please read the back page first (Note $ items and then fill out this page)

表紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 10 經濟部中央榀皁而h工消费合作妇印絮 A7 __ B7 五、發明説明（9 ) 本電路的輸入是所有的主要進位輸入項，輸出則非常 近似於電路LP的進位輸出。然而，6位元Cg中只包含 四個二輸入OR閛和一個二輸入NOR閘，電路非常簡單。 5然後，以Cgr取代標準二補數平行乘法器中的電路lp即 可獲得一個低面積、低誤差的固定寬度二補數平行乘法 器。一個完整的6位元低面積、低誤差固定寬度二補數 平行乘法器如圓四所示。 以上的結果可以直接應用於設計Γ]位元進位產生電 路Cg以及η位元低面積、低誤差固定寬度二補數平行 乘法器。亦即（17)式可以表示為如下的一般表示式： Σ xiys +h 其中 θ = (18) 本發明提出的n位元進位產生電路Cgr架構如圈五 所示’它包含11-2個二輸入0R閘和一個二輸入NOR閉。 一個完整的II位元低面積、低誤差固定寬度二補數平行 乘法器則如圖六所示。 3·實驗結果說明 為了驗證我們提出的固定寬度二補數平行乘法器是否 真的俱低乘積誤差’我們與乘法器MP，以及S. s. 本紙張尺度適削，囡國家樣率（CNS)八4胁（21〇χ2^釐 (請先閱讀背面之注意事項再填寫本頁)The paper size of the table applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). 10 Central Ministry of Economic Affairs and Consumer Cooperation Co., Ltd. Printing A7 __ B7 V. Description of the invention (9) The input of this circuit is all the major carry The input and output are very similar to the carry output of the circuit LP. However, the 6-bit Cg contains only four two-input OR 閛 and one two-input NOR gate, and the circuit is very simple. 5 Then, replace the circuit lp in the standard two-complement parallel multiplier with Cgr to obtain a low-area, low-error fixed-width two-complement parallel multiplier. A complete 6-bit low-area, low-error fixed-width two's complement parallel multiplier is shown in circle four. The above results can be directly applied to the design of Γ] bit carry circuit Cg and η bit low area, low error fixed width two's complement parallel multiplier. That is, formula (17) can be expressed as the following general expression: Σ xiys + h where θ = (18) The n-bit carry generation circuit Cgr structure proposed by the present invention is shown in circle five. It contains 11-2 two Input 0R gate and a two-input NOR block. A complete II-bit low-area, low-error fixed-width two-complement parallel multiplier is shown in Figure 6. 3. The experimental results show that in order to verify whether our proposed fixed-width two's-complement parallel multiplier is really low in product error, 'we and the multiplier MP, and S. s. This paper scales properly, and the national sample rate (CNS) Eight 4 threats (21〇χ2 ^ cent (please read the precautions on the back before filling in this page)

if 0=0 if0>〇 ά Σ xfyj> ij承 ήΑ 15 20 A7 ________B7 五、發明説明（i〇)if 0 = 0 if0 > 〇 ά Σ xfyj > ij bearing price 15 20 A7 ________B7 5. Description of the invention (i〇)

Kidambi等人提出的固定寬度二補數平行乘法器馮做 比較’此較結果表示在表二中。在表二中，n代表固定 寬度乘法器的位元數。令£代表標準乘法器所產生的乘積 5之高位區段尬3以及固定寬度乘法器所產生的乘積之差的 絕對值’則表二中的％和5分別代表對所有的輸入組合 所產生的全部s之最大值以及平均值。比較結果顧示本發 明所提出的固定寬度二補數平行乘法器確實擁有低乘積 誤差的特性。 10 特點及功效 經^部中央樣4'-^=;:1.消处合作妇印製 ----------- * (請先閲讀背面之注$項再填寫本筲) 本發明提出一個低誤差（low^error)固定寬度（fixed· width)二補數平行乘法器輸入兩個η位元的輸入到此 乘法器中，它將產生一個n位元（不是2η位元)低誤 15差乘積。未發明所提出的低誤差固定寬度二補數平行乘 法器特點在於其使用一個電路結構極為簡單，但是卻能 根據不同的輸入產生適當進位輸出的進位產生電路，使 得乘法器的面積大為減少卻仍然擁有極低的乘積誤差。 因此’它非常適合用在單一字元寬度的多媒競和數位訊 2〇號處理晶片中。更重要的是，它的面積與計算延遲大約 是標準二補數平行乘法器面積的一半。因此，在單一字 元寬度（Uniform word width)的多媒體和數位訊號處理的 _____12-__ 本紙張尺度適州中國國家標準（CNS ) A4規格（210X297公釐〉 A7 B7 五、發明説明（ii) 相關應用中，採用此低誤差固定寬度二補數平行乘法器 將可大大地降低所需要的硬體面積及其運算時間而不影 響輸出品質。 to 15 (請先閱讀背面之注意事項再填寫本買·) 20 25 30 35 40 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 訂 396321 A7 B7 五、發明説明（12 )表一 θ 0 1 2 3 4 5 6 其他部分乘 積項為1的 機率 0.0625 0.1406. 0.2500 0.3906 0.5625 0.7656 1.0000 (請先閲讀背面之注意事項再填寫本頁.) 表二 經濟部中央標芈局負工消費合作社印策 乘法器 誤差 η=4 η- 8 η= 12 η- 16 ~MP· 48 1792 45056 983040 Ml εΜ 32 1536 40960 917504 本發明 乘法器 16 512 8192 196608 MP· 13.75 450.75 11267.75 245764.7 Ml 7 5.375 222.57 7258.26 180474.5 本發明 乘法器 0.938 65.04 1570.32 30403.7 14 本紙張尺度適用中國國家榇準（CNS) A4規格（2丨0X297公釐）The fixed-width two's-complement parallel multiplier proposed by Kidambi et al. Was compared. The comparison results are shown in Table 2. In Table 2, n represents the number of bits in the fixed-width multiplier. Let £ represent the absolute value of the difference between the high-order section of the product 5 produced by the standard multiplier 3 and the product produced by the fixed-width multiplier '. Then the% and 5 in Table 2 represent the results for all input combinations. The maximum value and average value of all s. The comparison results show that the fixed-width two's-complement parallel multiplier proposed by the present invention does have the characteristic of low product error. 10 Features and Functions 4 '-^ = ;: 1. Printed by Consumer Cooperative Women ----------- * (please read the note $ on the back before filling in this card) The invention proposes a low ^ error fixed-width two-complement parallel multiplier that inputs two η-bit inputs into this multiplier, which will generate an n-bit (not 2η-bit) ) Low error 15 difference product. The low error fixed width two-complement parallel multiplier proposed by the invention is characterized in that it uses a circuit structure that is very simple, but it can generate a carry output circuit that appropriately carries output according to different inputs, which greatly reduces the area of the multiplier. Still has extremely low product errors. So it ’s very suitable for single character width multimedia and digital signal processing chip 20. More importantly, its area and calculation delay are about half that of a standard two's complement parallel multiplier. Therefore, _____ 12 -__ This paper size is suitable for China National Standard (CNS) A4 specification (210X297 mm> A7 B7) in a single word width (Uniform word width). In related applications, the use of this low-error fixed-width two's-complement parallel multiplier can greatly reduce the required hardware area and its operation time without affecting the output quality. To 15 Buy ·) 20 25 30 35 40 13 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) Order 396321 A7 B7 V. Description of the invention (12) Table 1 θ 0 1 2 3 4 5 6 Product of other parts The probability that the term is 1 is 0.0625 0.1406. 0.2500 0.3906 0.5625 0.7656 1.0000 (Please read the notes on the back before filling this page.) η = 12 η- 16 ~ MP48 1792 45056 983040 Ml εM 32 1536 40960 917504 Multiplier 16 512 8192 196608 MP13.75 450.75 11267.75 245764.7 Ml 7 5.375 222.57 7258.26 180 474.5 Multiplier of the present invention 0.938 65.04 1570.32 30403.7 14 This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297 mm)

Claims (1)

396321 b88 C8 —~ ------D8___. 六、申請專利範圍 1. 一種低誤差固定寬度二補數平行乘法器，其主要 ，生兩個η位元工補數表不的来數與被乘數之 尚η位元乘積，此一乘積等於或極近似於標準 二補數平行乘法器所產生乘積的高η位元；本 低誤差固定寬度二補數平行乘法器的實體結構包 括- a) η位元進位產生電路，其接收輸入兩數之部分 乘積項，且提供適常的進位輸出； b) II位元高位區段乘積產生電路，其接收前述乃 位元進位產生電路芩進位輸出以及輪入兩數之部 分乘積項’且提梃拿於或極近似於標準二補數平 行乘法器所產生的高21位元乘積。 2. 根據申請專利範圍第1項所述之η位元進位產 生電路’包括ίΐ-2個二輸入or閘和一個二輪入 NOR 閘。396321 b88 C8 — ~ ------ D8___. 6. Scope of patent application 1. A low-error fixed-width two's complement parallel multiplier, which mainly produces two η-bit labor complements. The n-bit product of the multiplicand, this product is equal to or very close to the high η-bit of the product produced by the standard two's complement parallel multiplier; the entity structure of this low error fixed-width two's complement parallel multiplier includes − a) η-bit carry generation circuit, which receives a partial product term of the input two digits, and provides a normal carry output; b) II-bit high-bit segment product generation circuit, which receives the aforementioned bit carry generation circuit 芩 carry The output and the rounded partial product term of the two numbers' are taken or closely approximated by the high 21-bit product produced by the standard two's complement parallel multiplier. 2. According to the n-bit carry generation circuit described in item 1 of the scope of the patent application, it includes ΐ2 two-input or gates and one two-wheel-in NOR gate.