經濟部中央標準局員工消費合作社印製 1615twf.DOC/002 A 7 B7 五、發明説明（I ) 本發明是有關於一種積體電路元件隔離結構之製造 方法，且特別是有關於一種淺溝渠隔離結構（shallow trench isolation, STI)之製造方法。 元件隔離區係用以防止載子（caririer)通過基底而 在相鄰之元件間移動，傳統上，元件隔離區形成於稠密的 半導體電路比如是動態隨機存取記憶體（DRAMs)中相鄰的 場效電晶體（field effect transistor, FET)間，藉以 減少由場效電晶體產生的電荷遺漏（charge leakage)。 元件隔離區時常以厚場氧化層的形式延伸，而在半導體基 底表面下P成，其中最傳統且普遍的技術爲矽局部氧化技 術（LOCOS)。由於LOCOS技術之日趨成熟，因此可藉此技 術，以較低的成本獲得信賴度高且有效之元件隔離結構， 然而LOCOS仍具有多項缺點，包括已知應力產生之相關問 題與LOCOS場隔離結構周圍鳥嘴區（bird’s beak)之形成 等。而特別是鳥嘴區所造成的問題，使得在小型的元件上， LOCOS場隔離結構不能做有效地隔離，而必須以高密度 (high density)元件取代。 習知淺溝渠隔離（shallow trench isolation, STI) 亦是一種普遍的元件隔離方法，一般使用氮化矽作爲硬罩 幕’以非等向性（anisotropic)蝕刻法在半導體基底上定 義陡峭的溝渠。之後再將溝渠塡滿氧化物層，而提供做爲 元件隔離結構，且此結構具有與原基底表面等高之上表 面。第1圖係顯示一種淺溝渠隔離結構，其中元件形成於p 型的砂基底10之上，且淺溝渠隔離結構12以蝕刻法在基 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背釕之注意事項^资寫本頁) -裝· 一5 丨-線 1615twf.DOC/002 A7 B7 五、發明説明（2 ) 底形成淺溝渠，再由化學氣相沈積法（CVD)在溝渠中塡滿 氧化物。並在STI結構周圍形成FET元件14、16，其中包 括基底通道區周圍之N型源極/汲極區（source/drain)， 以及以閘氧化層與通道區分離之閘電極。STI結構之厚度可 提供有效的隔離效果且可應用在較小的元件上，於此，STI 結構則不同於LOCOS隔離區，因後者會在LOCOS隔離區之 周圍形成鳥嘴結構，且不能提供有效的隔離作用。另外， STI結構的形成技術可以在隔離結構上產生堅固且平坦的 表面。習知一種淺溝渠隔離結構12之製造方法詳述在第2 圖至第12圖。 第2圖係顯示在記憶電路中，習知一種淺溝渠隔離區 之傳統技術的初步形成步驟。在此製程中，在矽基底1〇上 形成氧化層22 ’其中此氧化層22作爲墊氧化層（pad oxide)，並用於保護基底的表面，而於最後閘極氧化層形 成之前移去。之後以化學氣相沈積法（CVD)形成氮化矽層 24，接著形成光阻層，並定義此光阻層，以在氮化矽層24 的表面形成一植入罩幕層26，用以將離子植入基底，以形 成如隔離井之隔離元件，使其具p/n連接電性。接著請參 照第3圖，移去此植入罩幕26，然後，在氮化矽層24上^ 積罩幕28用以定義溝渠，接著經微影蝕刻製程而形成罩幕 28，再依序蝕刻氮化矽層24、墊氧化層22、及矽基底⑺ 內之溝渠3G (如第4圖），完成在基底上形成—溝渠後， 再移除触刻罩幕2 8。 然後，將溝渠30塡滿矽氧化物層32，例如，以矽酸四Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 1615twf.DOC / 002 A 7 B7 V. Description of the Invention (I) The present invention relates to a method for manufacturing an integrated circuit element isolation structure, and more particularly to a shallow trench isolation Structure (shallow trench isolation, STI) manufacturing method. The device isolation area is used to prevent carriers from moving between adjacent components through the substrate. Traditionally, the device isolation area is formed in dense semiconductor circuits such as adjacent ones in dynamic random access memories (DRAMs). Field effect transistors (FETs) are used to reduce charge leakage generated by the field effect transistors. The element isolation region often extends in the form of a thick field oxide layer, and is formed under the surface of the semiconductor substrate. The most traditional and common technology is the silicon local oxidation technology (LOCOS). As LOCOS technology becomes more mature, it can be used to obtain a reliable and effective component isolation structure at a lower cost. However, LOCOS still has a number of disadvantages, including problems related to known stress generation and the surrounding area of the LOCOS field isolation structure. Formation of bird's beak and so on. In particular, the problems caused by the bird's beak area make the LOCOS field isolation structure cannot be effectively isolated on small components, and must be replaced with high density components. Conventional shallow trench isolation (STI) is also a common method of device isolation. Generally, silicon nitride is used as a hard mask. An anisotropic etching method is used to define a steep trench on a semiconductor substrate. The trench is then filled with an oxide layer and provided as an element isolation structure, and this structure has a surface above the original substrate surface. Figure 1 shows a shallow trench isolation structure in which the elements are formed on a p-type sand substrate 10, and the shallow trench isolation structure 12 is etched on the base 3 paper standards in accordance with Chinese National Standard (CNS) A4 specifications (210X 297 mm) (Please read the precautions for backing ruthenium first to write this page)-Installation · 5 · 丨-Line 1615twf.DOC / 002 A7 B7 5. Description of the invention (2) A shallow trench is formed at the bottom, and then chemical gas is used. Phase deposition (CVD) is used to fill the trench with oxide. FET elements 14, 16 are formed around the STI structure, which include an N-type source / drain region around the substrate channel region, and a gate electrode separated from the channel region by a gate oxide layer. The thickness of the STI structure can provide effective isolation and can be applied to smaller components. Here, the STI structure is different from the LOCOS isolation region because the latter will form a bird's beak structure around the LOCOS isolation region and cannot provide effective Isolation. In addition, the STI structure formation technology can produce a strong and flat surface on the isolation structure. A conventional manufacturing method of a shallow trench isolation structure 12 is detailed in FIGS. 2 to 12. Fig. 2 shows the preliminary forming steps of a conventional technique in which a shallow trench isolation region is known in a memory circuit. In this process, an oxide layer 22 'is formed on the silicon substrate 10. The oxide layer 22 serves as a pad oxide and is used to protect the surface of the substrate, and is removed before the final gate oxide layer is formed. Then, a silicon nitride layer 24 is formed by a chemical vapor deposition (CVD) method, and then a photoresist layer is formed, and the photoresist layer is defined to form an implant mask layer 26 on the surface of the silicon nitride layer 24 for Ions are implanted into the substrate to form an isolation element such as an isolation well, so that it has p / n connection electrical properties. Referring to FIG. 3, the implant mask 26 is removed. Then, a mask 28 is formed on the silicon nitride layer 24 to define a trench, and then the mask 28 is formed by a lithography etching process, and then sequentially The silicon nitride layer 24, the pad oxide layer 22, and the trench 3G in the silicon substrate 蚀刻 are etched (as shown in FIG. 4). After the trench is formed on the substrate, the etch mask 28 is removed. Then, the trench 30 is filled with a silicon oxide layer 32, for example,
A 4規格 4A 4 size 4
經濟部中央標準局員工消費合作社印製 1615twf.DOC/002 ^7 _B7 五、發明説明（彡） 乙酯（tetra-ethyl-ortho-si licate, TEOS)爲氣源，例 如使用常壓化學氣相沈積法（atmospheric pressure chemical vapor deposition, APCVD)沈積，並使 TEOS 溢 出溝渠，如第5圖所示。因TEOS氧化層需經密實化 (dens i f i cat i on )步驟，比如在溫度1000°C下，進行時間 約10~30分鐘，而經密實化後，TEOS會產生收縮。在密實 化之後，則以化學機械硏磨法（chemical mechanical polishing, CMP)去除氮化矽層24上之TEOS氧化層，而 以TEOS氧化層爲硏磨終點，留下溝渠區中的氧化插塞34 (第6圖）。不同於第6圖所示，化學機械硏磨法進行時， 由於氧化插塞（oxide plug)較氮化砂層爲軟，因此氮化 矽表面下之氧化插塞34會有輕微的凹入現象。接著再移去 氮化矽層24,留下於墊氧化物層22表面高度上之氧化插塞 .34 (第7圖）。隨後以氫氟酸（HF)浸蝕移除墊氧化物層 22 (第8圖），由於TEOS氧化插塞的蝕刻速率較熱氧化之 墊氧化物層快速許多，而造成移去氧化插塞時，氧化插塞 34移除掉的厚度較墊氧化層22移除掉的爲厚，而使TEOS 氧化插塞34可拓展至基底表面上（第8圖）。 在基底10表面形成一層犧牲氧化層36,以做爲保護基 底表面免於遭受損壞。根據元件的需要進行一或更多的植 入法’包括一或更多的通道臨限（channel threshold)調 整植入法（第9圖）。之後，再次使用氫氟酸移除此犧牲 氧化物層36，而其所形成結構如第1〇圖所示。接著，如第 8圖及第1〇圖所示，氧化物層蝕刻步驟的進行常常引起氧 5 本紙張尺度適用中國國家標準（CMS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項罗4寫本頁) 'τ 1615twf.D〇C/002 A7 1615twf.D〇C/002 A7 經濟部中央標準局員工消費合作社印製 五、發明説明（>) 化插塞的過度融刻（over etching)，而使氧化物插塞34 表面凹入而低於基底10的表面。過度触刻通常會發生在氧 化插塞34鄰接著基底10表面的邊緣處，或是氧化插塞表 面會有低於基底表面的凹入現象。另外，過度蝕刻也可能 導致基底的“肩狀物” （shoulder)部份的暴露，及溝槽 側牆的部份蝕刻，或是一薄層的TE0S氧化物覆蓋在鄰接溝 槽側牆之基底上方。 請參照第11圖，利用熱氧化法，在基底10的表面形 成閘極氧化層40,接著，閘極氧化層40通常會在靠近溝渠 隔離區之基底的肩狀物區38形成一突出的邊緣輪廓。一般 而言，以化學氣相沈積法在基底的表面沈積多晶砂層42， 而多晶砂層42以離子植入（ion implantat ion )法植入摻 質，並經回火（annealing)製程，續以微影形成連接線44 (wi r ing 1 ine )，如第12圖所示。由於連接線44延伸於 閘極氧化層40及氧化插塞34上，而此氧化插塞34亦延伸 至近溝渠側邊之基底的肩狀物區38，因此，在肩狀物區38 所形成品質不良的閘極氧化層40，將會減低電晶體通道開 啓（turn-on)的臨限電壓（threshold voltage)而引起 頸結效應中不正常的次臨限電流（subthreshold current ) ° 有鑑於此，本發明的目的之一，就是在提供一種淺溝 渠隔離結構以作爲元件隔離之用，並增進與淺溝渠隔離結 構相鄰元件之可信賴度。 爲達上述之目的，本發明提供一種淺溝渠隔離結構之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背_面之注意事填寫本頁) 、-° !615twf.DOC/002 A7 B7 — -^ __〜 五、發明説明（义） (請先聞讀背面之注意事項寫本頁) 製造方法，本發明的第一部份其製造方法如下：在一基底 鈾刻一溝渠，與此溝渠相鄰處之部份此基底有一第一導電 性型.·.； 一摻雜介電材料層覆蓋溝渠’此摻雜介電材料層摻 雜複數個第一摻質；這些第一摻質從此摻雜介電材料擴散 到基底內部，在此沿著此溝渠的內壁形成一自行對準隔離 摻雜區，此隔離摻雜區和此溝渠形成一積體電路元件隔離 結構。 經濟部中央標準局員工消費合作社印製 本發明提供一種淺溝渠隔離結構之製造方法，本發明 的第二部份其製造方法如下：提供一基底’此基底至少有 一表面摻雜而且有一第一導電性型；在此基底上形成一定 義溝渠的罩幕；蝕穿此定義溝渠的罩幕蝕刻基底’在此基 底形成一溝_;提供一第一介電層’此桌一介電層摻雜複 數個第一摻質，此第一介電層位於此基底上方之溝渠內； 提供一第二介電層於此基底上方，在一預定的再熱流溫度 下此第二介電層的熱流速大於該第一介電層；加熱這些第 一和第二介電層至一再熱流溫度，此第一介電層的摻質從 此第一介電層擴散入此基底，且穿越此溝渠的內壁，沿著 溝渠的這些內壁形成複數個自行對準隔離摻雜區，其中這 些隔離摻雜區和此溝渠兩者均提供做爲積體電路兀件之元 件隔離結構。 爲讓本發明之上述和其他目的、特徵'和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1615twf.DOC/002 A7 B7 五、發明説明（) 第1圖係顯示一種積體電路元件中之_一淺溝渠隔離結 構。， 第2圖至第12圖係顯示習知技藝中一種.淺溝渠塥灕結 構之製造方法。 第13圖至第18圖係顯示裉據本發明較佳實施例之一 種淺溝渠隔離結構之製造方法。 實施例 本發明一較佳實施例，形成一淺溝渠隔離結構，在此 溝渠的內部表面上方沈積絕緣層，並將此絕緣層內的摻質 擴散到淺溝渠的內部表面。較佳的是，此摻雜的絕緣材料 爲氧化層且與此基底表面摻雜的導電性型相同。因此，對 一 P型矽基底而言，可以利用化學氣相沈積（chamical vapor deposition, CVD)法沈積硼砂玻璃（boron s i 1 i cate glass, BSG)形成一適當的絕緣層。提供一較佳摻雜的絕 緣材料於溝渠的內部表面上並部份塡滿此溝渠。另外，未 摻雜的絕緣材料接著沈積，並完全塡滿且過度塡滿此溝 渠。然後利用一高溫再熱流製程，將此較佳摻雜玻璃內的 摻質擴散到基底，並形成場摻雜或隔離摻雜。以此再熱流 製程完成摻雜玻璃的再熱流及密實化（densification)， 以及摻質從玻璃透過此溝渠的內部表面擴散入基底。較佳 的是，此摻雜的玻璃留在完成的淺溝渠隔離結構內。本發 明的本較佳實施例部份，在此溝渠整個內部表面提供場摻 質（f i e 1 d dopan t )，以形成自行對準此溝渠的隔離摻雜。 此溝渠之摻雜的內壁之形成亦提供此淺溝渠隔離結構一相 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1615twf.DOC/002 Μ Β7 五、發明説明（q ) 鄰的表面，此表面適合進一步的元件製程。尤其，在隨後 的製程期間，此溝渠的上邊緣將較不易被曝露，且與此溝 渠的上邊緣相鄰的此基底表面將較不易形成寄生MOSFET結 構。 第13圖所示，爲根據本發明一較佳實施例之一種淺溝 渠隔離結構的製造方法。首先，矽基底100具有一 P型背 景摻雜或摻雜P型的表面層。在此矽基底的表面形成墊氧 化層102,此墊氧化層102是做爲保護此基底免於遭受後續 製程的破壞。此墊氧化層102的形成，比如利用熱氧化法， 其厚度約爲.50〜500A。接著，在墊氧化層102上沈積罩幕 層104。此罩幕層104具有二項重要的功能，第一，作爲硏 磨終止層，使化學機械硏磨（chemical mechanical polishing, CMP)步驟完成定義淺溝渠內之絕緣插塞的形 成；第二，可以作爲定義溝渠的罩幕（trench definition mask)，利用對矽基底的非等向性蝕刻來定義此溝渠。然 而，此罩幕層104常只作爲硏磨終止層。由於上述兩個目 的，利用CVD沈積一厚度約爲800〜2000A的罩幕層104比 如氮化矽。 然後，在此罩幕層104上提供一光阻（photoresist) 層，而且用微影（photolithography)製程定義溝渠圖案。 此光阻層經過曝光後，形成罩幕106，如第13圖所示。隨 後透過此光阻罩幕106的開口（opemng) 108蝕刻氮化矽 層104, 一般飩刻的方法都使用乾式蝕刻製程和氟基電漿蝕 刻液（fluorine-based plasma etchant)。依據此氮化石夕 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ^ —.1】 Γ 抑本 、17矣 , - (請先閱讀背面之注意事咬表填寫本頁) 經濟部中央標隼局員工消費合作社印製 1615twf.DOC/002 1615twf.DOC/002 經濟部中央標準局員工消費合作杜印製 A7 __—_B7 ____ 五、發明説明（牙） 層104的總厚度，此蝕刻系統可以在氮化物和氧化物材料 之間有一顯著的選擇性。使用一高選擇性的蝕刻製程，將 使得蝕刻一相當厚的氮化矽層1〇4之製程，終止於墊氧化 層102的表面或其附近。這個策略提供較隹的製程步驟來 蝕刻此氮化矽層104。另一方面，如果使用一較低選擇性的 氮化物蝕刻製程，最好使用一較厚的墊氧化層來調節氮化 物的過度飽刻（over etching)。蝕刻此氮化物層104至 曝露出此罩幕開Q 1〇8內的墊氧化物層1〇2後，此罩幕開 口 108內的墊氧化層102將被移除，此移除方法爲利用乾 式氧化物蝕刻法或氫氟酸浸泡法。隨著依序移除氮化物層 104和罩幕開口 108內的墊氧化層102，此基底100亦會被 飩刻如第14圖所示。一般而言，利用非等向性的蝕刻製程， 蝕刻此矽基底10〇所形成的溝渠11〇，其深度約爲 2000~5000A。蝕刻溝渠11〇的蝕刻液，比如是氯化氫和溴 化氫氣體電漿的衍生物。通常寧可使用較等向性的蝕刻製 程來完成此溝渠的蝕刻，如此溝渠底部的角落將會較圓 滑。例如，蝕刻此溝渠可以使用蝕刻液來完成，此蝕刻液 爲SF6氣體的衍生物。當此溝渠蝕刻完成後，如第14圖所 示’將使用傳統的灰化製程來移除此光阻罩幕。 當溝渠完成後，此氮化矽層1〇4儘量留在原處，並利 用本發明，將絕緣材料塡滿此溝渠。本發明塡滿溝渠的製 程包括第一摻雜層的沈積，隨後沈積一第二未摻雜層，其 中第一摻雜層和第二未摻雜層均爲一種介電材料。大部 份，第一層沈積矽玻璃，混入的導電性型摻質與此溝渠的 10 本^尺度適用中國國·( CNS )^iiT21〇X297公釐) (請先閱讀背面之注意事寫本頁) 、-=5 A7 1615twf.DOC/002 五、發明説明（if ) 內表面和此基底的表層周圍部份相同。此製程當然可能改 變，但一般會變得太複雜且工廠將須較大的製程資源，因 此目前較少用。因此本發明如第15圖的元件圖例，此第一 層的介電材料爲硼矽玻璃（boron silicate glass，BSG)， 其硼的濃度約爲1〜5%且厚度約爲200~5000A°BSG層112 可以間隔著一層摻雜硼的氧化層（boron doped oxide payer)或另一種有相同的擴散能力使摻質可以擴散到溝渠 表面的介電材料。此外，BSG層112可以混入其他的摻質。 然而在這個例子，只有適當導電性的摻質有能力從介電層 112擴散一有效的量，到此溝渠u〇內之曝露出的基底表 面。 此摻雜的矽玻璃有可能完全塡滿此溝渠，但通常較佳 只有用此硼矽玻璃112部份塡滿此溝渠，如第15圖所示， 以利用摻雜和未摻雜矽玻璃材料之再熱流性質不同的優 點。一較佳例，沈積在第一介電材料上及在此溝渠內的第 二介電材料，具有高程度的再熱流性質，或可提供一顯著 平坦化的方法。不論第二介電層沈積的特性是透過再熱流 的製程’或是透過自然平坦化，達成平坦表面如第15圖的 元件，以較方便隨後的CMP或其他平坦化的製程。爲了這 個目的’第二介電層114 (如第15圖所示）可以是比如以 砍酸四乙酯爲氣源利用CVD法沈積厚度約爲1〇〇〇〜5〇〇〇人之 未摻雜的氧化物。 第15圖的結構包括塡滿摻雜的介電材料層U2和未捧 雜的介電材料層114之溝渠，其中此兩者介電材料將受到 11 (請先閱讀背面之注意事項^:填寫本頁) '11 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 1615twt：DOC/002 A7 _ B7 經濟部中央標隼局工消費合作社印黎 五、發明説明（丨ϋ ) 筒溫再熱流的製程’比如在溫度約爲8⑻〜⑺⑽^的熱爐中 進行約10~60分鐘，此製程會將元件的表面部份平坦化， 同時亦會導致摻質從摻雜的矽玻璃層U2擴散到部份與其 直接接觸的基底內。之後，一較佳例爲一導電性型摻質從 第一導電層112擴散到場摻雜區118，其中此慘質與此基底 100的表面相同。一較佳例爲摻雜摻質到場摻雜區U8的程 度’會有效提供元件隔離所預期的程度，其形成於如圖中 溝渠的任何一邊。如以上討論，在矽玻璃層112內提供濃 度約1~5%的硼可完成圖示結構的隔離。値得重視的是，其 他兀件的幾何圖形和其他摻質可能須要不同的摻雜程度和 不同的擴散過程。 當此溝渠塡滿了介電材料和預期的隔離摻雜區118形 成後，進一步的過程是定義介電插塞之形狀。雖然這個過 程可用乾式蝕刻技術或其他蝕刻技術完成，本發明的一實 施例爲使用CMP製程定義此介電插塞。爲了此目的，第15 圖的結構將受到CMP，並以氮化砂層1 〇4爲硏磨終止層。因 此，根據本發明一較佳實施例，此介電插塞將被定義爲一 BSG層120區隔此溝渠，一未摻雜TEOS氧化層Π2佔據此 插塞的中心（如第16圖）。當此硏磨製程結後，通常此插 塞的表面會凹陷’且低於氮化砂罩幕層的表面高度。 接者’從基底100的表面移除罩幕層1〇4和墊氧化層 102。以氮化矽罩幕層1〇4爲較佳例，其剝除方法係爲在熱 磷酸溶液中利用濕式蝕刻法來完成。用磷酸浸泡完後，之 後可以用氟酸浸泡移除墊氧化層102。在和]用浸、泡或其他蝕 12 (請先閲讀背面之注意事項再填寫本頁) -裝Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 1615twf.DOC / 002 ^ 7 _B7 V. Description of the Invention (彡) Tetra-ethyl-ortho-si licate (TEOS) is used as the gas source, such as atmospheric pressure chemical vapor phase Deposition (atmospheric pressure chemical vapor deposition, APCVD) deposition, and TEOS overflow the trench, as shown in Figure 5. Because the TEOS oxide layer needs to be densified (dens i f i cat i on), for example, at a temperature of 1000 ° C, the process takes about 10 to 30 minutes, and after the densification, TEOS shrinks. After compaction, the TEOS oxide layer on the silicon nitride layer 24 is removed by chemical mechanical polishing (CMP), and the TEOS oxide layer is used as the end point for honing, leaving oxidation plugs in the trench area. 34 (Figure 6). Unlike Figure 6, when the chemical mechanical honing method is performed, since the oxide plug is softer than the nitrided sand layer, the oxide plug 34 under the surface of the silicon nitride will have a slight concave phenomenon. Then the silicon nitride layer 24 is removed, leaving the oxide plugs .34 on the surface of the pad oxide layer 22 (Fig. 7). Subsequently, the pad oxide layer 22 is removed by etching with hydrofluoric acid (HF) (Fig. 8). Since the etching rate of the TEOS oxidation plug is much faster than that of the thermally oxidized pad oxide, the removal of the oxidation plug results The thickness of the oxide plug 34 is thicker than that removed by the pad oxide layer 22, so that the TEOS oxide plug 34 can be extended to the surface of the substrate (FIG. 8). A sacrificial oxide layer 36 is formed on the surface of the substrate 10 to protect the surface of the substrate from damage. One or more implantation methods 'according to the needs of the component' include one or more channel threshold adjustment implantation methods (Figure 9). Thereafter, the sacrificial oxide layer 36 is removed again using hydrofluoric acid, and the structure formed by the sacrificial oxide layer 36 is shown in FIG. 10. Next, as shown in Figure 8 and Figure 10, the oxide layer etching step often causes oxygen. 5 This paper size applies the Chinese National Standard (CMS) A4 specification (210X 297 mm) (please read the note on the back first) (Item 4 writes this page) 'τ 1615twf.D〇C / 002 A7 1615twf.D〇C / 002 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5.Invention (>) Excessive melting of plugs (Over etching), the surface of the oxide plug 34 is recessed and lower than the surface of the substrate 10. Excessive engraving usually occurs at the edge of the oxidation plug 34 adjacent to the surface of the substrate 10, or the surface of the oxidation plug 34 is recessed below the surface of the substrate. In addition, over-etching may also cause exposure of the "shoulder" portion of the substrate, and partial etching of the trench sidewalls, or a thin layer of TEOS oxide covering the substrate adjacent to the trench sidewalls Up. Referring to FIG. 11, a gate oxide layer 40 is formed on the surface of the substrate 10 by a thermal oxidation method. Then, the gate oxide layer 40 usually forms a protruding edge on the shoulder region 38 of the substrate near the trench isolation region. profile. Generally speaking, a polycrystalline sand layer 42 is deposited on the surface of a substrate by a chemical vapor deposition method, and the polycrystalline sand layer 42 is implanted with dopants by an ion implantat ion method, and is subjected to an annealing process, continued. The connecting line 44 (wiring 1 ine) is formed by lithography, as shown in FIG. 12. Since the connecting line 44 extends on the gate oxide layer 40 and the oxide plug 34, and this oxide plug 34 also extends to the shoulder region 38 of the base near the side of the trench, the quality formed in the shoulder region 38 A bad gate oxide layer 40 will reduce the threshold voltage of the turn-on of the transistor and cause an abnormal subthreshold current in the neck effect. ° In view of this, One of the objectives of the present invention is to provide a shallow trench isolation structure for element isolation, and to increase the reliability of adjacent components to the shallow trench isolation structure. In order to achieve the above purpose, the present invention provides a shallow trench isolation structure of the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back and fill out this page first),-°! 615twf.DOC / 002 A7 B7 —-^ __ ~ 5. Description of the invention (meaning) (please read the precautions on the back to write this page) Manufacturing method, the first part of the invention is manufactured as follows: on a substrate A trench is engraved with uranium, and the substrate has a first conductivity type in a portion adjacent to the trench. A doped dielectric material layer covers the trench. The doped dielectric material layer is doped with a plurality of first dopants. These first dopants diffuse from the doped dielectric material into the substrate, and a self-aligned isolation doped region is formed along the inner wall of the trench, and the isolated doped region and the trench form a integrated circuit. Component isolation structure. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics The present invention provides a method for manufacturing a shallow trench isolation structure. The second part of the present invention is manufactured as follows: A substrate is provided. The substrate has at least a surface doped and a first conductivity Forming a mask defining the trench on this substrate; etching through the mask defining the trench; etching the substrate to form a trench in the substrate; providing a first dielectric layer; and doping a dielectric layer of the table A plurality of first dopants, the first dielectric layer is located in a trench above the substrate; a second dielectric layer is provided above the substrate, and the thermal velocity of the second dielectric layer is at a predetermined reheat flow temperature Larger than the first dielectric layer; heating the first and second dielectric layers to a reheating temperature, the dopants of the first dielectric layer diffuse from the first dielectric layer into the substrate and pass through the inner wall of the trench A plurality of self-aligned isolation doped regions are formed along the inner walls of the trench, and both of these isolation doped regions and the trench provide an element isolation structure as an integrated circuit element. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: 7 papers The dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1615twf.DOC / 002 A7 B7 V. Description of the invention () Figure 1 shows a shallow trench isolation structure among integrated circuit components. Figures 2 to 12 show a manufacturing method of a shallow trench structure in the conventional art. 13 to 18 show a method for manufacturing a shallow trench isolation structure according to one of the preferred embodiments of the present invention. Embodiments A preferred embodiment of the present invention forms a shallow trench isolation structure. An insulating layer is deposited over the inner surface of the trench, and the dopants in the insulating layer are diffused to the inner surface of the shallow trench. Preferably, the doped insulating material is an oxide layer and has the same conductivity type as the surface of the substrate. Therefore, for a P-type silicon substrate, chemical vapor deposition (CVD) can be used to deposit boron s i 1 i cate glass (BSG) to form a suitable insulating layer. A better doped insulating material is provided on the inner surface of the trench and partially fills the trench. In addition, an undoped insulating material is then deposited and completely filled and overfilled the trench. Then, a high temperature reheat flow process is used to diffuse the dopants in the better doped glass to the substrate and form field doping or isolation doping. This reheat flow process completes the reheat flow and densification of the doped glass, and the dopants diffuse from the glass through the inner surface of the trench into the substrate. Preferably, the doped glass remains in the completed shallow trench isolation structure. In the part of the preferred embodiment of the present invention, a field dopant (f i e 1 d dopan t) is provided on the entire internal surface of the trench to form an isolated dopant that is self-aligned to the trench. The formation of the doped inner wall of this trench also provides the isolation structure of this shallow trench. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1615twf.DOC / 002 Μ B7 5. Description of the invention (q) This surface is suitable for further component processing. In particular, during the subsequent process, the upper edge of the trench will be less likely to be exposed, and the surface of the substrate adjacent to the upper edge of the trench will be less likely to form a parasitic MOSFET structure. FIG. 13 shows a method for manufacturing a shallow trench isolation structure according to a preferred embodiment of the present invention. First, the silicon substrate 100 has a P-type background doped or P-type surface layer. A pad oxide layer 102 is formed on the surface of the silicon substrate. The pad oxide layer 102 is used to protect the substrate from being damaged by subsequent processes. The pad oxide layer 102 is formed, for example, by a thermal oxidation method, and has a thickness of about .50 to 500 A. Next, a mask layer 104 is deposited on the pad oxide layer 102. This mask layer 104 has two important functions. First, as a honing stop layer, the chemical mechanical polishing (CMP) step is completed to define the formation of insulating plugs in shallow trenches. Second, you can As a trench definition mask, the trench is defined using anisotropic etching of the silicon substrate. However, this mask layer 104 is often used only as a honing stop layer. For the above two purposes, a mask layer 104, such as silicon nitride, is deposited by CVD to a thickness of about 800 to 2000 A. Then, a photoresist layer is provided on the mask layer 104, and a trench pattern is defined by a photolithography process. After the photoresist layer is exposed, a mask 106 is formed, as shown in FIG. 13. Subsequently, the silicon nitride layer 104 is etched through the opemng 108 of the photoresist mask 106. Generally, a dry etching process and a fluorine-based plasma etchant are used for the etching method. Based on this, Nitride Stone 9 This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) ^ —.1] Γ 本, 17 矣,-(Please read the precautions on the back first to fill in this page ) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 1615twf.DOC / 002 1615twf.DOC / 002 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ____B7 ____ 5. The total thickness of the layer 104 This etching system can have a significant selectivity between nitride and oxide materials. The use of a highly selective etching process will result in the etching of a relatively thick silicon nitride layer 104, ending on or near the surface of the pad oxide layer 102. This strategy provides a relatively expensive process step to etch the silicon nitride layer 104. On the other hand, if a less selective nitride etching process is used, it is better to use a thicker pad oxide layer to adjust the over etching of the nitride. After the nitride layer 104 is etched to expose the pad oxide layer 102 in the mask opening Q 108, the pad oxide layer 102 in the mask opening 108 will be removed. This removal method is to use Dry oxide etching method or hydrofluoric acid immersion method. As the nitride layer 104 and the pad oxide layer 102 in the mask opening 108 are sequentially removed, the substrate 100 is also engraved as shown in FIG. 14. Generally speaking, the trench 11 formed by etching the silicon substrate 10 is etched using an anisotropic etching process, and the depth is about 2000 to 5000 A. The etchant for etching the trench 110 is, for example, a derivative of hydrogen chloride and hydrogen bromide plasma. Usually, the isotropic etching process is used to complete the etching of this trench, so the corners of the bottom of the trench will be smoother. For example, etching this trench can be accomplished using an etchant, which is a derivative of SF6 gas. When the trench is etched, the photoresist mask is removed using a conventional ashing process as shown in FIG. 14. When the trench is completed, the silicon nitride layer 104 remains as far as possible, and the present invention is used to fill the trench with insulating material. The trench filling process of the present invention includes the deposition of a first doped layer, followed by the deposition of a second undoped layer, wherein the first doped layer and the second undoped layer are both a dielectric material. Mostly, the first layer is deposited silica glass, and the conductive type dopants mixed with this trench are 10 times the size of China (CNS) (iiT21〇X297 mm) (Please read the note on the back first Page),-= 5 A7 1615twf.DOC / 002 5. Description of the invention (if) The inner surface and the surrounding part of the surface of this substrate are the same. This process may change, of course, but it will generally become too complicated and the factory will require larger process resources, so it is currently less used. Therefore, the element diagram of the present invention is as shown in FIG. 15. The dielectric material of the first layer is boron silicate glass (BSG). The concentration of boron is about 1 to 5% and the thickness is about 200 to 5000 A ° BSG. The layer 112 may be separated by a boron doped oxide payer or another dielectric material having the same diffusion ability so that the dopants can diffuse to the surface of the trench. In addition, the BSG layer 112 may be mixed with other dopants. However, in this example, only an appropriately conductive dopant is capable of diffusing an effective amount from the dielectric layer 112 to the exposed surface of the substrate within the trench u0. The doped silica glass may completely fill the trench, but it is usually best to only partially fill the trench with the borosilicate glass 112, as shown in Figure 15, to use doped and undoped silica glass materials The advantages of different heat flow properties. In a preferred example, the second dielectric material deposited on the first dielectric material and in the trench has a high degree of reheat flow properties, or may provide a method of significant planarization. Regardless of whether the second dielectric layer is deposited through a process of reheat flow 'or through natural planarization, a flat surface such as the element in FIG. 15 is achieved to facilitate subsequent CMP or other planarization processes. For this purpose, the second dielectric layer 114 (as shown in FIG. 15) may be, for example, an un-doped layer having a thickness of about 10,000 to 50,000 by using CVD method using tetraethyl citrate as a gas source. Miscellaneous oxides. The structure of Figure 15 includes trenches filled with doped dielectric material layer U2 and undoped dielectric material layer 114, where the two dielectric materials will be subject to 11 (Please read the precautions on the back ^: fill in This page) '11 Printed by the Central Consumers ’Cooperative of the Ministry of Economic Affairs This paper is printed in accordance with the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 1615twt: DOC / 002 A7 _ B7 Li Wu. Description of the Invention (丨 ϋ) The process of reheating the barrel temperature 'for example, in a hot furnace with a temperature of about 8⑻ ~ ⑺⑽ ^ for about 10 ~ 60 minutes, this process will flatten the surface of the component, and also It will cause the dopant to diffuse from the doped silica glass layer U2 into the substrate directly in contact with it. After that, a preferred example is that a conductive type dopant diffuses from the first conductive layer 112 to the field doped region 118, and the quality is the same as the surface of the substrate 100. A preferred example is that the degree of doping of the dopant to the field doped region U8 'will effectively provide the desired degree of element isolation, which is formed on either side of the trench as shown in the figure. As discussed above, providing boron at a concentration of about 1 to 5% in the silica glass layer 112 can complete the isolation of the illustrated structure. It is important to note that the geometry and other dopants of other components may require different doping levels and different diffusion processes. After the trench is filled with dielectric material and the desired isolation doped region 118 is formed, a further process is to define the shape of the dielectric plug. Although this process can be performed using dry etching techniques or other etching techniques, one embodiment of the present invention defines this dielectric plug for the CMP process. For this purpose, the structure of Fig. 15 will be subjected to CMP, with a nitrided sand layer 104 as a honing stop layer. Therefore, according to a preferred embodiment of the present invention, the dielectric plug will be defined as a BSG layer 120 separating the trench, and an undoped TEOS oxide layer Π2 will occupy the center of the plug (as shown in FIG. 16). After the honing process is completed, the surface of the plug is generally recessed and is lower than the surface height of the nitrided sand mask layer. The connector 'removes the mask layer 104 and the pad oxide layer 102 from the surface of the substrate 100. Taking silicon nitride mask layer 104 as a preferred example, the stripping method is performed by using a wet etching method in a hot phosphoric acid solution. After soaking with phosphoric acid, the pad oxide layer 102 may be removed by soaking with hydrofluoric acid. In and] dip, soak or other etching 12 (Please read the precautions on the back before filling this page)-
、1T 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 1615twf.D〇C/002 A7 B7 經濟部中央標準局員工消费合作社印製 五、發明説明（丨丨） 刻製程移除墊氧化物102時，部份介電插塞會被進一步的 移除。之後的製程將使插塞的高度邊界些微高於基底1〇〇 的表面’且避免曝露出溝渠的內部邊緣。爲了完成這最後 的結構’須爲此罩幕層104選擇一適當的厚度。當一·適當 厚度的氮化砂提供作此罩幕層104時，此介電插塞120、122 將形成些微可預期的凹陷。隨後，氟酸的浸泡會將此介電 插塞移除一可預期的量。相對地，在第Π圖的圖示結構， 可用一可接受程度的統一製程來完成。由以上的製程，完 成之淺溝渠隔離結構是爲塡滿絕緣介電材料的溝渠。 當此淺溝渠隔離結構形成後，如第17圖所示，接著進 一步的製程是形成與淺溝渠隔離結構相鄰的預期元件。第 18圖顯示當進一步的製程在基底的內部和上方提供場效應 電晶體後’第17圖之隔離結構的些微應用擴張之剖面圖。 在基底的表面上，分開放置一對淺溝渠隔離結構混入自行 對準場摻雜區118和介電插塞124。在此基底的主動元件區 上形成閘極氧化層126，並定義在介電插塞124之間。形成 複數個摻雜的多晶矽閘電極128的方法如下，藉在元件上 沈積多晶矽層，利用離子植入法進行摻雜，然後定義此多 晶矽層’形成如圖示的電極128。藉離子植入法自行對準這 些閘電極128和介電插塞124,以形成複數個源極/汲極區 130 ’如第18圖所示。根據以上製程的結果，在每一個源 極/汲極區130和與淺溝渠隔離結構相鄰的自行對準場摻 雜區118之間，形成垂直延伸的p/N接合。此圖示的結構 有一優點’不只是提供一高程度的元件隔離，更可以限制 13 本紙張尺度適用中酬豕標準（CNS )八4規格（21〇χ 公楚） (請先閱讀背面之注意事項再填寫本頁) IM. f..:. 、-0 Γ1. The paper size of the 1T line is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 1615twf.D0C / 002 A7 B7 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Inventory (丨 丨) Engraving process When the pad oxide 102 is removed, some of the dielectric plugs are further removed. The subsequent process will make the height boundary of the plug slightly higher than the surface of the substrate 100 'and avoid exposing the inner edges of the trench. In order to complete this final structure ', an appropriate thickness must be selected for this cover layer 104. When a suitable thickness of nitrided sand is provided as the cover layer 104, the dielectric plugs 120, 122 will form slightly predictable depressions. Subsequent immersion in hydrofluoric acid will remove this dielectric plug by a predictable amount. In contrast, the structure shown in Figure Π can be completed with an acceptable degree of uniform process. By the above process, the completed shallow trench isolation structure is a trench filled with insulating dielectric material. After the shallow trench isolation structure is formed, as shown in FIG. 17, a further process is to form a desired element adjacent to the shallow trench isolation structure. Fig. 18 shows a cross-sectional view of a slightly applied expansion of the isolation structure of Fig. 17 after further processing provides field effect transistors inside and above the substrate. On the surface of the substrate, a pair of shallow trench isolation structures are placed separately and mixed with a self-aligned field doped region 118 and a dielectric plug 124. A gate oxide layer 126 is formed on the active element region of the substrate, and is defined between the dielectric plugs 124. The method of forming a plurality of doped polysilicon gate electrodes 128 is as follows. By depositing a polysilicon layer on the device, doping by ion implantation, and then defining the polysilicon layer 'to form the electrode 128 as shown in the figure. The gate electrodes 128 and the dielectric plugs 124 are aligned by the ion implantation method to form a plurality of source / drain regions 130 'as shown in FIG. According to the results of the above processes, a vertically extending p / N junction is formed between each source / drain region 130 and the self-aligned field doping region 118 adjacent to the shallow trench isolation structure. The structure of this illustration has the advantage of 'not only providing a high degree of component isolation, but also limiting the 13 paper sizes applicable to CNS 8.4 specifications (21〇χ 公 楚) (please read the note on the back first) (Fill in this page again) IM. F ..:., -0 Γ
I 16l5twf.DOC/002 A7 B7 五、發明説明（丨1) 寄生電晶體的行爲，而此寄生電晶體的行爲可導致淺溝渠 上邊緣的相接。因此，此圖示結構應該可以比傳統的淺溝 渠隔離結構更不受頸結效應（kink effect)的影響。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ί mi ln«——·— In nn I m (請先閲讀背齑之注意事項再填寫本頁) 訂 ▲ 經濟部中央標準局員工消費合作社印製 14 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）I 16l5twf.DOC / 002 A7 B7 V. Description of the Invention (1) The behavior of parasitic transistor, and the behavior of this parasitic transistor can lead to the connection of the upper edge of the shallow trench. Therefore, the illustrated structure should be more immune to the kink effect than traditional shallow trench isolation structures. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ί mi ln «—— · — In nn I m (Please read the precautions of the back page before filling in this page) Order ▲ Printed by the Central Consumers Bureau of the Ministry of Economy Staff Consumer Cooperatives 14 This paper size applies to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm)