TW394980B

TW394980B - Semiconductor device fabrication system and method of forming semiconductor device pattern using the same

Info

Publication number: TW394980B
Application number: TW087112710A
Authority: TW
Inventors: Gyu-Chan Jeoung; Kwang-Seok Choi; Jin-Hang Jung; Young-Sun Kim; Hong Lee
Original assignee: Samsung Electronics Co Ltd
Priority date: 1998-02-05
Filing date: 1998-07-31
Publication date: 2000-06-21
Also published as: KR19990071372A; KR100291331B1

Abstract

There are provided a semiconductor device fabrication system for carrying out a UV-bake on a photoresist pattern in the semiconductor device pattern formation and a method of forming a semiconductor device pattern using the same. The semiconductor device fabrication system comprises a photoresist coating unit for coating a wafer transferred from a wafer loading unit with a specific photoresist; a developing unit for forming a photoresist pattern on the wafer by aligning a photo mask on the wafer, exposing the wafer, and developing the exposed wafer; and a UV bake unit for irradiating the developed wafer with a UV light in order to guide a stabilized flow during the flow process for the photoresist pattern. The method of forming a semiconductor device pattern comprises the steps of: forming a photoresist pattern by coating a wafer with a photoresist by exposing the photoresist, and developing and cleaning the photoresist; carrying out a UV bake for the photoresist; and carrying out a flow bake for the photoresist pattern after the UV bake.

Description

經濟部中央樣牟而只工消费合作社印掣 A7 __ _ _ B7 五、發明説明（1 ) , 發明領域本發明係關於半導體裝置之製造，特別係關於經由照射紫外光（UV)於光阻圖樣然後進行流動製程而使用半導體裝置圖樣形成方法提供具有所需大小之半導體裝置圖樣之方法。相關技術之說明概略而言半導體裝置係由製程陣列組成如沉積，微影術，银刻及離子植入法等。換s之，半導體裝置圖樣係經由沉積多晶膜、氧化物膜、氮化物膜及金屬膜等於半導體晶圓上及進行微影術製程、蝕刻製程及離子植入製程等形成。微影術製程對於半導體裝置之製法上意義重大，其中使用光罩於晶圓上形成半導體裝置積體電路之預定圖樣。微影術製程用於多種16M DRAM、64M dram及又根據曝光加工步驟使用之光源256M DRAM及1G dram或以上之多種半導體裝置製法。目前用於光學加工之光源為心線（436 nm)、i_線（365 nm)、Duv(248 nm)及ΚΓρ雷射（i93 nm)等。微影術製程使用之光阻係由高度聚合感光物質製成，物質之溶解度隨著與光之化學.反應改變。換言之，光投射於預先形成微電路之光罩上，光入射部之光阻物質改變成比較光未入射部之光阻物質更為可熔物質或更不可熔物質。隨後以適當顯像劑顯像因而形成正型或負型光阻圖樣。如前製作之光阻圖樣用於微影術製程後之下列製程如蝕刻本紙張又舰财關家轉（(：叫八4規格（21似297公潑) ~ ' ----The Central Ministry of Economic Affairs and the Consumers ’Cooperative Printing Co., Ltd. A7 __ _ _ B7 V. Description of the Invention (1), Field of Invention The present invention relates to the manufacture of semiconductor devices, and in particular, to photoresist patterns by irradiating ultraviolet (UV) light. Then, a flow process is performed using a semiconductor device pattern forming method to provide a semiconductor device pattern having a desired size. Description of related technologies In general, semiconductor devices are composed of process arrays such as deposition, lithography, silver engraving, and ion implantation. In other words, the pattern of the semiconductor device is formed by depositing a polycrystalline film, an oxide film, a nitride film, and a metal film on a semiconductor wafer and performing a lithography process, an etching process, and an ion implantation process. The lithography process is of great significance to the manufacturing method of semiconductor devices, in which a photomask is used to form a predetermined pattern of a semiconductor device integrated circuit on a wafer. The lithography process is used for a variety of 16M DRAM, 64M dram, and light source 256M DRAM and 1G dram or more semiconductor device manufacturing methods based on the exposure processing steps. The light sources currently used for optical processing are cardiac (436 nm), i_line (365 nm), Duv (248 nm), and KΓρ laser (i93 nm). The photoresist used in the lithography process is made of a highly polymerized photosensitive material. The solubility of the material changes with the chemical reaction with light. In other words, light is projected on a photomask in which a microcircuit is formed in advance, and the photoresist substance at the light incident portion is changed to be more fusible or infusible than the photoresist substance at the light non-incident portion. Subsequent development with a suitable developer thus forms a positive or negative photoresist pattern. The photoresist pattern made as before is used for the following processes after the lithography process, such as etching. This paper is also used by the Jiancai Guanjia ((: called the 8-4 specification (21 like 297)) ~ '----

-4- 五、發叼説明（2 A7 B7 經"部中央樣苹^只工消牝合作社印龠及離子植入製程等作為光罩。光阻類型依據曝光光源如g_線、i_線及Duv劃分。但前述光阻通常難以形成尺寸比曝光光源波長更短的光阻圖樣。目前微影術製程之接觸孔圖樣之解析度低於線與空間圖樣之解析度，故晶圓整體表面上之圖樣均勻度不佳。因此需要新技術許可形成尺寸為〇2〇#m或以下之接觸孔圖樣，其為超過64M DRAM之高度積體半導體裝置所需俾克服光阻之解析度限制。目前形成尺寸比曝光光源波長更短的接觸孔之方法如下。首，先’作為光阻圖樣之流動加工方法，尺寸比所需更大之接觸孔之正常光阻圖樣係使用正常鉻（Cr)罩形成，然後间於光阻軟化點之熱量施加於光阻圖樣而使高度聚合光阻軟化及降低黏度而使光阻流動。結果光阻圖樣尺寸縮小〇其次，至於修改曝光方法，曝光部及未曝光部經由使用經修改之照光及相移光罩（pSM)曝光明確界定。結果光阻圖樣之接觸孔尺寸比使用正常光及光罩者更小。藉i-線光阻之流動方法包括酚醛清漆樹脂，光活性化合物（PAC) ’溶劑及添加劑利用由於pac受熱熱解以及樹脂於PAC交聯反應促成熱性質，及由於加熱使黏度降低促成光阻圖樣流動現象造成之速度差。線光阻之流動係以父聯反應進行，流動現象由交聯反應妥為控制。換言之，請先閲讀背面之注項再填訂線本紙張尺度適财_家轉（CNS ) 公釐經濟部中夹樣卑而只工消贽合作拉印掣改藉 A7 B7 五、發明説明（3 )-4- V. Description of the hairpin (2 A7, B7, " Ministry of Central Asia, Japan, Japan, Japan, Japan, Japan, Japan, etc. as photomasks. The type of photoresist is based on the exposure light source such as g_line, i_ Line and Duv division. However, the aforementioned photoresist is usually difficult to form a photoresist pattern with a size shorter than the wavelength of the exposure light source. At present, the resolution of the contact hole pattern in the lithography process is lower than the line and space pattern resolution, so the whole wafer The uniformity of the pattern on the surface is not good. Therefore, a new technology license is required to form a contact hole pattern with a size of 0 ## m or less, which is required for highly integrated semiconductor devices with more than 64M DRAM. The current method for forming contact holes with a size shorter than the wavelength of the exposure light source is as follows. First, as a flow processing method of the photoresist pattern, the normal photoresist pattern of contact holes with a larger size than required uses normal chromium (Cr ) The cover is formed, and then the heat between the photoresist softening point is applied to the photoresist pattern to soften the highly polymerized photoresist and reduce the viscosity to cause the photoresist to flow. As a result, the size of the photoresist pattern is reduced. Secondly, as to modify the exposure Method, the exposed part and the unexposed part are clearly defined by using modified light and phase shift mask (pSM) exposure. As a result, the contact hole size of the photoresist pattern is smaller than that of normal light and mask. Borrow i-line light Resistance flow methods include novolac resins, photoactive compounds (PACs), solvents and additives. The use of pac is thermally decomposed and the resin reacts with the PAC to promote thermal properties, and the reduction in viscosity caused by heating causes photoresist pattern flow. Speed difference. The flow of the linear photoresist is carried out by the parent-link reaction, and the flow phenomenon is properly controlled by the cross-link reaction. In other words, please read the note on the back before filling the line. This paper is suitable for financial standards_ 家转 (CNS) company In the Ministry of Economic Affairs, the Ministry of Economic Affairs and the Ministry of Economic Affairs only work to eliminate the need to cooperate to print and switch to A7 B7. 5. Description of the invention (3)

" I 因i-線光阻之流動現象緩慢隨時間之變化進行，故極少受製程與設備之溫度變化影響。以i-線光阻為例，藉流動方法獲得025微米圖樣。經由施加修改光及PSM於線光阻可達成〇·28微米圖樣。第1圖顯示習知半導體裂置之圖樣生成方法，換言之，顯示使m-線光阻形成接觸孔方法之加工順序。參照第1圖’首先作為以光阻塗布晶圓之步驟（s2)，^ 線光阻塗布於其上方預先沉積有六甲基二梦胺烧出mds) 之晶圓上。然後至於軟烘烤晶圓之光阻之步驟（s4)，光阻包含之溶劑藉軟烘烤去除故光阻之黏著性改良，及維持光阻以某種厚度塗布於晶圓上之狀態。軟烘烤後，至於光罩對正类阻後之曝光步驟（S6)，其上方具有i'線光阻之晶圓移動至i-線步進器，其上形成有細微圖樣之psM對正晶圓。然後其上有光阻之晶圓及對正晶圓之psM接受丨_線光源照射而進行曝光。然後至於曝光晶圓之後曝光烘烤（pEB) 步驟（S8)，通過曝光之晶圓於適當溫度烘烤而去除由駐波現象產生之波紋，駐波現象由於曝光光源之入射光及反射光之加強干擾及摧毁性干擾期間發生於光阻圖樣上，及良光阻圖樣外廓，及又改良光阻圖樣解析度。其次至於顯像及清潔通過PEB之晶圓而形成光阻圖樣之步驟（sl〇) ’ PEB已經完成之晶圓移動至顯像單元，顯像劑供給於晶圓上之光阻而形成光阻圖樣，及副產物之顯像係使用清潔溶液去除。然後莖於顯像‘後晶圓之硬烘烤步驟（s丨2)，已經完成本紙張尺度適用中國國家標準（〇奶）六4規格（210乂297公酱） -------」--^----^---、玎----- (請先閱讀背面之注意事項再填寫本頁) -6" I Because the flow phenomenon of i-line photoresist slowly changes with time, it is rarely affected by process and equipment temperature changes. Taking the i-line photoresist as an example, a 025 micron pattern was obtained by the flow method. By applying modified light and PSM to the linear photoresist, a 0.28 micron pattern can be achieved. FIG. 1 shows a conventional method for generating a pattern of semiconductor cracking, in other words, a processing sequence of a method for forming a contact hole by m-line photoresist. Referring to FIG. 1 ', as a step (s2) of coating a wafer with a photoresist, a photoresist is coated on a wafer on which hexamethyldimethyamine is deposited (the mds is burned out in advance). Then, as for the photoresist step (s4) of the soft baking wafer, the solvent included in the photoresist is removed by soft baking to improve the adhesion of the photoresist, and the state where the photoresist is coated on the wafer with a certain thickness is maintained. After the soft bake, as for the exposure step (S6) after the photoresist is aligned, the wafer with the i 'line photoresistor on the top is moved to the i-line stepper, and a fine pattern of psM alignment is formed thereon. Wafer. Then, the wafer with the photoresist on it and the psM of the alignment wafer are exposed to a line light source for exposure. Then, as for the exposure baking (pEB) step (S8) after exposing the wafer, the ripple generated by the standing wave phenomenon is removed by baking the exposed wafer at an appropriate temperature. The standing wave phenomenon is caused by the incident light and reflected light of the exposure light source. Enhanced interference and destructive interference occurred on the photoresist pattern, the outline of the good photoresist pattern, and the resolution of the photoresist pattern was improved. Secondly, as for the steps of developing and cleaning the photoresist pattern through the PEB wafer (sl0) 'The wafer that the PEB has completed is moved to the imaging unit, and the photoresist supplied by the developer on the wafer forms the photoresist. Patterns and by-products were removed using a cleaning solution. Then the stem is baked hard after the imaging step (s 丨 2), and the paper size has been completed to apply the Chinese national standard (〇奶) 6 4 specifications (210 乂 297 male sauce) ------- ''-^ ---- ^ ---, 玎 ----- (Please read the notes on the back before filling this page) -6

裝訂線 -7-Gutter -7-

I Α7 Β7 五、發明説明（5 ) 其上有i -線光阻6之晶圓2。然後使用i _、線光源對晶圓進行曝光、。隨後如第4圖所示’於曝光後之晶圓2進行pEB，及循序進灯顯像及,月潔因而形成第_接觸孔圖樣卜此時第一接觸孔圖樣8之尺寸為G.25«。㈣如第5圖所示，第一接觸孔圖樣8經流動及供烤而形成第二接觸孔9。但藉修改照光使用PSM進行流動之财，若干未曝光料均句曝光’高度聚合光阻圖樣之熱性質變不均勻。結果依據熱項度而定出現流動速率差囡而三丨2a 午是因而引起本體效應，其中如第5圖所示，於流動及煤烤期間第二接觸孔9扭曲。發明概述本發明係針對提供—種半導Μ置製造系統及使用該系統形成半導《置圖樣之方法，其可大體免除因先前技術之限制及缺點造成之—種或多種問題。本毛月之目的係提供—種於使用i'線光阻及相移阻罩 (PSM)之例許可進行流動方法形成均勾且具所需大小之接觸孔圖樣之半導體裝置圖樣之形成方法。本發明之另一目的係提供一種經由應用流動方法至深部紫外光(DUV)光阻透過形成具有均勻期望大小之接觸孔圖樣而形成半導體裝置圖樣之方法。本么明之又另一目的係提供一種形成本發明之半導體裝置圖樣之方法之半導體裝置製造系統。為了達成如具體表現及廣義說明之根據本發明之目的之此等及其他優點，—種半導體裝置製造系統包含：一個光阻塗布單元供以適當光阻塗布由晶圓載荷單元移送之晶本紙張尺麵财_ {請先閱讀背面之注意事项再填寫本頁j 、-'° -線- 經濟部中央標华而只工消贽合作社印製I Α7 Β7 5. Description of the invention (5) Wafer 2 with i-line photoresistor 6 on it. Then use i_, line light source to expose the wafer. Subsequently, as shown in Figure 4, 'the pEB was performed on the exposed wafer 2 and the light was progressively developed and Yuejie thus formed the first contact hole pattern. At this time, the size of the first contact hole pattern 8 was G.25. «. ㈣ As shown in FIG. 5, the first contact hole pattern 8 is formed by flowing and baking to form a second contact hole 9. However, by modifying the light to use PSM for the flow of money, some unexposed materials were exposed to light, and the thermal properties of the highly polymerized photoresist pattern became uneven. As a result, a flow rate difference occurs depending on the thermal term, and the bulk effect is caused by noon 3a and 2a. As shown in Fig. 5, the second contact hole 9 is distorted during flow and coal baking. SUMMARY OF THE INVENTION The present invention is directed to providing a semi-conductive manufacturing system and a method for forming a semi-conductive pattern using the system, which can substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art. The purpose of this month is to provide a method for forming a semiconductor device pattern that is uniform and has a contact hole pattern of the required size by using the flow method of i'-line photoresist and phase shift mask (PSM). Another object of the present invention is to provide a method for forming a semiconductor device pattern by applying a flow method to the formation of a deep ultraviolet (DUV) photoresist through a contact hole pattern having a uniform desired size. Another object of the present invention is to provide a semiconductor device manufacturing system for a method for forming a semiconductor device pattern of the present invention. In order to achieve these and other advantages according to the purpose of the present invention as embodied and broadly described, a semiconductor device manufacturing system includes: a photoresist coating unit for coating a crystalline paper transferred from a wafer load unit with an appropriate photoresist Rule noodles _ {Please read the notes on the back before filling in this page j,-'°-line-printed by the Central Ministry of Economic Affairs, China

經濟部屮央標率局；;'i工消贽合作社卬製Central Bureau of Standards, Ministry of Economic Affairs;

圓:一個顯像單元供於塗布有光阻之晶圓上形成光阻„ /形成方式係經由對正光草於晶圓，曝光晶圓，及 =後之晶圓；及—個紫外料烤單元供以紫外光照射顧像後之晶圓俾於.光阻圖樣流動製財導引穩定流動。半導體裝置製造系統可為旋轉器或軌道系統。較佳半導體裝置製造系統包含：—健刪塗布單元供提向光阻於由晶圓載荷單元移送之晶圓表面之黏著性. :個供烤單元供烘烤其上有光阻之晶圓，及通過曝光及顯 :緣ST個晶圓邊緣曝光(WEE)單元供以某種厚度曝光晶半導體裝置製造“較佳包含晶圓載荷單元、職D s Γ單元、絲塗布單元、塗布U、烘烤單元、晶圓緣曝光單7G及紫外光烘烤單元中之至少一者。較佳半導體裳置製造系統之軟供烤單元包含：一個軟供烤單元供去除包含於晶圓上光阻之溶U後曝光烘烤（PEB)單元供去除存在於絲圖樣之駐波等丨及一個硬烘烤單元供硬化光阻圖樣。二個紫外光烘烤單元包含：一盖紫外燈置於紫外光烘烤單元上#及產生紫外光；及熱板置於紫外光供烤單元下部，及加熱安裝成與紫外燈有某種距離之晶圓。紫外燈可為微波激光燈或汞_氙燈。本發明之另一具體例中，一種半導體裝置製造系統包含··一個紫外光烘烤單元供以紫外光照射通過顯像之晶圓俾於光阻圖樣之流動加工期間導引穩定流動於晶圓；及一本紙張尺度 (CNS) Αϋ 21Gx297公潑） (H 4 • ---|批衣-- (請先閲讀背面之注意事項再填寫本瓦〕訂線 -9- 五發明説明（ A7 B7 個加工腔至没置於接近紫外光烘烤單元，及使用光阻圖樣作為餘刻阻罩進行晶圓上亞層之蝕刻加工。紫外光烘烤單元及加工腔室可透過載荷閘室聯結。紫外光烘烤單元包含：—盞紫外燈置於紫外光烘烤單元上。卩及產生紫外光；及熱板置於紫外光烘烤單元下部，及加熱女裝成與紫外燈有某種距離之晶圓。紫外燈可為微波激光燈或汞_氙燈。本發明之另一態樣中，一種形成半導體裝置圖樣之方法I 3下列步驟.a)以光阻塗布晶圓；b)軟烘烤於晶圓之光阻，c)對正光罩於通過軟烘烤之光阻及進行曝光；旬對 ^過曝光之光阻進行後曝光烘烤（pEB) ; 〇經由顯像及清潔通4PEB之光阻而形成光阻圖樣；f)對光阻圖樣進行紫外光烘烤，及g)對紫外光烘烤後之光阻圖樣進行流動 (請先閱讀背面之注意事項再填寫本頁) -裝. 、1Τ 紐消部中央榀準扃只工消费合作社ίρ#Circle: a developing unit is provided for forming a photoresist on a wafer coated with a photoresist. / The formation method is by aligning the photoresist on the wafer, exposing the wafer, and the subsequent wafer; and an ultraviolet baking unit It is used to irradiate the wafer after UV light irradiation. The photoresist pattern flow guides the stable flow. The semiconductor device manufacturing system can be a rotator or a track system. The preferred semiconductor device manufacturing system includes:-a flexible coating unit Provides the adhesiveness of the photoresist on the surface of the wafer transferred by the wafer load unit .: A baking unit for baking the wafer with the photoresist on it, and exposure through the edge of the wafer (WEE) unit for the manufacture of crystalline semiconductor devices with a certain thickness "preferably includes wafer load unit, duty D s Γ unit, silk coating unit, coating U, baking unit, wafer edge exposure sheet 7G and UV baking At least one of the baking units. The soft baking supply unit of the preferred semiconductor rack manufacturing system includes: a soft baking supply unit for removing the photoresist contained in the wafer from the post-exposure bake (PEB) unit for removing the standing waves existing in the silk pattern, etc. 丨And a hard baking unit for hardened photoresist pattern. The two UV baking units include: a cover UV lamp placed on the UV baking unit # and generating UV light; and a hot plate placed on the lower part of the UV light baking unit, and heated to be installed at a distance from the UV lamp Of wafers. The ultraviolet lamp may be a microwave laser lamp or a mercury-xenon lamp. In another specific example of the present invention, a semiconductor device manufacturing system includes a UV baking unit for irradiating ultraviolet light through a developed wafer and guiding a stable flow on the wafer during the flow processing of the photoresist pattern. ; And a paper size (CNS) Αϋ 21Gx297 male splash) (H 4 • --- | batch clothes-(please read the precautions on the back before filling in this tile) The processing cavity is not placed near the ultraviolet baking unit, and the photoresist pattern is used as an etched mask to perform the sub-layer etching process on the wafer. The ultraviolet baking unit and the processing chamber can be connected through a load gate chamber. The ultraviolet light baking unit includes:-a ultraviolet lamp is placed on the ultraviolet light baking unit. It generates ultraviolet light; and a hot plate is placed on the lower part of the ultraviolet light baking unit, and the women's clothing is heated to a certain distance from the ultraviolet light. The UV lamp may be a microwave laser lamp or a mercury-xenon lamp. In another aspect of the present invention, a method for forming a semiconductor device pattern I 3 The following steps: a) coating the wafer with a photoresist; b) soft baking Bake the photoresist on the wafer, c) align the photomask on Soft-bake photoresist and exposure; post-exposure bake (pEB) for over-exposed photoresist; o photoresist pattern is formed through development and cleaning through 4PEB photoresist; f) photoresist The pattern is baked by UV light, and g) the photoresist pattern after the UV light is flowed (please read the precautions on the back before filling this page)-installed. Cooperatives ίρ #

光阻較佳用“線或深部紫外光（DUV)，及於使用i_線光阻之例光罩使用相移阻罩（PSM)。光阻圖樣為接觸孔圖樣。形成半導體裝置圖樣之方法又包含於進行紫外光烘烤步财之钱烤步驟。較佳紫外光供烤係藉使用紫外光照射光阻圖樣及同時加熱進行烘烤製程進行。加熱進行烘烤製程之加工溫度為5〇至14〇它，及紫外光照射步驟進行1 〇至8〇秒。流動烘烤之加工溫度係於140至20〇。(：之範圍，及流動烘烤之加工時間為.80至120秒。 iΓ ------------ -10- 經漪部中爽你4,·^狄工消费合作.#印製 A7 (_____________—_________—_____ 'B7 五、發明説明（8 ' 流動烘烤係至少重複進行一次。形成半導體裝置圖樣之方法之另一態樣包含下列步驟 • a)况積光阻於半導體基材上；…軟烘烤經過沉積之光阻 ’ c)對正光罩以經過軟、烘烤之綠及進行曝光；…對曝光後之光阻進行後曝光烘烤（PEB) ; e)經由顯像及清潔通過 PEB之光阻而形成光阻圖樣；f)硬烘烤光阻圖樣；幻對通過硬烘烤之光阻圖樣進行顯像；叫對通過顯像之光阻圖樣進行流動烘烤。光阻較佳用於卜線及光罩為相移阻罩（PSM)。光阻圖樣可為接觸孔圖樣。對通過硬烘烤之光阻之顯像至少重複進行兩次。埤動烘烤之加工溫度較佳為140至20(TC，及流動烘烤可進行80至120秒。需瞭解前文概略說明及後文詳細說明僅為舉例說明之用意圖對申請專利之本發明提供進一步解說。圖式之簡單說明附圖中：第1圖顯示習知半導體裝置之圖樣形成之加工順序；第2至5圖為剖面圖顯示根據第1圖之力?工順序之半導體裝置圖樣之形成；、第6圖為方塊圖顳.示根據本發明之半導體裝置製造系終之具體例； ’、第7圖為剖面圖顯示第6圖半導體裝置製造系統之紫先烘烤單元； “ 、 $ 紙張尺家轉（叫 Α·^ (------ ^-- (請先閲讀背面之注意事項再填寫本頁) 、-口線· A7 B7 上得及五、發問説明（9 ) 第8圖為加卫順序顯示根據本發明之裝置圖樣之形成；& 千導體第9至12圖為剖面圖顯示根據第8圖之加工順序之 f裝置圖樣之形成。較佳具體例之詳細說明現在參照附圖於後文更完整說明本發明，附圖顯示本 =明之較佳具體例。但本發明可以不同形式具體表現而不得視為囿限於此處陳述之具體例；反而提供此等具體例使其揭示内容更徹底完整，更完整傳遞本發明之範圍給業界人士 0 根據本發明，.提供-種半導體裝置之製造系統及使用該系統形成半導體裝置圖樣之方法，其中於半導體晶圓之光阻圖樣於微影術之顯像過程後使用紫外光照射俾獲較小臨界尺寸，因而防止流動製程期間光阻圖樣扭曲，可有效獲得所需圖樣的尺寸。於後文對本發明之具體例進行細節說明。第6圖為方塊圖.顯示根據本發明之半導體裝置製造系統之具體例，及第7圖為剖面圖顯示配備有第6圖之微波激光燈之紫外光單元。第6圖顯示半導體裝置製造系統3〇及曝光裝置9〇透過介面單元80線上聯結。半導體裝置製造系統30包含：晶圓載荷單元32載荷内含晶圓之晶圓卡匣；HMDS塗布單元34供提高光阻於由載射單元32#送至晶*圓表面之黏著性；光阻塗布單元36供 t紙張尺度適/fl中國國家標準（CNS ) A4規格（21〇X297公釐） ^--抑衣------、玎------10 (請先閱讀背面之注意事項再填寫本頁} 以 12 經浒部中央椋準乃負工消t合作社印fi A7 B7 五、發叨説明（10 ) , "~' - 光阻塗布含HMDS之晶圓；顯像單元44供於光阻塗布單元 36使用光阻塗布晶圓，曝光晶圓上之光阻及顯像曝光妥之晶圓後形成光阻圖樣；烘烤單元37包含軟烘烤單元％供去除其上含光阻之晶圓之溶劑，pEB單元42供去除於其上含光阻之晶圓曝光後存在於光阻圖樣上之細微駐波，及硬烘烤單元40供硬化光阻圖樣；及紫外光烘烤單元牝供以紫外光照射顯像妥之晶圓，及於光阻圖樣之流動加工期間提供穩定流動。半導體裝置製造系統可為旋轉器或軌道系統，半導體裝置製造系統中較佳又架設晶圓緣曝光單元供曝光晶圓緣部之某個厚度。至於使用半導體裝置製造系統之有效半導體裝覃多重製程，晶圓載荷單元32、HMDS沉積單元34、光阻載％單元36及顯像單元44、軟烘烤單元38、PEB單元 42、硬烘烤單元40及紫外光烘烤單元48較佳分別安裝數目為至少一者，換言之，多數。 Ί、外光烘烤單元4 8包含紫外燈照射於腔室上部提供紫外光，及熱板架設於腔室下部供以距離紫外燈之某種距離安裝晶圓並加熱晶圓。紫外燈較佳為微波激光燈或汞氙弧燈。參照具有微波激光燈60之紫外光烘烤單元48，紫外光烘烤單元48包含微波激光燈60包括汞燈泡62具有超高頻波導61，反射鏡63供遮蓋汞燈泡62及將經由超高頻波導61施加超高頻波而由汞燈泡62產生之紫外光聚焦於晶圓，及石英板置於皮射鏡63,下方；及熱板70供安裝晶圓68距離微波本紙張尺農適扣中國國家梯準（CNS ) A4規格（210X297公釐） ------------.裝------訂丨，----—線 (請先閲讀背面之注意事項再填寫本頁) 經於部中夾捃4,-^只工消费合作社印^ kl B7 五、發丨巧説明（11 ) -- 激光燈60之一段距離及加熱晶圓68。 #晶_係安裝於熱板70上，超高頻波導61施加能量於其中含有汞之汞燈泡62，汞轉成電浆態因而產生紫外光。反射細反射於多種方向散射之紫外光而使紫外光有效 I 到達晶圓68。 _本發明之半導體裝置製造系統3G之作業進行說明。首先當其中含有晶圓之卡E載荷於晶圓載荷單元32時，晶圓藉第一移送臂50移轉至HMDS沉積單元34。某種厚产之 HMDS沉積於HMDS沉積單元34内侧之晶圓上因而有:塗 #晶圓以光阻。然後其上附有HMDS之晶圓藉第二移送臂 52移轉至光阻塗布單元36,故晶圓表面塗布以特定製程用《特《光阻。僅說明移送臂5G、52俾解釋本發明之具體例，但如業界人士眾所周知其絕非限制本發明。 | 然後其上含有光阻之晶圓移轉至軟烘烤單元38及於某種溫度烘烤因而去除光阻所需溶劑，及確保維持塗布預定厚度之塗布態。然後軟烘烤晶圓通過介面80移轉至曝光系統9〇曝光。曝光妥之晶圓通過晶圓緣曝光單元46及移送入pEB單元42 供改良圖樣外廓，改良方式係經由消除駐波效應產生之波圖樣，駐波效應發生於某種溫度烘烤及顯像後，由入射光及曝光光源之反射光之加強性干擾及破壞性干擾而於光阻圖樣發生。然後已經元成PEB之晶圓移入顯像單元44，顯像劑喷灑於晶圓表面而藉.曝光形成正或負光阻圖樣。此時光阻圖本紙張尺度適用中國國家標準（CNS〉A4規格（210'乂2州^_〉… --- ^ά------ΐτ-----ί ^ (請先閱讀背面之注意事項再填寫本頁) -14-The photoresist is preferably "line or deep ultraviolet (DUV), and the phase mask (PSM) is used in the case of i_line photoresist. The photoresist pattern is a contact hole pattern. The method of forming a semiconductor device pattern It is also included in the step of roasting money in the step of baking with ultraviolet light. The preferred ultraviolet light for baking is carried out by using ultraviolet light to irradiate the photoresist pattern and heating at the same time for the baking process. The heating temperature for the baking process is 50 to It is carried out at a temperature of 140 to 80 seconds, and the ultraviolet irradiation step is performed for 10 to 80 seconds. The processing temperature of the flow baking is 140 to 200. The range of (:, and the processing time of the flow baking is .80 to 120 seconds. IΓ ------------ -10- Jing Yi Department Shuang You 4, · ^ Di Gong consumer cooperation. #Print A7 (____________________________ 'B7 V. Description of the invention (8' flow Baking is repeated at least once. Another aspect of the method for forming a pattern of a semiconductor device includes the following steps: a) Conditioning the photoresist on a semiconductor substrate; ... soft baking the deposited photoresist 'c) aligning the photomask to pass Soft, baked green and exposure;… post-exposure of photoresist after exposure Baking (PEB); e) forming a photoresist pattern by developing and cleaning the photoresist passing through the PEB; f) hard baking photoresist pattern; developing the photoresist pattern through hard baking; The developed photoresist pattern is flow-baked. The photoresist is preferably used for wire lines and the photomask is a phase shift mask (PSM). The photoresist pattern can be a pattern of contact holes. It should be repeated at least twice. The processing temperature of automatic baking is preferably 140 to 20 ° C, and the flow baking can be performed for 80 to 120 seconds. It should be understood that the foregoing brief description and the detailed description below are only for the purpose of illustration. The drawings provide a further explanation of the patented invention. Brief description of the drawings In the drawings: Figure 1 shows the processing sequence of the conventional semiconductor device pattern formation; Figures 2 to 5 are sectional views showing the force according to Figure 1 The formation of the semiconductor device pattern in the process sequence; Figure 6 is a block diagram of the time. Shows a specific example of the semiconductor device manufacturing system according to the present invention; ', Figure 7 is a sectional view showing the semiconductor device manufacturing system of Figure 6 Purple first baking unit; ", $ paper rule Transfer (called Α · ^ (------ ^-(Please read the precautions on the back before filling out this page),-mouth line · A7 B7 is accessible 5. Question instructions (9) Figure 8 is The guarding sequence shows the formation of the device pattern according to the present invention; & Thousands of conductors Figures 9 to 12 are sectional views showing the formation of the f device pattern according to the processing sequence of Figure 8. For a detailed description of the preferred specific examples, refer to the attached The drawings illustrate the present invention more fully later, and the drawings show the preferred specific examples of the present invention. However, the present invention may be embodied in different forms and should not be regarded as being limited to the specific examples set forth herein; instead, these specific examples are provided to make it The disclosure is more thorough and complete, and more completely conveys the scope of the present invention to the industry. According to the present invention, a semiconductor device manufacturing system and a method for forming a semiconductor device pattern using the system are provided, in which a photoresist pattern on a semiconductor wafer is provided. After the imaging process of lithography, a small critical size is obtained by irradiation with ultraviolet light, thereby preventing the photoresist pattern from being distorted during the flow process, and the size of the desired pattern can be effectively obtained. Specific examples of the present invention will be described in detail later. Fig. 6 is a block diagram showing a specific example of a semiconductor device manufacturing system according to the present invention, and Fig. 7 is a sectional view showing an ultraviolet light unit equipped with the microwave laser lamp of Fig. 6. FIG. 6 shows that the semiconductor device manufacturing system 30 and the exposure device 90 are connected via an interface unit 80 on line. The semiconductor device manufacturing system 30 includes: a wafer load unit 32 loads a wafer cassette containing a wafer; an HMDS coating unit 34 for improving the adhesiveness of the photoresist sent from the carrier unit 32 # to the round surface of the wafer; the photoresist Coating unit 36 is suitable for paper size / fl China National Standard (CNS) A4 specification (21 × 297 mm) ^-Suppressing clothing ------, 玎 ------ 10 (Please read the back first Please note this page before filling in this page} Printed on the 12th Ministry of Economic Affairs and the Central Government Standards Cooperative Cooperative Association to print fi A7 B7 V. Instructions (10), " ~ '-Photoresist coated wafers containing HMDS; The image unit 44 is provided for the photoresist coating unit 36 to coat the wafer with the photoresist, and the photoresist pattern on the wafer is exposed after exposure of the photoresist on the wafer and the image is exposed. The baking unit 37 includes a soft baking unit% for removal. The solvent of the photoresist-containing wafer thereon, the pEB unit 42 is used to remove the fine standing waves existing on the photoresist pattern after the wafer containing the photoresist is exposed, and the hard baking unit 40 is used to harden the photoresist pattern; And the UV baking unit is used to irradiate the developed wafer with UV light, and to provide a stable flow during the flow processing of the photoresist pattern. The semiconductor device manufacturing system may be a rotator or a track system. In the semiconductor device manufacturing system, a wafer edge exposure unit is preferably provided for exposing a certain thickness of the wafer edge. As for the effective semiconductor assembly multiple process using the semiconductor device manufacturing system, The wafer load unit 32, the HMDS deposition unit 34, the photoresistance load unit 36 and the developing unit 44, the soft baking unit 38, the PEB unit 42, the hard baking unit 40 and the ultraviolet baking unit 48 are preferably installed separately. The number is at least one, in other words, the majority. Ί, the external light baking unit 48 includes an ultraviolet lamp to irradiate the upper part of the chamber to provide ultraviolet light, and a hot plate is erected at the lower part of the chamber to install a crystal at a certain distance from the ultraviolet lamp. The wafer is rounded and heated. The ultraviolet lamp is preferably a microwave laser lamp or a mercury-xenon arc lamp. Referring to the ultraviolet baking unit 48 having a microwave laser lamp 60, the ultraviolet baking unit 48 includes a microwave laser lamp 60 including a mercury bulb 62 having The UHF waveguide 61 and the reflecting mirror 63 are used to cover the mercury bulb 62 and to focus the ultraviolet light generated by the mercury bulb 62 on the wafer and the quartz plate by applying ultra-high frequency waves through the UHF waveguide 61. It is placed under the skin mirror 63, and the hot plate 70 is used for mounting the wafer 68. The distance from the microwave to the paper ruler is suitable for China National Standard (CNS) A4 (210X297 mm) ---------- -. Equipment ------ Order 丨, ------ line (please read the precautions on the back before filling in this page) Fifth, the description (11)-a distance between the laser light 60 and the heating wafer 68. # 晶 _ is installed on the hot plate 70, the UHF waveguide 61 applies energy to the mercury bulb 62 containing mercury, Mercury converts to a plasma state and generates ultraviolet light. The reflections reflect the ultraviolet light scattered in various directions to make the ultraviolet light effective I reach the wafer 68. The operation of the semiconductor device manufacturing system 3G of the present invention will be described. First, when the card E containing the wafer is loaded on the wafer load unit 32, the wafer is transferred to the HMDS deposition unit 34 by the first transfer arm 50. Some thick-production HMDS is deposited on the wafer inside the HMDS deposition unit 34 and thus: #wafer is coated with photoresist. Then the wafer with the HMDS attached thereto is transferred to the photoresist coating unit 36 by the second transfer arm 52, so the wafer surface is coated with a special process photoresist. Only the transfer arms 5G, 52 'are explained to explain specific examples of the present invention, but as the person skilled in the art knows, it is by no means a limitation on the present invention. | Then the wafer containing the photoresist is transferred to the soft baking unit 38 and baked at a certain temperature to remove the solvent required for the photoresist, and to ensure that the coating state is maintained at a predetermined thickness. The soft-bake wafer is then transferred through the interface 80 to the exposure system 90 for exposure. The exposed wafer passes through the wafer edge exposure unit 46 and is transferred to the pEB unit 42 to improve the pattern outline. The improvement method is to eliminate the wave pattern generated by the standing wave effect. The standing wave effect occurs at a certain temperature for baking and imaging. Later, the enhanced interference and destructive interference of the incident light and the reflected light of the exposure light source occur in the photoresist pattern. Then the wafer that has been converted into PEB is moved into the developing unit 44 and the developer is sprayed on the wafer surface to form a positive or negative photoresist pattern by exposure. At this time, the paper size of the photoresist chart is in accordance with the Chinese national standard (CNS> A4 specification (210 '乂 2 states ^ _> ... --- ^ ά ------ ΐτ ----- ί ^ (Please read the back first) (Notes on this page, please fill out this page) -14-

發明説明經濟部中夾榇率扃只工消价合作社印繁樣之臨界尺寸比預定者更長。 ';後Ba圓移送人紫外光烘烤單元48，紫外光照射於光，圖樣及進行熱板之供烤製程，因而於光阻内部同時發生 3C聯反應及流動加卫’如此達成光阻圖樣比較顯像後之圖樣尺寸更小。前述半導體震置製造系統之各個單元可以不同方式對正以求備刹辟一單兀加工單元可垂直對正俾增加半導體裝置製程工廠内部占有之空間效率，此點乃業界人士顯然易明。本發月之主要特點係提供於習知旋轉器或軌道系統之紫外光烘烤單元48,但紫外光烘烤單元料之所在位置非僅限於此處陳述之。紫外歧烤單元_係於顯像後以製程循序，序進行故設置成接近顯像單元44。 -开/成光阻圖樣之晶圓通過含紫外光顯像單元料之半導體裝置製造系統，及移送至_系統供隨後加工。然後裝置圖樣係經由使用光阻圖樣作為_罩蝴晶圓亞層形成。别述裝置圖樣之形成係於進行紫外光供烤及對顯像形成之光阻圖樣進行流動烘烤及㈣亞層後完成。可使用其中配備有紫外光烘烤單元之蝕刻系統。因此姓刻系統之構造可包括紫外光供烤單元供照射紫二光於晶圓’及供給光阻圖#之穩定流動加工，及加工腔室安裝於接近料光烘烤單元供使用光阻圖祕刻晶圓亞層。較佳紫外光烘烤單元及加工腔室係透過載荷問本紙張尺度逃用中國國家標準（CNS ) A4規格（210X297公釐）私衣— (請先聞讀背面之注意事項再填寫本頁) 訂線 -15 - A7 B7 五、發明説明（l3 第8圖為加:L順序顯示根據本發明之具體例之半導體裝置圖樣之形成。 _第圖所不，於顯像及清潔後形成光阻圖樣且可由後述三種順序中選用任—種。二種順序標示為A、B及C。首先說明A順序後說明B 及C，但也可刪除A順序。首先說明A加工順序’至於以光阻塗布晶圓之步驟 (S20) ’晶圓塗布以i-線光阻。」後作為軟烘烤晶圓上丨-線光阻之步驟（S22)，光阻之 /合劑藉軟烘烤去除，及i_線光阻之黏著性亦改良。繂後至於對正光罩於已經完成軟烘烤之光阻及曝光步驟（S24) ’附有卜線沉積其上之晶圓移送入“線步進器，晶圓經由對正其上成形有細微接觸孔圖樣之PSM於晶圓，及使用1_線光透過PSM照射晶圓而曝光。然後進行曝光妥晶圓之PEB(S26)供？文良光阻圖樣之圖樣外廓及圖樣解析度，改良方式係去除由於來自光源之入射光與反射光之加強性干擾與破壞性干擾造成駐波而於晶圓表面產生之波圖樣之去除。然後已經完成PEB之晶圓經顯像及清潔，形成光阻圖樣（S28)。換言之，PEB後之晶圓移動至顯像系統，顯像劑供給於光阻上’形成光阻圖樣’然後使用清潔液去除顯像副產物。然後呈於紫外光烘烤光阻圖樣步驟（S32)，光阻圖樣本紙張尺度適用中國國家標準（CMS ) A4規格（210X297公釐） L--淋衣------、玎------線 (請先聞讀背面之注意事項再填寫本頁〕經濟部中央栳準杓只工消轮合作社印掣 -16- Α7 Β7 五、發明説明（Η 燈施熱照射，於光阻内部發生交聯反應，故光阻圖定性改良’於流動加工期間於溫度增高情況下可 :持穩態。紫外光烘烤製程包含照射紫外光於紗圖樣，及施熱’二者係同時進行。或於照射紫外光後，獨立施熱〇 "然後至於紫外光烘烤後之流動供烤步驟（S36)，於高於先阻軟化點之溫度施熱於光_樣俾減少高度聚合光阻之軟^及黏度，因而光阻圖樣之流動使圖樣尺寸變小。此外，兩密度圖樣單位部與低密度圖樣周緣部間之流動差異變乍，故可於晶圓上均勻形成光阻圖樣。 ^時B製程順序又包含於續程順序之紫外光供烤 ⑻2),於光阻圖樣進行硬供烤步驟（㈣)俾提供更穩定流動加工。 5時，於C製程順序，A製程順序之S32步驟被刪除，其中光阻圖樣經紫外光烘烤俾經由光阻内部之交聯反應供光阻圖樣之熱穩定性，及使光阻對流動加工期間之溫度升高較不敏感。替代S32，循序進行硬烘烤（S33)及幻4步驟，其中硬烘烤妥之晶圓以S28顯像步驟使用之相同顯像齊J處理換δ之，於C製程順序中，藉顯像過程形成之光阻圖樣以顯像劑處理而改變光阻性質及達成與前述紫外光烘烤所達成之相同性質。第9至12圖為剖面圖顯示經由使用線光阻及第8圖之 PSM藉流動方法形成接觸孔圖樣，特別示例說明a製程。如第9圖所示’ 線光阻16塗布晶圓12，晶圓12表面本紙張尺度適用中國ϋ家操準（CNS )八4規格⑺似297公麓） ----------私衣！ (請先閲讀背面之注意事項再^寫本頁) 之、\=口經¾部中央標準而只工消费合作社印製 ί ^---------Description of the invention The critical size of the rate of printing in the Ministry of Economic Affairs is only longer than the intended size. '; The back Ba circle is transferred to the ultraviolet baking unit 48, the ultraviolet light is irradiated to the light, the pattern and the baking process of the hot plate are performed, so the 3C reaction and the flow protection are simultaneously performed inside the photoresist. The size of the pattern after comparison is smaller. Each unit of the aforementioned semiconductor vibration manufacturing system can be aligned in different ways to prepare for a brake. A single processing unit can be vertically aligned to increase the space efficiency occupied by the semiconductor device manufacturing plant. This is obviously easy for people in the industry to understand. The main features of this month are provided in the conventional UV baking unit 48 of the conventional spinner or rail system, but the location of the UV baking unit is not limited to those stated here. The UV-curing unit_ is set in order to be close to the developing unit 44 after the development process in order. -The on / off photoresist patterned wafer is passed through a semiconductor device manufacturing system containing ultraviolet light development unit material, and transferred to the system for subsequent processing. The device pattern is then formed by using a photoresist pattern as the wafer sublayer. The formation of the device pattern is completed after the ultraviolet light is baked and the photoresist pattern formed by the development is flow-baked and the sublayer is completed. An etching system equipped with a UV baking unit can be used. Therefore, the structure of the engraving system can include a UV light for the baking unit to irradiate the purple light on the wafer and a stable flow processing of the photoresist pattern, and the processing chamber is installed near the light-baking unit for the photoresist pattern. Secret wafer sublayer. The preferred UV light baking unit and processing chamber use the paper size to avoid the use of Chinese National Standard (CNS) A4 specifications (210X297 mm). Clothing — (Please read the precautions on the back before filling this page) -15-A7 B7 V. Description of the Invention (l3 Figure 8 shows the formation of the semiconductor device pattern according to the specific example of the present invention in the order of L: _. The photo resist is formed after development and cleaning. The pattern can be selected from any of the three sequences described below. The two sequences are labeled A, B, and C. First explain the A sequence and then explain B and C, but you can also delete the A sequence. First explain the A processing sequence. As for photoresist The step of coating the wafer (S20) 'The wafer is coated with an i-line photoresist.' After that, as a step (S22) of the photo-resistance on the soft-baking wafer, the photoresist / mixture is removed by soft baking. The adhesion of the photoresist and i_line photoresist is also improved. Afterwards, as for the photoresist and exposure step of the alignment mask after the soft baking has been completed (S24), the wafer with the Bu line deposited thereon is transferred to the "line step Device, the wafer is aligned on the wafer via a PSM with a fine contact hole pattern formed thereon, and Use 1_line light to expose the wafer through the PSM to expose it. Then the PEB (S26) of the exposed wafer is provided for the pattern outline and pattern resolution of the Wenliang photoresist pattern. The improvement method is to remove the incident light from the light source and the The enhanced interference and destructive interference of the reflected light caused the removal of the wave pattern generated on the wafer surface by the standing wave. Then the PEB wafer was developed and cleaned to form a photoresist pattern (S28). In other words, after PEB The wafer is moved to the imaging system, and the developer is supplied to the photoresist to 'form a photoresist pattern' and then the cleaning by-products are removed using a cleaning solution. Then, the photoresist is subjected to a UV baking pattern step (S32), and the photoresist is The paper size of the drawing sample is applicable to the Chinese National Standard (CMS) A4 specification (210X297 mm). L--Lichen -------- 、玎 ------ line (please read the precautions on the back before filling in this Page] Central Government of the Ministry of Economic Affairs 栳杓消 -16- Α7 Β7 V. Description of the invention (Η The lamp is exposed to heat and cross-linking occurs inside the photoresist, so the photoresist diagram is qualitatively improved. During the increase in temperature during the period can be: steady state. The external light baking process includes irradiating ultraviolet light on the yarn pattern and applying heat both at the same time. Or, after the ultraviolet light is irradiated, the heat is applied separately. Then, the flow is provided for baking after the ultraviolet light is baked (S36 ), Heating at the temperature above the softening point of the first resist reduces the softness and viscosity of the highly polymerized photoresist, so the flow of the photoresist pattern reduces the size of the pattern. In addition, the unit area of the two-density pattern and the low The difference in flow between the peripheral portions of the density pattern changes, so that a photoresist pattern can be formed uniformly on the wafer. ^ The B process sequence is also included in the UV sequence for the baking sequence. 2) The hard pattern is baked on the photoresist pattern. Step (i) 俾 provides more stable flow processing. At 5:00, the S32 step of the A process sequence is deleted in the C process sequence, and the photoresist pattern is baked by ultraviolet light. The photoresist pattern is thermally stabilized by a cross-linking reaction inside the photoresist, and the photoresist is allowed to flow. Temperature increases during processing are less sensitive. In place of S32, the hard baking (S33) and magic 4 steps are performed sequentially. The hard baked wafer is processed with the same imaging used in the S28 imaging step. J is processed for δ. In the C process sequence, the imaging is performed by imaging. The photoresist pattern formed in the process is treated with a developer to change the photoresist properties and achieve the same properties as those achieved by the aforementioned ultraviolet baking. Figures 9 to 12 are cross-sectional views showing contact hole patterns formed by the flow method using a line photoresist and PSM of Figure 8, and a particular example illustrates the a process. As shown in Figure 9, 'Line photoresist 16 is used to coat wafer 12, and the surface of the wafer 12 is in accordance with China Paper Standard (CNS) 8-4 specifications (like 297 feet) --------- -Private! (Please read the notes on the back before ^ writing this page), \ = Oral and printed by ¾ central standard and printed only by consumer cooperatives ί ^ ---------

I —II —-II I « .I —II —-II I «.

I A7B7 I,部—蒙f S—作社— 五、發叨説明（1S ) 上形成亞層14 ,及於80至12〇t溫度軟烘烤5〇至1〇〇秒。軟 =烤去除i-線光阻16所含溶劑而維持丨_線光阻16之烘烤狀恝具有某種厚度。軟烘烤所需加工溫度為9〇至丨丨〇。〇。然後如第10圖所不，晶圓12移動至卜線步進器，其上形成有細微接觸孔圖樣之PSM 17對正i_線妹16而使用卜線光進行曝光。然後如第11圖所示，於曝光妥之晶圓12於1〇〇至14〇它咖度進仃PEB歷50至100秒。然後進行顯像及清潔製程，形成第-接觸孔18。進行PEB俾經由去除存在於光阻圖樣上細微駐波改良圖樣外廓，及改善圖樣解析度。此時第一接觸孔圖樣18之尺寸為0.28微米，晶圓12表面之第一接觸孔18之均勻度不佳。然後如第12圖所示，於第一接觸孔圖樣18循序進行紫外光烘烤及流動烘烤而形成尺寸比第一接觸孔圖樣18小〇.2〇微米之第二接觸孔圖樣2〇。紫外光烘烤係藉照射紫外光之同時施熱而於第—躺孔圖樣18進行。紫外光照射進。订歷10至80純佳10至5G秒。加熱輯溫度較料5〇至 c，及更佳11 〇 C。換言之，第一接觸孔圖樣〗8藉紫外光照射及烘烤而熱穩定化’及與第一接觸孔圖樣18内側出現交聯反應。然後於紫外光供烤後，終止照射紫外光，及於相同腔室或移動入個別烘烤腔室後對晶圓於〗40至200。匸溫度進行流動烘烤歷80至120秒。結果形成第二接觸孔2〇。流動烘烤之較佳加’工溫度為170至19〇。〇：。流動烘烤中其可防止光本紙張緖準（CNS) ^JY^._X297公董） -—~- "18- -------^^— (請先閱讀背面之注意事項再填寫本頁)I A7B7 I, Ministry-Mongolian f S-Zuosha-V. Description of the hair bun (1S) A sub-layer 14 is formed, and soft-baked at a temperature of 80 to 120 t for 50 to 100 seconds. Soft = baking removes the solvent contained in i-line photoresist 16 and maintains the baking state of __line photoresist 16 恝 has a certain thickness. The processing temperature required for soft baking is between 90 and 丨丨. 〇. Then, as shown in FIG. 10, the wafer 12 is moved to a line stepper, and a PSM 17 with a fine contact hole pattern formed thereon is exposed to the positive i_line girl 16 using line light. Then, as shown in FIG. 11, the exposed wafer 12 is subjected to a PEB for 50 to 100 seconds from 100 to 140. Then, development and cleaning processes are performed to form the first contact hole 18. PEB is used to improve the outline of the pattern by removing the fine standing waves existing on the photoresist pattern, and to improve the resolution of the pattern. At this time, the size of the first contact hole pattern 18 is 0.28 m, and the uniformity of the first contact hole 18 on the surface of the wafer 12 is not good. Then, as shown in FIG. 12, ultraviolet light baking and flow baking are sequentially performed on the first contact hole pattern 18 to form a second contact hole pattern 20 which is 0.2 μm smaller in size than the first contact hole pattern 18. Ultraviolet light baking is performed on the first-lying hole pattern 18 by applying heat while irradiating ultraviolet light. Ultraviolet light shines into the. Schedule 10 to 80 pure good 10 to 5G seconds. The heating temperature is 50 to c, and more preferably 110 ° C. In other words, the first contact hole pattern 8 is thermally stabilized by ultraviolet light irradiation and baking, and a cross-linking reaction occurs with the inside of the first contact hole pattern 18. Then, after the ultraviolet light is provided for baking, the irradiation of ultraviolet light is stopped, and the wafer is processed at 40 to 200 in the same chamber or moved into a separate baking chamber.匸 Temperature bake for 80 to 120 seconds. As a result, a second contact hole 20 is formed. The preferred processing temperature for flow baking is 170 to 190. 〇 :. It can prevent light paper (CNS) in mobile baking (CNS) ^ JY ^ ._ X297 public director) -—— ~-" 18- ------- ^^ — (Please read the precautions on the back before (Fill in this page)

、1T ^II---------, 1T ^ II ---------

J A7 B7 五、發叨説明（16 ) , ~— 阻圖樣扭曲之本體效應，該效應之發生原因為密集圖樣部分與稀少圖樣部分間之高度聚合光阻之流動差異所致。結果尺寸比曝光波長亦即〇.20微米或以下更小的第二接觸孔 2〇可遍佈晶圓表面12形成。流動烘烤依據光阻種類及流動量而定至少進行一次。因此根據本發明，經由於光阻圖樣形成後以紫外光照射於光阻圖樣及對南度聚合光阻進行交聯反應俾穩定光阻 …、女疋丨生，可達成尺寸比曝光波長更小的均勻光阻圖樣，且防止於其次流動製程產生本體效應。本體效應為由於稠密圖樣部分與稀疏圖樣部分間之流動差導致光阻圖樣扭曲現象。業.界人士顯然易知可未悖離本發明之精髓及範圍對本發明做出多種修改及變化。如此意圖本發明涵蓋落入隨附之申睛專利範圍及其相當範圍之本發明之修改及變化。 -------卜丨裝------訂-----：1線 (請先閱讀背面之注意事項再填寫本頁) 經M·部中央梂ai'-^isc工消費合作社印掣 :用通尺張紙 I本準標家國祕 I釐公 97 -19- 經濟部中央摇率工消費合作社印製 A7 B7 五、發明説明（W ) ，元件標號對照 2…晶圓 44... ，顯像單元 4...亞層 46... ，晶圓緣烘烤單元 6...i線光阻 48... ，紫外光烘烤單元 7...PSM，相移阻罩 50... .第一移送臂 8...第一接觸孔圖樣 52... .第二移送臂 9...第二接觸孔 60... .微波激光燈 30…半導體裝置製造系統 61... .超Γ§3頻波導 32...晶圓載荷單元 62... ,汞燈泡 34··.HMDS塗布單元 63... .反射鏡 36...光阻塗布單元 68... .晶圓 37...烘烤單元 70... .熱板 38…軟烘烤單元 80... .介面裝置 40…硬烘烤單元 90... .曝光裝置 42...後曝光烘烤單元批农訂線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐)J A7 B7 Fifth, explanation (16), ~~ The main effect of the distortion of the resist pattern is caused by the difference in the flow of the highly condensed photoresistance between the dense pattern part and the sparse pattern part. As a result, the second contact hole 20 having a size smaller than the exposure wavelength, that is, 0.20 μm or less, may be formed all over the wafer surface 12. Flow baking is performed at least once depending on the type of photoresist and the amount of flow. Therefore, according to the present invention, after the photoresist pattern is formed, the photoresist pattern is irradiated with ultraviolet light and the cross-linking reaction of the southern polymerization photoresist is performed to stabilize the photoresist ... Uniform photoresist pattern and prevent bulk effect in the next flow process. The ontological effect is the distortion of the photoresist pattern due to the flow difference between the dense pattern part and the sparse pattern part. It will be apparent to those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention. It is thus intended that the present invention cover modifications and variations of the present invention which fall within the scope of the accompanying patent and its equivalents. ------- Bu 丨 Installation -------- Order -----: 1 line (please read the precautions on the back before filling this page) Consumption Cooperative Print: Use a ruled sheet of paper, a standard bidder, the National Secret Secretary, and I. 97-19 -19- Printed by the Central Government of the Ministry of Economic Affairs and Consumer Cooperatives A7 B7 V. Description of the invention (W), component number comparison 2 ... Circle 44 ..., development unit 4 ... sublayer 46 ..., wafer edge baking unit 6 ... i-line photoresist 48 ..., ultraviolet light baking unit 7 ... PSM, Phase shift cover 50 .... First transfer arm 8 ... First contact hole pattern 52 .... Second transfer arm 9 ... Second contact hole 60 ... Microwave laser lamp 30 ... Semiconductor Device manufacturing system 61 .... Super § 3 frequency waveguide 32 ... Wafer load unit 62 ..., Mercury bulb 34 ... HHMDS coating unit 63 ... Reflector 36 ... Photoresist coating Units 68 ... Wafer 37 ... Baking unit 70 ... Hot plate 38 ... Soft baking unit 80 ... Interface device 40 ... Hard baking unit 90 ... Exposure device 42. .. Post-exposure baking unit batch farm line (please read the precautions on the back before filling this page) This paper size applies Chinese national standards CNS) A4 size (210X297 mm)

Claims

申請專利範園 h —種半導體裝置製造系統包含：一個光阻塗布單元供以適當光阻塗布由晶圓載荷單元移送之晶圓； —個顯像單元供於塗布有光阻之晶圓上形成光阻圖樣，其形成方式係經由對正光罩於晶圓，曝光晶，及顯像曝光後之晶圓；及。個务外光烘烤單元供以紫外光照射顯像後之圓俾於光阻圖樣流動製程中導引穩定流動。 2. 如申請專利範圍第i項之半導體裝置製造系統，其特為旋轉器或執道系統。 3. 如申請專利範圍第1項之半導體裝置製造系統，其又含·：圓曰曰徵包 --------AI- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製個HMDS塗布單元供提高光阻於由晶圓載荷單元移送之晶圓表面之黏著性；一個烘烤單元供烘烤其上有光阻之晶圓，及通過曝光及顯像；及一個晶圓邊緣曝光（WEE)單元供以某種厚度曝光晶圓緣部。 4·如申請專利範圍第3項之半導體裝置製造系統，其包含、晶圓載荷單元、HMDS塗布單元、光阻塗布單元、塗布早το、烘烤單元、晶圓緣曝光單元及紫外光烘烤單元中之至少一者。 s’如申請專利範圍第3項之半導體裝置製造系統，其中該烘烤單元包含·· -訂· -21 - 申請專利範園 A8 B8 C8 D8 經濟部中央操準局員工消費合作社印製 —個軟烘烤單元供去除包含於晶圓上光阻之溶劑 7 —個後曝光烘烤（PEB)單元供去除存在於光阻圖樣之駐波等；及 —個硬烘烤單元供硬化光阻圖樣。 6·如申請專利範圍第](項之半導體裝置製造系統，其中赛紫外光烘烤單元包含：一盞紫外燈置於紫外處棋烤單元上部及產生紫外光；及 t熱板置於紫外光烘烤單元下部，及加熱安裝成與紫外燈有某種距離之晶圓。 7·如申請專利範圍第6項之半導體裝置製造系統，其中該紫外燈為微波激光燈或汞_氙燈。 8· 一種半導體裝置製造系統包含：一個紫外光烘烤單元供以紫外光照射通過顯像之晶圓俾於光阻圖樣之流動加工期間導引穩定流動於晶圓；及 .. 一個加工腔室設置於接近紫外光烘烤單元，及使用光阻圖樣作為蝕刻阻罩進行晶圓上亞層之蝕刻加工 9.如申請專利範圍第8項之半導體裳置製造系統，其中紫外光供烤單元及加工腔室係透過載荷閘室聯結。1〇·如申請專利範圍第8項之半導體裝置製造系統，其中該免外光供烤單元包含：該 --------：^------訂------ 線 (請先聞讀背面之注意事項再填寫本頁)Patent application park h-A semiconductor device manufacturing system includes: a photoresist coating unit for coating a wafer transferred from a wafer load unit with an appropriate photoresist;-a developing unit for forming on a wafer coated with photoresist The photoresist pattern is formed by aligning the mask on the wafer, exposing the crystal, and developing the exposed wafer; and The external light baking unit is used to guide the stable flow in the photoresist pattern flow process after the ultraviolet rays are irradiated and developed. 2. If the semiconductor device manufacturing system of item i of the patent application scope is a rotator or a track system. 3. For the semiconductor device manufacturing system under the scope of patent application No. 1, it also contains :: Round signing contract -------- AI- (Please read the precautions on the back before filling this page) Ministry of Economic Affairs The Central Standards Bureau employee consumer cooperative prints a HMDS coating unit to improve the adhesion of the photoresist to the surface of the wafer transferred by the wafer load unit; a baking unit is used to bake the wafer with the photoresist on it, and through exposure And development; and a wafer edge exposure (WEE) unit for exposing the wafer edge with a certain thickness. 4. The semiconductor device manufacturing system according to item 3 of the scope of patent application, which includes, a wafer load unit, an HMDS coating unit, a photoresist coating unit, a coating early το, a baking unit, a wafer edge exposure unit, and ultraviolet light baking. At least one of the units. s' For example, the semiconductor device manufacturing system in the third scope of the patent application, wherein the baking unit contains ··-order · -21-patent application Fanyuan A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Office of the Ministry of Economic Affairs Soft baking unit for removing the photoresist contained in the wafer 7-Post-exposure baking (PEB) unit for removing the standing wave existing in the photoresist pattern; and-Hard baking unit for hardening the photoresist pattern . 6. The semiconductor device manufacturing system according to item [] in the patent application scope, wherein the ultraviolet baking unit includes: an ultraviolet lamp is placed on the upper part of the chess baking unit and generates ultraviolet light; and a hot plate is placed on the ultraviolet light The lower part of the baking unit, and the wafer installed to be heated at a certain distance from the ultraviolet lamp. 7. The semiconductor device manufacturing system according to item 6 of the patent application scope, wherein the ultraviolet lamp is a microwave laser lamp or a mercury-xenon lamp. 8 · A semiconductor device manufacturing system includes: an ultraviolet light baking unit for irradiating ultraviolet light through a developed wafer and guiding a stable flow on the wafer during the flow processing of the photoresist pattern; and a processing chamber provided in Close to the ultraviolet baking unit, and use the photoresist pattern as an etching mask to etch the sub-layers on the wafer. 9. For example, the semiconductor rack manufacturing system of the patent application No. 8 in which the ultraviolet light is used for the baking unit and processing cavity. The chambers are connected through a load lock chamber. 10. If the semiconductor device manufacturing system according to item 8 of the patent application scope, wherein the external light-free baking unit includes: The --------: ^ ----- - ------ line (please read the Notes on the back of the smell and then fill the page)

A4規格（210X297公釐） — — -22-A4 specification (210X297 mm) — — -22-

中讀專利範圍趣濟部中夫祿率局WT工靖t合作衽印製一盞紫外燈置於紫外光烘烤單元上部及產生紫外光；及熱板置於紫外光烘烤單元下部，及加熱安裝成與紫外燈有某種距離之晶圓。 k如申請專利範圍第10項之半導體裂置製造系統，其中該紫外燈為微波激光燈或汞_氣燈。 2’種形成半導體裝置圖樣之方法包含下列步驟： a) 以光阻塗布晶圓； b) 軟烘烤於晶圓之光阻； c) 對正光罩於通過軟烘烤之光阻及進行曝光； d) 對通過曝光之光阻進行後曝光烘烤(pEB); .e)經由顯像及清潔通過pEB之光阻而形成光阻圖樣； 0對光阻圖樣進行紫外光烘烤；及 g)對紫外光烘烤後之光.阻圖樣進行流動烘烤。 13‘如申請專利範圍第H)項之形成半導體裝置圖樣之方法，其中該光阻係用於i-線或深部紫外光（DUV)。 14 ·如申請專利範圍第13項之形成半導體裝置圖樣之方法 ’其中該光罩於使用i ·線光阻之例使用相移阻罩（p s M) ο 1Τ-----; 10 (請先閲讀背面之注意事項再填寫本頁) 15.如申請專利《第12項之形成半導體裝置圖樣之方法 .，其中該光阻圖樣為接觸孔圖樣。 16·如申請專利範圍第12項之形成半導體裝置圖樣之方法 ’其又包含於騎紫外光供烤步㈣之硬烘烤步驟。The scope of the Chinese patents is in cooperation with the Ministry of Economic Affairs and China ’s Fulu led the Bureau of WT and Jingtung to print a UV lamp placed on the upper part of the UV baking unit and generate UV light; and a hot plate placed on the lower part of the UV baking unit, and Wafers mounted at a distance from the UV lamp. k The semiconductor split manufacturing system according to claim 10, wherein the ultraviolet lamp is a microwave laser lamp or a mercury-gas lamp. 2 'A method for forming a pattern of a semiconductor device includes the following steps: a) coating a wafer with a photoresist; b) photoresist for soft baking on a wafer; c) exposing a photomask to the photoresist through soft baking and exposing D) post-exposure baking (pEB) of the photoresist that passed through the exposure; .e) forming a photoresist pattern by developing and cleaning the photoresist passing through the pEB; 0 UV baking of the photoresist pattern; and g ) Flow bake the light-resistance pattern after UV light baking. 13 ′ The method for forming a pattern of a semiconductor device as described in the scope of the patent application item H), wherein the photoresist is used for i-line or deep ultraviolet (DUV) light. 14 · Method for Forming a Pattern of a Semiconductor Device as in Item 13 of the Patent Application 'where the photomask uses i. For example, a line photoresist uses a phase shift mask (ps M) ο 1Τ -----; 10 (Please (Please read the notes on the back before filling in this page) 15. If you apply for the patent "Method of Forming a Semiconductor Device Pattern," the photoresist pattern is a contact hole pattern. 16. The method for forming a pattern of a semiconductor device as described in item 12 of the scope of patent application, which further includes a hard baking step of riding ultraviolet light for a baking step.

-23- 經濟部中央標準局員工消費合作社印裝 A8 B8 C8 D8 六、申請專利範圍， !7_如申料#11範Uj扣項之形成半導錄置圖樣之方法其中該务外光烘烤係藉使用紫外光照射光阻圖樣及同時加熱進行烘烤製程進行。 18.如申請專利範圍第17項之形成半導體裝置圖樣之方法其中加熱進行烘烤製程之加工溫度為5〇至14〇艺。 .19.如切專利_第17項之形成半導财置圖樣之方法 /、中"亥各外光照射之步驟係進行歷1 〇至8〇秒。 20. 如申請專利範圍第12項之形成半導體裝置圖樣之方法 ’其中該流動烘烤之加工溫度為140至20(TC之範圍。 21. 如申請專利範圍第12項之形成半導體裝置圖樣之方法，其中流動烘烤之加工時間為80至120秒之範圍。 22·如申明專利範圍第12項之形成半導體裝置圖樣之方法 ’其中流動烘烤係至少重複進行一次。 23. 種形成半導體裝置圖樣之方法包含下列步驟： a) 沉積光阻於半導體基材上； b) 軟烘.烤經過沉積之光阻； -c)對正光罩以經過教供烤之光阻及進行曝光； d) 對曝光後之光阻進行後曝光烘烤（ppB); e) _由顯像及清潔通過PEB之光阻而形成光阻圖樣； ,0硬烘烤光阻圖樣； g) 對通過硬烘烤之光.阻圖樣進行顯像；及 h) 對通過顯像之光阻圖樣進行流動烘烤。 24. 如申請#利範圍第23項之形成半導體裝置圖樣之方法本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公金） (請先閱讀背面之注意事項再填寫本頁) -裝. -Γ線 1 A8 B8 C8 ---------08_ 六、申請專利範圍，，其中該光阻係用於i-線。 25. 如申請專利範圍第23項之形成半導體裝置圖樣之方法，其中該光罩為相移阻罩(PSM)。 26. 如申請專利範圍第23項之形成半導體裝置圖樣之方法，其中該光阻圖樣為接觸孔圖樣。 27. 如申請專利範圍第23項之形成半導體裝置圖樣之方法、’其中該通過硬烘烤之光阻麗樣之顯像係重複至少進行兩次。 . 28·如申請專利範圍第23項之形成半導體裝置圖樣之方法 ’其中該流動烘烤之加：ί；溫度係於14〇至200。(：之範圍〇 29.如申請專利範圍第28項之形成半導體裝置圖樣之方法 ’其中該流動烘烤係進行80至120秒時間。裝訂~~ 線 (請先閲讀背面之注$項再填寫本頁) 經濟部中央標準局買工消費合作社印製本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-23- Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. The scope of patent application, such as the method of forming a semi-conductive recording pattern for the application of # 11 范 Uj deductions The baking process is performed by irradiating the photoresist pattern with ultraviolet light and heating at the same time. 18. The method for forming a pattern of a semiconductor device according to item 17 of the scope of the patent application, wherein the processing temperature for heating and baking is 50 to 140 art. .19. The method of forming the semi-conductive wealth pattern according to the patent of No.17 / / "The step of irradiating the external light of Haige is performed for 10 to 80 seconds. 20. The method for forming a pattern of a semiconductor device as described in item 12 of the patent application, wherein the processing temperature of the flow baking is in the range of 140 to 20 ° C. 21. The method of forming the pattern of a semiconductor device as described in item 12 of the patent application. Among them, the processing time of flow baking is in the range of 80 to 120 seconds. 22 · As stated in the patent scope of the method of forming a semiconductor device pattern 'wherein the flow baking is repeated at least once. 23. Forming a semiconductor device pattern The method includes the following steps: a) depositing a photoresist on a semiconductor substrate; b) soft baking. Baking the deposited photoresist; -c) aligning the photomask with the photoresist for teaching and exposure; d) Post-exposure photoresist is subjected to post-exposure baking (ppB); e) _ forming a photoresist pattern by developing and cleaning the photoresist through the PEB;, 0 hard-bake photoresist pattern; g) for hard-bake Develop the photoresist pattern; and h) flow bake the photoresist pattern that passed through the development. 24. If you apply for the method of forming the semiconductor device pattern in # 23 of the scope of this application, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 gold) (Please read the precautions on the back before filling this page)-Installation.- Γ line 1 A8 B8 C8 --------- 08_ 6. The scope of patent application, where the photoresist is used for i-line. 25. The method for forming a semiconductor device pattern according to item 23 of the patent application, wherein the photomask is a phase shift mask (PSM). 26. The method for forming a pattern of a semiconductor device according to item 23 of the patent application, wherein the photoresist pattern is a contact hole pattern. 27. If the method for forming a semiconductor device pattern according to item 23 of the patent application, wherein the development of the photoresist pattern by hard baking is repeated at least twice. 28. The method for forming a pattern of a semiconductor device as described in the scope of patent application No. 23, wherein the flow baking is added: ί; the temperature is between 14 and 200. (: Scope 〇29. The method of forming a semiconductor device pattern according to item 28 of the patent application 'wherein the flow baking is performed for 80 to 120 seconds. Binding ~~ Line (Please read the note on the back before filling in (This page) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed in accordance with Chinese National Standard (CNS) A4 (210X297 mm).