TW388967B - Semiconductor device - Google Patents

Abstract

To cut fuses with high accuracy, in a semiconductor device having fuses to be laser-trimmed. And, to reduce the area of a laser trimming positioning pattern occupied in the scribe line. The laser trimming positioning pattern has a boundary between the high light reflectivity region and the low reflectivity region, I.e., the area having a light reflectivity abruptly varies, which can be defined by a pattern formed by a thin film same as a laser trimming fuse element. Further, showing was made for the preferred relationship between the inner dimension of the laser trimming positioning pattern and the laser beam spot diameter. Also, the laser trimming positioning pattern can be formed in existing pad areas within a semiconductor integrated circuit chip, or placed at intersections between the scribe lines as a continuous structure used both as a theta mark function for comparatively rough positioning with respect to a semiconductor wafer rotating direction and as a trimming mark function for accurately positioning one by one semiconductor integrated circuits placed in repetition, thereby reducing the occupying area.

Description

經淨-部中央標59-局只工消费合作社印^ A7 ______H7 五、發明説明（1 ) 發明背景 本發明係關於半導體裝置，其具有定位圖型以藉著雷 射光束照射切割形成在半導體晶片上之結合元件。 在類比半導體積體電路裝置中，存在著用以調節類比 特性之習知的雷射修正方法。舉例而言，日本專利公開公 報第H5-1 3670號即有說明》積體電路係二維地印 製於半導體晶圓上，隨後在晶圓狀態上做各種積體電路電 子特性之測量。然後選擇互相連結之結合元件群以調節類 比特性並藉由·照射雷射光束以切割它們。此雷射修正方法 透過選擇性地切割結合元件可使積體電路類比特性調節至 所需之特性。半導體晶圓表面上有定位圖型以便照射雷射 光束至預定的結合元件上。圖3 ( a〉係習知的定位圖型 之平面圖，圖3 ( b )係習知的定位圖型之剖面圖，而圖 3 ( c )係顯示以光束沿著c — C /線之方向掃描定位圖 型所呈現之光反射量之變動。如圖3 ( a )中所示，習知 的定位圖型包含在畫線區域2 0 3中之用以比較粗糙地定 位於半導體晶圓轉動方向之所謂theta標誌，以及用以精確 地依序定位重複安置之半導體積體電路晶片2 0 1之X方 向修正標誌3 0 2及Y方向修正標誌3 0 3。theta標誌 3 0 1應具有異於半導體積體電路晶片2 0 1中墊區域 202形狀之特殊形狀以便能自動辨識。 雖然在圖3 ( a )之例子中顯示Γ形狀，但其它形狀 仍然合適只要它係特殊形狀且容易進行辨識。 如圖3 ( b )中所示，習知的定位圖型係由矩形鋁薄 本紙张尺度適用中國國家榡準（CNS ) Λ4#1：^ ( ) ---------·--^-I------ΐτ (-fifl閱誚背而之注&中項再填-κ•本玎) d -4- 經濟部中央標準局只工消*ί合竹社印β 鋁圖型之定位圖型 晶矽薄膜上實行雷 多晶矽薄膜所形成 中所顯示之雷射照 差。雷射照射區3 射照射周端係低能 間中多晶矽薄膜圖 生無法穩定切割結 A7Printed by Jing-Ministry Central Standard 59-Bureau Consumer Cooperatives ^ A7 ______H7 V. Description of the Invention (1) Background of the Invention The present invention relates to a semiconductor device, which has a positioning pattern to be formed on a semiconductor wafer by cutting by laser beam irradiation.上 的 组合 Element。 On the coupling element. In the analog semiconductor integrated circuit device, there is a conventional laser correction method for adjusting analog characteristics. For example, there is a description in Japanese Patent Laid-Open Publication No. H5-1 3670 "Integrated circuits are printed two-dimensionally on a semiconductor wafer, and then the electrical characteristics of various integrated circuits are measured on the wafer state. Then select the group of interconnected bonding elements to adjust the analog characteristics and cut them by irradiating the laser beam. This laser correction method allows the analog characteristics of integrated circuits to be adjusted to the desired characteristics by selectively cutting the bonding elements. A positioning pattern is provided on the surface of the semiconductor wafer to irradiate the laser beam onto a predetermined bonding element. Fig. 3 (a) is a plan view of a conventional positioning pattern, Fig. 3 (b) is a cross-sectional view of a conventional positioning pattern, and Fig. 3 (c) shows the direction of the light beam along the c-C / line The variation of the light reflection amount displayed by the scanning positioning pattern. As shown in FIG. 3 (a), the conventional positioning pattern is included in the line drawing area 203 for relatively rough positioning on the semiconductor wafer rotation The so-called theta mark of the direction, and the X-direction correction mark 3 0 2 and the Y-direction correction mark 3 0 3 of the semiconductor integrated circuit wafer 2 0 1 which are used to accurately and sequentially locate the repeated placement. The theta mark 3 0 1 should be different The special shape of the pad area 202 shape in the semiconductor integrated circuit wafer 201 can be automatically identified. Although the Γ shape is shown in the example of FIG. 3 (a), other shapes are still suitable as long as it is a special shape and easy to identify As shown in Figure 3 (b), the conventional positioning pattern is made of rectangular aluminum thin paper. The standard is applicable to China National Standards (CNS) Λ4 # 1: ^ () --------- · -^-I ------ ΐτ (-fifl read the back note & fill in the middle item -κ • 本 玎) d -4- Central Standard of the Ministry of Economic Affairs The bureau only eliminates the laser aberrations shown in the β-aluminum pattern printed by Hezhusha. The laser aberration shown in the implementation of the laser polysilicon film on the crystalline silicon film. The laser irradiation zone 3 is a low-energy intermediate zone. Polycrystalline silicon film can not stably cut junction A7

___ \M 五、發明説明（2 ) 膜1 0 5在矽基底1 01上之氧化矽第一絕緣 上形成之。倘若光束沿著圖3 (a )中的C — 向而掃描，則由於鋁薄膜1 0 5之高反射率故 3 ( c )中所顯示光反射圓型。在鋁薄膜1 〇 光反射量，然而不含鋁薄膜1 0 5之部分則呈 量。使用光反射量在高光反射量及低光反射量 分來界定作爲修正之用的參考位置。在設計期 位圖型及由積體電路之多晶矽薄·膜所形成之結 位置關係。據此，藉著將光束照射至定位圖型 反射變動的位置，則計算出所需之結合元件的 雷射照射該位置，可選擇性地修正結合元件。 無論如何，在習知的雷射修正中，結合元 型係由不同的薄膜所形成，以致不可能精確地 p測參考位置然後在作爲結 射修正，由於在半導體製程 之元件間發生排版誤差而產 射區域3 2與結合元件3 1 2係在高斯分布之能量分布 量密度。因此之故，倘若在 型及鋁薄膜圖型間具有排版 合元件的問題。附帶一提， 層燃燒，而3 4係^合元件之未切斷部分。 此外，在習知的雷射修正中，定位圖型常 體積體電路晶片間之畫線區域中。畫線區域係 本紙張尺度適用中國國家樣準（CNS > ( 2I0X2V7公軲> 薄膜1 0 2 C /線之方 可獲得如圖 5上顯出高 現低光反射 間變動的部 間中確定定 合元件間之 上以偵測光 座標。利用 件及定位圖 定位。藉由 合元件之多 中鋁圖型及 生如圖1 4 間之校準誤 中，而在雷 晶圓製程期 誤差，則產 3 3係在下 放置於半導 用於描畫（ ----；--------1T------G (-?.>?1閱讳背而之注&事項再填«?本頁) -5- 經津部中央標準局工消#合竹社印犁 Α7 Β7 五、發明说明（3 ) 切割）半導體晶圓之切割許可。倘若在此區域中存有許多 薄膜，則在.分割程序中切塊之切緣可能會受損，使得分割 程序之通量降低並且在極端情況下由於不利的分割使得半 導體積體電路晶片受損。 因此之故，卒發明之里J5傲提供可精確地定位和修正 半導之結合元件的半導體裝置。再者*本發明之目 » 的係藉由降低結件面寸及成本而加強修正定位 精確度》 ‘ 本發明之另一目的係提供半經由降低在 畫線區域中所佔用之雷射修位圖型區域惑在^半導體積 體電路晶片中引入雷射修正定位圖型而使得在分割程序中 —— . 不會遭遇困難。 發明槪述： 本發明採用下列方式以解決上述問題。 (1 )在具弟導表面上畫線而二維地重 複放置成矩陣形狀之半導體積體電路的半導體裝置中，利 用雷射修正以切割在半導體積體電路上之結合元件，並且 在半導體晶圓表面上具有雷射修正定位圖型，半導體^Τ 之特徵爲雷射修正定位圖型係由和結含元件相同之 建構而成·。 (2 )如（1 )中所詳述之半導體裝置，其中雷射修 正定位圖型係由高光反射區域及被高光反射區域夾住之低 光反射區域所形成。或者相反地，如（1 )中所詳述之半 本紙張尺度適用中國國家標率（CNS ) ( 2丨0XW7公犮> ----..---^------訂------—；--- (对1閱诔外而之注&事項再^:}ϊ?本頁) -6- A7 __ Π7 _ 五、發明説明（4 ) 導體裝置，其中雷射修正定位圖型係由低光反射區域及被 低光反射區域夾住之高光反射區域所形成。 (3)如（2)中所詳述之半導體裝置，其中低光反 射區域係用以使光擴散反射之點狀或格狀或條狀圖型。 (4 )如（2 )中所詳述之半導體裝置，其中雷射修 正結合元件係由多晶矽薄膜所形成。 (5 )在具有通過半導體晶圓表面上畫線而二維地重 複放置成矩陣形狀之半導體積體·電路的半導體裝置中，半 導體積體電路上具有結合元件，並且半導體晶圓表面上具 有雷射修正定位圖型，半導體裝置之特徵爲包含由高光反 射區域及低光反射區域所形成之雷射修正定位圖型，高光 反射區域係由形成於平坦底層上之高光反射薄膜所形成， 並且低光反射區域係由形成於點狀或格狀或條狀光擴散反 射圖型上之高光反射薄膜所形成，該光擴散反射圖型係由 和結合元件相同的薄膜所建構而成》 經滴部中央標準局只工消费合作社印¾ (6 )如（5 )中所詳述之半導體裝置，其中雷射修 正定位圖型係由高光反射區域及被高光反射區域夾住之低 光反射區域所形成。 (7) 如（5)中所詳述之半導體裝置，其中雷射修 正定位圖型係由低光反射區域及被低光反射區域夾住之高 光反射區域所形成。 (8) 如（5)中所詳述之半導體裝置，其中結合元 件係由多晶矽薄膜所建構而成。 (9 )如（5 )中所詳述之.半導體裝置，其中高光反 本紙張尺度適用中國國家榡準（CNS ) 枋（210X297公疗） 經濟部中央標準局只工消费合竹社印聚 A7 R7 五、發明説明（5 ) 射薄膜係由鋁所建構而成。 (1 0 )如（5 )中所詳述之半導體裝置，其中雷射 修正定位圖型係放置於半導體積體電路晶片內作爲和外部 電性連結之墊區域上。 (1 1 )如（1 0 )中所詳述之半導體裝置，其中雷 射修正定位圖型係由高光反射區域及低光反射區域所形成 ，高光反射區域係由形成於平坦底層上之高光反射薄膜所 形成，低光反射區域係由形成於'格狀或條狀或點狀光擴散 反射圖型上之'高光反射薄膜所形成，該光擴散反射圖型係 由和雷射修正結合元件相同的薄膜所建構而成。 (1 2 )如（1 1 )中所詳述之半導體裝置，其中雷 射修正定位圖型係由高光反射區域及受高光反射區域包圍 之低光反射區域所形成》 (1 3)如（1 1 )中所詳述之半導體裝置，其中雷 射修正定位圖型係由低光反射區域及受低光反射區域所包 圍之高光反射區域所形成。 (1 4 )如（1 1 )中所詳述之半導體裝置，其中雷 射修正結合兀件係由多晶砂薄膜所建構而成。 (1 5)如（1 1 )中所詳述之半導體裝置，其中高 光反射薄膜係由鋁所形成。 (1 6 )如（5 )中所詳述之半導體裝置，其中雷射 修正定位圖型係放置於畫線之交叉處。 (1 7 )如（5 )中所詳述之半導體裝置，其中雷射 修正定位圖型係連續結構，可用作爲關於半導體晶圓之轉___ \ M 5. Description of the invention (2) The film 105 is formed on the silicon oxide first insulation on the silicon substrate 101. If the light beam is scanned along the C-direction in FIG. 3 (a), the light reflection circle shown in 3 (c) is due to the high reflectivity of the aluminum thin film 105. The amount of light reflection in the aluminum film is 10, but the amount in the portion not containing the aluminum film is 105. Use the light reflection amount in the high light reflection amount and the low light reflection amount to define the reference position for correction. During the design phase, the bit pattern and the positional relationship of the junction formed by the polycrystalline silicon thin film of the integrated circuit. According to this, by irradiating the light beam to the position where the reflection pattern of the positioning pattern changes, a laser irradiating the required position of the coupling element is calculated to selectively correct the coupling element. In any case, in the conventional laser correction, the combined element system is formed of different films, so that it is impossible to accurately measure the reference position and then use it as a shot correction because of typographical errors between components in the semiconductor process. The emission area 3 2 and the coupling element 3 1 2 are the energy distribution quantity densities in the Gaussian distribution. Therefore, if there is a problem of layout elements between the pattern and the aluminum film pattern. Incidentally, the layer burns, and the uncut portion of the 3 4 series coupling element. In addition, in the conventional laser correction, the positioning pattern is in the area of the line drawn between the wafers of the constant volume circuit. The area where the line is drawn is based on the Chinese standard of the paper scale (CNS > (2I0X2V7 公 轱 > film 1 0 2 C / line), as shown in Figure 5, which shows the variation between high and low light reflections. Determine the space between the fixed components to detect the optical coordinates. Use the components and positioning maps to locate. With the many aluminum components in the combined components and the calibration errors shown in Figure 14 and 4, the errors in the process of lightning wafers , Then the 3 3 series is placed on the semiconductor for drawing (----; -------- 1T ------ G (-?. ≫? 1 & Refill «? This page） -5- Ministry of Economy and Trade Central Standards Bureau Gong Xiao # 合 竹 社 印 栗 A7 Β7 V. Description of the invention (3) Cutting) Cutting permission for semiconductor wafers. If in this area There are many thin films, the cutting edge of the dicing may be damaged during the division process, which reduces the throughput of the division process and, in extreme cases, damages the semiconductor integrated circuit wafer due to unfavorable division. Therefore, The invention of J5 is a semiconductor device that can accurately locate and correct the semiconductor components. Furthermore, * the purpose of the invention » Reducing the size and cost of the component and enhancing the accuracy of correcting positioning "" Another object of the present invention is to provide a semi-conductor integrated circuit chip by reducing the laser trimming pattern area occupied in the line drawing area. The laser correction positioning pattern is introduced so that in the segmentation process-no difficulties will be encountered. Description of the invention: The present invention adopts the following methods to solve the above problems. (1) Draw a line on the surface of the guide and two-dimensionally In a semiconductor device in which semiconductor integrated circuits are repeatedly placed in a matrix shape, laser correction is used to cut bonding components on the semiconductor integrated circuit, and a laser correction positioning pattern is provided on the surface of the semiconductor wafer. The feature is that the laser correction positioning pattern is constructed from the same structure as the junction component. (2) The semiconductor device as detailed in (1), wherein the laser correction positioning pattern is composed of a high-light reflection area and a substrate. It is formed by the low-light reflection area sandwiched by the high-light reflection area. Or, conversely, the Chinese paper standard (CNS) (2 丨 0XW7 public 犮 > ----..--- ^ ------ Order --------; --- (Note 1 for the first reading & matters again ^:} ϊ? This page) -6- A7 __ Π7 _ V. Description of the invention (4) The conductor device, wherein the laser correction positioning pattern is formed by the low-light reflection area and the high-light reflection area sandwiched by the low-light reflection area. (3) Such as ( The semiconductor device detailed in 2), wherein the low-light reflection area is a dot-shaped or lattice-shaped or bar-shaped pattern for diffusely reflecting light. (4) The semiconductor device detailed in (2), wherein The laser correction bonding element is formed of a polycrystalline silicon thin film. (5) In a semiconductor device having semiconductor integrated circuits and circuits that are repeatedly placed in a matrix shape two-dimensionally by drawing lines on the surface of the semiconductor wafer, the semiconductor integrated circuit has bonding elements on the semiconductor wafer and the semiconductor wafer has lightning on the surface. Radiation correction positioning pattern. A semiconductor device is characterized by a laser correction positioning pattern formed by a high-light reflection region and a low-light reflection region. The high-light reflection region is formed by a high-light reflection film formed on a flat bottom layer, and has a low The light reflection area is formed by a high-light reflection film formed on a point, lattice, or strip light diffusion reflection pattern, and the light diffusion reflection pattern is formed by the same film as the bonding element. Printed by the Central Bureau of Standards for Consumer Cooperatives ¾ (6) A semiconductor device as detailed in (5), in which the laser correction positioning pattern is formed by a high-light reflection area and a low-light reflection area sandwiched by the high-light reflection area . (7) The semiconductor device as detailed in (5), wherein the laser correction positioning pattern is formed by a low-light reflection area and a high-light reflection area sandwiched by the low-light reflection area. (8) The semiconductor device as detailed in (5), wherein the bonding element is constructed of a polycrystalline silicon film. (9) As detailed in (5). Semiconductor devices, in which the specular reflection paper size is applicable to China National Standards (CNS) 枋 (210X297 public therapy). The Central Standards Bureau of the Ministry of Economics only consumes Hezhusha Yinju A7 R7 V. Description of the Invention (5) The thin film is made of aluminum. (10) The semiconductor device as detailed in (5), wherein the laser correction positioning pattern is placed on a semiconductor integrated circuit chip as a pad area electrically connected to the outside. (1 1) The semiconductor device as detailed in (1 0), wherein the laser correction positioning pattern is formed by a high-light reflection area and a low-light reflection area, and the high-light reflection area is formed by a high-light reflection formed on a flat bottom layer Formed by a thin film, the low light reflection area is formed by a high light reflection film formed on a 'lattice, stripe, or dot light diffusion reflection pattern, and the light diffusion reflection pattern is the same as that of the laser correction combining element Made of thin film. (1 2) The semiconductor device as detailed in (1 1), wherein the laser correction positioning pattern is formed by a high-light reflection area and a low-light reflection area surrounded by the high-light reflection area "(1 3) as (1 1) The semiconductor device detailed in 1), wherein the laser correction positioning pattern is formed by a low-light reflection area and a high-light reflection area surrounded by the low-light reflection area. (1 4) The semiconductor device as detailed in (1 1), wherein the laser correction bonding element is constructed of a polycrystalline sand film. (1 5) The semiconductor device as detailed in (1 1), wherein the high-light reflection film is formed of aluminum. (16) The semiconductor device as detailed in (5), wherein the laser correction positioning pattern is placed at the intersection of the drawing lines. (1 7) The semiconductor device as detailed in (5), in which the laser correction positioning pattern is a continuous structure, which can be used as a semiconductor wafer

本紙張尺度適用中國國家榡车（CNS ) Λ4«ί^· ( 210X297公H ——ΙΊ0------IT------α (对汔閱誚11'而之注^事項再續寫本s) -8 - A7 H? 五、發明説明（6 ) 動方向之粗糙定位的theta標誌以及作爲精確地依序定位重 複放置之半導體積體電路的修正標誌。 (1 8 ) —種半導體裝置，其定義雷射修正定位圖型 之內部尺寸作爲雷射光束直徑之指標，以便增加介於高光 反射區域及低光反射區域間之光反射量的差異（對比）。 圖示簡單說明： 圖1 ( a )係本發明之半導·體裝 型之平面圖，·並且圖1 (b)係顯示 一 A /線之光反射量。 圖2 ( a )係本發明之半導體裝 射修正定位圖型之平面圖，並且圖2 3 (a)中C_C<線之光反射量。 置之雷射修正定位圖 沿著圖1 ( a )中A 置之第二實施例中雷 (b )係顯示沿著圖This paper size applies to China National Car (CNS) Λ4 «ί ^ · (210X297 Male H ——ΙΊ0 ------ IT ------ α Continued s) -8-A7 H? V. Description of the invention (6) Theta mark for rough positioning in the moving direction and a correction mark for precisely positioning the repeatedly placed semiconductor integrated circuit. (1 8) — Kind A semiconductor device that defines the internal dimensions of the laser correction positioning pattern as an indicator of the laser beam diameter in order to increase the difference (contrast) in the light reflection amount between the high-light reflection area and the low-light reflection area. Fig. 1 (a) is a plan view of a semiconducting and body-mounting type of the present invention, and Fig. 1 (b) is a light reflection amount of an A / line. Fig. 2 (a) is a semiconductor shot correction positioning of the present invention A plan view of the pattern, and the amount of light reflection of the C_C < line in Fig. 2 (a). The laser correction positioning map is shown along the laser (b) in the second embodiment of A in Fig. 1 (a). Along the graph

圖3 面® 之光反射 圖4 ( a )係本發明之半導體裝 係習知_導體裝置 ( HIT係福ϋ著圖3( mm 之雷射修正定位 |_ )中Fig. 3 Light reflection of surface ® Fig. 4 (a) is the conventional semiconductor device of the present invention. _Conductor device (HIT is shown in Fig. 3 (laser correction positioning in mm | _)

經潢部中央標準扃另工消费合竹社印絮Central Standards of the Ministry of Economics and Decoration

置之第三實施例中雷 )係本發明之半導體 正定位圖型之平面圖，圖4 ( b 之第三實施例中雷射修正定位圖型之剖面圖，並且圖 c )係顯示沿著圖4 ( a )中A — A >線之光反射量 圖5 ( a )係本發明之半導體裝置之第四實施例中雷 射修正定位圖型之平面圖，圖5 ( b )係本發明之半導體 裝置之第四實施例中雷射修正定位圖型之刮面圖，並且圖 本紙張尺度適用中國國家椋卑（CNS > AOt枯（210Χ?ς^Η4, > ；-IT—Q t α—— -9· 經满部中央標準局β工消费合作社印裂 A7 B7 五、發明説明（7 ) 5 (c)係顯示沿著圖5 (a)中C_C<線之光反射量 〇 圖6 ( a )係本發明之半導體裝置之第五實施例中雷 射修正定位圖型之平面圖，圖6 ( b )係本發明之半導體 裝置之第五實施例中雷射修正定位圖型之剖面圖’並且圖 6 (c)係顯示沿著圖6 (a)中D_D>線之光反射量 〇 圖7 ( a )係本發明之半導·體裝置之第六實施例中雷 射修正定位圖型之平面圖，圖7 (b)係本發明之半導體 裝置之第六實施例中雷射修正定位圖型之剖面圖，並且圖 7 ( c )係顯示沿著圖7 ( a )中E — E β線之光反射量 〇 圖8 ( a )係包含根據本發明半導體裝置之第七實施 例中雷射修正定位圖型之半導體積體電路晶片的典型平面 圖，圖8 (b)係放大配置著圖8 (a)之雷射修正定位 圖型之墊區域的典型平面圖。 圖9 ( a )係本發明之半導體裝置之第七實施例中雷 射修正定位圖型之平面圖，圖9 ( b )係本發明之半導體 裝置之、第七實施例中雷射修正定位圖型之剖面圖，並且圖 9 (c)係顯示沿著圖9 (a)中A — A >線之光反射量 〇 圖1 0 ( a )係本發明之半導體裝置之第八實施例中 雷射修正定位圖型之平面圖，圖1 0 ( b )係本發明之半 導體裝置之第八實施例中雷射修正定位圖型之剖面圖，並 本紙張尺度適用中國國家摞準（CNS ) 梠（210Χ297公犮） (对汔閱讀背而之注&市項4>/!寫本页)The third embodiment is a plan view of the semiconductor positive positioning pattern of the present invention, and FIG. 4 (b) is a cross-sectional view of a laser correction positioning pattern in the third embodiment, and FIG. Fig. 5 (a) is a plan view of a laser correction positioning pattern in the fourth embodiment of the semiconductor device of the present invention, and Fig. 5 (b) is a plan view of the present invention. Scraped view of the laser correction positioning pattern in the fourth embodiment of the semiconductor device, and the paper size of the map is applicable to the Chinese national standard (CNS > AOt dry (210 ×? Σ ^ Η4, >; -IT-Q t α—— -9 · A7 B7 printed by the Central Bureau of Standards of the People ’s Republic of China. V. Invention description (7) 5 (c) shows the amount of light reflection along the line C_C < in Figure 5 (a). 6 (a) is a plan view of a laser correction positioning pattern in the fifth embodiment of the semiconductor device of the present invention, and FIG. 6 (b) is a cross section of the laser correction positioning pattern in the fifth embodiment of the semiconductor device of the present invention Fig. 6 (c) shows the amount of light reflection along the line D_D > in Fig. 6 (a). Fig. 7 (a) shows the semiconductor and bodywear of the present invention. A plan view of a laser correction positioning pattern in the sixth embodiment, FIG. 7 (b) is a cross-sectional view of the laser correction positioning pattern in the sixth embodiment of the semiconductor device of the present invention, and FIG. 7 (c) shows The amount of light reflection along the E-E β line in FIG. 7 (a). FIG. 8 (a) is a typical semiconductor integrated circuit wafer including a laser correction positioning pattern in a seventh embodiment of a semiconductor device according to the present invention. Plan view, FIG. 8 (b) is a typical plan view of a pad region in which the laser correction positioning pattern of FIG. 8 (a) is enlarged. FIG. 9 (a) is a laser correction in the seventh embodiment of the semiconductor device of the present invention A plan view of a positioning pattern, FIG. 9 (b) is a cross-sectional view of a laser correction positioning pattern in a seventh embodiment of the semiconductor device of the present invention, and FIG. 9 (c) is a view taken along FIG. 9 (a) A — A > The amount of light reflection of the line. FIG. 10 (a) is a plan view of a laser correction positioning pattern in the eighth embodiment of the semiconductor device of the present invention, and FIG. 10 (b) is a semiconductor device of the present invention Sectional drawing of laser correction positioning pattern in the eighth embodiment, and this paper scale is applicable to China National Standards (CNS) (210 × 297 public address) (Note to the back of the reading & market item 4 > /! Write this page)

QQ

,1T -10- 經濟部中央標準局只工消费合竹社印製 A7 H7 五、發明説明（8 ) 且圖10(C)係顯示沿著圖10 (a)中C-CZ線之 光反射量。 圖1 1 ( a )係本發明之半導體裝置之第九實施例中 雷射修正定位圖型之平面圖，圖1 1 ( b )係本發明之半 導體裝置.之第九實施例中雷射修正定位圖型之剖面圖，並 且圖11 (c)係顯示沿著圖11 (a)中D_D<線之 光反射量。 圖1 2 ( a )係本發明之半導體裝置之第十實施例中 雷射修正定位圖型之平面圖，圖12 (b)係本發明之半 導體裝置之第十實施例中雷射修正定位圖型之剖面圖，並 且圖12 (c)係顯示沿著圖12 (a)中E — 線之 光反射量。 圖1 3 ( a )係本發明之半導體裝置之第十一實施例 中雷射修正定位圖型之平面圖，圖1 3 ( b )係本發明之 半導體裝置之第十一實施例中雷射修正定位圖型之剖面圖 ，並且圖13 (c)係顯示沿著圖13 (a)中A — A 一 線之光反射量。 圖1 4係習知的半導體裝置之結合元件的平面圖。 圖1 5 ( a )係本發明之半導體裝置之第十二實施例 中雷射修正圖型之平面圖，圖15 (b)係本發明之 半導體裝置十二實施例中雷射修正定位圖型之剖面圖 ’並且圖1 c)係顯示沿著圖15 (a)中B — 線之光反射 圖_1 6 ( a )係表示根據本發明之雷射修正定位圖型 本紙張尺度適用中國國象抵率（CNS ) Λ4叱柢（210X 297^)^.〉 ----：---；--------IT------Q (計九閱讳背而之注ΐ»枣^βί/ί-ίί?本刃) -11 · 經濟部中央標津局只工消费合竹社印製 A7 _H7 _ 五、發明説明（9 ) 的一部分及雷射光點之典型平面圖，並且圖1 6 ( b )係 表示高光反.射區域光反射量與低光反射區域光反射量間差 異之對比，並且每點多晶矽薄膜有線及體尺寸a。 圖1 7 ( a )係代表根據本發明之雷射修正定位圖型 的一部分及雷射光點之典型平面圖，並且圖1 7 ( b )係 表示高光反射區光反射量與低光反射區域光反射量間差異 之對比，並且尺寸b係在低.光反射區域之雷射掃描方向。 圖18係習知的半導體裝置之結合元件的平面圖。 圖1 9係本發明之半導體裝置之區塊圖。 ----i—Q------.訂------α (計先閱讀背而之注念事項再功寫本Κ ) 主要元件對照表 3 0 1 t h e t a標誌 2 0 3 畫線區域 3 0 2 修正標誌 3 0 3 修正標誌 2 0 1 半導體積體電路晶片 2 0 2 墊區域 1 0 2 第一絕緣薄膜 1 0 1 基底 1 0 5 鋁薄膜 3 2 雷射照射區域 3 1 結合兀件 1 0 6 高光反射區域 1 0 7 低光反射區域 本紙張尺度適用中國國家榡率（CNS ) Λ4%柏（210X29·?公# > -12- 經溁部中央標準局只工消費合作社印製 A7 Η 7 五、發明説明（1〇 ) 1 0 3 多 晶矽 薄 膜 1 0 4 第 二 絕 緣 薄 膜 2 0 4 雷 射 修 正 定 位 圖 型 4 0 1 雷 射 修 正 定 位 圖 型 5 0 1 雷 射 光 點 發明之實施例： 雷射修正定位圖型具^高光·反射I域及低光反射區域 ___ —— ' * 。利用與雷射·修正結合元件相同之薄膜所形成之圖型1 龙 出高光_反射區域及低光之邊界，即光反射度急 劇變動之區_域。此使雷射修正_之_宜行^受晶圓製造期間中 排版誤差的影響而得以精確。 此外，雷射修正定位圖型亦得從畫線區域轉換至墊區 域，該墊區域係作爲半導體積體電路晶片之內部及外部間 的電性連結。在畫線區域中形成連續結構，該結構得作爲 用以比較粗糙地定位半導體晶圓轉動方向之theta標誌及用 以精確地依序定位重複安置之半導體積體電路之修正標誌 。安置於畫線交叉處可減少雷射修正定位圖型在畫線區域 中所佔據的面積。 再者，雷射修正定位圖型尺寸之定義係以雷射光束之 直徑作爲指標，以使高光反射區域與低光反射區域間之反 射度有大差異（以便增加對比）。因此之故可獲得能完全 顯示雷射修正定位圖型之性能的結構。 下文中將基於圖示來說明本發明。 本紙張尺度適用中國國家榡準（CNS > 祐（210χ2<ίΠ公尨} !!q------1------α {^先閲^"而之注^5^項再-"{"本页) -13- 經漪部中央標枣局只工消费合作社印裝 A7 B1 五、發明説明（11 ) 附帶提及地，除非其他用於雷射修正之著名結合元件 由多晶矽薄膜所形成，爲了簡化起見在下文中將省略說明 〇 圖1 (a)係本發明之定位圖型之平面圖，而圖1 ( b )係顯示光束掃描處之光反射量的變動。光反射量係沿 著圖1 ( a )中A — A /方向掃描而得之値。本發明之定 位圖型係由高光反射區域1 0 6及在他們內部之低光反射 區域1 07所建構而成，如圖1_( a )所示。在圖1之例 子中，低光反射區域1 0 7係利用光擴散反射之效應而形 成。多晶矽薄膜1 0 3，該薄膜與結合元件相同，係呈點 狀以便擴散反射。爲了擴散反射，圖型得爲非點狀之格狀 、條狀或諸如此類者，藉此可獲得如圖1(b)所示之光 反射圖型。結合元件最好係易於吸收光且適合切割之薄膜 。較佳的薄膜係多晶矽薄膜。多晶矽薄膜容易吸收光並且 適合用雷射照射來切割。藉著形成如圖1 ( a )所示之點 狀圖型的多晶矽薄膜1 0 3以作爲定位圖型內部上之低光 反射區域1 0 7，可獲得具有大光反射量之對比。在半導 體基底上之高光反射區域1 0 6可如習知般地由氧化物薄 膜或諸如此類者所形成之場區域建構而成。 圖2 ( a )係本發明之第二實施例中定位圖型之平面 圖，而圖2 (b)係顯示光束掃描處之光反射量的變動。 光反射童係沿著圖2 ( a )中C — C /方向掃描而得之値 。本發明之定位圖型係由低光反射區域1 0 7及在其內部 上之高光反射面域1 0 6所建構而成，如圖2 ( a )所示 本紙張尺度適用中國囤家樣隼（CNS ) ΛΜί栳（2WX297公於） I n n n n n II n u I I n n τψ I--- I Lt Q 1 ό •14- 經淹部中央標卑局只工消费合作杜印¾ A7 _'_ Η 7 五、發明説明（12 ) ，係與圖1 ( a )所示之例子相反的結構。只要低光反射 區域1 0 7或高光反射區域1 0 6其中之一將對方夾住貝[J 得爲合適的雷射修正定位圖型，如圖2 ( a )中之結構也 允許。至於其他部分，與圖1相同之參考特徵便省略不再 說明。 圖4 ( a )係本發明之第三實施例中定位圖型之平面 圖，圖4 ( b )係本發明之第三實施例中定位圖型之剖面 圖，並且圖4 (c)係顯示光束·掃描第三實施例之定位圖 型處之光反射·量的變動。光反射量係沿著圖4 ( a )中A 一 A /方向掃描而得之値。本發明之第三實施例中定位圖 型係由高光反射區域1 0 6及在其內部上之低光反射區域 1 0 7所建構而成，如圖4 ( b )所示。 將使用圖4 ( a )及圖4 (b )來說明本發明之定位 圖型的結構。 ’ 在矽基底1 0 1上形成氧化矽薄膜或諸如此類者之第 一絕緣薄膜1 0 2。在第一絕緣薄膜1 〇 2上群體地形成 點狀多晶矽薄膜1 0 3。在未形成多晶矽薄膜1 0 3之面 積上，顯露出平坦的第一絕緣薄膜1 0 2。在其上形成 P S G薄膜或諸如此類者之第二絕緣薄膜1 0 4，並且鋁 薄膜1 0 5係形成於第二絕緣薄膜1 〇 4上。位於點狀多 晶矽薄膜1 0 3形成面積上之鋁薄膜1 〇 5表面因多晶矽 薄膜1 0 3圖型之影響而粗糙。照射於此區域上之光會擴 散反射。因此之故，此區域可作爲低光反射區域1 0 7。 另一方面，在未形成多晶矽薄膜1 0 3之面積上鋁薄膜 本紙張尺度適用中國國家榡丰（CNS ) Λ4悅拮（) IHIQ 訂-----d (誚51閱¾.¾而之注念事項再说寫本R ) -15- 經漪部中央標準局β工消费合竹社印裝 A7 _____ B7 ___ 五、發明説明（13 ) 1 0 5有平坦的表面，可作爲高光反射區域1 〇 6。 在光束沿著圖4 ( a )中A — A >線方向上掃描之處 ，如圖4 (c)所示，在由平坦表面之鋁薄膜1〇5所形 成之高光反射區域1 0 6處有大的光反射量，並且在由粗 糙表面之鋁薄膜1 0 5所形成之低光反射區域1 0 7處有 小的光反射量。 在圖4 ( a )、 （ b )及（c )之例子中，利用光擴 散反射效應形成低光反射區域1·〇 7。爲了產生光擴散反 射，點狀圖型由和結合元件相同薄膜之多晶矽薄膜1 〇 3 所形成。也可利用非點狀，例如格狀或條狀之圖型來產生 光擴散反射，藉而獲得如圖4 ( c )所示之光反射圖型。 在圖4 ( b )中之第一絕緣薄膜1 〇 2及第二絕緣薄 膜1 0 4係不必然需要而得以省略。再者，得使用例如鎢 及鉻之金屬材料代替鋁薄膜1 0 5作爲高反射薄膜。 如前所述，高光反射區域1 0 6及低光反射區域 1 0 7之邊界係由和結合元件相同薄膜材料之多晶矽薄膜 1 0 3圖型所確定。如此則消除了在習知的定位圖型中所 遭遇因形成結合元件之多晶矽與形成定位圖型之鋁圖型間. 校準誤差而產生之問題。 圖5 ( a )係本發明之半導體裝置的第四實施例中定 位圖型之平面圖，圖5 ( b )係本發明之半導體裝置的第 四實施例中定位圖型之剖面圖，並且圖5 ( c )係顯示光 束掃描本發明之半導體裝置的第四實施例中定位圖型處之 光反射量的變動。光反射量係沿著圖5 (a)中C — 本紙張尺度適用中國國家椋牟（CNS > 柏（210X297^1 .'-n I n In - —.1 n I I i Hi ----. *5TI m n___ ("先間試背而之注&事項44¾本頁) -16 - 經滴部中央標準局只工消费合作社印裝 A7 _______Η 7 ___ 五、發明説明（14 ) 線方向上掃描而得之値。本發明之第四實施例中定位圖型 係由高光反射區域1 0 6及在其內部上之低光反射區域 107所建構而成，相似於圖4 (a)至（c)中所示之 第三實施例。 與圖4中所示之第三實施例不同處在於高光反射區域 1 0 6係由位於平坦多晶矽薄膜1 0 3上之鋁薄膜1 0 5 所形成。倘若高光反射區域1 0 6係由在平坦底層上之高 反射薄膜所形成，則它的效應可·達成。因而如此的結構係 可能的。藉著參照和圖4 (a)至（c)相同的參考特徵 以便省略其他說明。 圖6 ( a )係本發明之半導體裝置的第五實施例中定 位圖型之平面圖，圖6 ( b )係本發明之半導體裝置的第 五實施例中定位圖型之剖面圖，並且圖6 ( c )係顯示光 束掃描本發明之半導體裝置的第五實施例中定位圖型處之 光反射量的變動。光反射量係沿著圖6 ( a )中D — D 一 線方向上掃描而得之値。本發明之第五實施例中定位圖型 係由配置低光反射區域1 0 7於外部及配置高光反射區域 1 0 6於其內部所建構而成。定位圖型得爲高光反射區域 1 0 6或低光反射區域1 0 7其中之一被其他區域夾住之 形狀。在圖6 ( a )至（c )中所示之第五資施例顯示與 圖4 ( a )至（c )中所示之第三實施例排列相反之例子 ，以表明該形狀係合適的。藉著參照和圖4 ( a )至（c )相同的參考特徵以便省略其他說明。 圖7 ( a )係本發明之半導體裝置的第六實施例中定 本紙張尺度適历中國國家榡车（CNS > Λ4故枯（2丨0x297d ) ----ΊΙΊ—Q------訂------Q (""間请匁而之注^事項再填巧本頁) -17- 經潢部中央標??-局只工消费合竹社印裝 A7 B7 五、發明説明（15 ) 位圖型之平面圖，圖7 ( b )係本發明之半導體裝置的第 六實施例中.定位圖型之剖面圖，並且圖7 ( c )係顯示光 束掃描本發明之半導體裝置的第六實施例中定位圖型處之 光反射量的變動。光反射量係沿著圖7 ( a )中E-E > 線方向上掃描而得之値。本發明之第六實施例中定位圖型 係由配置低光反射區域1 0 6於外部及配置高光反射區域 1 0 7於其內部所建構而成。 定位圖型得爲高光反射區域1 0 6或低光反射區域 1 0 7其中之一被其他區域夾住之形狀，類似於第五實施 例中之說明。在圖7 (a )至（c )中所示之第六實施例 係顯示與圖5 ( a )至（c )中所示之第四實施例排列相 反之例子。藉著參照和圖4(a)至（c)相同的參考特 徵以便省略其他說明。 在圖4至圖7中之第一絕緣薄膜1 0 2及第二絕緣薄 膜1 0 4並不必然需要，而得省略。再者，得使用例如鎢 、鉻及金之金屬材料代替鋁薄膜10作爲高反射薄膜。 圖8 ( a )係具有根據本發明之半導體裝置的第七至 第十實施例之定位圖型的半導體稹體電路晶片之典型平面 圖。圖8 (b)係放大配置於圖8 (a)中雷射修正定位 圖型中之墊區域之典型平面圖。 如圖8 (a)所示，在半導體積體電路晶片201中 配置有墊區域2 0 2，其係由導電薄膜例如鋁所形成以作 爲電性連結至外部。再者，相鄰的半導體晶片2 0 1之間 具有畫線區域2 0 3。 本紙張尺度通用中國國家榡丰（CNS ) Α4规柏（210x?V7^$ ) ·--^--------iT------ -18- 經漪部中央標準趵只工消费合竹社印製 A7 R7 五、發明説明（16 ) 在此，根據本發明之雷射修正定位圖型係形成於墊區 域2 0 2內。 圖8 ( b )係顯示倂有根據本發明之雷射修正定位圖 型204的墊區域202之平面圖。在圖8(b)中，墊 區域2 0 2之一部分爲雷射修正定位圖型2 0 4 » 墊區域2 0 2在本質上係作爲電性連結至外部。因爲 雷射修正定位圖型區域2 0 4係形成於墊區域2 0 2內， 所以可以在不增加半導體積體電-路晶片面積下將雷射修正 定位圖型2 0 4引入半導體積體電路晶片中。 在圖8 ( a )及（b)中，所顯示的例子係一個雷射 修正定位圖型2 0 4形成於一個墊區域2 0 2中。無論如 何，倘若需要，一個墊區域2 0 2中得形成多數個雷射修 正定位圖型2 0 4。一個或多數個雷射修正定位圖型 2 0 4得形成於多數個墊區域2 0 2中。 茲利用圖9至圖1 2以詳細說明根據本發明之雷射修 正定位圖型。 圖9 ( a )係本發明之半導體裝置之第七實施例中雷 射修正定位圖型之平面圖，圖9 ( b )係本發明之半導體 裝置之第七實施例中雷射修正定位圖型之剖面圖，並且圖 9 ( c )係顯示光束掃描本發明之半導體裝置的第七實施 例中雷射修正定位圖型處之光反射量的變動》光反射量係 沿著圖9 ( a )中A — A —線方向上掃描而得之値。如圖 9 ( b )所示，本發明之第七實施例中雷射修正定位圖型 係由高光反射區域1 0 6及在其內部之低光反射區域 本紙張尺度適用中國國家標準（CNS〉( 2丨0X297公处） —ιί!ο^------訂------α <計先間"背而之注念事項/}-"-{>,3本^?) * 19 - A7 ____B7 五、發明説明（17〉 1 0 7所建構而成。 利用圖9 (a)及圖9 (b)，茲將說明雷射修正定 位圖型之結構。 氧化矽薄膜或諸如此類者之第一絕緣薄膜1 〇 2係形 成於矽基底1 0 1上。在第一絕緣薄膜1 〇 2上，點狀多 晶矽薄膜1 0 3成群地形成。在無多晶矽薄膜1 〇 3形成 之面積中，顯露出第一絕緣薄膜1 〇 2。P S G薄膜或諸 如此類者之第二絕緣薄膜1 〇 4_係形成於其上，並且鋁薄 膜1 0 5形成於第二絕緣薄膜1 〇 4上。位於點狀多晶矽 薄膜1 0 3形成面積上之鋁薄膜表面因多晶矽薄膜1 〇 3 圖型之影響而粗糙，使得照射於此區域上之光擴散反射。 因此之故，此區域可作爲低光反射區域1 〇 7 »另一方面 ，在未形成多晶矽薄膜1 0 3之面積上鋁薄膜1 〇 5係平 坦的，可作爲高光反射區域1 0 6。 在光束沿著圖9 ( a )中A- A >線方向上掃描之處 經濟部中央標準局只工消费合竹社印製 ，如圖9 (c)所示，在由平坦表面之鋁薄膜1〇5所形 成之高光反射區域1 0 6處有大的光反射量，並且在由粗 糙表面之鋁薄膜1 0 5所形成之低光反射區域1 〇 7處有 小的光反射量。 在圖（a )、 （ b )及，（c )之例子中，利用光擴散 反射效應形成低光反射區域1 0 7。爲了產生光擴散反射 ，點狀圖型由和結合元件相同薄膜之多晶矽薄膜1 〇 3所 形成。也可利用格狀或條狀圖型來產生光擴散反射，以獲 得如圖3( c )所示之光反射圖型。 本紙張尺度il财關家料·（ CNS ) Λ4㈣（210X297^1 -20 - 經潢部中央標準局工消f合竹社印¾ Α7 Η 7 五、發明説明（18〉 在圖9 (b )中之第一絕緣薄膜1 〇 2或第二絕緣薄 膜1 0 4其中之一係不必然需要’而得以省略。再者’可 使墊區域2 0 2內配置雷射修正定位圖型2 0 4之處具有 和矽基底1 0 1相同的電位’該配置得係使鋁薄膜10 5 及矽基底101電性連結。再者’在電位得相同於矽基底 1 0 1之墊區域中放置雷射修正定位圖型2 0 4之處，第 —絕緣薄膜1 0 2及第二絕緣薄膜1 〇 4得省略以提供鋁 薄膜1 0 5與矽基底1 〇 1電性—連結之形式。再者，金屬 材料例如鎢、鉻及金可用來代替鋁薄膜1 〇 5作爲高光反 射薄膜只要它適合用於電性連結至外部。 如前所述，高光反射區域1 0 6及低光反射區域 1 0 7之邊界係由和結合元件相同薄膜材料之多晶矽薄膜 1 0 3圖型所確定。因此之故消除了在習知的雷射修正定 位圖型中所遭遇因形成結合元件之多晶矽與形成雷射修正 定位圖型之鋁薄膜間校準誤差而產生之問題。 圖1 0 ( a )係本發明之半導體裝置的第八實施例中 雷射修正定位圖型之平面圖，圖1 0 ( b )係本發明之半 導體裝置的第八實施例中雷射修正定位圖型之剖面圖，並 且圖1 0 ( c )係顯示光束掃描本發明之半導體裝置的第 八實施例中雷射修正定位圖型處之光反射量的變動。光反 射量係沿著圖1 〇 ( a )中C — C —線方向上掃描而得之 値。本發明之第八實施例中雷射修正定位圖型係由高光反 射區域1 0 6及在其內部之低光反射區域1 〇 7所建構而 成，類似於圖9(a)至（c)中所示之實施例。 本紙張尺度適用中國囷家榡準（CNS ) Λ4規枱（2丨0χ?^ϋ厂5 ----.---^------訂------ (i而之注¾事項再填巧本Η ) -21 - A7 _____ Η 7 五、發明説明（19 ) 與第七實施例不同處在於高光反射區域1 〇 6係由位 於平坦多晶矽薄膜1 0 3上之鋁薄膜1 0 5所形成。該結 構係可能的因爲只要高光反射區域係由高光反射薄膜在平 坦底層上所形成則高光反射薄膜1 〇 6可達成它的角色。 藉著參照和圖9 ( a )至（c )相同的參考特徵以便省略 其他說明。 圖1 1 ( a )係本發明之半導體裝置的第九實施例中 雷射修正定位圖型之平面圖，圖1 1 ( b )係本發明之半 導體裝置的第九實施例中雷射修正定位圖型之剖面圖，並 且圖1 1 ( C )係顯示光束掃描本發明之半導體裝置的第 九實施例中雷射修正定位圖型處之光反射量的變動》光反 射量係沿著圖1 1 ( a )中D — D >線方向上掃描而得之 値。本發明之第九實施例中雷射修正定位圖型係由配置低 光反射區域1 0 7於外部及配置高光反射區域1 〇 6於其 內部所建構而成。雷射修正定位圖型得爲高光反射區域 1 0 6或低光反射區域1 0 7其中之一被其他區域夾住之 形狀。在圖1 1 ( a )至（c )中所示之第九實施例係表 經^部中央櫺^局只工消费合作社印袈 .-IMIQI. ("1閱详15'而之注态事項再填寫本R ) α 示與圖9 ( a )至（c )中所示之第七實施例排列相反之 例子，顯示此排列之可能性。藉著參照和圖3 ( a )至（ c)相同的參考特徵以便省略其他說明。 圖1 2 ( a )係本發明之半導體裝置的第十實施例中 雷射修正定位圖型之平面圖，圖1 2 ( b )係本發明之半 導體裝置的第十實施例中雷射修正定位圖型之剖面圖，並 且圖1 2 ( c )係顯示光束掃描本發明之半導體裝置的第 本紙張尺度遒用中國國家椋準（CNS ) Λ4规祐（2丨0Χ297公犮） •22· A7 B7 _ 五、發明説明（2〇 ) 十實施例中雷射修正定位圖型處之光反射量的變動。光反 射量係沿著圖1 2 ( a )中E — E -線方向上掃描而得之 値。本發明之第十實施例中雷射修正定位圖型係由配置低 光反射區域1 0 7於外部及高光反射區域1 〇 6於其內部 所建構而成。雷射修正定位圖型得爲高光反射區域1 〇 6 或低光反射區域1 0 7其中之一受其他區域夾住之形狀， 類似第八實施例中之說明。圖12(a)至（c)所示之 第十實施例代表與圖1 0 ( a )至（c )所示之第八實施 例排列相反之例子，顯示此排列的可能性。藉著參照和圖 9 (a)至（c)相同之參考特徵將省略其他說明。 圖1 3 ( a )係本發明之半導體裝置的第十一實施例 中定位圖型之平面圖，圖1 3 ( b )係本發明之半導體裝 置的第十一實施例中定位圖型之剖面圖，並且圖1 3 ( c )係顯示光束掃描本發明之半導體裝置的第十一實施例中 定位圖型處之光反射量的變化。光反射量係沿著圖1 3 ( a )中A — A >線方向上掃描而得之値。本發明之第十一 實施例中雷射修正定位圖型4 0 1係位於垂直及水平畫線 區域203之交叉處，如圖1 (a)所示，並且係連續結 構，具有比較粗糙地定位於晶圓轉動方向之所謂theta標誌 功能以及精確地依序定位半導體積體電路晶片2 0 1之X 方向修正標誌及Y方向修正標誌之功能。雷射修正定位圖 型4 0 1之形狀應具有異於半導體積體電路晶片2 0 1中 墊區域202之特殊形狀以便自動辨識。據此，圖13( a)之例子係形成爲十字形狀。 本紙張尺度述jiT中^國家標隼（CNS ) A4規格（210X297公釐) n n I n 4— I J— n - - I n I n n---n I——----I (誚先間讀背面之注意事項再功1本頁--- -23- A7 B7 五、發明説明（21〉 茲利用圖1 3 ( b )來說明根據本發明第十一實施例 之雷射修正定位圖型4 0 1之剖面結構。 {誚1閲讀背面之注意事項再蛾艿本頁) 氧化矽薄膜或諸如此類者之第一絕緣薄膜1 0 2係形 成於矽基底1 0 1上，並且在第一絕緣薄膜1 0 2上群體 地形成點狀多晶矽薄膜1 0 3。在未形成多晶矽薄膜 1 0 3之面積上顯露出平坦的第一絕緣薄膜1 0 2。在其 上形成鋁薄膜1 0 5。位於點狀多晶矽薄膜1 0 3形成面 積上之鋁薄膜1 0 5表面因多晶矽薄膜1 0 3圖型之影響 而粗糙。照射於此部分之光會擴散反射。因此之故，此區 域可作爲低光反射區域1 0 7。另一方面，在未形成多晶 矽薄膜1 0 3之面積上鋁薄膜1 0 5係平坦的，可作爲高 光反射區域106。光束沿著圖13 (a)中A — A#線 方向上掃描而得之光反射量，在由平坦表面之鋁薄膜 1 0 5所形成之高光反射區域中係大的，並且在由粗糙表 面之鋁薄膜1 0 5所形成之低光反射區域1 0 7中係小的 ，如圖13(c)所示。在圖13 (a)、 （b)及（c )之例子中，利用光擴散反射效應形成低光反射區域 1 0 7。爲了產生光擴散反射，點狀圖型由和結合元件相 同薄膜之多晶矽薄膜1 0 3所形成。也可利用非點狀之格 狀或條狀圖型來產生光擴散反射，藉而獲得如圖1 3 ( c )所示之光反射圖型。 在圖1 3 ( b )中，第二絕緣薄膜得形成於第一絕緣 薄膜102或多晶矽薄膜103上。再者，金靨材料例如 鎢、鉻及金得用來代替鋁薄膜1 0 5作爲高反射薄膜。 本紙張尺度述州中囤國家捸準（CNS ) Λ4規格（210X297公釐） •24- A7 B7 五、發明説明（22) 如前所述，高光反射區域1 0 6及低光反射區域 1 0 7之邊界係由和結合元件相同薄膜材料之多晶矽薄膜 1 0 3圖型所確定。因此之故消除在習知的定位圖型中所 遭遇因形成結合元件之多晶矽與形成定位圖型之鋁圖型間 校準誤差而產生之問題。 再者，雷射修正定位圖型4 0 1係位於垂直及水平畫 線區域2 0 3之交叉處，並且形成連續結構，具有比較粗 糙地定位於晶圓轉動方向之所謂iheta標誌功能以及精確地 定位每一個重複配置的半導體積體電路晶片2 0 1於X及 Y方向之修正標誌功能。據此，可減少在畫線區域2 0 3 中雷射修正定位圖型所佔據的面積。 圖1 5 ( a )係本發明之半導體裝置的第十二實施例 中定位圖型之平面圖，圖1 5 ( b )係本發明之半導體裝 置的第十二實施例中定位圖型之剖面圖，並且圖1 5 ( c )係顯示光束掃描本發明之半導體裝置的第十二實施例中 定位圖型處之光反射量的變動。光反射量係沿著圖1 5 ( a )中B — B -線方向上掃描而得之値。 本發明之第十二實施例中雷射修正定位圖型401係 位於垂直及水平畫線區域2 0 3之交叉處，類似於圖1 3 (a )至（c )中所示之第十—實施例。 與第十一實施例不同處係在於高反射區域1 〇 6由低 反射區域1 0 7所夾住並且雷射修正定位圖型4 0 1之形 狀係鑰匙形相對於圖1 3所示之第--實施例中之十字形 本紙張尺度通/0中囤國家標準（CNS ) Α4规格（210x297公釐） 1JI0------訂----Id (誚尤閲讀背面之注意事項再"寫本頁) -25- 部 屮 K 3< -T :<1ί f 合 η >λ 印 h- 當每點多晶矽薄膜1 A7 _______ B7 五、發明説明（23 ) 雷射修正定位圖型得爲高光反射區域1 0 6或低光反 射區域1 0 7其中之一被其他區域夾住之形狀。圖1 5 ( a)至（c)中所示之第十二實施例顯示與圖13 (a) 至（c )中所示之第十一實施例排列相反之例子，顯示如 此的結構係適合的。再者，雷射修正定位圖型4 0 1之形 狀得爲異於半導體積體電路晶片2 0 1中墊區域2 0 2及 諸如此類者之特殊形狀，以便能自動地辨識。雖然圖1 5 (a)之例子係鑰匙形，但圖13 (a)及圖15(a) 中所示之形狀並不受限制。 藉著參照圖13 (a)至（c)之參考特徵以便省略 其他說明。 圖1 6 ( a )係表示根據本發明之雷射修正定位圖型 的一部分及雷射光束之典型平面圖。 在圖16 (a)中，a代表點狀多晶矽薄膜1〇3集 合之線及體尺寸（與結合元件相同材料之點的尺寸及未形 成點之部分的尺寸之和。） 再者，d表示雷射光點50 1之直徑。 圖1 6 ( b )係表示高光反射區域光反射量與低光反 射區域光反射量間差異之對比關係，並且每點多晶矽薄膜 有線及體尺寸a » 0 3之線及體尺寸a減少時對比 會改善。考慮以雷射光一5 0 1之直徑d作爲指標，倘若 每點多晶矽薄膜1 0 3之線及體尺寸a小於雷射光點直徑 d ’則可獲得實用的對比。無論如何，爲了取得較高的對 本纸張尺度違州中國國家榇準（CNS ) A4规格（210X297公藿） ----IO------訂------0 (邡ilwti背面之注意事項再iAWT本页) -26- ，-""'中^^^球而”^^^爹^竹^印*'·'^ A7 B7 五、發明説明（24 ) 比，每點多晶矽薄膜1 0 3之線及體尺寸a最好係小於雷 射光點直徑d之一半。雖然圖1 6中之說明係針對點狀多 晶矽薄膜1 〇 3之例子，但對於格狀或條狀圖型前述之說 明仍然真實。例如對於條狀圖型，圖1 6中所說明之尺寸 a即換成多晶矽薄膜1 0 3之較短邊與至同線上相鄰多晶 矽薄膜103之間隙之和》 圖1 7 ( a )係代表根據本發明之雷射修正定位圖型 的一部分及雷射光束之典型平面圖。 在圖17 (a)中，b代表低光反射區域107之雷 射掃描方向之尺寸，然而d代表雷射光點直徑。 圖1 7 ( b )係顯示高光反射區域1 0 6與低光反射 區域1 0 7間光反射量差異之對比與低光反射區域1 0 7 之雷射掃描方向尺寸間之關係。 對比會隨著低光反射區域107在雷射掃描方向上尺 寸b之增加而增加。考慮以雷射光點5 0 1之直徑d作爲 指標，在b幾乎大於b處可獲得實用的對比。爲了取得較 高的對比，b之尺寸最好係d的雨倍。雖然在圖1 7中係 說明點狀例子，但對於低光反射區域1 0 7係格狀或條狀 圖型之例子前述之說明仍然真實。 再者，圖1 7中之說明係針對低光反射面域10 7被 高光反射區域1 0 6夾住之例子》對於如同說明於圖2例 子中之高光反射區域1 0 6被低光反射區域1 0 7夾住之 例子，將圖1 7中所說明之b應用至高光反射區域1 〇 6 之尺寸也會獲得類似結果。 本紙張尺度迭扪肀囤國家標準（CNS } A4規格（210X297公釐） ----io—-----訂--------0 (誚先閲讀背面之注意事項再功朽本頁) -27- A7 _____ B7 五、發明説明（25 ) 再者，在本發明之雷射修正定位圖型中每點多晶矽薄 膜1 0 3之線及體尺寸a與畲射光點5 0 1之直徑d間之 較佳尺寸關係和低光反射區域1 0 7之雷射掃描方向上尺 寸b與雷射光點5 0 1直徑d間之較佳尺寸關係也可以應 用至前述之本發明第一至第十二實施例每一個中，如同利 用圖16及圖17所作之說明。 圖1 8係利用本發明之定位圖型作雷射修正之結合元 件的平面圖。雷射點3 2可照射在結合元件3 1之中央。 根據本發明之半導體裝置相當適合於包含涉及重大變 動之半導體元件的半導體積體電路。舉例而言，圖1 9係 由具高崩潰強度之MOS電晶體所形成之電壓偵測IC之 區塊圖。與雙載子I C比較下MO S I C涉及重大的變動 。尤其對高崩潰強度特徵而言，因爲閘極介電薄膜厚，類 比特性中之變動便較大。因此之故，對於類比MO S I C 而言，如圖1 9中所示需要大面稹予結合元件。藉著預備 1 0個或更多個結合元件，可獲得變動減低之類比特性。 藉著利用本發明之雷射修正定位圖型，如圖1 0所示 對於電壓偵測I C而言可降低結合元件所佔據的面積，進 而達成整個I C面積之降低。雖然未顯示出，但根據本發 明之雷射修正圖型，倘若應用於串聯調節器I C、交換調 節器I C、鋰電池保護I C及諸如此類者，仍會獲得相似 的效應。再者，因爲雷射修正定位精確度改善了，故可藉 由平面地更動排列方向而使在這些I C s中所使用的結合 元件放置於兩個或更多個位置上。本發明之定位圖型可施 本紙張犬度这州中囤國家標準（CNS ) A4規格（2丨0X297公釐） 1—J 訂 ο {"先閱讀背面之注意事項再楨ίΗ本頁) -28- A7 __ _B7 五、發明説明（26 ) * 行於任何畫線區域或T E G晶片或半導體積體電路晶片上 。在所配置之畫線區域或T E G晶片上，提供減少半導體 積體電路晶片面積之效應。 再者，雖然本發明適合用於類比MO S I C s ，但仍 然可用於數位I C s。本發明適合用於具極低變動之高密 度類比雙載子I C s。 目前爲止所討論之實施例係以用於雷射修正之結合元 件由多晶矽薄膜所形成之例子作·說明。本發明並不限於多 晶矽薄膜。藉著使用和形成雷射修正結合元件之薄膜相同 的薄膜，低光反射區域1 0 7得爲點狀圖型或諸如此類者 之形狀以產生光擴散反射。 雷射修正定位圖型具有介於高光反射區域與低光反射 區域間之邊界，即光反射度突然變動之區域，可由和雷射 修正結合元件相同薄膜所形成之圖型來界定。再者，顯示 了雷射修正定位圖型之內部尺寸與雷射光點直徑間之較佳 關係。此提供如下之效應。 (1 )可穩定地切割結合元件。 (2 )在需要多數個結合元件之I C s中，可使結合 元件面積縮小。 (3 )在需要多數個結合元件之I C s中，可設計在 不同方向上二個或更多個位置處之結合元件區域。 再者，根據本發明之雷射修正定位圖型可形成於半導 體積體電路晶片內所存在的墊區域上，或放置於畫線區域 交叉處作爲連續結構，以便用爲比較粗糙地定位關於半導 本紙張尺度述州十囤國家標準（CNS ) A4規格（210X297公釐） (誚先閱讀背面之注意事項再填寫本頁) ό 訂 -29 - A7 ___B7 五、發明说明（27 ) 體晶圓轉動方向之theta標誌功能及精確地依序定位重複放 置之半導體積體電路之修正標誌功能。 此提供如下之效應。 (4 )在切割（分割程序）成半導體積體電路中，分 割切口受損害極少而使通量增加。再者’減低半導體積體 電路受損害之恐懼。 (5 )在畫線區域中’半導體積體電路製造程序（所 謂第一半程序）中所用之檢測圖·型或圖型校準標誌等揷入 處之面積擴大了，藉此得有適合的程序控制。 本紙張尺度速/11中國國家標準（CNS ) A4規格（210X297公嫠） --------^—o—-----1T------0 (誚先閱讀背面之注意事項再妨寫本頁) -30 -, 1T -10- The Central Standards Bureau of the Ministry of Economic Affairs only prints A7 H7 printed by Hezhu Co. 5. Description of the invention (8) and Figure 10 (C) shows the light reflection along the line C-CZ in Figure 10 (a) the amount. FIG. 11 (a) is a plan view of a laser correction positioning pattern in a ninth embodiment of a semiconductor device of the present invention, and FIG. 11 (b) is a laser correction positioning pattern in a ninth embodiment of a semiconductor device of the present invention. A cross-sectional view of the pattern, and FIG. 11 (c) shows a cross section along D_D in FIG. 11 (a). < Amount of light reflection of the line. Fig. 12 (a) is a plan view of a laser correction positioning pattern in the tenth embodiment of the semiconductor device of the present invention, and Fig. 12 (b) is a laser correction positioning pattern in the tenth embodiment of the semiconductor device of the present invention Fig. 12 (c) shows the amount of light reflection along line E- in Fig. 12 (a). FIG. 13 (a) is a plan view of a laser correction positioning pattern in the eleventh embodiment of the semiconductor device of the present invention, and FIG. 13 (b) is a laser correction in the eleventh embodiment of the semiconductor device of the present invention A cross-sectional view of the positioning pattern, and FIG. 13 (c) shows the amount of light reflection along the line A-A in FIG. 13 (a). FIG. 14 is a plan view of a coupling element of a conventional semiconductor device. FIG. 15 (a) is a plan view of a laser correction pattern in a twelfth embodiment of the semiconductor device of the present invention, and FIG. 15 (b) is a laser correction positioning pattern of the twelfth embodiment of the semiconductor device of the present invention. Sectional view 'and Figure 1c) are light reflection diagrams along line B — in Figure 15 (a) _1 6 (a) are laser correction positioning patterns according to the present invention. Compensation rate (CNS) Λ4 叱 柢 (210X 297 ^) ^.> ----: ---; -------- IT ------ Q ΐ »Jujube ^ βί / ί-ί? 本 刀) -11 · Printed by A7 _H7 _ of the Zhubei Co., Ltd., the Shibuzu Bureau of the Central Ministry of Economic Affairs, and only a part of the description of the invention (9) and a typical plan view of the laser light spot, and Fig. 16 (b) shows the comparison between the light reflection amount in the high-light reflection area and the light reflection amount in the low-light reflection area, and the polycrystalline silicon thin film at each point is wired and the size a. Fig. 17 (a) is a typical plan view representing a part of a laser correction positioning pattern and a laser light spot according to the present invention, and Fig. 17 (b) is a diagram showing a light reflection amount in a high light reflection area and a light reflection in a low light reflection area The difference between the quantities, and the size b is in the laser scanning direction of the low light reflection area. FIG. 18 is a plan view of a coupling element of a conventional semiconductor device. FIG. 19 is a block diagram of a semiconductor device of the present invention. ---- i-Q ------. Order ------ α (Count reading the memorandum and then write the script) The main component comparison table 3 0 1 theta mark 2 0 3 drawing Line area 3 0 2 Correction mark 3 0 3 Correction mark 2 0 1 Semiconductor integrated circuit wafer 2 0 2 Pad area 1 0 2 First insulating film 1 0 1 Substrate 1 0 5 Aluminum film 3 2 Laser irradiation area 3 1 Combination Elements 1 0 6 High-light reflection area 1 0 7 Low-light reflection area The paper size is applicable to the Chinese National Standard (CNS) Λ4% cypress (210X29 ·? 公 # > -12- Ministry of Economic Affairs, Central Bureau of Standards, Only Consumer Cooperatives Printed A7 Η 7 V. Description of the invention (1〇) 1 0 3 Polycrystalline silicon film 1 0 4 Second insulating film 2 0 4 Laser correction positioning pattern 4 0 1 Laser correction positioning pattern 5 0 1 Laser spot invention Example: Laser correction positioning pattern with ^ highlight · reflection I domain and lowlight reflection area ___ —— '*. Pattern 1 formed by using the same film as the laser · correction combination element. Long highlight_ The boundary of the reflection area and low light, that is, the area where the light reflectance changes sharply. This makes the laser正 _ 之 _ 宜 行 ^ Accurate due to the influence of typographical errors during wafer manufacturing. In addition, the laser correction positioning pattern must also be changed from the line drawing area to the pad area, which is used as a semiconductor integrated circuit chip The electrical connection between the inside and the outside. A continuous structure is formed in the area of the line drawing, and the structure can be used as the theta mark for relatively rough positioning of the semiconductor wafer rotation direction and for the precise and sequential positioning of repeatedly placed semiconductor products The correction mark of the body circuit. Placed at the intersection of the drawing lines can reduce the area occupied by the laser correction positioning pattern in the drawing area. Furthermore, the size of the laser correction positioning pattern is defined by the diameter of the laser beam. Index to make the reflectance between the high-light reflection area and the low-light reflection area have a large difference (in order to increase the contrast). Therefore, a structure that can fully display the performance of the laser correction positioning pattern can be obtained. The following will be based on the illustration To illustrate the invention. This paper size is applicable to China National Standards (CNS > You (210χ2 < ίΠ 公 尨} !! q ------ 1 ------ α {^ Read first ^ " and note ^ 5 ^ item again- " {" this page) -13- The Central Standard Bureau of the Ministry of Economic Affairs of the People's Republic of China only prints A7 B1 in the Consumer Cooperatives. 5. Description of the Invention (11) Incidentally, unless other well-known bonding elements used for laser correction are formed of polycrystalline silicon thin films, for the sake of simplicity, it is described below. Explanation will be omitted. FIG. 1 (a) is a plan view of a positioning pattern of the present invention, and FIG. 1 (b) is a graph showing changes in the amount of light reflection at the scanning of a light beam. The amount of light reflection is obtained by scanning along the direction A-A / in Figure 1 (a). The positioning pattern of the present invention is constructed by the high-light reflection area 106 and the low-light reflection area 107 inside them, as shown in Fig. 1 (a). In the example of Fig. 1, the low-light reflection area 107 is formed by the effect of light diffusion reflection. Polycrystalline silicon film 103, which is the same as the bonding element, is spot-shaped for diffuse reflection. In order to diffuse the reflection, the pattern should be a non-spotted grid, stripe or the like, thereby obtaining a light reflection pattern as shown in Fig. 1 (b). The bonding element is preferably a thin film that easily absorbs light and is suitable for cutting. The preferred film is a polycrystalline silicon film. Polycrystalline silicon films absorb light easily and are suitable for cutting with laser irradiation. By forming a polycrystalline silicon thin film 1 0 3 with a dot pattern as shown in FIG. 1 (a) as a low light reflection region 1 0 7 on the inside of the pattern, a contrast having a large light reflection amount can be obtained. The high-light reflection area 106 on the semiconductor substrate can be constructed conventionally from a field region formed by an oxide film or the like. Fig. 2 (a) is a plan view of a positioning pattern in a second embodiment of the present invention, and Fig. 2 (b) is a graph showing changes in the amount of light reflection at the scanning of a light beam. The light reflection child is obtained by scanning along the C-C / direction in Fig. 2 (a). The positioning pattern of the present invention is constructed by a low-light reflection area 107 and a high-light reflection area 10 6 on the inside thereof, as shown in FIG. 2 (a). (CNS) ΛΜί 栳 (2WX297) I nnnnn II nu II nn τψ I --- I Lt Q 1 ό • 14- The Central Bureau of Standards and Economics of the Ministry of Economic Affairs only works with consumer cooperation Du Yin ¾ A7 _'_ Η 7 5 The invention description (12) has a structure opposite to the example shown in FIG. 1 (a). As long as one of the low-light reflection area 1 07 or the high-light reflection area 10 6 clamps the other side [J to obtain a suitable laser correction positioning pattern, the structure shown in FIG. 2 (a) is also allowed. As for the other parts, the same reference features as those of Fig. 1 are omitted and will not be described again. Fig. 4 (a) is a plan view of a positioning pattern in a third embodiment of the present invention, Fig. 4 (b) is a sectional view of the positioning pattern in a third embodiment of the present invention, and Fig. 4 (c) is a light beam Scanning of the light reflection at the positioning pattern of the third embodiment. The amount of light reflection is obtained by scanning along the A-A / direction in Fig. 4 (a). The positioning pattern in the third embodiment of the present invention is constructed by a high-light reflection area 106 and a low-light reflection area 107 on the inside thereof, as shown in FIG. 4 (b). The structure of the positioning pattern of the present invention will be described using Figs. 4 (a) and 4 (b). ’A silicon oxide film or the first insulating film 10 2 is formed on a silicon substrate 1 0 1. Dot-shaped polycrystalline silicon films 103 are collectively formed on the first insulating film 102. On the area where the polycrystalline silicon thin film 103 is not formed, a flat first insulating thin film 102 is exposed. A second insulating film 104 is formed thereon with a PSG film or the like, and an aluminum film 105 is formed on the second insulating film 104. The surface of the aluminum thin film 105 on the formation area of the dot-shaped polycrystalline silicon thin film 103 is roughened by the pattern of the polycrystalline silicon thin film 103. Light shining on this area will diffuse and reflect. Therefore, this area can be used as a low-light reflection area 107. On the other hand, in the area where the polycrystalline silicon thin film 1 0 3 is not formed, the aluminum paper is suitable for the Chinese paper standard (CNS) Λ4 Yue Hong () IHIQ Order ----- d (诮 51 阅 ¾.¾) Note the remarks R) -15- Printed by the Central Standards Bureau of the Ministry of Economic Affairs, β Industrial Consumption, Hezhu Co., Ltd. A7 _____ B7 ___ V. Description of the invention (13) 1 0 5 has a flat surface, which can be used as a high-light reflection area 1 〇 6. Where the light beam is scanned along the A-A > line direction in Fig. 4 (a), as shown in Fig. 4 (c), in the high-light reflection area 1 0 6 formed by the flat surface aluminum thin film 105 There is a large amount of light reflection at the place, and there is a small amount of light reflection at the low light reflection area 10 7 formed by the aluminum film 105 with a rough surface. In the examples of Figs. 4 (a), (b), and (c), a low-light reflection area 1 · 07 is formed using the light diffusion reflection effect. In order to generate light diffusive reflection, the dot pattern is formed by a polycrystalline silicon thin film 103 which is the same thin film as the bonding element. It is also possible to use a non-spot-like pattern such as a grid or a strip to generate light diffusion reflection, thereby obtaining a light reflection pattern as shown in FIG. 4 (c). The first insulating film 102 and the second insulating film 104 in FIG. 4 (b) are not necessarily necessary and can be omitted. Further, a metal material such as tungsten and chromium may be used instead of the aluminum thin film 105 as the highly reflective thin film. As mentioned before, the boundary between the high-light reflection area 106 and the low-light reflection area 107 is determined by the polycrystalline silicon thin film 103 pattern of the same thin film material as the bonding element. In this way, the problems caused by the calibration error between the polycrystalline silicon forming the bonding element and the aluminum pattern forming the positioning pattern encountered in the conventional positioning pattern are eliminated. 5 (a) is a plan view of a positioning pattern in a fourth embodiment of a semiconductor device of the present invention, FIG. 5 (b) is a cross-sectional view of the positioning pattern in a fourth embodiment of a semiconductor device of the present invention, and FIG. 5 (c) shows the variation of the amount of light reflection at the positioning pattern in the fourth embodiment of the semiconductor device of the present invention by beam scanning. The amount of light reflection is along C in Figure 5 (a). This paper scale is applicable to the Chinese national standard (CNS > Bai (210X297 ^ 1 .'- n I n In-—.1 n II i Hi ---- * 5TI m n___ (" Note from previous test & item 44¾ page) -16-Printed by the Central Standards Bureau of the Ministry of Industry and Industry Cooperatives and printed A7 _______ Η 7 ___ 5. Direction of the invention (14) Line direction It is obtained by scanning above. The positioning pattern in the fourth embodiment of the present invention is constructed by the high-light reflection area 106 and the low-light reflection area 107 on the inside, similar to FIG. 4 (a) to The third embodiment shown in (c) is different from the third embodiment shown in FIG. 4 in that the high-light reflection area 10 6 is formed of an aluminum thin film 10 5 on a flat polycrystalline silicon thin film 103. If the high-light reflection area 106 is formed by a high-reflection film on a flat bottom layer, its effect can be achieved. Therefore, such a structure is possible. By referring to and FIG. 4 (a) to (c) The same reference features are omitted in order to omit other explanations. Fig. 6 (a) is a plan view of a positioning pattern in a fifth embodiment of a semiconductor device of the present invention, 6 (b) is a cross-sectional view of a positioning pattern in a fifth embodiment of the semiconductor device of the present invention, and FIG. 6 (c) is a light beam scanning showing the light at the positioning pattern in the fifth embodiment of the semiconductor device of the present invention Changes in the reflection amount. The light reflection amount is obtained by scanning along the line D-D in FIG. 6 (a). The positioning pattern in the fifth embodiment of the present invention is configured by configuring a low-light reflection area 1 0 7 It is constructed on the outside and configured with a high-light reflection area 10 6 inside. The positioning pattern is a shape in which one of the high-light reflection area 1 06 or the low-light reflection area 1 0 7 is sandwiched by other areas. In the figure The fifth embodiment shown in 6 (a) to (c) shows an example opposite to the arrangement of the third embodiment shown in Figs. 4 (a) to (c) to show that the shape is suitable. 4 (a) to (c) are referred to in order to omit other descriptions. Fig. 7 (a) is a sixth embodiment of the semiconductor device of the present invention. ; Λ4 so dry (2 丨 0x297d) ---- ΊΙΊ—Q ------ subscribe ------ Q (" " Note ^ Matters, please fill in this page again) -17- Central standard of the Ministry of Economic Affairs and Decoration --- The bureau only consumes and prints A7 B7 of Hezhusha V. Description of the invention (15) A plan view of the bitmap, Figure 7 (b) FIG. 7 is a cross-sectional view of a positioning pattern in a sixth embodiment of the semiconductor device of the present invention, and FIG. 7 (c) shows the amount of light reflection at the positioning pattern in the sixth embodiment of the semiconductor device of the present invention by a light beam scanning change. The amount of light reflection is obtained by scanning along the E-E > line direction in Fig. 7 (a). The positioning pattern in the sixth embodiment of the present invention is constructed by arranging a low-light reflection area 106 on the outside and arranging a high-light reflection area 107 on the inside. The positioning pattern is a shape in which one of the high-light reflection area 106 or the low-light reflection area 1 07 is sandwiched by other areas, similarly to the description in the fifth embodiment. The sixth embodiment shown in Figs. 7 (a) to (c) shows an example in which the arrangement is reversed to that of the fourth embodiment shown in Figs. 5 (a) to (c). The other descriptions are omitted by referring to the same reference features as those of Figs. 4 (a) to (c). The first insulating film 102 and the second insulating film 104 in Figs. 4 to 7 are not necessarily required, and may be omitted. Further, instead of the aluminum thin film 10, a metal material such as tungsten, chromium, and gold may be used as the highly reflective thin film. Fig. 8 (a) is a typical plan view of a semiconductor body circuit wafer having positioning patterns of the seventh to tenth embodiments of the semiconductor device according to the present invention. Fig. 8 (b) is a typical plan view of the pad area in the laser correction positioning pattern in Fig. 8 (a). As shown in Fig. 8 (a), a semiconductor integrated circuit wafer 201 is provided with a pad region 202, which is formed of a conductive film such as aluminum to be electrically connected to the outside. In addition, there is a line drawing area 230 between adjacent semiconductor wafers 201. The size of this paper is common to China National Fengfeng (CNS) Α4 gauge (210x? V7 ^ $) ·-^ -------- iT ------ -18- Central Standard of the Ministry of Economic Affairs Printed by the Industrial and Commercial Hezhu Company A7 R7 V. Description of the Invention (16) Here, the laser correction positioning pattern according to the present invention is formed in the pad area 202. Fig. 8 (b) is a plan view showing the pad area 202 having the laser correction positioning pattern 204 according to the present invention. In FIG. 8 (b), a part of the pad area 2 0 2 is a laser correction positioning pattern 2 0 4 »The pad area 2 0 2 is essentially electrically connected to the outside. Since the laser correction positioning pattern region 204 is formed in the pad region 202, the laser correction positioning pattern pattern 204 can be introduced into the semiconductor integrated circuit without increasing the semiconductor integrated circuit-circuit chip area. Wafer. In Figs. 8 (a) and (b), the example shown is a laser correction positioning pattern 2 0 4 formed in a pad area 2 0 2. In any case, if necessary, a plurality of laser correction positioning patterns 2 0 4 must be formed in a pad area 2 0 2. One or more laser correction positioning patterns 2 0 4 must be formed in the plurality of pad regions 2 0 2. 9 to 12 are used to explain the laser correction positioning pattern according to the present invention in detail. FIG. 9 (a) is a plan view of a laser correction positioning pattern in a seventh embodiment of a semiconductor device of the present invention, and FIG. 9 (b) is a plan view of a laser correction positioning pattern in a seventh embodiment of a semiconductor device of the present invention Sectional view, and FIG. 9 (c) shows the variation of the light reflection amount at the laser correction positioning pattern in the seventh embodiment of the semiconductor device of the present invention when the beam is scanned. The light reflection amount is along FIG. 9 (a). A — A — Scanning in the line direction. As shown in FIG. 9 (b), in the seventh embodiment of the present invention, the laser correction positioning pattern is composed of a high-light reflection area 106 and a low-light reflection area inside the paper. The paper dimensions are applicable to the Chinese national standard (CNS> (2 丨 0X297 Public Office) —ιί! Ο ^ ------ Order ------ α < Jian Xianjian " Notes on the back /}-"-{>, 3 books ^?) * 19-A7 ____B7 V. Description of the invention (17> 1 0 7). 9 (a) and FIG. 9 (b), the structure of the laser correction positioning pattern will be described. A silicon oxide film or the first insulating film 10 2 is formed on a silicon substrate 101. In the first On the insulating film 100, dot-shaped polycrystalline silicon films 103 are formed in groups. In the area where no polycrystalline silicon film 103 is formed, the first insulating film 100 is exposed. The second insulation of the PSG film or the like The thin film 1 04 is formed thereon, and the aluminum thin film 105 is formed on the second insulating thin film 104. The surface of the aluminum thin film located on the formation area of the dot-shaped polycrystalline silicon thin film 103 is due to the polycrystalline silicon thin film 103 It is rough due to the influence of the type, so that the light irradiated on this area diffuses and reflects. Therefore, this area can be used as a low-light reflection area 107. On the other hand, an aluminum thin film is formed on the area where the polycrystalline silicon thin film 103 is not formed. 1 05 is flat and can be used as the highlight reflection area 1 06. The light beam is along A-A in Fig. 9 (a) > Scanning in the line direction The Central Standards Bureau of the Ministry of Economic Affairs only prints the products printed by Hezhusha, as shown in Figure 9 (c), in the high-light reflection area 1 0 6 formed by a flat aluminum film 105. There is a large amount of light reflection at the place, and there is a small amount of light reflection at the low light reflection area 107 formed by the aluminum film 105 with a rough surface. In the figures (a), (b), and (c ) Example, the low-light reflection area 1 107 is formed by the light diffusion reflection effect. In order to generate the light diffusion reflection, the dot pattern is formed by a polycrystalline silicon thin film 103 which is the same thin film as the bonding element. A grid or The strip pattern is used to generate light diffusion reflection to obtain the light reflection pattern as shown in Figure 3 (c). The paper size il Caiguan household materials (CNS) Λ4㈣ (210X297 ^ 1 -20-the center of the Ministry of Economic Affairs) Standard Bureau Consumption and Printing of Hezhusha ¾ A7 Η 7 V. Description of the Invention (18) One of the first insulating film 1 0 2 or the second insulating film 1 0 4 in Figure 9 (b) is not necessarily required 'It can be omitted. Moreover', the laser correction positioning pattern 2 0 4 can be provided in the pad area 2 0 2 with silicon. The same potential at the bottom 1 0 1 'This configuration is to electrically connect the aluminum thin film 10 5 and the silicon substrate 101. Furthermore,' laser correction positioning pattern 2 is placed in a pad region having the same potential as the silicon substrate 1 0 1 At point 04, the first-insulating film 102 and the second-insulating film 104 may be omitted to provide a form of electrical-connection between the aluminum film 105 and the silicon substrate 101. Furthermore, metal materials such as tungsten, chromium, and gold can be used instead of the aluminum thin film 105 as a high-gloss reflective film as long as it is suitable for electrical connection to the outside. As mentioned before, the boundary between the high-light reflection area 106 and the low-light reflection area 107 is determined by the polycrystalline silicon thin film 103 pattern of the same thin film material as the bonding element. Therefore, the problems caused by the alignment error between the polycrystalline silicon forming the bonding element and the aluminum thin film forming the laser correction positioning pattern encountered in the conventional laser correction positioning pattern are eliminated. FIG. 10 (a) is a plan view of a laser correction positioning pattern in an eighth embodiment of a semiconductor device of the present invention, and FIG. 10 (b) is a laser correction positioning pattern of an eighth embodiment of a semiconductor device of the present invention FIG. 10 (c) is a cross-sectional view showing the change in the amount of light reflection at the laser correction positioning pattern in the eighth embodiment of the semiconductor device of the present invention by beam scanning. The amount of light reflection is obtained by scanning along the C-C-line direction in Fig. 10 (a). In the eighth embodiment of the present invention, the laser correction positioning pattern is constructed by a high-light reflection area 106 and a low-light reflection area 107 inside it, similar to FIGS. 9 (a) to (c). Example shown in. This paper size is applicable to China National Standards (CNS) Λ4 gauge (2 丨 0χ? ^ Ϋfactory 5 ----.--- ^ ------ order ------ (i 而 之Note ¾ Matters need to be refilled.) -21-A7 _____ Η 7 V. Description of the invention (19) The seventh embodiment differs from the seventh embodiment in that the high-light reflection area 1 06 is an aluminum thin film located on a flat polycrystalline silicon thin film 103. It is formed by 105. This structure is possible because as long as the high-light reflection region is formed by a high-light reflection film on a flat bottom layer, the high-light reflection film 10 can fulfill its role. By referring to FIG. 9 (a) to (C) The same reference features are omitted in order to omit other explanations. Fig. 1 (a) is a plan view of a laser correction positioning pattern in a ninth embodiment of the semiconductor device of the present invention, and Fig. 1 (b) is a semiconductor of the present invention A cross-sectional view of a laser correction positioning pattern in a ninth embodiment of the device, and FIG. 11 (C) shows a light reflection amount at the laser correction positioning pattern in a ninth embodiment of the semiconductor device of the present invention by scanning a light beam The change of "light reflection amount" is obtained by scanning along the D-D > line direction in Fig. 1 1 (a). In the ninth embodiment, the laser correction positioning pattern is constructed by arranging a low-light reflection area 107 on the outside and a high-light reflection area 1 06 on the inside. The laser correction positioning pattern is a high-light reflection area 1 A shape in which one of the 0 or low-light reflection area 1 0 7 is sandwiched by the other area. The ninth embodiment shown in FIGS. 1 1 (a) to (c) is the central part of the watch body. Industrial and consumer cooperatives' seals.-IMIQI. (&Quot; 1 read 15 for details and fill in this R again) α is the opposite of the seventh embodiment shown in Figures 9 (a) to (c) An example shows the possibility of this arrangement. By referring to the same reference features as in Figs. 3 (a) to (c) in order to omit other explanations. Fig. 12 (a) is a tenth embodiment of the semiconductor device of the present invention. FIG. 12 (b) is a cross-sectional view of a laser correction positioning pattern in a tenth embodiment of the semiconductor device of the present invention, and FIG. 12 (c) shows a beam scanning of the present invention. The first paper standard for semiconductor devices uses China National Standards (CNS) Λ4 Regulations (2 丨 0 × 297 cm) • 22 A7 B7 _ 5. Description of the invention (20) The variation of the light reflection amount at the laser correction positioning pattern in the tenth embodiment. The light reflection amount is scanned along the E-E-line direction in Fig. 12 (a) Then, the laser correction positioning pattern in the tenth embodiment of the present invention is constructed by arranging the low-light reflection area 107 on the outside and the high-light reflection area 1 06 on the inside. The laser correction positioning The pattern is a shape in which one of the high-light reflection area 106 or the low-light reflection area 107 is sandwiched by other areas, similarly to the description in the eighth embodiment. The tenth embodiment shown in Figs. 12 (a) to (c) represents an example opposite to the arrangement of the eighth embodiment shown in Figs. 10 (a) to (c), showing the possibility of this arrangement. Other explanations will be omitted by referring to the same reference features as those in FIGS. 9 (a) to (c). FIG. 13 (a) is a plan view of a positioning pattern in the eleventh embodiment of the semiconductor device of the present invention, and FIG. 13 (b) is a cross-sectional view of the positioning pattern in the eleventh embodiment of the semiconductor device of the present invention And FIG. 13 (c) shows the change in the amount of light reflection at the positioning pattern in the eleventh embodiment of the semiconductor device of the present invention scanned by a light beam. The amount of light reflection is obtained by scanning in the direction of the A-A > line in Fig. 13 (a). In the eleventh embodiment of the present invention, the laser correction positioning pattern 401 is located at the intersection of the vertical and horizontal drawing area 203, as shown in FIG. 1 (a), and is a continuous structure with relatively rough positioning. The so-called theta mark function in the direction of wafer rotation and the function of accurately positioning the X-direction correction mark and Y-direction correction mark of the semiconductor integrated circuit wafer 201 in sequence. The shape of the laser correction positioning pattern 401 should have a special shape different from that of the pad area 202 in the semiconductor integrated circuit chip 201 for automatic identification. Accordingly, the example of FIG. 13 (a) is formed in a cross shape. The dimensions of this paper are described in ^ National Standard (CNS) A4 (210X297 mm) nn I n 4— IJ— n--I n I n n --- n I ——---- I (诮 先Note on the back of the occasional reading 1 page --- -23- A7 B7 V. Description of the invention (21) Figure 13 (b) is used to explain the laser correction positioning map according to the eleventh embodiment of the present invention The cross-sectional structure of type 4 0 1. {阅读 1 Read the precautions on the back of this page, and then go to this page) A silicon oxide film or the first insulating film 1 0 2 is formed on a silicon substrate 1 0 1 and A dot-shaped polycrystalline silicon thin film 103 is collectively formed on the insulating thin film 102. A flat first insulating thin film 102 is exposed on an area where the polycrystalline silicon thin film 103 is not formed. An aluminum thin film 105 is formed thereon. The surface of the aluminum thin film 105 on the formation area of the point-shaped polycrystalline silicon thin film 103 is roughened by the pattern of the polycrystalline silicon thin film 103. The light irradiated on this part will diffuse and reflect. Therefore, this area can be regarded as low Light reflecting area 107. On the other hand, the aluminum thin film 105 is flat on the area where the polycrystalline silicon thin film 103 is not formed, and can be used as a high Reflecting area 106. The amount of light reflection obtained by scanning the light beam along the direction of the A-A # line in FIG. 13 (a) is large in the high-light reflection area formed by the flat surface aluminum thin film 105. The low-light reflection area 107 formed by the aluminum film 105 with a rough surface is small as shown in Fig. 13 (c). In the examples of Figs. 13 (a), (b), and (c) The light diffusion reflection effect is used to form a low-light reflection area 107. In order to generate light diffusion reflection, the dot pattern is formed by a polycrystalline silicon thin film 1 0 3 of the same film as the bonding element. A non-dot grid or The strip pattern is used to generate light diffusion reflection, thereby obtaining a light reflection pattern as shown in Fig. 13 (c). In Fig. 13 (b), the second insulating film must be formed on the first insulating film 102 or Polycrystalline silicon film 103. In addition, gold materials such as tungsten, chromium, and gold can be used instead of aluminum films 105 as highly reflective films. This paper is described in the National Standards (CNS) Λ4 specification (210X297 mm) ) • 24- A7 B7 V. Description of the invention (22) As mentioned above, the high-light reflection area 106 and the low-light reflection area The boundary of 107 is determined by the polycrystalline silicon thin film pattern of the same thin film material as the bonding element. Therefore, the polycrystalline silicon forming the bonding element and the formation of the positioning pattern encountered in the conventional positioning pattern are eliminated. Problems caused by calibration errors between aluminum patterns. Furthermore, the laser correction positioning pattern 4 0 1 is located at the intersection of vertical and horizontal line drawing regions 2 0 3 and forms a continuous structure with relatively rough positioning on the crystal. The so-called iheta mark function of the circular rotation direction and the correction mark function of accurately positioning each repeatedly arranged semiconductor integrated circuit chip 2 01 in the X and Y directions. Accordingly, the area occupied by the laser correction positioning pattern in the line drawing area 230 can be reduced. FIG. 15 (a) is a plan view of a positioning pattern in the twelfth embodiment of the semiconductor device of the present invention, and FIG. 15 (b) is a cross-sectional view of the positioning pattern in the twelfth embodiment of the semiconductor device of the present invention Moreover, FIG. 15 (c) shows the change of the light reflection amount at the positioning pattern in the twelfth embodiment of the semiconductor device of the present invention by beam scanning. The amount of light reflection is obtained by scanning in the direction of the B-B- line in Fig. 15 (a). In the twelfth embodiment of the present invention, the laser correction positioning pattern 401 is located at the intersection of the vertical and horizontal line drawing areas 203, similar to the tenth shown in FIGS. 13 (a) to (c) — Examples. The difference from the eleventh embodiment lies in that the high-reflection area 1 06 is sandwiched by the low-reflection area 10 7 and the shape of the laser correction positioning pattern 4 0 1 is a key shape. -Cross-shaped paper standard in the example / 0 National Standard (CNS) Α4 size (210x297 mm) 1JI0 ------ Order ---- Id (Read the notes on the back of Chiyou & quot (Write this page) -25- Ministry K 3 < -T: < 1ί f 合 η &λ; λ mark h- When each point of polycrystalline silicon film 1 A7 _______ B7 V. Description of the invention (23) The laser correction positioning pattern is a high light reflection area 1 0 6 or a low light reflection area 1 0 7 The shape where one of them is sandwiched by the other area. The twelfth embodiment shown in Figs. 15 (a) to (c) shows an example of the reverse arrangement of the eleventh embodiment shown in Figs. 13 (a) to (c), showing that such a structure is suitable of. Furthermore, the shape of the laser correction positioning pattern 401 is different from the special shape of the pad area 202 in the semiconductor integrated circuit wafer 021 and the like, so as to be automatically recognized. Although the example of FIG. 15 (a) is a key shape, the shapes shown in FIGS. 13 (a) and 15 (a) are not limited. By referring to the reference features of Figs. 13 (a) to (c), other explanations are omitted. Fig. 16 (a) is a typical plan view showing a part of a laser correction positioning pattern and a laser beam according to the present invention. In FIG. 16 (a), a represents the line and volume size of the spotted polycrystalline silicon thin film 103 (the sum of the size of the point of the same material as the bonding element and the size of the portion where the point is not formed). In addition, d represents The diameter of the laser spot 501. Figure 16 (b) shows the contrast between the light reflection in the high-light reflection area and the light reflection in the low-light reflection area, and the polycrystalline silicon thin film at each point has a line and body size a »0 3 when the line and body size a decrease. Will improve. Considering the diameter d of laser light 501 as an index, a practical comparison can be obtained if the line and volume size a of each polycrystalline silicon thin film 103 is smaller than the diameter d 'of the laser light spot. In any case, in order to achieve a higher standard for this paper, it is against the Chinese National Standard (CNS) A4 specification (210X297). ---- IO ------ Order ------ 0 (邡 ilwti Note on the back, iAWT page again) -26-,-" " '中 ^^^ 球 而 "^^^ 爸爸 ^ 竹 ^ 印 *' · '^ A7 B7 V. Explanation of the invention (24) The polyline silicon thin film 103 line and volume size a per point is preferably smaller than one and a half of the diameter d of the laser light spot. Although the description in FIG. 16 is for the example of the dot polysilicon thin film 103, but for the grid or stripe The foregoing description of the pattern pattern is still true. For example, for a strip pattern, the dimension a illustrated in FIG. 16 is replaced by the short side of the polycrystalline silicon film 103 and the gap between adjacent polycrystalline silicon films 103 on the same line. 》 FIG. 17 (a) represents a part of the laser correction positioning pattern according to the present invention and a typical plan view of a laser beam. In FIG. 17 (a), b represents the laser scanning direction of the low-light reflection area 107. Size, but d represents the diameter of the laser light spot. Figure 17 (b) shows the contrast and low difference in light reflection between the high-light reflection area 1 0 6 and the low-light reflection area 1 0 7 The relationship between the size of the laser scanning direction of the reflective region 1 0 7. The contrast will increase as the size b of the low-light reflecting region 107 increases in the laser scanning direction. Consider the diameter d of the laser light spot 5 0 1 as an indicator A practical contrast can be obtained where b is almost larger than b. In order to obtain a high contrast, the size of b is preferably a rain multiple of d. Although point-like examples are illustrated in Figure 17, for low-light reflection area 1 0 7 is an example of a grid or bar pattern. The foregoing description is still true. Furthermore, the description in Figure 17 is for the example of the low-light reflection area 10 7 sandwiched by the high-light reflection area 1 0 6. In the example shown in FIG. 2, the high-light reflection area 1 0 6 is sandwiched by the low-light reflection area 10 7. Similar results can be obtained by applying b illustrated in FIG. 17 to the size of the high-light reflection area 1 0 6. . The national standard of this paper size (CNS) A4 specification (210X297 mm) ---- io —----- Order -------- 0 (诮 Please read the precautions on the back before (Deterioration page) -27- A7 _____ B7 V. Description of the invention (25) Furthermore, in the laser correction positioning of the present invention Polycrystalline silicon thin film 1 0 3 line and body size a and the size of the ray point 5 0 1 diameter d and the preferred dimensional relationship between the low-light reflection area 1 0 7 laser scanning direction size b and laser light The preferred dimensional relationship between the points 501 and the diameter d can also be applied to each of the aforementioned first to twelfth embodiments of the present invention, as described with reference to FIGS. 16 and 17. Fig. 18 is a plan view of a combination element for laser correction using the positioning pattern of the present invention. The laser point 32 can be irradiated in the center of the coupling element 31. The semiconductor device according to the present invention is quite suitable for a semiconductor integrated circuit including a semiconductor element involving a significant change. For example, Figure 19 is a block diagram of a voltage detection IC formed by a MOS transistor with high breakdown strength. MO S I C involves significant changes when compared to BIC. Especially for high collapse strength characteristics, because the gate dielectric film is thick, the variation in the analog characteristics is large. For this reason, for the analog MO S IC, a large-area pre-bonding element is required as shown in FIG. 19. By preparing 10 or more coupling elements, an analog characteristic with reduced variation can be obtained. By using the laser to modify the positioning pattern of the present invention, as shown in FIG. 10, for the voltage detection IC, the area occupied by the bonding element can be reduced, thereby reducing the entire IC area. Although not shown, according to the laser correction pattern of the present invention, similar effects can still be obtained if applied to the series regulator IC, the switching regulator IC, the lithium battery protection IC, and the like. Furthermore, since the laser correction positioning accuracy is improved, the alignment elements used in these ICs can be placed at two or more positions by changing the arrangement direction in a plane. The positioning pattern of the present invention can be applied to this paper. The national standard of the state (CNS) A4 specification (2 丨 0X297 mm) 1—J Order ο {" Read the precautions on the back before you read this page) -28- A7 __ _B7 V. Description of the Invention (26) * Run on any line drawing area or TEG chip or semiconductor integrated circuit chip. The effect of reducing the area of a semiconductor integrated circuit wafer is provided on the line drawing area or the T E G wafer. Furthermore, although the present invention is suitable for analogous MO S I C s, it is still applicable to digital I C s. The present invention is suitable for high-density analog bistatic I C s with extremely low variation. The embodiments discussed so far have been explained by taking an example in which the bonding element for laser correction is formed of a polycrystalline silicon film. The present invention is not limited to a polycrystalline silicon film. By using the same thin film as the thin film forming the laser correction bonding element, the low-light reflection area 107 can be a dot pattern or the like to generate light diffusion reflection. The laser correction positioning pattern has a boundary between the high-light reflection area and the low-light reflection area, that is, an area where the light reflectance changes suddenly. It can be defined by the pattern formed by the same film as the laser correction combination element. Furthermore, a better relationship is shown between the internal dimensions of the laser correction positioning pattern and the laser spot diameter. This provides the following effects. (1) The bonding element can be stably cut. (2) In the case of I C s that requires a plurality of bonding elements, the area of the bonding elements can be reduced. (3) In I C s which requires a plurality of bonding elements, the bonding element regions at two or more positions in different directions may be designed. Furthermore, the laser correction positioning pattern according to the present invention can be formed on a pad area existing in a semiconductor integrated circuit wafer, or placed at the intersection of a line drawing area as a continuous structure, so as to be used for relatively rough positioning about half The size of the paper is described in the State Ten Standards (CNS) A4 specification (210X297 mm) (诮 Please read the precautions on the back before filling in this page) ό Rev. 29-A7 ___B7 V. Description of the invention (27) Bulk wafer The theta sign function in the direction of rotation and the correct mark function for accurately positioning the repeatedly placed semiconductor integrated circuits in sequence. This provides the following effects. (4) In the dicing (dividing procedure) into a semiconductor integrated circuit, the dicing incision is rarely damaged and the flux is increased. Moreover 'reduces the fear of damage to the semiconductor integrated circuit. (5) In the line drawing area, the area of the entry area such as the test pattern, pattern, or pattern calibration mark used in the semiconductor integrated circuit manufacturing process (the so-called first half process) has been enlarged, thereby obtaining a suitable process. control. Standard paper speed / 11 Chinese National Standard (CNS) A4 specification (210X297 male) -------- ^ — o —----- 1T ------ 0 (诮 read the first (Notes, please write this page) -30-

Claims (1)

經濟部中央標準局負工消費合作社印製 B8 C8 ___D8__ 六、申請專利範圍 1 . 一種半導體裝置，具有通過半導體晶圓表面上畫 線而二維地重複放置成矩陣形狀之半導體積體電路，由雷 射修正所切割之結合元件、以及在半導體晶圓表面上之雷 射修正定位圖型，半導體裝置之特徵爲雷射修正定位圖型 係由和結合元件相同之薄膜所建構而成。 2 .如申請專利範圍第1項之半導體裝置，其中雷射 修正定位圖型係由高光反射區域及被高光反射區域夾住之 低光反射區域所形成。 · 3 .如申請專利範圍第1項之半導體裝置，其中雷射 修正定位圖型係由低光反射區域及被低光反射區域夾住之 高光反射區域所形成。 4 .如申請專利範圍第2項之半導體裝置，其中低光 反射區域係用以使光擴散反射之點狀或格狀或條狀圖型。 5 .如申請專利範圍第3項之半導體裝置，其中低光 反射區域係用以使光擴散反射之點狀或格狀或條狀圖型。 6 .如申請專利範圍第2項之半導體裝置，其中結合 元件係由多晶矽薄膜所形成。 7 .如申請專利範圍第3項之半導體裝置，其中結合 元件係由多晶矽薄膜所形成。 8 種半導體裝置，具有通過半導體晶圓表面上畫 線而二維地重複放置成矩陣形狀之半導體積體電路，半導 體積體電路上之結合元件、以及半導體晶圓表面上之雷射 修正定位圖型，半導體裝置之特徵爲包含由高光反射區域 及低光反射區域所形成之雷射修.正定位圖型、高光反射區 本紙張尺度逋用中國國家揉率（CNsTa4规格（210X297公釐) 10! (請先Μ讀背面之注$項再填寫本頁) -II 订 -31 - 經濟部中央#準局負工消費合作社印掣 A8 B8 C8 ___D8六、申請專利範圍 域係由形成於平坦底層上之髙光反射薄膜所 光反射區域係由形成於點狀或格狀或條狀光 上之高光反射薄膜所形成，該光擴散反射圖 元件相同的薄膜所建構而成。 9 .如申請專利範圔第8項之半導體裝 修正定位谓型係由高光反射區_及被高光反 1 低光反射區域所形成。 1 0 .如申請專利範圍第8·項之半導體 射修正定位圖'型係由低光反射^域及被低光 之髙光反射區域所形成。 1 1 .如申請專利範圍第8項之半導體 合元件係由多晶矽薄膜所建構而成。 1 2 .如申請專利範圍第8項之半導體 光反射薄膜係由鋁所建構而成。 1 3 .如申請專利範圍第8項之半導體 射修正定位圖型係放置於半導體積體電路晶 部電性連結之墊區域上。 1 4 .如申請專利範圍第8項之半導體 射修正定位圖型係放置於畫線之交叉處。 1 5 .如申請專利範圍第 射修正定位圖型係藉連續的高 地定位關於半導體晶圓k動方ή之所謂theta 地依序定位半導體積體電路於X方向及Y方 標誌所建構而成。 8項之半導體 光反射薄膜而 形成，並且低 擴散反射圖型 型係由和結合 置，其中雷射 射區域夾住之 裝置，其中雷 反射區域夾住 裝置，其中結 裝置，其中高 裝置，其中雷 片內作爲和外 裝置，其中雷 裝置，其中雷 整合比較粗糙 標誌以及緊密 向之所謂修正 (請先聞讀背面之注意事項再填寫本頁) ό 訂· 本紙張尺度適用中國國家橾率（CNS ) Α4规格（210X297公釐） -32- 經濟部中央標準局負工消费合作社印製 六、申請專利範固 1 6 .如申請專利範圍第1項之半導體裝置，其中在 雷射修正定位圖型中，由和結合元件相同材料之薄膜所形 成之點狀或格狀或條狀低光反射區域之線及體尺寸係小於 雷射光點之直徑》 1 7 .如申請專利範圍第1項之半導體裝置，其中在 雷射修正定位圖型中，由和結合元件相同材料之薄膜所形 成之點狀或格狀或條狀低光反射區域之線及體尺寸係小於 雷射光點直徑之一半》 · 1 8 .如申請專利範圍第2項之半導體裝置，其中低 光反射區域在雷射光束掃描方向上之尺寸係大於雷射光點 之直徑。 1 9 .如申請專利範圍第3項之半導體裝置，其中高 光反射區域在雷射光束掃描方向上之尺寸係大於雷射光點 之直徑。 · 2 〇 .如申請專利範圍第2項之半導體裝置，其中低 光反射區域在雷射光束掃描方向上之尺寸係大於兩倍雷射 光點之直徑。 2 1 .如申請專利範圍第3項之半導體裝置，其中高 光反射區域在雷射光束掃描方向上之尺寸係大於兩倍雷射 光點之直徑。 2 2 .如申請專利範圍第8項之半導體裝置，其中在 雷射修正定位圖型中，由和結合元件相同材料之薄膜所形 成之點狀或格狀或條狀低光反射區域之線及體尺寸係小於 雷射光點之直徑。 本紙張尺度適用中國國家梯準（CNS ) A4現格（210><297公釐） AVI— (請先聞讀背面之注$項再填寫本頁) •IT 订 -33 - 經濟部中央標率局真工消费合作社印11 A8 B8 C8 D8 夂、申請專利範圍 2 3 .如申請專利範圍第8項之半導體裝置，其中在 雷射修正定位圖型中，由和結合元件相同材料之薄膜所形 成之點狀或格狀或條狀低光反射區域之線及體尺寸係小於 雷射光點直徑之一半。 2 4 .如申請專利範圍第9項之半導體裝置，其中低 光反射區域在雷射光束掃描方向上之尺寸係大於雷射光點 之直徑》 2 5 .如申請專利範圍第Γ0項之半導體裝置，其中 高光反射區域在雷射光束掃描方向上之尺寸係大於雷射光 點之直徑。 2 6 .如申請專利範圍第9項之半導體裝置，其中低 光反射區域在雷射光束掃描方向上之尺寸係大於兩倍雷射 光點之直徑。 2 7 .如申請專利範圍第1 0項之半導體裝置，其中 高光反射區域在雷射光束掃描方向上之尺寸係大於兩倍雷 射光點之直徑。 2 8 .如申請專利範圍第1項之半導體裝置，其中在 半導體積體電路中之結合元件數目係10個或更多個。 2 9 .如申請專利範圍第8項之半導體裝置，其中在 半導體積體電路中之結合元件數目係10個或更多個。 3 〇 .如申請專利範圍第1項之半導體裝置，其中半 導體積體電路內具有位於不同方向之幾個結合元件群，該 結合元件群係由數目上至少一個或更多個排列於相同方向 之結合元件所形成。 本紙張尺度逍用中國國家橾率（CNS ) A4规格（210><297公釐） (請先Μ讀背面之注意事項再填窝本頁) 訂 -34 - 經濟部中央標準局工消費合作社印製 B8 C8 D8 六、申請專利範困 3 1 .如申請專利範圍第8項之半導體裝置，其中半 導體積體電路內具有位於不同方向之幾個結合元件群，該 結合元件群係由數目上至少一個或更多個排列於相同方向 之結合元件所形成。 3 2 .如申請專利範圍第1項之半導體裝置，其中半 導體積體電路係電壓偵測I C。 3 3 .如申請專利範圍第1項之半導體裝置’其中半 導體積體電路係串聯調節器I C。 3 4 ·如申請專利範圍第1項之半導體裝置’其中半 導體積體電路係交換調節器I C。 3 5 .如申請專利範圍第1項之半導體裝置’其中半 導體積體電路係鋰電池保護1C。 3 6 .如申請專利範圍第8項之半導體裝置’其中半 導體積體電路係電壓偵測I C。 3 7 .如申請專利範圍第8項之半導體裝置’其中半 導體積體電路係串聯調節器I C。 3 8 .如申請專利範圍第8項之半導體裝置’其中半 導體積體電路係交換調節器I C。 3 9 .如申請專利範圍第8項之半導體裝置’其中半 導體積體電路係鋰電池保護I C。 本紙張尺度逋用中國國家榡率（CNS ) A4规格（210X297公釐） • · * Ί 丨 _J 丨-otr------0--7 (請先»讀背面之注$項再填寫本頁} -35-Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives B8 C8 ___D8__ VI. Patent application scope 1. A semiconductor device having a semiconductor integrated circuit that is repeatedly placed in a matrix shape in two dimensions by drawing lines on the surface of a semiconductor wafer. The bonding element cut by the laser correction and the laser correction positioning pattern on the surface of the semiconductor wafer. The semiconductor device is characterized in that the laser correction positioning pattern is constructed of the same thin film as the bonding element. 2. The semiconductor device according to item 1 of the scope of patent application, wherein the laser correction positioning pattern is formed by the high-light reflection area and the low-light reflection area sandwiched by the high-light reflection area. 3. The semiconductor device according to item 1 of the patent application scope, wherein the laser correction positioning pattern is formed by the low-light reflection area and the high-light reflection area sandwiched by the low-light reflection area. 4. The semiconductor device according to item 2 of the patent application scope, wherein the low-light reflection area is a dot-like or grid-like or bar-like pattern for diffusely reflecting light. 5. The semiconductor device according to item 3 of the patent application scope, wherein the low-light reflection area is a dot-like or grid-like or strip-like pattern for diffusely reflecting light. 6. The semiconductor device according to item 2 of the patent application, wherein the bonding element is formed of a polycrystalline silicon thin film. 7. The semiconductor device as claimed in claim 3, wherein the bonding element is formed of a polycrystalline silicon thin film. Eight types of semiconductor devices with semiconductor integrated circuits that are repeatedly placed in a matrix shape in two dimensions by drawing lines on the surface of the semiconductor wafer, bonding elements on the semiconductor integrated circuit, and laser correction positioning maps on the surface of the semiconductor wafer Type, the semiconductor device is characterized by laser repair formed by the high-light reflection area and the low-light reflection area. Positive positioning pattern, high-light reflection area This paper scale uses the Chinese national kneading rate (CNsTa4 specification (210X297 mm) 10 ! (Please read the note on the back before filling in this page) -II Order-31-Ministry of Economic Affairs Central #Associate Bureau Consumption Cooperative Press A8 B8 C8 ___D8 VI. The scope of patent application is formed on the flat bottom layer The light-reflecting area formed by the above light-reflecting film is formed by a high-light-reflecting film formed on dot-shaped, lattice-shaped, or strip-shaped light, and the light-diffusing reflection pattern element is the same thin film. 9. If applying for a patent The semiconductor device modification positioning positioning pattern of item 8 is formed by the high-light reflection area _ and the high-light reflection 1 low-light reflection area. 1 0. As described in the patent application scope No. 8 · The "corrected positioning map" type is formed by the low-light reflection region and the low-light reflection region. 1 1. The semiconductor device according to item 8 of the patent application is constructed of a polycrystalline silicon film. 1 2. For example, the semiconductor light-reflective thin film of the scope of the patent application No. 8 is constructed of aluminum. 1 3. The semiconductor radiation correction positioning pattern of the scope of the patent application No. 8 is placed on the electrical connection of the crystal portion of the semiconductor integrated circuit. On the pad area. 1 4. As in the patent application scope No. 8 of the semiconductor radiation correction positioning pattern is placed at the intersection of line drawing. 1 5. As the patent application scope No. radiation correction positioning pattern is based on continuous highland positioning. The so-called theta of the semiconductor wafer is constructed by sequentially positioning the semiconductor integrated circuit in the X direction and the Y square mark. The semiconductor light reflecting film of 8 items is formed, and the low diffusion reflection pattern is formed by the and Combined device, device in which the laser area is clamped, device in which the laser reflection area is clamped, device in which the device is knotted, device in which is high, in which the device is inside and outside the device, where device is in which device Integration of relatively rough signs and the so-called corrections (please read the notes on the back before filling out this page). The paper size applies to the Chinese National Standard (CNS) Α4 specification (210X297 mm) -32- Ministry of Economic Affairs Printed by the Central Bureau of Work Consumer Cooperatives 6. Application for Patent Fangu 16. For the semiconductor device under the scope of patent application 1, the laser correction positioning pattern is formed by a thin film of the same material as the bonding element The line and body size of the dot-shaped or grid-shaped or strip-shaped low-light reflection area are smaller than the diameter of the laser light point "1 7. For the semiconductor device of the first scope of the patent application, in the laser correction positioning pattern, The line and body size of the dot-shaped or grid-shaped or strip-shaped low-light reflection area formed by the thin film of the same material as the bonding element are smaller than one and a half of the diameter of the laser light spot. The size of the low-light reflection area in the laser beam scanning direction is larger than the diameter of the laser light spot. 19. The semiconductor device according to item 3 of the scope of patent application, wherein the size of the high-light reflection area in the laser beam scanning direction is larger than the diameter of the laser light spot. 2. The semiconductor device according to item 2 of the patent application range, wherein the size of the low-light reflection region in the laser beam scanning direction is greater than twice the diameter of the laser light spot. 2 1. The semiconductor device according to item 3 of the patent application range, wherein the size of the high-light reflection area in the laser beam scanning direction is greater than twice the diameter of the laser light spot. 2 2. The semiconductor device according to item 8 of the scope of patent application, wherein in the laser correction positioning pattern, the dot-like or grid-like or strip-like low-light reflection area lines formed by a thin film of the same material as the bonding element and The body size is smaller than the diameter of the laser light spot. This paper size is applicable to China National Standard (CNS) A4 (210 > < 297 mm) AVI— (Please read the note on the back before filling in this page) • IT Order -33-Ministry of Economy Central Standard Printed by the Bureau of Real Industrial Consumer Cooperatives 11 A8 B8 C8 D8 夂, patent application scope 2 3. For the semiconductor device of patent application item 8, in which the laser correction positioning pattern is made of a thin film of the same material as the bonding element The line and body size of the dot-shaped or lattice-shaped or strip-shaped low-light reflection areas are smaller than one and a half of the diameter of the laser light spot. 2 4. If the semiconductor device under the scope of patent application No. 9 in which the size of the low light reflection area in the laser beam scanning direction is larger than the diameter of the laser light point "2 5. If the semiconductor device under the scope of patent application No. Γ0, The size of the specular reflection area in the laser beam scanning direction is larger than the diameter of the laser light spot. 26. The semiconductor device according to item 9 of the patent application scope, wherein the size of the low-light reflection region in the laser beam scanning direction is greater than twice the diameter of the laser light spot. 27. The semiconductor device according to item 10 of the patent application range, wherein the size of the high-light reflection area in the laser beam scanning direction is greater than twice the diameter of the laser light spot. 28. The semiconductor device according to item 1 of the scope of patent application, wherein the number of bonding elements in the semiconductor integrated circuit is 10 or more. 29. The semiconductor device according to item 8 of the scope of patent application, wherein the number of bonding elements in the semiconductor integrated circuit is 10 or more. 3. The semiconductor device according to item 1 of the scope of patent application, wherein the semiconductor integrated circuit has several coupling element groups located in different directions, and the coupling element group is arranged by at least one or more in the same direction. Formed by bonding elements. This paper uses China National Standard (CNS) A4 specification (210 > < 297 mm) (please read the precautions on the back before filling this page) Order -34-Industrial and Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Printed B8 C8 D8 VI. Patent application difficulties 3 1. For the semiconductor device under the scope of patent application item 8, the semiconductor integrated circuit has several bonding element groups located in different directions. At least one or more bonding elements arranged in the same direction are formed. 32. The semiconductor device according to item 1 of the patent application range, wherein the semiconductor volume circuit is a voltage detection IC. 3 3. The semiconductor device according to item 1 of the patent application, wherein the semiconductor volume circuit is a series regulator IC. 3 4 · The semiconductor device according to item 1 of the scope of the patent application, wherein the semiconductor volume circuit is a switching regulator IC. 35. The semiconductor device according to item 1 of the scope of the patent application, wherein the semiconductor volume circuit is a lithium battery protection 1C. 36. The semiconductor device according to item 8 of the patent application, wherein the semiconductor volume circuit is a voltage detection IC. 37. The semiconductor device according to item 8 of the patent application, wherein the semiconductor volume circuit is a series regulator IC. 38. The semiconductor device according to item 8 of the scope of patent application, wherein the semiconductor volume circuit is a switching regulator IC. 39. The semiconductor device according to item 8 of the scope of the patent application, wherein the semiconductor volume circuit is a lithium battery protection IC. This paper uses China National Standard (CNS) A4 size (210X297 mm). • * Ί 丨 _J 丨 -otr ------ 0--7 (please read the "$" on the back side first) Fill out this page} -35-