TW386222B - Electric device having non-light emitting type display and method for making the electric device - Google Patents
Electric device having non-light emitting type display and method for making the electric device Download PDFInfo
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1、發明説明（1 ) I明背景 A7 B7 1 .發明領域 本發明關於具有 電裝置及製造該電裝 體（T F T )形成於 之TFT所構成的驅 動矩陣電路。 2 .相關技藝說明 近來，藉著液晶 攜帶型電裝置（個人 的顯示器*詳言之， 主動矩陣型液晶顯示 置。 諸如液晶顯示器之非發光型顯示器的 置之方法，主動矩陣電路由薄膜電晶 基底上。詳言之，形成於同一基底上 動電路驅動控制本發明之電裝置的主 顯示器薄且輕，液晶顯示器做爲各種 電腦、文字處理機、電子筆記簿等） 由於一一控制使用T F T之各圖素的 器有優良顯示特性，故用於許多電裝 (請先聞讀背面之注意事項再填寫本頁) 經 f 部 中 央 標 準 員 工 消 入 社 印 製 有各種主動矩 具有TFT所形成 體電路晶片所構成 接合）等將半導體 分，故半導體器變 接線（連線）的寬 1 0 0 0，故有接 面積•由於玻璃基 數和玻璃基底之接 故對正精確度約6 以下之圖素間距的 陣型液晶顯示器•一顯示器（第一種） 的主動矩陣電路和外部型單晶半導體積 的驅動電路。由於須由TAB(帶自動 晶片和半導體封裝連接玻璃基底旁的部 得相當大。由於延伸自主動矩陣電路之 度變小以增進開口率，且接線總數超過 線連接的問題•再者，在連接部需要大 底之接線與外部晶片之接間的熱膨脹係 線與TAB之帶間的熱膨脹係數不同， 0仁m ·因此，不能用於具有6 0 髙解析度顯示器，無法縮小顯示器，因 本紙張尺度適用中國國家檩準（CNS ) A4規格（210x297公釐） -4 -1. Description of the invention (1) Background of the invention A7 B7 1. Field of the invention The present invention relates to a driving matrix circuit composed of an electric device and a TFT formed by manufacturing the electric device (T F T). 2. Description of related techniques Recently, by means of a liquid crystal portable electric device (personal display *, in detail, an active matrix type liquid crystal display device. For a non-light emitting type display device such as a liquid crystal display device, an active matrix circuit is formed by a thin film transistor On the substrate, in detail, the main display is formed on the same substrate to drive and control the electrical device of the present invention. The main display is thin and light, and the liquid crystal display is used as various computers, word processors, electronic notebooks, etc.). Each pixel device has excellent display characteristics, so it is used in many Denso (please read the precautions on the back before filling this page). The central standard staff of the f department has printed various active moments with TFTs. Circuit wafers are bonded, etc.) to separate semiconductors, so the semiconductor device wiring (wiring) has a width of 1 0 0, so there is a connection area Element-pitch array LCD • One display (first type) active matrix circuit and external single crystal semiconductor . Because TAB (with automatic chip and semiconductor package connected to the glass substrate, the part is quite large. Since the degree of extension from the active matrix circuit is reduced to increase the aperture ratio, and the total number of wires exceeds the problem of wire connection The thermal expansion coefficient between the connection between the bottom wire and the external chip is different from that of the TAB tape. The coefficient of thermal expansion is different from 0 mm. Therefore, it cannot be used for a display with a resolution of 60 0 and the display cannot be reduced. Standards are applicable to China National Standard (CNS) A4 (210x297 mm) -4-
1、發明説明（1 ) I明背景 A7 B7 1 .發明領域 本發明關於具有 電裝置及製造該電裝 體（T F T )形成於 之TFT所構成的驅 動矩陣電路。 2 .相關技藝說明 近來，藉著液晶 攜帶型電裝置（個人 的顯示器*詳言之， 主動矩陣型液晶顯示 置。 諸如液晶顯示器之非發光型顯示器的 置之方法，主動矩陣電路由薄膜電晶 基底上。詳言之，形成於同一基底上 動電路驅動控制本發明之電裝置的主 顯示器薄且輕，液晶顯示器做爲各種 電腦、文字處理機、電子筆記簿等） 由於一一控制使用T F T之各圖素的 器有優良顯示特性，故用於許多電裝 (請先聞讀背面之注意事項再填寫本頁) 經 f 部 中 央 標 準 員 工 消 入 社 印 製 有各種主動矩 具有TFT所形成 體電路晶片所構成 接合）等將半導體 分，故半導體器變 接線（連線）的寬 1 0 0 0，故有接 面積•由於玻璃基 數和玻璃基底之接 故對正精確度約6 以下之圖素間距的 陣型液晶顯示器•一顯示器（第一種） 的主動矩陣電路和外部型單晶半導體積 的驅動電路。由於須由TAB(帶自動 晶片和半導體封裝連接玻璃基底旁的部 得相當大。由於延伸自主動矩陣電路之 度變小以增進開口率，且接線總數超過 線連接的問題•再者，在連接部需要大 底之接線與外部晶片之接間的熱膨脹係 線與TAB之帶間的熱膨脹係數不同， 0仁m ·因此，不能用於具有6 0 髙解析度顯示器，無法縮小顯示器，因 本紙張尺度適用中國國家檩準（CNS ) A4規格（210x297公釐） -4 - A7 B7 五.、發明説明（2〉 而使用能在低溫形成之非晶矽的T F τ用於此顯示器。 (請先閲讀背面之注意事項再填寫本頁) 另一顯示器（第二種）¥ι薄膜積-體電路，扃有主動矩 I電、路及身器/驅動雜紅Y解碼器^驅動器（使 用T F Τ..形成於同—基底上）的福動電路。由於上述=逐部 f半.導體未用脸嚣，故鬣.示器變-得~顧當小。 由於不需連接許多接線，故對顯示器縮小較佳。此顯示器 中，，須复直慶良特件夕結晶政Τ'用於驅動 電路。 ; ' 因此，第二種顯示器在顯示器縮小方面優於第一種顯 示器。但第二種顯示器中，進一步縮小、減輕、變薄不足 。亦即，腦中，既姐中-央處理單元（匕、主 記憶、影像信號處理單元、影橡記億等的各種半導體晶片 形成於液晶顯示器板之外)的主t基底（主機板），因此須使 奚^二個基底_或板（主機板和·液晶顯示器板）。 爲了顯示器的進一步縮小、減輕、變薄，要只用一個 • ...-------- 板取代二個板。 經濟部央橾隼局貝工消费合作社印製 發明概要 本發明將半導體„晶_方設在液晶顯示¥之至少一基底的 上述主機板，要達成顯示器的縮小、減輕、變薄，液，晶材 料保持在一對基底之間。這些晶片設在形成主動矩陣電路 的基底（板）。薄膜電晶體（TFT)形成驅動主動矩陣 電路的驅動電路。 依據本發明，提供電裝置，包括：基底；至少包含一 本紙張尺度逋用中國國家標準（CNS ) A4規格（210 X 297公釐） 五、發明説明（ A7 B7 經濟部中夬捸準局貝工消费合作社印製 個薄膜電晶體的主動矩陣電路；驅動中動钽陣電路之至少 包含另一薄膜《晶_的_麗_動電路^控制驅動電路的至少— 個半導體積體電路晶片，其中主動矩陣電路、驅動電路、 半導體積體電路晶片形成於基底上。 圖式簡流 圖1是光電裝置的方塊圖； 圖2顯示線接合的例子； 圖3是本發明之實施例1和2之液晶顯示器面板的示 意圖： 圖4A和4B顯示FCOG的例子； 圖殳A至5 G顯示實施例、之T F T電路基底的製程 ♦ 圖6 A至6 G顯示實施例j之TF 丁電路基底的製程 1 圖7 A至7G顯示實施例5之TFT電路基底的製程 f 圖8A至8 I和9 A至9 I顯示實施例6之TFT電 路的製路； 圖10A至10C分別是實施例6之TFT電路的上 視圖、剖面圖、電路配置圖； 圖11 A至1 1D顯示實施例7之TFT電路基底的 製程。 本紙張尺度適用中國國家標準（CNS > A4规格（210x297公釐） 請 ▲ 閲 讀 背 之 注1. Description of the invention (1) Background of the invention A7 B7 1. Field of the invention The present invention relates to a driving matrix circuit composed of an electric device and a TFT formed by manufacturing the electric device (T F T). 2. Description of related techniques Recently, by means of a liquid crystal portable electric device (personal display *, in detail, an active matrix type liquid crystal display device. For a non-light emitting type display device such as a liquid crystal display device, an active matrix circuit is formed by a thin film transistor On the substrate, in detail, the main display is formed on the same substrate to drive and control the electrical device of the present invention. The main display is thin and light. Each pixel device has excellent display characteristics, so it is used in many Denso (please read the precautions on the back before filling this page). The central standard staff of the f department has printed various active moments with TFTs. Circuit wafers are bonded, etc.) to separate semiconductors, so the semiconductor device wiring (wiring) has a width of 1 0 0, so there is a connection area Element-pitch array LCD • One display (first type) active matrix circuit and external single crystal semiconductor . Because TAB (with automatic chip and semiconductor package connected to the glass substrate, the part is quite large. Since the degree of extension from the active matrix circuit is reduced to increase the aperture ratio, and the total number of wires exceeds the problem of wire connection The thermal expansion coefficient between the connection between the bottom wire and the external chip is different from that of the TAB tape. The coefficient of thermal expansion is different from 0 mm. Therefore, it cannot be used for a display with a resolution of 60 0 and the display cannot be reduced. Standards are applicable to China National Standard (CNS) A4 specifications (210x297 mm) -4-A7 B7 V. Description of the invention (2> And use TF τ of amorphous silicon which can be formed at low temperature for this display. (Please first Read the notes on the back and fill in this page again) Another display (second type) ¥ thin film integrated body circuit, which has active moment I, circuit, and body / driver mixed red Y decoder ^ driver (using TF Τ ..Formed on the same-base) of the Fudong circuit. Because the above = part by f f. The conductor is not used, so the indicator changes-get ~ Gu Dang small. Because there is no need to connect a lot of wiring, so It is better to shrink the display. This display In order to reduce the size of the display, the second display is better than the first display. However, the second display is further reduced, lightened, Insufficient thinning. That is, in the brain, the main substrate of the central-central processing unit (a variety of semiconductor wafers such as daggers, main memory, image signal processing units, and Yingyingjiyi are formed outside the LCD panel) Motherboard), so you must use two substrates (or motherboard and LCD panel). In order to further reduce, reduce, and thin the display, use only one • ...------ -The board replaces two boards. Summary of the invention printed by the Bayong Consumer Cooperative of the Central Bureau of the Ministry of Economics The present invention uses the above-mentioned main board with the semiconductor crystal on at least one substrate of the liquid crystal display ¥, to achieve the reduction of the display, Lighten, thin, liquid and crystalline materials are held between a pair of substrates. These wafers are located on the substrate (board) that forms the active matrix circuit. Thin film transistors (TFTs) form the driving circuit that drives the active matrix circuit. Ming, providing electrical equipment, including: the base; at least one paper size using the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 5. Description of the invention (A7 B7 Shell Ministry of Economic Affairs, China Standards Bureau) The cooperative prints an active matrix circuit of a thin film transistor; the driving tantalum array circuit includes at least another thin film "crystalline__ 丽 _ 动 电路 ^ controlling at least one semiconductor integrated circuit chip, of which the active matrix Circuits, drive circuits, and semiconductor integrated circuit wafers are formed on the substrate. Schematic diagram Figure 1 is a block diagram of a photovoltaic device; Figure 2 shows an example of wire bonding; Figure 3 is a liquid crystal display of Embodiments 1 and 2 of the present invention Schematic diagram of the panel: Figures 4A and 4B show examples of FCOG; Figures 殳 A to 5G show the manufacturing process of the TFT circuit substrate of the embodiment and Figure ♦ Figures 6A to 6G show the manufacturing process of the TF butt circuit substrate of the embodiment j Figure 1 A to 7G show the manufacturing process of the TFT circuit substrate of Example 5. Figures 8A to 8 I and 9 A to 9 I show the manufacturing method of the TFT circuit of Example 6. Figures 10A to 10C are the top of the TFT circuit of Example 6. View, section, electrical FIG. 11A to 11D show the manufacturing process of the TFT circuit substrate of the seventh embodiment. This paper size applies to Chinese national standards (CNS > A4 size (210x297 mm). Please read the note on the back.)
I 裝 訂 A7 B7 五、發明説明（4) 較佳眚施例詳述 . . + (請先閱讀背面之注意事項再填寫本頁) 圖1顯示本發明的觀念。在笔璃製的基底（板）1 5 (也..做.爲液晶顯示器基底）上使用TFT， 形成具有多個 圖素的丰動矩陣電路1 .4和驅動主動矩陣電路14的驛動 電、路，各圖素包含薄膜電晶體（T F T ) 1 1、圖素電極 1 2、輔助電容器1 3。驅動電路X解碼器/驅動器7 5 、Y解碼器/驅動器7 6、χγ分割器7 4。驅動電路可 包含X Y分割器7 4，或X γ分割器7 4可包含於晶片。I Binding A7 B7 V. Description of the invention (4) Detailed description of the preferred embodiment.. + (Please read the notes on the back before filling this page) Figure 1 shows the concept of the present invention. Using a TFT on a substrate (plate) 1 5 made of glass (also used as a substrate for a liquid crystal display), a multi-matrix matrix circuit 1.4 having multiple pixels and a relay circuit driving the active matrix circuit 14 are formed. , Circuit, each pixel includes a thin film transistor (TFT) 1 1, a pixel electrode 1 2, and an auxiliary capacitor 1 3. The driving circuit X decoder / driver 7 5, Y decoder / driver 76, and χγ divider 74. The driving circuit may include an X Y divider 74 or an X γ divider 74 may be included in the wafer.
•I 具有與主動矩陣電—路太致40固之結搆的了 I T可構成 驅動主動矩I電路的電篇，亦即周邊電路。大致相同的結 構代表間極材料、本發明材料、通道形成區材料的至少一 種輿主動矩陣電路的T F T—'致。互補型電路、只有N通 道型TFT (不用P通道型T:F 丁）、、直只„有P .通道型 TF T可構成此周邊電路。因此，構成使用T F T的電路 0 〆其它晶片另設在基底1 5上。這些晶片由線接合、 、- ' V·. COG (包含 flip chip on glass ，F COG)等連接 —- 經濟部中夾樣隼局貝工消费合作社印東 基^^_上_.的電路。圖1中，校正記憶7 1、記憶7 3、 CPU (中央處理單元）7 2、輸入埠7 0做爲上述方法 所提供的晶片，可提供另一晶片。 線接合中，得到具有圖2之剖面的形狀。亦即，晶片 2 2·由向上形成的端子部2 3裝在產生電路的主動矩陣電 0上，鼇路的端子、電端2 .1由金屬製的接.合線J 4接 史L晶片2 子部2 3 °樹—脂2 5密封（覆蓋）此部分 適用中國國家揉準（CNS ) A4規格（210X 297公釐} A7 B7 五、發明説明（5) 以保護連接部免於外部電，撃'。爲穩定保_持端子連接/附著 ，端子電歡2 1的表而爲諸.如鋁的金靥線笼中，由於 ®J旨、2 5在端子連接部大爲上升，故樹脂2 5變厚。 f 4 A和4 B的F .C 0 G .中，晶片4 2由向下形成的 端子部4 3裝在製造電路的玻璃基底4 0上，電路的端子 電極4 1由凸緣4 4 (圖4A).或金屬粒子（圖4B)連 、、· 4 2的向下形成端子部4 3。樹脂4 5密封此部分 以將晶片4 2固定在基底4 0上。因此，由於端子連接部 •r 厚^度大致對應晶片厚度，故可製造薄型顯示器q銘除外的 材料，例如透明導電氧化物膜（I T 0 (氧化銦錫）等） 可用於玻璃基底上的端子。當液晶顯示器的主動矩陣電路 形成於坡璃基底上時，由於在許多情形使用透明導電氧化 物膜構成大部分上層的接線，：故F C 0 G在此方面較佳。 經濟部中央標準局負工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 輸入埠7 0是從外部（例如主電腦）接收輸入信號並 將接收之輸入信號轉換成影像信號的電路。校正記憶71 是在主動矩陣面板固有的記憶，依據主動矩陣面板特性用 來校正輸入信號等。詳言之，，校正記憶7 1是不變性記憶 ，儲存各圖素固有的資訊 '當點缺陷產生在光電裝置的圖 素時，對產生點缺陷之圖素旁的圖素產生校正信號，因而 補償點缺陷。當圖素與周圍圖素比較較暗時，產生圖素與 周圍圖素有相同亮度的信號丨由於圖素缺陷資訊在各主動 矩陣面板不同，故存入校正記憶7 1的資訊在各主動矩陣 面板不同。CPU 7 2和記憶7 3與共用電腦者有相同功 能，記憶是R AM (.隨機存取記憶），儲存對應於各圖素 本紙張尺度適用中國國家標準（CMS ) A4規格（210 X 297公釐） 經濟部中央標準局貝工消费合作社印裝 A7 B7 五、發明説明（6) 的影像資訊。 〔實施例1〕 .圖3是此實施例-^面的圖。圖3中 ，碁底（板）2L 9與蓋底（-.板）3〇.相對’液晶材料保持 在基底2 9和3 0之間。使用TFT，主動矩陣鼇路3 i 和主動矩陣電路3 1的周邊驅動電路3「2至34形成 於諸如玻璃基底的基底3 0上。主記憶晶片3 .6.、M u (微處理單元）3 7或CPU (中央處理單元）記 憶3 8附在形成電路3 1至3 4之基底3 0的表面，電連 接電路3 1至3 4。當..晶.片由FCOG連接基底時，， I TO製的接線端子部（接線連接墊）3 9 (對應於圖 4 A和4 B的接線部4 1 )形k於基底3 0的部分3 5 ό 實施例中，使用有圖4 Α和4 Β之形狀的接點。圖 4 A中，形成於晶片4 2之電極部4 3的導電凸起（凸緣 )4 4電連接基底4 〇上的接線部4 1，有機樹脂4 5用 以在基底4 0上保持晶片4 2。無電電鍍所形成的金可做 爲凸緣4 4 〇 . 圖4 3中，使用導電粒子（例如金粒子）4 6分布的 有機樹脂4 5，基底4 〇附在晶片4 2。因此，使接線部 41接觸分布在晶片42與電極部43之間的導電（金屬 )验子4 6，進行電路連接。可光固化樹脂、可熱固化樹 脂、可自然固化樹脂等做爲黏著劑的有機樹脂4 5。在附 著晶片後」液、晶林料哥曈到液晶顯示器。 (請先閲讀背面之注意事項再填寫本頁)• I has a structure that is 40 ohms from that of the active matrix circuit. I T can constitute the electric chapter that drives the active moment I circuit, that is, the peripheral circuit. The substantially identical structure represents the T F T ′ of at least one of the active matrix circuit of the interpolar material, the material of the present invention, and the material of the channel forming region. Complementary circuits, only N-channel TFTs (without P-channel T: F D), and only P. Channel-type TF T can constitute this peripheral circuit. Therefore, circuits that use TFTs can be configured. 〆Other chips are provided separately On the substrate 15. These wafers are connected by wire bonding,-'V ·. COG (including flip chip on glass, F COG), etc. --- In the sample of the Ministry of Economic Affairs of the Bureau of Plastics and Rubber Cooperatives, ^^ _ _. Circuit. In Figure 1, calibration memory 7 1, memory 7 3, CPU (Central Processing Unit) 7 2, input port 70, as the chip provided by the above method, another chip can be provided. Wire bonding in progress The shape of the cross-section of FIG. 2 is obtained. That is, the wafer 2 2 · a terminal portion 23 formed upward is mounted on the active matrix circuit 0 of the generating circuit, and the terminals and terminals 2.1 of the circuit are made of metal. Connection. Junction J 4 Connection History L Chip 2 Sub-section 2 3 ° Tree-Grease 2 5 Seal (cover) This part applies to China National Standard (CNS) A4 (210X 297 mm) A7 B7 V. Description of the invention ( 5) In order to protect the connection part from external electricity, 撃 '. To ensure the stability of the connection / attachment of the terminal, the terminal electric Huan 2 1 table is provided. In the aluminum wire cage, the resin J 2 is thicker because of the J rise, 2 5 at the terminal connection portion. In F. C 0 G. Of f 4 A and 4 B, the wafer 4 2 is oriented to The terminal part 43 formed below is mounted on the glass substrate 40 for manufacturing the circuit, and the terminal electrode 41 of the circuit is connected by the flange 4 4 (Fig. 4A) or the metal particles (Fig. 4B). The terminal portion 43 is formed. The resin 4 5 seals this portion to fix the wafer 4 2 to the substrate 40. Therefore, since the terminal connection portion has a thickness approximately corresponding to the thickness of the wafer, materials other than the thin display can be manufactured. For example, a transparent conductive oxide film (IT 0 (Indium Tin Oxide), etc.) can be used for a terminal on a glass substrate. When an active matrix circuit of a liquid crystal display is formed on a sloped glass substrate, since a transparent conductive oxide film is used in many cases It constitutes most of the upper-layer wiring, so FC 0 G is better in this respect. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) Input port 7 0 is from the outside ( (Eg host computer) receives the input signal and converts the received input signal The circuit that forms an image signal. Correction memory 71 is an inherent memory in the active matrix panel, which is used to correct the input signal according to the characteristics of the active matrix panel. In particular, the correction memory 71 is an invariant memory that stores the inherent characteristics of each pixel. Information 'When a point defect is generated in a pixel of a photovoltaic device, a correction signal is generated for the pixel next to the pixel where the point defect is generated, thereby compensating for the point defect. When the pixel is darker than the surrounding pixels, the pixel The surrounding pixels have the same brightness signal. Since the pixel defect information is different in each active matrix panel, the information stored in the correction memory 71 is different in each active matrix panel. The CPU 7 2 and the memory 7 3 have the same functions as those who share the computer. The memory is RAM (. Random Access Memory). The storage corresponds to each pixel. The paper size applies the Chinese National Standard (CMS) A4 specification (210 X 297 male). Ii) A7 B7 printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Image information of the invention description (6). [Embodiment 1] Fig. 3 is a diagram of the embodiment. In FIG. 3, the base (plate) 2L 9 and the lid bottom (-.plate) 30 are opposed to each other and the liquid crystal material is held between the substrates 29 and 30. Using the TFT, the active matrix circuit 3 i and the peripheral drive circuits 3 ″ 2 to 34 of the active matrix circuit 31 are formed on a substrate 30 such as a glass substrate. The main memory chip 3.6., Mu (micro processing unit) 3 7 or CPU (Central Processing Unit) memory 3 8 is attached to the surface of the substrate 3 0 forming the circuits 3 1 to 3 4 and is electrically connected to the circuits 3 1 to 3 4. When the ..chip is connected to the substrate by FCOG, I TO terminal block (wiring connection pad) 3 9 (corresponding to the wiring part 4 1 of FIGS. 4 A and 4 B) is a portion 3 5 formed on the base 3 0. In the embodiment, FIG. 4 A and FIG. 4 B-shaped contacts. In FIG. 4A, the conductive bumps (flange) 4 formed on the electrode portion 4 3 of the wafer 4 2 are electrically connected to the wiring portion 41 on the substrate 4 and the organic resin 45 is used. The wafer 4 2 is held on the substrate 40. The gold formed by electroless plating can be used as the flange 4 4. In FIG. 4, conductive resin (such as gold particles) 4 6 is used as the organic resin 4 5 and the substrate 4 〇Attached to the wafer 4 2. Therefore, the wiring portion 41 is brought into contact with the conductive (metal) test piece 4 6 distributed between the wafer 42 and the electrode portion 43 for circuit connection. The photocurable resin, Organic resins, such as heat-curable resins and natural curable resins, are used as adhesives. 5. After the wafer is attached, the liquid and crystal materials are applied to the liquid crystal display. (Please read the notes on the back before filling this page)
A7 B7 五、發明説明（7) 在上述處理後，CPU和記憶形成於液晶顯示器基底 上，使用一基底，構成諸如個人電腦的電裝置。 (請先閲讀背面之注意事項再填寫本頁) 〔實施例2〕 產生圖3的面板，主動矩陣電路3 .1和周邊驅動電路 3 2至3 4由TFT形成於基底3 0上。主記憶晶片3 6 、熥卩113 7(或〇?1；)、校正記憶3 8附在形成電路 3 1至3 4之基底3 0的表面，電連接鋁合金薄膜製的接 <1 線端子部（接線連接墊）3 9 (對應於端子電極2 1 )， 由圖2的線接合形成於基底4 0上。細金線做爲接合線。 〔實施例3〕 " 晶片由FCOG附在Τ^Τ電路（單石型主動矩陣電 路）基底，構成更增進的電路。稍後使用圖5 A至5 G， 說明單石主動矩陣電路的製程。1 0 0 0至3 0 0 0A。 厚的氧化矽膜在基底（Coming 7 5 9 ) 5 0 1上形成基 經濟部中央樣準局貝工消费合作社印製 本氧化物膜5 0 2。形成此氧化物膜的方法可包含在含有 氧之氣氛中的濺射或電漿CVD(化學蒸鍍）。 非晶或結晶的矽膜由電漿CVD或低壓CVD( L P C V D)形成3 0 0至1 5 0 0A厚，最好5 0 0至 1 〇 〇 〇A。爲形成結晶矽膜，在形成非晶矽膜後，可照 射（光退火）雷射或相當於雷射的强光，或在5 0 0 °C以 上長期熱退火。在熱退火的結晶後，可光退火以增進結晶 。熱退火的結晶中，，可添加促進矽結晶的元素（催化元素A7 B7 V. Description of the invention (7) After the above processing, the CPU and the memory are formed on the liquid crystal display substrate, and a substrate is used to constitute an electric device such as a personal computer. (Please read the precautions on the back before filling in this page) [Embodiment 2] The panel of FIG. 3 is generated, the active matrix circuit 3.1 and the peripheral driving circuits 3 2 to 3 4 are formed on the substrate 30 by TFTs. The main memory chip 36, 熥 卩 113 7 (or 〇1;), and the correction memory 3 8 are attached to the surface of the substrate 3 0 forming the circuits 3 1 to 3 4 and are electrically connected to a connection made of an aluminum alloy thin film <1 line The terminal portion (wiring connection pad) 3 9 (corresponding to the terminal electrode 2 1) is formed on the substrate 40 by wire bonding in FIG. 2. Fine gold wire is used as the bonding wire. [Embodiment 3] " The chip is attached to the substrate of the T ^ T circuit (monolithic active matrix circuit) by FCOG to constitute a more enhanced circuit. The process of the monolithic active matrix circuit will be described later using FIGS. 5A to 5G. 1 0 0 0 to 3 0 0 0A. A thick silicon oxide film was formed on the substrate (Coming 7 5 9) 501. This oxide film was printed by the Central Samples Bureau of the Ministry of Economic Affairs, and was printed by Shelley Consumer Cooperative. The method for forming this oxide film may include sputtering or plasma CVD (chemical vapor deposition) in an atmosphere containing oxygen. The amorphous or crystalline silicon film is formed by plasma CVD or low-pressure CVD (LPC V D) to a thickness of 300 to 1500 A, preferably 500 to 1000 A. To form a crystalline silicon film, after the amorphous silicon film is formed, it can be irradiated (photoannealed) with a laser or a strong light equivalent to a laser, or long-term thermally annealed above 500 ° C. After thermally annealed crystallization, light annealing can be used to promote crystallization. In the thermally annealed crystal, an element (catalytic element) that promotes the crystallization of silicon may be added.
本紙張尺度適用中國國家標举（CNS ) A4規格（ 210X297公釐）Q A7 _^_______B7 ____ 五、發明説明（Q ) 〇 )，例如鎳。 蝕刻矽膜形成周邊驅動電路的TFT活性層5 0 3和 5 0 4及主動矩陣電路的TFT活性層5 0 ^，做爲島狀 區。再者，5 0 0至2 0 0 0 A厚的氧化矽在含氧昀氣氛 中由濺射形成閘極絕緣膜$0 6。形成閘極絕緣膜5 0 6 的方法可包含電漿CVD。 閘極絕緣膜要有足夠髙的耐壓。這是因爲電場在陽極 化處理中施於閘極與矽活性層之間。因此，一氧化二氮（ 一 ** N2〇)或氧（〇2)和甲矽烷（S i H4)宜用於閘極絕 緣膜由電漿CVD所得之氧化矽膜形成的情形。（圖5 A )This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm) Q A7 _ ^ _______ B7 ____ 5. Description of the invention (Q) 〇), such as nickel. The silicon film is etched to form the TFT active layers 503 and 504 of the peripheral driving circuit and the TFT active layer 504 of the active matrix circuit as island regions. Furthermore, a gate insulating film of $ 0 6 is formed by sputtering a silicon oxide having a thickness of 500 to 2000 A in an oxygen-containing atmosphere. The method of forming the gate insulating film 506 may include plasma CVD. The gate insulation film must have a sufficient withstand voltage. This is because the electric field is applied between the gate and the silicon active layer during the anodizing process. Therefore, nitrous oxide (N ** O) or oxygen (O2) and silane (SiH4) are suitable for the case where the gate insulating film is formed by a silicon oxide film obtained by plasma CVD. (Figure 5 A)
2 0 0 0A 至 5"m 厚（'最好 2 0 0 0 至 6 Ο 0 0A )的鋁膜（含0. 1至0. 5¼量％的銃）由濺射形成於 基底上，再蝕刻形成閘極（或蘭極線）5 0 7至5 1 0。 閘極線5 0 9連接陽極化接線（未回）。周邊邏輯電路的 閘極5 0 7和5 0 8與陽極化接線絕緣。（圖5 B ) 基底浸入電解液，然後使電流流入陽極化接線，令閘 經濟部中央橾準局貝工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 極線5 0 9和閘極5 1 0陽極化。陽極化條件描述於日本 特許公開5 — 2 6 7 6 6 7號。因此，在閘極線5 0 9和 閘極5 1 0的上和側表面得到陽極氧化物5 1 1和5 1 2 的厚度取決於要施加的電壓，在實施例爲2 〇 0 0 A。 在大部分中性溶液由陽極化所得的陽極氧化物細且硬 ，具有髙耐壓。耐壓等於及髙於要在陽極化中施加之最大 電壓的7 0 %。此陽極氧化物稱爲障壁型陽極氧化物。（ 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公嫠）， A7 B7 五、發明説明（9) 圖 5 C.)2 0 0 0A to 5 " m thick ('preferably 2 0 0 0 to 6 0 0 0A) aluminum film (including 0.1 to 0.5¼% by weight of 铳) is formed on the substrate by sputtering, and then etched Form the gate (or blue line) 5 0 7 to 5 1 0. The gate wire 5 0 9 is connected to the anodized wiring (not returned). The gates 507 and 508 of the peripheral logic circuit are insulated from the anodized wiring. (Fig. 5B) The substrate is immersed in the electrolyte, and then the current flows into the anodized wiring, which is printed by the Central Laboratories of the Ministry of Economic Affairs and the Pai Gong Consumer Cooperative (please read the precautions on the back before filling out this page) Polar wire 5 0 9 And gate 5 1 0 anodized. Anodizing conditions are described in Japanese Patent Laid-Open No. 5-2 6 7 6 6 7. Therefore, the thicknesses of the anodic oxides 5 1 1 and 5 1 2 obtained on the upper and side surfaces of the gate lines 509 and 5 1 0 depend on the voltage to be applied, and in the embodiment are 2000 A. In most neutral solutions, the anodic oxide obtained by anodization is thin and hard, and has high pressure resistance. The withstand voltage is equal to or less than 70% of the maximum voltage to be applied during anodization. This anodic oxide is called a barrier type anodic oxide. (This paper size applies to China National Standard (CNS) A4 specifications (210X297 cm), A7 B7 V. Description of invention (9) Figure 5 C.)
以自動對正使用閘極部（閘極和其周圍的陽極氧化物 膜）做爲罩，雜質由離子摻雜引入島狀TFT活性層 5 0 3和5 0 4。此摻雜中，在使用磷化氫（p Η 3 )做 爲摻雜氣體狀磷引入整個表面後，只有T F Τ活性層 5 0 3覆以光阻，使用乙硼烷（Β2Η 6)做爲摻雜氣體將 硼引入T F Τ活性層5 0 4和5 0 5。劑量在碟爲4 X 1 0 14至 4 X 1 〇 15原子 / c m a，在硼爲 1 X，1 0 15至 1 ·ι 8 X 1 0 15原子/ c m 3。硼劑量高於磷。因此，形成Ν 型區5 1 3及P型區5 1 4和51 5。（圖5D) 照射KrF準分子電射光（248nm波長和 2 0 n s脈寬），增進因雜質引入雜質區而晶性變差之部 分的晶性。雷射能量密度爲2’0 0至4 0 OmJ/cm2 ，最好2 5 〇至3 0 OmJ/cm2。因此，激活N型和 P型區。這些區域的薄片電阻爲2 0 0至8 Ο Ο Ω/平方 。在閘極的熱阻範圍內熱退火可進行此處理。 經濟部中央梂準扃員工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 3 0 0 〇至6 Ο Ο OA厚的氧化矽膜由電漿CVD形 成中間層絕緣體5 1 6。氮化矽膜（或氧化矽膜）的多層 可做爲中間層絕緣體5 1 6。由濕蝕刻來蝕刻中間層絕緣 體51 6，在N型和P型區形成接觸孔5 1 7至5 1 9。 同時’孔5 2 〇形成於閘極（閘極線）5 〇9。由於陽極 氧化物膜511做爲障壁，故蝕刻停止，因而閘極線 5 0 9仍未鈾刻。（圖5 E ) -2 〇的.圖型再度由光石印術形成於接觸孔， 本紙張跋適用中國國家棣準（CNS)从胁（21()><297公羞） -12 - A7 B7 _ 五、發明説明（1〇) 然後使用含鉻酸的蝕刻劑來蝕刻，例如鉻酸（1至5 % ) 和磷酸（或硝酸、醋酸）的混合溶液，形成接觸孔5 2 1 。（圖 5 F ) 濺射形成2 0 0 0 S 6 Ο Ο Ο A厚的鈦膜，再蝕刻形 成周邊電路的電極接線5 2_. 2至5 2 4、主動矩陣電路的 資料線5 2 5、圖素TFT的電極5 2 6。接綠5 2 3連 接閘極線5 0 9。 . 濺射形成5 0 0至1 5 0 0A厚的I TO膜，再蝕刻 ‘， 形成圖素電極52 7。1 0 0.0至3 0 0 0A厚的氮化矽 膜5 2 8形成鈍化膜。因此，集積周邊邏輯電路和主動矩 陣電路。（圖5 G ) 蝕刻接到外部I C晶片之端子部（對應於部分4 1 ) 的氮化矽膜5 2 8，露出端子k接部的I TO接線墊。圖 4 A和4 B的:F C ◦ G附著I C晶片。 〔實施例4〕 經濟部中央標準扃貝工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 以圖6 A至6 G說明將I C晶片附在液晶顯示器單石 g主動矩陣電路由F COG形成之TFT電路基底的方法 。CMOS電路做爲周邊電路。只顯示NTFT做爲周邊 電路TFT，周邊邏輯電路顯示於左側，主動矩陣電路顯 示於右側。 2 0 0 〇A厚的基本氧化矽膜6 0 2由電漿CVD形 成於玻璃基底上。電漿CVD的原料氣體爲甲矽烷（ 5 i Η 4 ).和一氧化二氮(Ν 2 Ο )。膜形成的基底溫度爲 本紙張尺度逋用中國國家棵準（CNS ) Α4規格（210 X 297公釐） -13 - 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（n) 3 8 0至5 0 0 °C，例如4 3 0 °C，形成的氧化矽膜 6 0 2有相當低的蝕刻率且爲固體。這是因爲—氧化二氮 做爲原料氣體，故得到含1至1〇%氮的氧化矽/氮化砂 膜。在2 3°C使用添加酯酸的緩衝氫氟酸（ABHF)( 氫氟酸：氟化銨：醋酸=1-. : 5 0 : 5 0 )，標準蝕刻率 爲8 0 0至1 0 0 0A/分鐘。 電漿CVD形成5 0 0 A厚的非晶矽膜。在含氧的氣 氛中於5 5 0 °C熱退火1小時，在非晶矽膜表面上形成極 *· 膜（估計約4 0至1 0 0 A )氧化矽膜。藉由旋轉塗覆， 使用1至1 0 0 ppm酯酸鎳溶液，形成醋酸鎳的極薄膜 。先在非晶矽膜表面上形成薄氧化矽膜，溶液分布在非晶 矽膜表面上。 ’ 在含氮的氣氛中於5 5 0 °C熱退火4小時。酯酸鎳在 約4 0 0 °C分解而得到鎳。由於醋酸鎳薄膜大致附在非晶 矽膜，故鎳由熱退火擴散到非晶矽膜。因此，非晶矽膜結 晶而形成結晶矽區。The gate portion (gate and surrounding anodic oxide film) is used as a cover for automatic alignment, and impurities are introduced into the island-shaped TFT active layer by ion doping 503 and 504. In this doping, after using phosphine (p Η 3) as the doping gas-like phosphorus to introduce the entire surface, only the TF Τ active layer 5 0 3 is covered with photoresist, and diborane (B2Η 6) is used as the dopant. The doping gas introduces boron into the TF T active layers 504 and 505. The dose is 4 X 1 0 14 to 4 X 1 0 15 atoms / cm in the dish, and 1 X, 10 15 to 1 · 8 X 1 0 15 atoms / cm 3 in boron. The dose of boron is higher than that of phosphorus. Accordingly, N-type regions 5 1 3 and P-type regions 5 1 4 and 5115 are formed. (Fig. 5D) KrF excimer light (248 nm wavelength and 20 n s pulse width) is irradiated to improve the crystallinity of the portion where the crystallinity is deteriorated due to the introduction of impurities into the impurity region. The laser energy density is 2'0 0 to 40 OmJ / cm2, preferably 2 50 to 30 OmJ / cm2. Therefore, the N-type and P-type regions are activated. The sheet resistance in these areas is 200 to 8 0 Ω / square. This treatment can be performed by thermal annealing in the thermal resistance range of the gate. Printed by the Central Consumers ’Cooperative of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 3 0 0 to 6 〇 〇 OA thick silicon oxide film is formed by plasma CVD to form an interlayer insulator 5 1 6. Multiple layers of silicon nitride film (or silicon oxide film) can be used as the interlayer insulator 5 1 6. The interlayer insulator 5116 is etched by wet etching, and contact holes 5 1 7 to 5 1 9 are formed in the N-type and P-type regions. At the same time, a 'hole 5 2 0' is formed in the gate (gate line) 5 0 9. Since the anodic oxide film 511 serves as a barrier, the etching is stopped, and the gate line 509 is not yet etched with uranium. (Figure 5 E) -2. The pattern is again formed in the contact hole by light lithography. This paper is applicable to China National Standards (CNS) Congxie (21 () > < 297 public shame) -12- A7 B7 _ 5. Description of the invention (10) Then, a chromic acid-containing etchant is used to etch, for example, a mixed solution of chromic acid (1 to 5%) and phosphoric acid (or nitric acid or acetic acid) to form a contact hole 5 2 1. (Figure 5 F) Sputtering a 2 0 0 0 S 6 Ο Ο Ο Ο thick titanium film, and then etching to form the electrode wiring of the peripheral circuit 5 2_. 2 to 5 2 4. The data line of the active matrix circuit 5 2 5. The pixels 5 2 6 of the pixel TFT. Connect green 5 2 3 and connect gate line 5 0 9. . Sputtering to form an I TO film with a thickness of 500 to 150 A, and then etch ′ to form a pixel electrode 52 7. A silicon nitride film with a thickness of 0.0 to 300 A is 5 2 8 to form a passivation film. Therefore, peripheral logic circuits and active matrix circuits are integrated. (Fig. 5G) The silicon nitride film 5 2 8 connected to the terminal portion (corresponding to the portion 4 1) of the external IC chip is etched to expose the I TO wiring pad of the terminal k connection portion. Figure 4 A and 4 B: F C ◦ G is attached to IC chip. [Embodiment 4] Printed by the Central Standard of the Ministry of Economic Affairs of the Bayer Consumer Cooperative (please read the precautions on the back before filling out this page) Figure 6 A to 6 G illustrates the IC chip attached to the LCD monolithic active matrix circuit Method of TFT circuit substrate formed by F COG. CMOS circuits are used as peripheral circuits. Only the NTFT is displayed as the peripheral circuit TFT, the peripheral logic circuits are displayed on the left, and the active matrix circuit is displayed on the right. A 200 Å thick basic silicon oxide film 602 is formed on a glass substrate by plasma CVD. The source gases for plasma CVD are silane (5 i Η 4). And nitrous oxide (N 2 0). The base temperature of the film formation is based on the paper standard, using the Chinese National Standard (CNS) Α4 size (210 X 297 mm) -13-Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (n) 3 8 0 to 5 0 ° C, for example 4 3 0 ° C, the silicon oxide film 6 2 2 formed has a relatively low etching rate and is solid. This is because—nitrogen oxide is used as a raw material gas, so a silicon oxide / nitride nitride film containing 1 to 10% nitrogen is obtained. Ester-added buffered hydrofluoric acid (ABHF) (hydrofluoric acid: ammonium fluoride: acetic acid = 1- .:: 50: 50) is used at 23 ° C, and the standard etching rate is 80 to 100. 0A / minute. Plasma CVD forms a 500 A thick amorphous silicon film. A silicon oxide film was formed on the surface of the amorphous silicon film by thermal annealing at 55 ° C for 1 hour in an oxygen-containing atmosphere (estimated about 40 to 100 A). By spin coating, a 1 to 100 ppm nickel ester acid solution is used to form an extremely thin film of nickel acetate. First, a thin silicon oxide film is formed on the surface of the amorphous silicon film, and the solution is distributed on the surface of the amorphous silicon film. ’Thermal annealing at 5 50 ° C for 4 hours in a nitrogen-containing atmosphere. Nickel ester is decomposed at about 400 ° C to obtain nickel. Since the nickel acetate film is roughly attached to the amorphous silicon film, nickel diffuses to the amorphous silicon film by thermal annealing. Therefore, the amorphous silicon film is crystallized to form a crystalline silicon region.
XeC 1準分子雷射光（3 0 8 nm波長）照在矽膜 。雷射能量密度爲2 5 0至3 0〇!111/(：1112，進一步 增進結晶矽膜晶性。再者，爲由雷射照射鬆弛應力應變， 在5 5 0 °C再度熱退火4小時。 蝕刻矽膜形成島狀活性層6 0 3和6 0 4。 1 2 0 0 A厚的氧化矽膜6 5由濺射形成閘極絕緣膜。 濺射形成4 0 0 0 A厚的鋁（含〇 . 2至〇 . 3重量 %的銃）膜。使表面陽極化，形成1 0 0至3 0 0 A厚的 本紙張尺度適用中國國家標準（CNS ) 规格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) d -14 - A7 B7 五、發明説明（12) _ (請先聞讀背面之注意事項再填寫本頁) 氧化鋁膜（未顯示）。由於氧化鋁膜存在，故鋁膜對光阻 有高黏性。防止電流光阻漏出，多孔型陽極氧化物在下述 陽極化處理形成於閘極側部。 旋轉塗覆形成光阻.（例如Τ 〇 k y 〇 0 h k a公司 的產品0卩？尺8 0 0/ 3_.0〇口），再形成閘極6 0 9 和6 1 1及閘極線6 1 0。周邊電路的閘極6 Ο 9和閘極 線61 〇與主動矩陣電路的閘極6 11絕緣。用於蝕刻的 光阻（罩）6 0 6至6 0 8乃在。（圖6Α).XeC 1 excimer laser light (30.8 nm wavelength) shines on the silicon film. The laser energy density is from 250 to 300.111 / (: 1112, which further improves the crystallinity of the crystalline silicon film. Furthermore, to relax the stress and strain by laser irradiation, thermal annealing is performed again at 5 50 ° C for 4 hours. The silicon film is etched to form island-shaped active layers 603 and 604. 1 2 0 0 A thick silicon oxide film 65 is formed by sputtering to form a gate insulating film. Sputtered to form 4 0 0 A thick aluminum ( Contains 0.2 to 0.3% by weight of 铳) film. The surface is anodized to form a thickness of 100 to 300 A. This paper size is applicable to China National Standard (CNS) specifications (210 X 297 mm) ( Please read the notes on the back before filling in this page) d -14-A7 B7 V. Description of the invention (12) _ (Please read the notes on the back before filling in this page) Alumina film (not shown). Due to oxidation The aluminum film is present, so the aluminum film has high viscosity to the photoresist. To prevent the leakage of the current photoresist, the porous anodic oxide is formed on the gate side in the anodizing process described below. Spin coating is used to form the photoresist. (Such as Τ〇ky 〇0 products of Hka company 0 卩? Ruler 8 0 0 / 3_.0 port), and then form the gates 6 09 and 6 1 1 and the gate line 6 1 0. The gate of the peripheral circuit 6 0 9 and gate line 61 0 are insulated from gate 6 11 of the active matrix circuit. Photoresistors (covers) 6 6 to 6 8 for etching are present (Fig. 6A).
•I 在光阻6 0 6至6 0 8仍在的狀態使電流流經閘極線 6 1 0和閘極6 1 1，進行多孔陽極化，在閘極線6 1 0 和閘極6 1 1的側部形成多孔陽極氧化物6 1 2和6 1 3 。3至2 0 %的酸溶液（例如 '檸檬酸、草酸、磷酸、鉻酸 9>· 或硫酸）用於陽極化。1 0至'3 OV電壓施於閘極。實施 例中，在草酸溶液（在3 0 °C ρΗ=0. 9至1. 0) 經濟部中央標準局員工消费合作社印製 於1 0V陽極化2 0至80分鐘。陽極化時間控制陽極氧 化物厚度。藉由使用酸溶液的陽極化，形成多孔陽極氧化 物。多孔陽極氧化物厚度爲3 0 0 0至1 〇 〇 〇 〇 A，例 如 500 0A。（圖 6B) 在除去光阻6 0 6至6 0 8後，使電流流經閘極線 610來進行障壁陽極化，在閘極線61〇和閘極611 的側部和上表面形成各1 2 Ο 0A厚的細障壁型陽極氧化 物膜614和615。（圖6C) 使用多孔陽極氧化物6 1 2和6 1 3做爲罩，由乾蝕 刻來蝕刻氧化矽膜6. 〇 5，形成閘極絕緣膜6 1 6至 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐）~ —1 R . 經濟部中央揉準局員工消費合作社印装 A7 B7_ _• I In the state that the photoresistors 6 0 6 to 6 0 8 are still in the state, the current flows through the gate line 6 1 0 and the gate electrode 6 1 1 for porous anodization, and the gate line 6 1 0 and the gate electrode 6 1 The sides of 1 form porous anodic oxides 6 1 2 and 6 1 3. An acid solution of 3 to 20% (e.g. 'citric acid, oxalic acid, phosphoric acid, chromic acid 9 > · or sulfuric acid) is used for anodization. A voltage of 10 to '3 OV is applied to the gate. In the example, printed in an oxalic acid solution (at 30 ° C ρΗ = 0.9 to 1.0) at the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs at 10V for 20 to 80 minutes. The anodizing time controls the thickness of the anodic oxide. By anodization using an acid solution, a porous anodic oxide is formed. The thickness of the porous anodic oxide is 3000 to 100 A, such as 500 A. (Fig. 6B) After removing the photoresist 6 06 to 6 0 8, current is passed through the gate line 610 to perform barrier anodization, and 1 and 1 are formed on the side and upper surfaces of the gate line 61 and the gate 611 respectively. 2 0 0 A thick thin barrier type anodic oxide films 614 and 615. (Fig. 6C) Using porous anodic oxides 6 1 2 and 6 1 3 as a cover, the silicon oxide film 6.05 is etched by dry etching to form a gate insulating film 6 1 6 to this paper standard using Chinese national standards (CNS) A4 size (210X297 mm) ~ —1 R. Printed by the Consumer Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs A7 B7_ _
五、發明説明（J 1〇 6 1 8。此蝕刻可包含各向同性蝕刻的電漿模式或各向異 性蝕刻的反應離子蝕刻模式。充分增加矽與氧化矽的選擇 比，不要過蝕刻活性層。當C 1 F 4做爲蝕刻氣體時，不 蝕刻陽極氧化物，只蝕刻氧化矽膜6 0 5。形成於多孔陽 極氧化物6 1 2和6 13Έ的氧化矽膜6 1 7和6 1 8仍 未蝕刻。（圖6 D ) 使用磷酸、酯酸、硝酸的混合溶液，只蝕刻多孔陽極 氧化物6 12和6 1 3。混合溶液幾乎不蝕刻障壁陽極氧 ·' 化物6 1 4和6 1 5。由於混合溶液蝕刻鋁，故使用光阻 以保護周邊電路部的閘極6 0 9 ,掩蔽周邊電路部。因此 ，比較實施例3，另添加光石印術處理。 藉由使用閘極絕緣膜6 1 ”6和6 1 8的離子摻雜，雜 質（磷和硼）引入活性層。雖中只顯示NMOS，但也V. Description of the invention (J 1086 1 8. This etching may include plasma mode of isotropic etching or reactive ion etching mode of anisotropic etching. Fully increase the selection ratio of silicon to silicon oxide, and do not over-etch the active layer When C 1 F 4 is used as an etching gas, the anodic oxide is not etched, and only the silicon oxide film 6 0 5 is formed. The silicon oxide films 6 1 7 and 6 1 8 are formed on the porous anodic oxides 6 1 2 and 6 13Έ. Still not etched. (Figure 6D) Using a mixed solution of phosphoric acid, ester acid, and nitric acid, only the porous anodic oxides 6 12 and 6 1 3. The mixed solution hardly etches the barrier anodic oxides 6 1 4 and 6 1 5. Since the mixed solution is used to etch aluminum, a photoresist is used to protect the gate 609 of the peripheral circuit portion to mask the peripheral circuit portion. Therefore, in comparison with Example 3, a photolithography process is additionally added. By using a gate insulating film 6 1 ”6 and 6 1 8 doped with ions, impurities (phosphorus and boron) are introduced into the active layer. Although only NMOS is shown, but also
摻雜硼。磷摻雜中，加速電壓相當低（1 0至3 OKeV )，劑量相當高（5X1 014至5X1 015原子/ cm3 )。由於加速電壓低，故離子引入深度淺，主要將磷引入 露出矽層的區域6 1 9和6 2 0。Doped with boron. In phosphorus doping, the acceleration voltage is quite low (10 to 3 OKeV) and the dose is quite high (5X1 014 to 5X1 015 atoms / cm3). Due to the low acceleration voltage, the ion introduction depth is shallow, and phosphorus is mainly introduced into the regions 6 1 9 and 6 2 0 that expose the silicon layer.
磷以6 0至9 5 K e V的相當高加速電壓以1 X 1 012至IX 1014原子/ cm3的相當低劑量引入。由 於加速電壓高，故離子引入深度深，將磷引入覆以閘極絕 緣膜的區域6 2 1。因此，形成滲入高濃度之磷的區域 6 1 9和6 2 0及摻入低濃度之磷的區域6 2 1。亦即， 圖素T F T中，可得到所謂的雙汲極結構。硼中可進行相 同處理0 ._ - '，'_______ 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X 297公釐） T丨^^丨Γ — — -®-裝！ (請先閲讀背面之注意事項再填寫本頁) 訂 •Ια. 經濟部中央橾準局貝工消费合作社印製 A7 B7 五、發明説明（14) 在4 5 0 °C熱退火1小時，激活摻雜的雜質。由於鎳 &爲結晶促進元素，故可在低於正常激活的溫度激活。（ 圖6 E ) 具有氧化矽膜（2.0 0A厚）和氮化矽膜（ 4 〇 Ο 0A厚）的多層膜6_2 2由電漿CVD形成第一中 間靥絕緣體，再由乾餽刻形成接觸孔6 3 2至6 2 7。（ 圖6F) 具有鈦（5 0 0 A厚）、銀（4 0 0 0 A厚）、鈦（ 5 ο 〇 A厚）的三層金屬膜由濺射沈積，再蝕刻形成電極 接線6 2 8至6 3 1。再者，藉由電漿CVD， 2 〇 Ο Ο A厚的氧化矽膜6 3 2沈積爲第二中間層絕緣體 ，接觸孔形成於圖素T F T的汲極6 3 1 ，I T 0形成圖 素電極6 3 3。因此，可產生^單石型主動矩陣電路。（圖 .6 G ) 上述處理的基底中，IC晶片裝在連接外部IC晶片 之端子部（對應於部分4 1 )的I TO接線墊上，由圖 4A和4B的FCOG黏著。 〔實施例5〕 晶片由線接合附在TFT電路（單石型主動矩陣電路 )基底，構成更改良的電路。圖7八至7 D顯示實施例的 主動矩陣電路製程。圖7 A至7 D中’左側是周邊邏輯電 路區，右側是主動矩陣電路區。 2 0 0 Π A厚的某本氢化物膜7 0. 1由濺射沈積在玻 本紙張尺度適用中國國家標準（CNS ) A4规格；（ 210X297公釐)_ 17 i i.·-11#裝丨| (請先閲讀背面之注意事項再填寫本頁) 訂 A7 _____B7__ 五、發明説明（1C) 15 (請先閲讀背面之注意事項再填寫本頁) 璃基底（未顯示）上。5 0 〇A厚的I TO膜由濺射形成 於基本氧化物膜7 0 1上，再蝕刻形成周邊邏輯電路區的 接線7 0 2至7 0 4及主動矩陣電路區的接線7 0 5和圖 素電極7 0 β 〇 5 0 0至15 0 0 Α厚的非晶矽膜由電漿CVD或 LP CVD形成，而甲矽烷或乙矽烷做爲原料氣體。非晶 矽膜的氧濃度宜爲1 0 18·原子/ c m 3以下。 磷和硼以類似已知CMO S製造的離子摻雜來摻入。 亦即，在磷摻雜後，光阻掩蔽形成N通道型TF T的區域 ，硼再摻入形成P通道型TF T的區域。 摻雜磷的摻雜氣體是磷化氫（p H3)摻雜硼的摻雜 氣體是乙硼烷（B 2 Η 6 )。加速電歷在磷宜爲5至3 0 Κ V。劑量1 X 1 〇 14至5 1 0 15原子/ c m 3，例如 在磷爲2 X 10 14原子/ cm3，在硼爲5 X 1 0 14原子 _/ c m 3 0 做爲各TFT之通道形成區的部分（在源極與汲極之 間）蝕刻形成N型半導體區7 0 7、7 0 8、7 1 1、 7 12和P型半導體區7 0 9和7 1 〇。1 〇 〇至 5 0 0 A (例如2 0 0 A )厚的本質非晶氫化的矽膜 7 13由電漿CVD形成於這些區域上。 圖7 A中，使用不_接觸膜7 1 3的非黏著罩7 1 4， 照射Kr F準分子電射光（24 8 n m'波長和2 〇 n s脈 寬），使膜7 1 3的周邊電路區（左側）結晶。雷射能量 密度爲2 0〇至4〇,〇!!11/(：1112，最好是2 5 0至 t a a ( CNS ) ( 210 X 297^* ) ' A7 B7 五、發明説明（16) 3 0 OmJ/ cm2。由於照射的電射.光未到達覆以罩 7 14的區域（包含主動矩陣電路區），故該區仍爲非晶 矽。照射雷射的區域在膜7 1 3和區域7 0 7至7 1 〇結 晶。 . 矽膜（N型和P型半導體區7 0 7至7 1 0及本質砍 膜7 1 3 )鈾刻成島狀，形成周邊電路的島狀區7 2 1至 7 2 3。同時，也形成周邊邏輯電路之N通道型TFT的 源極7 1 5和汲極7 1 6、周邊邏輯電路之P通道型 ·· TFT的源極7 1 8和及7 1 7、主動矩陣電路之N通道 型TFT的源極719和汲極720。（圖7B) 使用一氧化二氮（N2〇)和氧（02)做爲.原料，電 漿C V D形成1 2 0 0 A厚的氧化矽膜7 2 4。由於膜 7 2 4做爲閘極絕緣膜或保持:電容器的介電物質，故膜須 有夠低的介面位準密度和高耐壓。實施例中，甲矽烷和一 氧化二氮分別以1 0SCCM和1 0 0SCCM引入反應 室。基底溫度爲4 3 0 °C，反應壓力爲0. 3Torr ， 施加功率在1 3 . 5 6 Μ Η z爲2 5 0 W。這些條件取決 於要用的反應裝置。 形成於上述條件之氧化矽膜7 2 4的膜形成速度約 1 00 〇Α/分鐘。當使用1 : 5 0 : 50比率之氫氟酸 、醋酸、氟化銨的混合溶液（在2 0°C)時，蝕刻速度約 1000A/分鐘。2000至8000A(例如 3 〇 〇 〇A)厚的鈦膜由濺射沈積，再蝕刻形成閘極 .. · 7 2 5至7 2_ 7和保持電容器電極7 2 8。 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） . -19 - |-------\----裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 iu 經濟部中央標準扃貝工消费合作社印装 A7 B7 五、發明説明（17) 3 Ο Ο 0A厚的氮化矽膜7 2 9由電漿CVD形成鋪 化膜。因此，可形成周邊邏輯電路之結晶矽的NS道型和 P通道型TFT (周邊p-Si N-ch TFT和周 邊p — Si P - c h . TFT)、主動矩陣電路的]^通 道型非晶矽TFT (圖素a. - Si N - c h T F T } 、保持電容器。（圖7 C ) 周邊邏輯電路的TF T結構可異於主動矩陣電路。例 如，主動矩陣電路之TFT閘極與汲極分開距-之圖7D 的偏移結構中，OFF電流可進一步降低。 爲進行與周邊邏輯電路相同的高速作業，半導體須結 晶，源極和汲極也結晶，薄片電阻低。雖照射雷射以製造 周邊邏輯電路，但由於通道形誠區及對應於源極和汲極的 部分都結晶，故滿足上述要求^。爲進一步增進源極和汲極 的結晶，促進非晶较結晶的催化元素（例如鎳、鉑、鈀、 鈷或鐵）能以1 X 1 0 17至2 X 1 〇 μ原子/ c m 3的濃 度加入矽膜。 上述處理的基底中，蝕刻連接外部IC晶片之端子部 (對應於部分2 1 )的氮化矽膜7 2 9，露出端子連接部 的鈦接線墊，由圖2的線接合連接rc晶片。 〔實施例6〕 圖8A至8I顯示主動矩陣電路部的剖面，圖9A至 9 1顯示周邊電路部的剖面。圖1 〇 a是所製之主動矩陣 _電路的上視圖，圖8· I和9 I顯示圄1 〇 A之線A — B — 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X 297公兼） ^ ~ 20 - (請先閲讀背面之注意事項再填寫本頁)Phosphorus is introduced at a rather high acceleration voltage of 60 to 95 KeV at a relatively low dose of 1 X 1 012 to IX 1014 atoms / cm3. Due to the high acceleration voltage, the depth of ion introduction is deep, and phosphorus is introduced into the region 6 2 1 covered with the gate insulating film. As a result, regions 6 1 9 and 6 2 0 infiltrated with high concentration of phosphorus and regions 6 2 1 doped with low concentration of phosphorus are formed. That is, in the pixel T F T, a so-called double-drain structure can be obtained. The same treatment can be performed in boron. 0._-',' _______ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) T 丨 ^^ 丨 Γ — — -®-pack! (Please read the notes on the back before filling out this page) Order • Ια. Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (14) Thermal annealing at 4 50 ° C for 1 hour, activation Doped impurities. Since nickel & is a crystallization promoting element, it can be activated at temperatures below normal activation. (Fig. 6E) A multilayer film 6_2 with a silicon oxide film (2.0 0A thick) and a silicon nitride film (4000A thick). The first intermediate rhenium insulator is formed by plasma CVD, and the contact hole is formed by dry-feed etching. 6 3 2 to 6 2 7. (Figure 6F) A three-layer metal film with titanium (500 A thick), silver (4 0 0 A thick), and titanium (5 ο 0 A thick) is deposited by sputtering and then etched to form electrode wiring 6 2 8 To 6 3 1. In addition, by plasma CVD, a 2000 A thick silicon oxide film 6 3 2 is deposited as a second interlayer insulator, a contact hole is formed at the drain electrode 6 3 1 of the pixel TFT, and IT 0 forms a pixel electrode. 6 3 3. Therefore, a monolithic active matrix circuit can be generated. (Fig. 6G) In the substrate treated as described above, the IC chip is mounted on the I TO terminal pads (corresponding to part 41) of the external IC chip, and is adhered by the FCOG of Figs. 4A and 4B. [Embodiment 5] The chip was attached to the substrate of a TFT circuit (monolithic active matrix circuit) by wire bonding, and constituted a modified circuit. 7A to 7D show an active matrix circuit process of the embodiment. In FIGS. 7A to 7D, the left side is the peripheral logic circuit area, and the right side is the active matrix circuit area. 2 0 0 Π A thickness of a certain hydride film 7 0.1 1 deposited on glass paper by sputtering. Applicable to China National Standard (CNS) A4 specifications; (210X297 mm) _ 17 i i. · -11 # equipment丨 | (Please read the notes on the back before filling this page) Order A7 _____B7__ V. Description of the invention (1C) 15 (Please read the notes on the back before filling this page) on the glass substrate (not shown). A 50 μA thick I TO film is formed on the basic oxide film 7 0 1 by sputtering, and then the wiring of the peripheral logic circuit area 7 0 2 to 7 0 4 and the wiring of the active matrix circuit area 7 0 5 and The pixel electrode 7 0 β 0 5 0 to 15 1 0 A thick amorphous silicon film is formed by plasma CVD or LP CVD, and silane or disilane is used as the raw material gas. The oxygen concentration of the amorphous silicon film is preferably 10 18 · atoms / cm 3 or less. Phosphorus and boron are doped with ion doping similar to those made by known CMO S. That is, after phosphorus doping, photoresist masks the area where the N-channel TTF is formed, and boron is then doped into the area where the P-channel TTF is formed. The doping gas for phosphorus doping is phosphine (p H3) and the doping gas for boron is diborane (B 2 Η 6). Accelerated electric calendar is preferably 5 to 30 κ V in phosphorus. Dose 1 X 1 〇14 to 5 1 0 15 atoms / cm 3, for example, 2 X 10 14 atoms / cm 3 in phosphorus and 5 X 1 0 14 atoms / cm 3 0 in boron as the channel forming region of each TFT Parts (between the source and the drain) are etched to form N-type semiconductor regions 7 0 7, 7 0 8, 7 1 1, 7 12 and P-type semiconductor regions 7 9 and 7 1 0. A 100 to 500 A (for example, 2000 A) thick amorphous hydrogenated silicon film 7 13 is formed on these regions by plasma CVD. In FIG. 7A, a non-adhesive cover 7 1 4 that does not contact the film 7 1 3 is irradiated with Kr F excimer electroradiation light (24 8 n m ′ wavelength and 20 ns pulse width) to make the periphery of the film 7 1 3 The circuit area (left) crystallizes. Laser energy density is from 200 to 40,000. 11 / (: 1112, preferably from 2 50 to taa (CNS) (210 X 297 ^ *) 'A7 B7 V. Description of the invention (16) 3 0 OmJ / cm2. Due to the irradiated light, the light does not reach the area covered by the cover 7 14 (including the active matrix circuit area), so the area is still amorphous silicon. The area irradiated with laser is in the film 7 1 3 and the area 7 0 7 to 7 1 0 crystal.. Silicon film (N-type and P-type semiconductor regions 7 7 to 7 1 0 and essentially cut film 7 1 3) Uranium is carved into an island shape, forming an island-like region of peripheral circuits 7 2 1 To 7 2 3. At the same time, the source 7 1 5 and the drain 7 1 6 of the N-channel TFT of the peripheral logic circuit are also formed, and the source 7 1 8 and 7 1 of the TFT of the peripheral logic circuit 7. The source 719 and the drain 720 of the N-channel TFT of the active matrix circuit. (Figure 7B) Using nitrous oxide (N2O) and oxygen (02) as raw materials, plasma CVD to form 1 2 0 0 A thick silicon oxide film 7 2 4. Since the film 7 2 4 is used as a gate insulating film or a dielectric substance of a capacitor, the film must have a sufficiently low interface level density and a high withstand voltage. In the embodiment, Silane and nitrous oxide were 0 0 SCCM was introduced into the reaction chamber. The substrate temperature was 4 3 0 ° C, the reaction pressure was 0.3 Torr, and the applied power was 13 .56 Μ Η z was 2 50 W. These conditions depend on the reaction device to be used. Formation The film formation speed of the silicon oxide film 7 2 4 under the above conditions is about 100 〇A / minute. When using a mixed solution of hydrofluoric acid, acetic acid, and ammonium fluoride at a ratio of 1: 50: 50 (at 20 ° C) ), The etching rate is about 1000 A / min. 2000 to 8000 A (for example, 3,000 A) thick titanium film is deposited by sputtering, and then etched to form a gate electrode. · 7 2 5 to 7 2_ 7 and holding capacitor electrode 7 2 8. The size of this paper is applicable to China National Standard (CNS) A4 (210X297 mm). -19-| ------- \ ---- packing-(Please read the precautions on the back before (Fill in this page) Order the central standard of the Ministry of Economic Affairs and print the A7 B7 of the Cooperative Cooperative. V. Description of the invention (17) 3 0 0 0A silicon nitride film 7 2 9 is formed by plasma CVD. Therefore, NS channel type and P channel type TFTs (peripheral p-Si N-ch TFT and peripheral p — Si P-ch. TFT), crystalline silicon that can form peripheral logic circuits] ^ channel type non Crystal silicon TFT (pixel a.-Si N-c h T F T}), holding capacitor. (Figure 7C) The TTF structure of the peripheral logic circuit may be different from the active matrix circuit. For example, in the offset structure of FIG. 7D where the TFT gate and the drain of the active matrix circuit are separated from each other, the OFF current can be further reduced. In order to perform the same high-speed operation as the peripheral logic circuits, the semiconductor has to be crystallized, the source and the drain are also crystallized, and the sheet resistance is low. Although the laser is irradiated to manufacture peripheral logic circuits, the above requirements are satisfied because the channel-shaped area and the portions corresponding to the source and the drain are crystallized. In order to further promote the crystallization of the source and drain electrodes, catalytic elements that promote amorphous crystals (such as nickel, platinum, palladium, cobalt, or iron) can be used at a concentration of 1 X 1 0 17 to 2 X 1 0 μ atoms / cm 3 Add silicon film. In the substrate treated as described above, the silicon nitride film 7 2 9 connected to the terminal portion (corresponding to the portion 2 1) of the external IC chip is etched to expose the titanium connection pad of the terminal connection portion, and the RC chip is connected by wire bonding in FIG. 2. [Embodiment 6] FIGS. 8A to 8I show cross sections of an active matrix circuit section, and FIGS. 9A to 91 show cross sections of a peripheral circuit section. Figure 1 〇a is a top view of the active matrix _ circuit, Figures 8 · I and 9 I show the line 圄 1 OA A — B — This paper size is applicable to China National Standard (CNS) A4 (210X 297) (Concurrent) ^ ~ 20-(Please read the notes on the back before filling out this page)
經濟部中央橾準局貝工消費合作杜印製 Α7 Β7 五、發明説明（） . 18’ C的剖面。圖χ 0 b顯示圖1 〇A之線a — b的剖面。圖 l〇c顯示所製之主動矩陣電路的電路配置。 第—閘極接線電極8 0 2至8 0 5形成於其上形成 1 〇 G 〇 A厚之氮化矽膜（未顯示）之玻璃基底的絕綠表 .面8 0 1上。蝕刻由磷摻雜而降低電阻之3 〇 〇 〇A厚的 多晶矽膜，形成閘極接線電極8 0 2至8 0 5。低壓 CVD形成多晶矽膜.，在形成此膜時有多晶狀態。 爲得到多晶矽膜，有上述方法除外的以下方法。亦即 ’在電漿CVD或低壓CVD形成本質非晶矽膜後，諸如 磷的雜質由離子摻雜等引入矽膜。再者，在5 0 0至 6 〇 〇 °C熱退火。熱退火中，可稍微沅入促進結晶的元素 ，例如鎳。實施例中，使用矽，但可用各種金屬矽化物。 .電漿CVD形成3 0 0 0至6 0 0 0 A (例如 4 0 0 〇 A)厚的氮化矽膜8 0 6，也做爲閘極絕緣膜。 電漿CVD形成3.0 0至1 0 0 0A (例如5 0 0A)厚 的非晶砂膜，再蝕刻形成島狀矽區8 0 7至8 0 9。（圖 8 A 和 9 A ) 電漿CVD形成3 0 0 0至6 0 0 〇A (例如 2 0 0 0A)厚的氮化矽膜8 1 0，也做爲閘極絕緣膜。 雷射光只照入周邊電路部，使島狀矽膜8 0 8和8 0 9結 晶。雷射是XeCl準分子雷射（308nm波長）。雷 射照射能量密度和脈衝數目隨矽膜8 0 8和8 0 9及氮化 矽膜810的特性而變。 蝕刻氮化矽膜8 0 6和8 1 0，形成到達第-閘極接 本紙張尺度逋用中國國家標準（CNS ) Μ規格（210X297公釐） ^-----^--------β裝 II (請先閲請背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印轚 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（19) 線的接觸孔（未顯示）。此接觸孔用來形成第一閘極接線 與第二閘極接線（形成於第一閘極接線上，對應於接點 8 4 5如圖1 0A和1 〇B)之間的接點。 在形成接觸孔後，濺射形成3000至800〇A( 例如3 0 0 0A)厚的鋁膜8 1 1。當鋁膜8 1 1含有 0 . 1至0. 5重量％的銃（Sc)時，可防止小丘產生 〇 (圖 8 B 和 9 B ) 蝕刻鋁膜8 1 1形成第二閘極接線電極8 1 2至 8 1 5。因此，經由形成的接觸孔形成第一閘極接線與第 二閘極接線的接觸。須以第二閘極接線完全覆蓋接觸孔。 這是因爲當矽所構成的第一閘極接線在接觸孔露出時，電 流在陽極化處理中流經露出部，而不進行陽極化作用。（ 圖8。和9 C ) 電解液中，電流送到第二閘極接線電極8 1 2至 8 1 5。使用將氨加入3至1 0 %酒石酸所得且有6 . 8 至7. 2 pH的乙二醇溶液。當溶液比室溫底約10 °C時 ，形成具有高品質的氧化物膜。因此，障壁陽極氧化物 8 1 6至8 1 9形成於第二閘極接線電極的上和側表面。 陽極氧化物厚度正比於施加電壓，最好是1 0 0 0至 3 0 0 0A。在1 5 0V形成2 0 0 0A厚的陽極氧化物 。爲得到3 0 0 0 A厚以上的陽極氧化物，須施加 2 5 0 V以上。但這影響T F T特性。（圖8 D和9 D ) 藉由乾蝕刻，自動對正蝕刻氮化矽膜8 1 0。但由於 不蝕刻陽極氧化物8 1 6至8 1 9 ，故閘極絕緣膜8 2 0 本紙張尺度適用中國國家標準（CNS ) A4規格（21,0X297公釐） (請先閲讀背面·之注意事項再填寫本頁)Printed by Shellfish Consumer Cooperation of the Central Bureau of Standards, Ministry of Economic Affairs Α7 Β7 V. Description of the invention (). 18 ′ C section. Figure χ 0 b shows a cross section along line a-b of Figure 10A. Figure 10c shows the circuit configuration of the active matrix circuit. The first-gate wiring electrodes 802 to 805 are formed on a green surface of a glass substrate on which a 10 G thick silicon nitride film (not shown) is formed. A polycrystalline silicon film with a thickness of 300 A, which is doped with phosphorus to reduce resistance, is etched to form gate wiring electrodes 802 to 805. Low-pressure CVD forms a polycrystalline silicon film. There is a polycrystalline state when this film is formed. To obtain a polycrystalline silicon film, there are the following methods except the above method. That is, after forming an essentially amorphous silicon film by plasma CVD or low-pressure CVD, impurities such as phosphorus are introduced into the silicon film by ion doping. Furthermore, thermal annealing is performed at 500 to 600 ° C. In thermal annealing, elements that promote crystallization, such as nickel, can be slightly incorporated. In the embodiment, silicon is used, but various metal silicides can be used. Plasma CVD forms a silicon nitride film 806 with a thickness of 300 to 600 A (for example, 400 A), which is also used as a gate insulating film. Plasma CVD forms an amorphous sand film having a thickness of 3.0 to 100 A (for example, 500 A), and is then etched to form island silicon regions 807 to 809. (Figures 8 A and 9 A) Plasma CVD forms a silicon nitride film 8 1 0 to 3 0 to 6 0 0 A (for example, 2 0 0 A), which is also used as a gate insulating film. The laser light strikes only the peripheral circuit portion, and crystallizes the island-shaped silicon films 808 and 809. Laser is XeCl excimer laser (308nm wavelength). The laser irradiation energy density and the number of pulses vary depending on the characteristics of the silicon films 808 and 809 and the silicon nitride film 810. Etching the silicon nitride film 8 0 6 and 8 1 0 to form the paper size to reach the-gate electrode, using China National Standard (CNS) M specifications (210X297 mm) ^ ----- ^ ----- --- β Pack II (Please read the notes on the back before filling this page) Order the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, India, and the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed by A7 B7 5. Description of the invention (19 ) Contact hole for the wire (not shown). This contact hole is used to form a contact between the first gate connection and the second gate connection (formed on the first gate connection, corresponding to the contact 8 4 5 as shown in FIGS. 10A and 10B). After the contact hole is formed, an aluminum film 8 1 1 with a thickness of 3000 to 800 OA (for example, 30000 A) is formed by sputtering. When the aluminum film 8 1 1 contains 0.1 to 0.5% by weight of rhenium (Sc), generation of hillocks can be prevented (see FIGS. 8 B and 9 B). The aluminum film 8 1 1 is etched to form a second gate wiring electrode 8 1 2 to 8 1 5. Therefore, a contact between the first gate wiring and the second gate wiring is formed through the formed contact hole. The contact hole must be completely covered with the second gate wiring. This is because when the first gate wiring made of silicon is exposed at the contact hole, current flows through the exposed portion during the anodizing process without anodizing. (Figure 8. and 9C) In the electrolyte, a current is sent to the second gate terminal electrodes 8 1 to 8 1 5. An ethylene glycol solution obtained by adding ammonia to 3 to 10% tartaric acid and having a pH of 6.8 to 7.2 was used. When the solution is about 10 ° C below the room temperature, an oxide film with high quality is formed. Therefore, barrier anodic oxides 8 16 to 8 1 9 are formed on the upper and side surfaces of the second gate wiring electrode. The thickness of the anodic oxide is proportional to the applied voltage, and preferably 100 to 3 0 0A. A 20000A thick anodic oxide was formed at 150V. To obtain an anodic oxide with a thickness of more than 3 00 A, more than 2 500 V must be applied. But this affects the T F T characteristics. (Figures 8D and 9D) By dry etching, the silicon nitride film 8 1 0 is automatically aligned and etched. But because the anodic oxide 8 1 6 to 8 1 9 is not etched, the gate insulating film 8 2 0 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21,0X297 mm) (Please read the note on the back first (Fill in this page again)
-裝------訂I io· -22 - A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（2()) 至8.,.2 3仍在第二閘極接線電極8 1 2至8 1 5與島狀政 膜8 0 7至8 0 9之間。（圖8 E和9 E ) 藉由離子摻雜，自動對正使用閘極部（閘極8 i 3至 8 1 5和其旁的陽極氧化物8 1 7至8 1 9 )，N型和P 型雜質引入島狀矽膜8 0 7至8 0 9，形成N型雜質區（ 源極/汲極區）8 2 4至8 2 7和P型雜質區8 2 8和 8 2 9。N型雜質摻雜的摻雜氣體爲氮化氫（ph3)， P型雜質摻雜的摻灘氣體爲乙硼烷（B2H6)。劑量爲 5X 1 0 14至5 X 1 0 15原子/ cm3，加速電壓爲1 〇 至3 OKeV。照射KrF準分子電射光（2 4 8nm波 長和2 0 n s脈寬），.激活引入矽膜8 0 7至8 0 9的雜 質離子。（圖8F和9F) 5 0至5 0 0A厚之諸如鈦膜8 3 0的金屬由濺射形 成於整個表面上。（圖8G和9G) 在4 5 0至5 0 0 eC (例如5 0 0 °C )熱退火1 0至 6 0分鐘，鈦與矽反應，形成矽化物（矽化鈦）區8 3 1 至8 3 6。此熱退火中，進一步激活摻雜的雜質。可進行 雷射光照射的雷射退火和可見光照射或近紅外光照射的燈 退火，取伐矽化物處理的熱退火。 使用分別以5:2:2之比率在過氧化氫、氨、水之 間混合所得的蝕刻液，蝕刻鈦膜8 3 0。由於不接觸露出 活性層的鈦膜（例如形成於氮化矽膜8 0 6和陽極氧化物 膜上的鈦膜〉留在金屬狀態，故可在此蝕刻處理中蝕刻。 另一方面，矽化鈦不蝕刻，因此仍在。（圖8A和9H) (請先閲讀背面之注意事項再填寫本頁)-Equipment ------ Order I io · -22-A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2 ()) to 8.,. 2 3 is still at the second gate The wiring electrodes 8 1 2 to 8 1 5 and the island-shaped political film 8 07 to 8 0 9. (Figures 8 E and 9 E) By ion doping, the gate portion is automatically aligned (gates 8 i 3 to 8 1 5 and anodic oxides 8 1 7 to 8 1 9 next to it), N-type and P-type impurities are introduced into the island-shaped silicon film 807 to 809, forming N-type impurity regions (source / drain regions) 8 2 4 to 8 2 7 and P-type impurity regions 8 2 8 and 8 2 9. The doping gas doped with N-type impurities is hydrogen nitride (ph3), and the doping gas doped with P-type impurities is diborane (B2H6). The dose is 5X 1 0 14 to 5 X 1 0 15 atoms / cm3, and the acceleration voltage is 10 to 3 OKeV. Irradiate KrF excimer electroradiation light (2 8 nm wavelength and 20 n s pulse width) to activate the introduction of foreign ions in the silicon film 807 to 809. (Figs. 8F and 9F) A metal such as a titanium film 830 having a thickness of 50 to 500 A is formed on the entire surface by sputtering. (Figures 8G and 9G) At 450 to 500 eC (for example, 500 ° C) for 10 to 60 minutes, titanium reacts with silicon to form silicide (titanium silicide) regions 8 3 1 to 8 3 6. In this thermal annealing, doped impurities are further activated. Laser annealing with laser light irradiation, lamp annealing with visible light irradiation or near-infrared light irradiation, and thermal annealing with silicide treatment can be performed. The titanium film 830 was etched using an etching solution obtained by mixing hydrogen peroxide, ammonia, and water at a ratio of 5: 2: 2, respectively. Since the titanium film (for example, the titanium film formed on the silicon nitride film 806 and the anodic oxide film) that does not contact the active layer is left in a metallic state, it can be etched in this etching process. On the other hand, titanium silicide Does not etch, so it is still. (Figures 8A and 9H) (Please read the precautions on the back before filling this page)
IP 裝. 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（.210X297公釐） Α7 Β7 五、發明説明'（21) 5 Ο Ο 0A厚的氧化矽膜由CVD形成於整個表面上 做爲第一中間層絕緣體8 3 7。接觸孔形成於TFT的源 極和汲極。在形成第一中間層絕緣體後，在4 〇 〇°C退火 1 0至3 0分鐘。形成銘接線電極8 3 8至8 4 1，使用 ITO膜形成圖素電極842。 爲不使水分、活性離子等從外部進入TFT，電漿IP package. The size of the paper is in accordance with Chinese National Standard (CNS) A4 (.210X297mm) A7 B7 V. Description of the invention '(21) 5 〇 〇 0A thick silicon oxide film formed by CVD on the entire surface as First Intermediate Layer Insulator 8 3 7. The contact holes are formed at the source and the drain of the TFT. After the first interlayer insulator is formed, it is annealed at 400 ° C. for 10 to 30 minutes. The wiring electrodes 8 3 8 to 8 4 1 are formed, and the pixel electrodes 842 are formed using an ITO film. In order to prevent moisture, active ions, etc. from entering the TFT from the outside, the plasma
CVD 形成 2 0 0 〇 至 5 Ο Ο 〇A (例如 3 Ο Ο 0A)厚 的氮化矽膜8 4 3，圖素部.8 4 4和連接外部I C晶片的 端子部（未·顯示）打開而露出I TO膜。（圖8 I和9 I ) 藉由上述處理，形成主動矩陣電路的接線交叉部 8 4 7、接到圖素的TFT、周邊電路的N通道型TFT 8 4 9和P通道型TFT8 5 0，得到單石型主動矩陣電 路。 圖10A是設有圖素部之TFT的上視圖。延伸自掃 描驅動器的閘極線在圖1 0 A似乎爲單線。但第一閘極線 8 0 2平行形成於第二閘極線8 1 2。第一和第二閘極線 經由接點8 4 5互連。實施例的主動矩陣電路中，對一 TFT形成一接點。 第一和第二閘極線8 0 2和8 1 2的其中一個雖損壞 ，但整體不變差。實施例中，如圖10A，接點形成於閘 極線分叉的分支部。這是因爲，提供墊區（有厚寬度的接 線區）以形成接點時，分支部不需提供特殊空間，因此在 _配置上較優。 本紙張尺度適用中國國家標準（CNS ) Μ規格（21.0X297公釐） ---------裝— (請先閲讀背面之注意事項再填寫本頁)CVD forms a silicon nitride film with a thickness of 2000 to 5 〇 〇A (for example, 3 〇 〇 0 A) 8 4 3, the pixel portion. 8 4 4 and the terminal portion (not shown) connected to the external IC chip is opened. The I TO film is exposed. (Figures 8 I and 9 I) Through the above processing, the wiring cross section 8 4 7 of the active matrix circuit, the TFT connected to the pixel, the N-channel TFT 8 4 9 and the P-channel TFT 8 50 of the peripheral circuit are formed. A monolithic active matrix circuit is obtained. FIG. 10A is a top view of a TFT provided with a pixel portion. The gate line of the extended self-scanning driver appears to be a single line in FIG. 10A. However, the first gate line 8 0 2 is formed in parallel with the second gate line 8 1 2. The first and second gate lines are interconnected via a contact 8 4 5. In the active matrix circuit of the embodiment, a contact is formed for a TFT. Although one of the first and second gate lines 80 2 and 8 1 2 is damaged, the whole remains unchanged. In the embodiment, as shown in FIG. 10A, the contact is formed at a branch portion where the gate line is branched. This is because when providing a pad area (a connection area with a thick width) to form a contact, the branch does not need to provide special space, so it is better in _ configuration. The size of this paper applies to Chinese National Standard (CNS) M specifications (21.0X297 mm) --------- packing— (Please read the precautions on the back before filling this page)
1T1T
-ID 經濟部中央標準局員工消費合作社印製 -24 - A7 . B7 五、發明説明（22) 圖1 OB顯示沿著圖1 〇 A之閘極線之線a — b的剖 面結構。圖1 0 c顯示具有圖1 〇 a之多個電路的主動矩 陣電路。閘極線8 1 2和8 0 2也分叉到在上線圖素電極 之下延伸的接線8 4 6。電容器形成於接線8 4 6與圖素 .電極之間，平行.於電路上之5圖素電極所形成的液晶電容器 。處理的基底中，I C晶片裝在連接外部I C晶片之 I TO的端子部（對應於部分4 1)，由圖4A和4 B的 F C 0 G附在I C晶片。 〔實施例7〕 I C晶片連接單石型主動矩陣電路（TFT電路）基 底，使用非晶矽（a — S i ) T F 丁的主動矩陣電路和使 用結晶矽T F T的周邊電路形成於同一玻璃基底上。 經濟部中夬標準局員工消費合作社印製 (請先聞讀背面之注意事項再填寫本頁) 圖11A至11D顯示實施例之單石型主動矩陣電路 的製程。1000至3000 A厚的氧化矽膜形成於玻璃 基底9 0 1上成爲基本氧化物膜9 0 2。藉由電漿V D 或L P C V D，非晶的矽膜9 0 3沈積3 0 0至 1 5 0 〇A 厚，例如 5 0 0A。再者，5 0 至 1 〇 〇 〇A (例如2 0 0A)厚的氧化矽膜（或氮化矽膜）由電漿 CVD形成保護膜904。 照射Kr F準分子電射光（2 4 8 nm波長和，增進 的矽膜9 0 3的晶性。雷射能量密度爲2 0 0至 4 0 OmJ/cm2，最好是 2 5 0 至 3 0 OmJ / cm2 。（圖 1 1 A ) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐) ' ： -25 - A7 B7 五、發明説明（23) 保護膜9 0 4除去而露出的矽膜9 0 3，定成島形以 形成N通道型TFT的島狀矽區9 0 5和P通道型TFT 的島狀矽區9 0 6。再者，在含氧的氣氛中濺射、或使用 電漿CVD來分解並沈積T E 0 S，形成閘極絕緣膜 .9 0 7 ° ' 濺射形成2 0 0 0_六至5 厚的銘膜，再触刻形成 閘極9 0 8和9 0 9。同時，也形成主動矩陣部之反交錯 型T F T的閘極9 1 0 ° (圖1 1 B ) 基底浸入電解液，將電流送到閘極，在閘極旁形成陽 極氧化物層9 1 1至9 1 3。周邊電路區之TFT (左側 )的陽極氧化物膜薄以增進TFT移動率，主動矩陣電路 之T F T (右側之反交錯型T F T )的陽極氧化物膜厚以 防閘極洩漏。實施例中，陽極氧化物膜皆爲2 0 0 0至 2 5 Ο 0 A 厚。（圖 Γ 1 C) 自動對正使用閘極部（閘極和其旁的陽極氧化物膜） 做爲罩》雜質由離子慘雜引入各TFT的島狀砍區9 0 5 和9 0 6。亦即，使用磷（PH3)做爲摻雜氣體，磷先 引入整個表面。在光阻只掩蔽島狀矽區9 〇 5後，硼只引 入島狀矽區9 0 6。劑量在磷爲2X1 〇i5至8X1 原子/cm3，在硼爲4 X 1 0 15至5 X 1 〇 15原子/ cm3 。硼的劑量高於磷。 照射K/r F準分子電射光（2 4 8 nm波長和 2 Ο n s脈寬，增進晶性因雜質引入而變差之部分的晶性 。雷射能量密度爲2 0 0至4 0 OmJ/cm2，最好是 本紙張尺度適用中國國家標準（ CNS ) A4规格（210X297公釐） _______裝 II (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作社印製 經濟部中央楳準局員工消費合作社印裝 A7 B7 五、發明説明（24) 2 5〇至3 0〇111】/(：1112。（圖 11D) 結果，形成N型區9 1 4和9 1 5及P型區9 1 6和 9 1 7。這些區域的薄片電阻爲2 0 〇至8 Ο Ο Ω/平方 〇 .藉由電漿CVD，3 0>0 0A厚的氮化矽膜形成於整 個表面上成爲中間層絕緣體9 18。氮化矽膜是周邊電路 的中間層絕緣體。但由於氮化矽膜做爲主動矩陣電路的 TFT閘極，故須注意膜製造。 1 0 0至5 0 0 A (例如2 0 0 A )厚的非晶矽層 9 1 9形成於主動矩陣部的閘極9 1 0上，然後使用電漿 CVD所形成的單晶矽層（5 0 0至1 〇 〇 〇A厚），形 成非晶矽TFT的源極9 2 0和汲極9 2 1。將諸如 I T 0的透明導電材料用於主動矩陣部的T F T，形成圖 素電極Θ 2 5 〇 接觸孔形成於周邊電路部之各TF T的源極和汲極，-ID Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economy -24-A7. B7 V. Description of the Invention (22) Figure 1 OB shows the cross-sectional structure along the line a-b of the gate line of Figure 10 A. Fig. 10c shows an active matrix circuit having a plurality of circuits of Fig. 10a. The gate lines 8 1 2 and 80 2 also branch to wirings 8 4 6 which extend below the on-line pixel electrode. The capacitor is formed between the wiring 8 4 6 and the pixel electrode, parallel to the liquid crystal capacitor formed by the 5 pixel electrode on the circuit. In the processed substrate, the IC chip is mounted on the terminal portion (corresponding to part 41) of the I TO connected to the external IC chip, and is attached to the IC chip by F C 0 G of FIGS. 4A and 4B. [Example 7] An IC chip was connected to a monolithic active matrix circuit (TFT circuit) substrate, and an active matrix circuit using amorphous silicon (a-Si) TF and a peripheral circuit using crystalline silicon TFT were formed on the same glass substrate . Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page). Figures 11A to 11D show the manufacturing process of the monolithic active matrix circuit of the embodiment. A silicon oxide film having a thickness of 1000 to 3000 A is formed on a glass substrate 9 01 to become a basic oxide film 9 02. With the plasma V D or L P C V D, the amorphous silicon film 903 is deposited to a thickness of 300 to 1500 A, such as 500 A. In addition, a silicon oxide film (or a silicon nitride film) having a thickness of 50 to 100 A (for example, 2000 A) is formed by a plasma CVD to form a protective film 904. Irradiated with Kr F excimer electroluminescence light (2 4 8 nm wavelength and enhanced crystallinity of the silicon film 9 0 3. The laser energy density is 2 0 to 4 0 OmJ / cm2, preferably 2 5 0 to 3 0 OmJ / cm2. (Figure 1 1 A) This paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 mm) ': -25-A7 B7 V. Description of the invention (23) Protective film 9 0 4 is removed and exposed The silicon film 903 is formed in an island shape to form an island silicon region 905 of an N-channel TFT and an island silicon region 906 of a P-channel TFT. Furthermore, sputtering is performed in an oxygen-containing atmosphere, or Plasma CVD is used to decompose and deposit TE 0 S to form a gate insulating film. 9 0 7 ° 'Sputtered to form 2 0 0 0_6 to 5 thick film, and then etched to form gates 9 0 8 and 9 0 9. At the same time, the gate electrode of the inverse staggered TFT of the active matrix portion 9 1 0 ° (Fig. 1 B) is immersed in the electrolyte, sends the current to the gate electrode, and forms an anodic oxide layer 9 next to the gate electrode. 1 1 to 9 1 3. The anodic oxide film of the TFT (left side) in the peripheral circuit area is thin to increase the TFT mobility, and the anodic oxide film thickness of the TFT of the active matrix circuit (the right-side staggered TFT) is to prevent the gate electrode. In the embodiment, the anodic oxide film is 2 000 to 2 5 0 0 A thick. (Figure Γ 1 C) The gate part (gate and the anodic oxide film next to it) is used for automatic alignment. For the mask, impurities are introduced into the island-shaped cut-out areas of each TFT by ions 905 and 906. That is, using phosphorus (PH3) as the doping gas, phosphorus is introduced into the entire surface first. The island is only masked by the photoresist Boron was introduced into the island-like silicon region 906 after the sol-like silicon region 905. The dose was 2X1 0i5 to 8X1 atoms / cm3 in phosphorus, and 4 X 1 0 15 to 5 X 1015 atoms / cm3 in boron. The dose of boron is higher than that of phosphorous. Irradiate K / r F excimer electroradiation light (wavelength of 2 4 8 nm and pulse width of 20 ns to improve the crystallinity of the part whose crystallinity is deteriorated due to the introduction of impurities. The laser energy density is 2 0 0 to 4 0 OmJ / cm2, preferably this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) _______Pack II (Please read the precautions on the back before filling this page) Printed by the Standards Bureau's Consumer Cooperatives A7 B7 printed by the Consumers' Cooperatives of the Central Prospectus Bureau of the Ministry of Economic Affairs 5. Description of the invention (24) 2500 to 300111] / (: 1112. ( 11D) As a result, N-type regions 9 1 4 and 9 1 5 and P-type regions 9 1 6 and 9 1 7 are formed. The sheet resistance of these regions is 2 0 to 8 0 0 Ω / square. By plasma CVD A silicon nitride film with a thickness of 3 0 > 0 0A is formed on the entire surface to form an intermediate layer insulator 918. The silicon nitride film is an interlayer insulator for peripheral circuits. However, since the silicon nitride film is used as the TFT gate of the active matrix circuit, attention must be paid to the film manufacturing. A 100 to 5 0 A (eg, 2 0 A) thick amorphous silicon layer 9 1 9 is formed on the gate 9 1 0 of the active matrix portion, and then a single crystal silicon layer formed by plasma CVD ( 5,000 to 10,000 A thick), forming a source 920 and a drain 921 of an amorphous silicon TFT. A transparent conductive material such as I T 0 is used for the T F T of the active matrix portion to form a pixel electrode θ 2 5 〇 contact holes are formed at the source and drain of each TF T of the peripheral circuit portion,
形成鋁接線9 2 2至9 2 4。在左側使用N通道型TFT 和P通道型T F T，製ϋ相器電路。在3 5 0 °C於含氫 的氣氛中退火2小時，減少矽膜懸掛鍵。藉由上述處理， 集積周邊電路和主動矩陣電路。 .實施例中，反交錯型TF T做爲主動矩陣電路的非晶 矽TFT，而不將光照入通道部。這是因爲非晶矽導電性 由光照射改變。處理的基底中，使用圖2的線接合法， I C晶片連接接到外部I C晶片之鋁接線的端子部（對應 於部分2 1 ) 。 ___ 本紙張尺度適用中國國家標準（CNS ) Λ4规格（210X297公釐) ' (請先閲讀背面之注意事項再填寫本頁) >ΤΓForming aluminum wiring 9 2 2 to 9 2 4. An N-channel type TFT and a P-channel type T F T are used on the left to make a phaser circuit. Anneal at 350 ° C for 2 hours in a hydrogen-containing atmosphere to reduce dangling bonds on the silicon film. Through the above processing, peripheral circuits and active matrix circuits are integrated. In the embodiment, the de-interleaved TF T is used as the amorphous silicon TFT of the active matrix circuit, and the light does not enter the channel portion. This is because the conductivity of amorphous silicon is changed by light irradiation. In the processed substrate, the IC chip was connected to the terminal portion of the aluminum wiring of the external IC chip (corresponding to part 2 1) using the wire bonding method of FIG. 2. ___ This paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 mm) '(Please read the precautions on the back before filling this page) > ΤΓ
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32965294A JPH07209672A (en) | 1993-12-03 | 1994-12-02 | Electronic device with light nonemission type display |
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| Publication Number | Publication Date |
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| TW386222B true TW386222B (en) | 2000-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW88101918A TW396329B (en) | 1994-12-02 | 1995-11-24 | Electric device having non-light emitting type display and method for making the electric device |
| TW88101919A TW394922B (en) | 1994-12-02 | 1995-11-24 | Electric device having non-light emitting type display and method for making the electric device |
| TW84112555A TW386222B (en) | 1994-12-02 | 1995-11-24 | Electric device having non-light emitting type display and method for making the electric device |
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| Application Number | Title | Priority Date | Filing Date |
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| TW88101918A TW396329B (en) | 1994-12-02 | 1995-11-24 | Electric device having non-light emitting type display and method for making the electric device |
| TW88101919A TW394922B (en) | 1994-12-02 | 1995-11-24 | Electric device having non-light emitting type display and method for making the electric device |
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| CN (4) | CN1248318C (en) |
| TW (3) | TW396329B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002175056A (en) * | 2000-12-07 | 2002-06-21 | Hitachi Ltd | Liquid crystal display |
| JP2005101527A (en) * | 2003-08-21 | 2005-04-14 | Seiko Epson Corp | Electronic component mounting structure, electrooptic device, electronic equipment, and method of mounting electronic component |
| KR101052960B1 (en) * | 2004-04-29 | 2011-07-29 | 엘지디스플레이 주식회사 | Semi-transmissive polysilicon liquid crystal display device manufacturing method |
| CN100405143C (en) * | 2005-05-19 | 2008-07-23 | 友达光电股份有限公司 | Liquid crystal module |
| CN102270415A (en) * | 2010-06-04 | 2011-12-07 | 刘舸 | Built-in system type TFT-LCD (thin film transistor-liquid crystal display) liquid crystal display module |
| CN102331645B (en) * | 2011-10-11 | 2013-11-06 | 信利半导体有限公司 | Liquid crystal display and manufacturing method thereof |
| CN102842586B (en) * | 2012-08-15 | 2019-02-26 | 京东方科技集团股份有限公司 | Display base plate, display panel and display device |
| CN106940506A (en) * | 2017-05-12 | 2017-07-11 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
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| JP3123616B2 (en) * | 1991-10-09 | 2001-01-15 | キヤノン株式会社 | Liquid crystal display device mounting method |
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1995
- 1995-11-24 TW TW88101918A patent/TW396329B/en not_active IP Right Cessation
- 1995-11-24 TW TW88101919A patent/TW394922B/en not_active IP Right Cessation
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| Publication number | Publication date |
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| CN1395317A (en) | 2003-02-05 |
| TW396329B (en) | 2000-07-01 |
| CN1395318A (en) | 2003-02-05 |
| CN100539139C (en) | 2009-09-09 |
| CN1237622C (en) | 2006-01-18 |
| CN1092803C (en) | 2002-10-16 |
| CN1790710A (en) | 2006-06-21 |
| TW394922B (en) | 2000-06-21 |
| CN1154488A (en) | 1997-07-16 |
| CN1248318C (en) | 2006-03-29 |
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