TW382859B - D/A converter with Gamma correction - Google Patents

Abstract

A D/A converter with Gamma correction according to the invention is designed for C-DAC which takes up much less space than the conventional R-DAC and 2-divided C-DAC. Therefore, this D/A converter has advantages of simple design and low cost. Furthermore, this invention provides a D/A converter with a Gamma correction circuit with which users can freely define the shape of a Gamma correction conversion curve to thereby widen application areas by adjusting terminal voltages.

Description

A7 B7 五、發明説明（l ) 本發明係有於數位類比轉換器，特別是有關於具有 Gamma校正之數位類比轉換器。 t (請先閱讀背面之注意事項再填寫本頁) 傳統之數位類比轉換器（digital-to-analog converter ， 簡稱DAC)，其輸出電壓均儘可能要求與輸入之數位數值 成線性之關係，然而在特定之應用場合下，DAC之輸出電 懕盥輪入之數值卻必須爲非綠性之關係。例如在液晶顯示 器（liquid crystal display，簡稱lcd)之應用上，液晶亮度 和電壓之間並非為線性關係，故必須使用校正電路來作補 償，一般稱此種校正電路為Gamma校正電路。 --° 請參照第1圖所示R-DAC之架構，其為傳統具有 Gamma校正電路之DAC，主要是利用ROM解碼器i來進 行解碼D0~D5之數位資料，再由參考電壓產生器2中選擇 對應之電阻分壓輸出。其方法雖然簡單，但是以LCD之應 用為例，當灰階（gray level)數增加時，上述架構的面積也f 會隨著急劇增加，例如256階R_DAC之面積約為64，時 的5.3倍。因此在LCD應用中，DAc即佔去了數位式資料 驅動器（data driver)絕大部份之面積。 經濟部中央標準局員工消費合作社印裝 如第2圖所示為2-divided C-DAC之電路架構，為另 一具有Gamma校正電路之DAC，其雖較R-DAC之面積為 小’但是其所用之電容器數目頗多，因電容器所佔之面積 不小’故其仍有改善之空間。 為改善上述問題，本發明之目的為提出一種電路架構 簡單’面積更小之具有Gamma校正電路數位類比轉換器， 其面積均小於傳統之R-DAC和2-divided C-DAC所佔用之 本紙張尺度通《 T u U家標準（CNS )从麟 (210X297公釐 經濟部中央標準局員工消費合作社印裝 A7 ------- B7 五、發明説明（2 ) ~~ 面積，故可以簡化電路設計戒本。 本發明之另-目的為提供—種具有Gamma校正電路 數位類比轉換器，使用者可藉由調整端點電壓，而自行定 義Gamma校正轉換曲線之形狀，而增加其應用性。 為達到上述目的，依據本發明之具有仏_校正之數 位類比轉換器，其接收N位元數位資料輸入而輸出相對應 之類比電壓’其包括：複數端點電壓源；一端點電壓選擇 裝置’其輸入端分別耦接於上述端點電壓；一第一解碼器， 將上述N位元數位資料的最高k位元加以解爲，藉以梭制 ’述端點龟壓選擇裝置’而由上述端點電壓中得出相對 應、電壓大小值相鄰之第一電壓和第二電壓，盆中上返弟 -電壓之電壓值小於上述第二電壓之電壓值；一第二解碼 器’其接收m位元之資料組而將其解碼輸出，其中上述每 一 m位元資料組’係由上述1^位域位資料的最低财位 疋區分成資料組而得’並由位於低位元之m位元資 料組往位於高位元之m位元資料組依序加以解碼，其中u」 表不大於或等於X之最小整數；一分壓選擇裝置，將上述 第一和第二電壓之電壓差值加以均等分壓而再得出2m_2 個節點電壓，其電壓大小值介於上述第一電壓和第二電壓 之間’再依據上述第二解碼器輸出之控制，而由上述第一 電壓、第二電壓和上述節點電壓中選擇出每一上述爪位元 資料組其相對應之電壓加以輸出;—第—開關、第二開關、 第三開關、第四開關依序串連’而耗接於上述分壓選擇裝 置之輸出和-接地參考點之間；一第六開關、第五開關依 4 本紙張尺度適用中國國家標準（CNS) Α4規格（2]Gx297公着） (請先閱讀背面之注意事項再填寫本頁) 策-A7 B7 V. Description of the Invention (l) The present invention relates to digital analog converters, and particularly relates to digital analog converters with gamma correction. t (Please read the notes on the back before filling this page) The output voltage of a traditional digital-to-analog converter (DAC) is required to have a linear relationship with the input digital value as much as possible. However, In specific applications, the value of the DAC's output voltage must be non-green. For example, in the application of liquid crystal display (LCD), the relationship between liquid crystal brightness and voltage is not a linear relationship, so a correction circuit must be used for compensation. This type of correction circuit is generally called a Gamma correction circuit. -° Please refer to the R-DAC architecture shown in Figure 1. It is a traditional DAC with a gamma correction circuit. It mainly uses the ROM decoder i to decode the digital data of D0 ~ D5, and then the reference voltage generator 2 Select the corresponding resistor divider output. Although the method is simple, taking the application of LCD as an example, when the number of gray levels increases, the area of the above-mentioned architecture will also increase sharply. For example, the area of 256-level R_DAC is about 64, which is 5.3 times. . Therefore, in LCD applications, DAc occupies most of the area of the digital data driver. The consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed the circuit structure of the 2-divided C-DAC as shown in Figure 2. It is another DAC with a gamma correction circuit. Although it has a smaller area than the R-DAC, its The number of capacitors used is quite large, and the area occupied by the capacitors is not small, so there is still room for improvement. In order to improve the above problems, the purpose of the present invention is to propose a digital analog converter with a simple circuit structure and a smaller area and a Gamma correction circuit, the area of which is smaller than that of traditional R-DAC and 2-divided C-DAC. Standards "Tu U Home Standards (CNS) Conglin (210X297 mm printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ------- B7 V. Description of the invention (2) ~ ~ area, so it can be simplified Circuit design or copybook. Another object of the present invention is to provide a digital analog converter with a gamma correction circuit. Users can define the shape of the gamma correction conversion curve by adjusting the terminal voltage to increase its applicability. In order to achieve the above object, the digital analog converter with 仏 _correction according to the present invention receives N-bit digital data input and outputs a corresponding analog voltage 'which includes: a complex terminal voltage source; a terminal voltage selection device' Its input terminals are respectively coupled to the above-mentioned endpoint voltages; a first decoder resolves the highest k-bits of the above N-bit digital data into the above-mentioned endpoint pressure selection Device 'and the corresponding first and second voltages are obtained from the terminal voltages, and the voltages are adjacent to each other. The voltage of the upper voltage in the basin is lower than the voltage of the second voltage; a second The decoder 'receives m-bit data sets and decodes them, wherein each of the m-bit data sets' is obtained by dividing the lowest financial level of the 1-bit field data into data sets, and is obtained by The m-bit data set located at the lower bit is decoded sequentially to the m-bit data set located at the higher bit, where u ″ is not the smallest integer greater than or equal to X; a partial pressure selection device converts the first and second above The voltage difference between the voltages is divided into two equal voltages to obtain 2m_2 node voltages. The voltage value is between the first voltage and the second voltage, and then according to the control of the output of the second decoder. A voltage, a second voltage, and the above-mentioned node voltage are selected to output the corresponding voltage of each of the claw bit data sets;-the first switch, the second switch, the third switch, and the fourth switch are connected in series. And consumes the above partial pressure Between the output of the device and the ground reference point; a sixth switch and a fifth switch apply the Chinese National Standard (CNS) A4 specification (2) Gx297 according to 4 paper standards (please read the precautions on the back first) (Fill in this page)

、1T A7 經濟部中央標準局貝工消費合作社印裝 五、發明説明（3) =門而Τί，擇裝置之輸出和上述接地參 =:二 輕接於上述第-開關及第二開關 連接節點和上述接地參相之間； _於上述第三開關及第二開關之連接節點，另谷 於上述第六開關及第五開關之連接節點，·一第三電容器與 四：關並聯；以及一第四電容器耦接於上述分壓選 (置之輸出端和上述接地參考點之m，藉由控制 沭菌一是第六開關之睹床莲诵㈣，錄上述第一 三電容器進行電荷重分配之動作，而將每—上述爪位元資 料組其相對應之電壓合成一類比輸出電壓，而由上述第二 電容器與上述第二、第三開關之連接節點輸出。 另外，上述第一至第六開關之時序導通動作如下步 驟：⑷關閉上述第一、第六開關，將上述第三至第五開關 導通，藉以將上述第一至第三電容器之電位放電至與上述 接地^考點相同之位準，此時上述第二解碼器也對上述m 位凡資料組之-加以解碼輸出，使得上述分壓選擇裂置輸 出其相對應之電壓；⑻將上述第一、四、五開關導通，關 閉上述第一、二、六開關，此時上述分壓選擇裝置輸出之 電壓對上述第一電容器充電；（c)關閉上述第一、四、六開 關，使上述第二、三、五開關導通，而儲存於上述第一電 谷器之電荷將會和上述第二、第三電容器進行電荷重分 配，此時上述第二解碼器也對下一m元資料組加以解 碼輪出，使得上述分壓選擇裝置輸出其相對應之電壓；（d) 重覆上述步驟b和C，直到上述第二解碼器將最後一組（最， 1T A7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. 5. Description of the invention (3) = door and til, select the output of the device and the above ground parameters =: Second lightly connected to the above-mentioned switch-and the second switch connection node And the above ground reference phase; _ at the connection node of the third switch and the second switch, and at the connection node of the sixth switch and the fifth switch, a third capacitor is connected in parallel with four: off; and The fourth capacitor is coupled to the above-mentioned divided voltage selection (the output terminal and the ground reference point m), and the first and third capacitors are recorded for charge re-distribution by controlling the first and sixth switches of the lotus root. In the operation, the corresponding voltage of each of the above-mentioned claw bit data sets is combined into an analog output voltage, and is output by the connection node of the second capacitor and the second and third switches. In addition, the first to the first The sequence of the six switches is as follows: ⑷ Turn off the first and sixth switches and turn on the third to fifth switches, so as to discharge the potentials of the first to third capacitors to the ground. At the same level, the above-mentioned second decoder also decodes the output of the m-bit ordinary data set at this time, so that the above-mentioned partial voltage selection splits and outputs its corresponding voltage; ⑻ switches the above-mentioned first, fourth, and fifth switches Turn on and close the first, second, and sixth switches. At this time, the voltage output by the voltage division selection device charges the first capacitor. (C) Turn off the first, fourth, and sixth switches to enable the second, third, and fifth switches. The switch is turned on, and the charge stored in the first electric valley device will be redistributed with the second and third capacitors. At this time, the second decoder also decodes the next m-ary data set to rotate out, so that The above-mentioned voltage-dividing selection device outputs its corresponding voltage; (d) repeating steps b and C above, until the second decoder converts the last group (most

I I 閲 讀 背 ιδ 之 注 意 事 項 再 填 寫 本 頁 X- 訂I I read the notes and notes on the back and fill in this page.

經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（4 ) 高位元）m位元資料組完成解碼，而使得上述分壓選擇裝置 輸出其相對應之電壓；以及（e)關閉上述第一、二、三、五 開關，將上述第四、六開關導通，位於最高位元之上述m 位元資料組其相對應之電壓將對上述第四電容器充電，最 後上述第一電谷器之電壓值加上上述第四電容器之電壓值 即為上述數位類比轉換器之輸出電壓值。 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉出一較佳之實施例，並配合所附圖式，做詳細說 明如下。 圖式之簡單說明： 第1圖係顯示傳統r_DAC之線路架構圖。 第2圖係顯示2-divided C-DAC之線路架構圖。 第3圖係顯示本發明一較佳實施例之線路架構圖。 第4圖係顯示256灰階DAC之Gamma校正轉換曲線。 符號說明： 1〜ROM解碼器，2〜參考電壓產生器，D〇 D5〜數 位資料，V〇_V8〜參考電壓源(端點電壓源），C1_C4〜電 容器，3〇〜端點電壓選擇裝置，31〜第一解碼器，32〜第二 解碼器，33〜分壓選擇裝置，34〜選擇裝置，35〜暫存器， 36〜位移暫存器，37〜輸出緩衝器，以·％〜開關，％〜第 一電壓，VT〜第二電壓，Ν〇·Ν8〜曲線端點。 實施例： 第3圖係顯示本發明一較佳實施例之線路架構圖。本 實施以256階（2Ν階）之數位癫比棘換器為例，其輸入之數 6 本紙張尺度顏中關紐：^NS)機格（2丨以297公楚了Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (4) High bit) The m-bit data set has been decoded so that the above-mentioned partial voltage selection device outputs its corresponding voltage; and (e) the above is turned off The first, second, third, and fifth switches turn on the fourth and sixth switches, and the corresponding voltage of the m-bit data set at the highest bit will charge the fourth capacitor, and finally the first electric valley device The voltage value plus the voltage value of the fourth capacitor is the output voltage value of the digital analog converter. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings. Brief description of the diagram: Figure 1 is a circuit architecture diagram showing a conventional r_DAC. Figure 2 shows the circuit architecture of the 2-divided C-DAC. FIG. 3 is a circuit architecture diagram showing a preferred embodiment of the present invention. Figure 4 shows the Gamma-corrected conversion curve for a 256-level DAC. Symbol description: 1 ~ ROM decoder, 2 ~ reference voltage generator, D〇D5 ~ digital data, V〇_V8 ~ reference voltage source (end point voltage source), C1_C4 ~ capacitor, 3 end point selection device , 31 ~ first decoder, 32 ~ second decoder, 33 ~ divide voltage selection device, 34 ~ selection device, 35 ~ register, 36 ~ shift register, 37 ~ output buffer, %% ~ Switch,% ~ first voltage, VT ~ second voltage, NO · N8 ~ end point of curve. Embodiment: FIG. 3 is a circuit architecture diagram showing a preferred embodiment of the present invention. In this implementation, a 256-level (2N-level) digital epilepsy converter is used as an example. The number of inputs is 6 paper scales. Yanzhongguan: ^ NS).

經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（5 ) 位資料為8位元(N位元）資料[士 d6 d5 d4 d3 d2山d0]。 請參照第3圖’本發明之具有Gamma校正之數位類比 轉換器，包括下诚之各部份。 9個（2K+1個）端點電壓源v〇〜v8(V2k)，用以決定 Gamma校正曲線之形狀，其中νγνγ,./νδ。 一端點電壓選擇裝置30,其輸入端分別耦接於上述端 點電壓源V〇〜V8。 一第一解碼器31，將上述8位元(N位元）數位資料的 最高3位元（k位元）即[d7d6d5]加以解碼，藉以控制上述端 點電壓選擇裝置30，而由上述端點電壓v〇〜乂8中得出相 對應、電壓大小值相鄰之第一電壓VB和第二電壓VT，其 中上述第一電壓VB之電壓值小於上述第二電壓Vt之電壓 值。例如，若[Α & ds]為[〇 1 1]則選出端點電壓％和％ 作為第一電壓VB和第二電壓VT，若[d7d6d5]為[1 1 1]則選 出端點電壓V7*V8作為第一電壓VB和第二電壓VT〇 第一解碼器32 ’其接收2位元（m位元）之資料組而 將其解碼輸出。其中上述每個資料組，係將輸入之8位元 (N位元）數位資料中，其最低位元的5位元(N_k位元）資料 [Α 1 4山d〇]分割成每組2位元(m位元）之資料組，[d4 d3] 、[d2山]、和[d〇 0]，分割方式是由高位元往低位元依 序分割，最後不足2位元（m位元）之資料組則予以補 上 ”〇”，如[dG 0]。 一分壓選擇裝置33，將上述第一電壓VB和第二電壓 VT之電壓差值加以均等分壓而再得出2個（2m_2個）節點電 本紙張尺度適用中國國家標準（CNS >以規格（21Qx 297公楚） nn ml ^^^^1 —ml mu —^n an^i *1^ —^ϋ* In n^— 一OJ (請先閲讀背面之注意事項再填寫本頁} A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（6 ) H電撼壓广小值介於上述第—電磨Vb和第二電… 依據上述第二解碼器32輸出之控制，而由上述第— 擇二::和上述節點電壓v…、及第二電壓ντ中選 出―:相對應之電壓輸出。其中上述分壓選擇裝置％，包 •接於上述上述第由一3: f:1電::比例電阻R串連而成， 2m 矛第一電壓輪入之間’藉以得出上述 固：點電壓，·以及，一選擇裝置34，輸入端輕接上述 電壓和上述節點電壓Vbi、Vb2、及Vt，藉由上 ^ -解碼盗32解碼上述2位元(m位元）資料組的輸出控 制’而選擇相對應的電㈣為輸出，即2位元f料組為、 1〇 11時’上述選擇裝置34對應之輸出電壓分別為 Vb、VB1、γΒ2、及 Vt。 第-開關SI、第二開關S2、第三開關S3、第四開 關S4依序串連，而耗接於上述分壓選擇裝i33之輸出和 一接地參考點之間。 -第六開關S6、第五開M S5依序串連，而耦接於上 述分愿選擇裝置33之輸出和上述接地參考點之間。 第一電容器ci耦接於上述第一開關S1及第二開關 S2之連接節點和上述接地參考點之間。 一第二電容器C2之一端耦接於上述第三開關S3及第 二開關S2之連接節點，另-端耦接於上述第六開關S6及 第五開關S5之連接節點。 一第二電容器C3與上述第四開關s4並聯；以及，一 第四電容器C4耦接於上述分壓選擇裝置33之輸出端和上 本紙張尺度適用中國國豕標準（€呢）八4規格（210乂 297公楚)Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China. A7 B7 V. Description of invention (5) The data is 8-bit (N-bit) data [Shi d6 d5 d4 d3 d2 mountain d0]. Please refer to Fig. 3 'The digital analog converter with gamma correction of the present invention includes various parts of the sincerity. Nine (2K + 1) endpoint voltage sources v0 ~ v8 (V2k) are used to determine the shape of the gamma correction curve, where νγνγ, ./νδ. An input terminal of the terminal voltage selection device 30 is coupled to the terminal voltage sources V0 ~ V8, respectively. A first decoder 31 decodes the highest 3 bits (k bits) of the 8-bit (N-bit) digital data, that is, [d7d6d5], so as to control the terminal voltage selection device 30, and the terminal The corresponding first voltages VB and second voltages VT are obtained from the point voltages v0 to 相邻 8, where the voltage value of the first voltage VB is smaller than the voltage value of the second voltage Vt. For example, if [Α & ds] is [〇1 1], the terminal voltage% and% are selected as the first voltage VB and the second voltage VT, and if [d7d6d5] is [1 1 1], the terminal voltage V7 is selected. * V8 is the first voltage VB and the second voltage VT. The first decoder 32 ′ receives the data set of 2 bits (m bits) and decodes it to output. For each of the above data groups, the lowest 5 bits (N_k bits) of the input 8-bit (N-bit) digital data are divided into 2 for each group. Data set of bit (m bit), [d4 d3], [d2 mountain], and [d〇0], the division method is to sequentially divide from high bit to low bit, and finally less than 2 bits (m bit ) The data group is supplemented with "〇", such as [dG 0]. A partial voltage selection device 33 divides the voltage difference between the first voltage VB and the second voltage VT into equal voltages to obtain 2 (2m_2) nodes. The paper size of the paper applies Chinese national standards (CNS > Specifications (21Qx 297 Gongchu) nn ml ^^^^ 1 —ml mu — ^ n an ^ i * 1 ^ — ^ ϋ * In n ^ — One OJ (Please read the notes on the back before filling this page} A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) The value of the H electric shock is between the first and the second electric mill Vb and the second electric ... According to the control of the output of the second decoder 32 above, and From the above-mentioned second option :: and the node voltage v ..., and the second voltage ντ, the corresponding voltage output is selected. Among them, the above-mentioned partial voltage selection device% includes: : 1 Electricity :: Proportional resistance R is connected in series, and the 2m spear first voltage is turned in between to obtain the above solid: point voltage, and a selection device 34, the input terminal is lightly connected to the above voltage and the above node voltage Vbi, Vb2, and Vt are controlled by the output control of the above-mentioned decoding bit 32 to decode the above 2-bit (m-bit) data set. Select the corresponding battery as the output, that is, when the 2-bit f material group is 1011, the output voltages corresponding to the above-mentioned selection device 34 are Vb, VB1, γB2, and Vt. The first switch SI and the second switch S2, the third switch S3, and the fourth switch S4 are connected in series, and are consumed between the output of the above-mentioned voltage-dividing selection device i33 and a ground reference point.-The sixth switch S6 and the fifth switch M S5 are connected in series. The first capacitor ci is coupled between the connection node of the first switch S1 and the second switch S2 and the ground reference point. One terminal of a second capacitor C2 is coupled to the connection node of the third switch S3 and the second switch S2, and the other terminal is coupled to the connection node of the sixth switch S6 and the fifth switch S5. A second capacitor C3 and The fourth switch s4 is connected in parallel; and a fourth capacitor C4 is coupled to the output end of the voltage-dividing selection device 33 and the size of the previous paper. The Chinese national standard (€?) 8 4 specifications (210 乂 297 cm) are applicable.

經濟部中央標準局員工消費合作社印掣 A7 B7 五、發明説明（7 ) 述接地參考點之間。 上述第一電容器C1、第二電容器C2、第三電容器C3 其電容器之比值為1 : 1 : 2(亦即1 : i : 2m_2)。 以上為本發明實施例之概要架構，藉由一時序控制電 路（未圖示）控制上述第一至第六開關S1〜S6之時序導通動 作，使得上述第一至第四電容器C1〜C4進行電荷重分配之 動作，而將每一上述2位元(m位元）資料組其相對應之電 壓合成一類比輸出電壓，而由上述第二電容器C2與上述 第二、第三開關S2、S3之連接節點輸出。上述第一趸第 六開關可利用例如MOS電晶體加以實現，其閘極接收上述 時序控制電路之控制信號，而完成開關之動作。 假設輸入之8位元數位資料⑷4小a a山士]為u 0000111]。請參照第3圖，則暫存器中高位元資料[d7d6 d5]為Π 00]，在經上第一解碼@ 31解碼後，據以控制上述 端點電壓選擇裝置30而輸出端點電壓％、％分別作為上 述第一電壓VB和第二電壓ντ。 μ 接著經由時序控制電路（未圖示）之控制，由位移暫 器36依序輸出[d〇 0]、[d2山]、和⑷屯]，供上述第: 器解碼。在得出上述第一電壓％和第二電 、 類比電壓之轉換，將參照如下表一所示之步驟進行，^ 一中’，i”表示開關導通，，，〇，，表示開關關閉。 牧衣 良紙張尺度適用中國國家標準（CNS) M規格（2丨GO7公楚 n m n - I I» I I- n I .^-— —— —^ — I __ 丁 1 ,"、-'° (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標隼局員工消費合作社印裝 五、發明説明（8 ) 表一： 步驟 S1 S2 S3 S4 S5 S6 解碼 ---- id〇 〇1 1 0 1 1 1 1 0 2 1 0 0 1 1 0 3 0 1 1 0 1 0 fd7 dil 4 1 0 0 1 1 0 5 0 1 1 0 1 0 \dd d.l 6 0 0 0 1 0 1 步驟1 關閉上述第一、第六開關SI、S6，將上述第二至第 五開關S2〜S5導通，藉以將上述第一至第三電容器ci〜c3 之電位放電至與上述接地參考點相同之位準。此時上述第 二解碼器32也對上述[d〇0]=[l 〇]資料組加以解碼輸出/使 得上述分壓選擇裝置34輸出其相對應之電壓Vb2。 步驟2 將上述第一、四、五開關（SI、S4、S5)導通，關閉 上述第二、三、六開關（S2、S3、S6)，此時上述分壓選 擇裝置34輸出之電壓VB2對上述第一電容器Cl充電，所 以第一電容器C1之電壓為VB2。 步驟3 關閉上述第一、四、六開關（SI、S4、S6)，使上述 第二、三、五開關（S2、S3、S5)導通，而儲存於上述第 一電容器C1之電荷將會和上述第二、第三電容器（c2、 本紙張尺度適) Α4“Τ^χ297公楚） nn ^^^1 ml nn n —^n J ml tn^— m m ^^^1 一OJ (請先閲讀背面之注意事項再填寫本頁) ΑΊ ΑΊ 經濟部中央標準局貝工消費合作社印裝 關閉上述第 —— 五、發明説明（9) C3)進行電荷重分配，因為ci:C2:C3 = l:l:2 ，所以第二電 容器 C2 之電壓 V_ = VB2 X C1/(C1+C2+C3) = VB2/4。 此時上述第二解碼器32也對下一資料組[d2dl] = [1 加以解碼輸出’使得上述分壓選擇裝置34輸出其相對應之 電壓VT。 步驟4 將上述第一、四、五開關（S1、S4、S5)導通，關閉 上述第二、三、六開關（S2、S3、S6)，此時上述分壓選 擇裝置34輸出之電壓Vt對上述第一電容器C1充電，所以 第一電容器C1之電壓為Vt。 步驟5 關閉上述第一、四、六開關（SI、S4、S6)，使上述 第—、二、五開關（S2、S3、S5)導通，而儲存於上述第 電谷器C1之電何將會和上述第二、第三電容器（c。、 C3)進行電荷重分配，所以第二電容器C2此時之電壓為 Vsum=(Cl X VT+C2 X VB2/4)/(Cl+C2-hC3) = VT/4+vB2/16 c 此時上述第二解碼器32也對下一資料組[(14山]=[〇 〇] 加以解碼輸出，使得上述分壓選擇裝置34輸出盆相 電壓VB。 八 步驟6 五開關（SI、S2、S3、S5)， 將上述第四、六„(S4、S6)導通，最高位Μ料組資料 組[d4 d3]其相對應之電壓％將對上述第四電容$ a充電 至VB電位’所以輸出端點γ之電壓Vy將會被推升至 11 ---1 - - - II - I I— I- . 1^1 I —| - -i n -in n^i (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（10 )Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (7) Between the ground reference points. The ratio of the capacitors of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is 1: 1: 2 (that is, 1: i: 2m_2). The above is a schematic structure of an embodiment of the present invention. A timing control circuit (not shown) controls the timing conduction operations of the first to sixth switches S1 to S6, so that the first to fourth capacitors C1 to C4 are electrically powered. Load distribution operation, and the corresponding voltage of each of the above 2-bit (m-bit) data sets is combined into an analog output voltage, and the second capacitor C2 and the second and third switches S2 and S3 Connect the node output. The above-mentioned first to sixth switches can be implemented by, for example, MOS transistors, and the gates thereof receive the control signals of the timing control circuit to complete the switching operation. Assume that the input 8-bit digital data (4 small a a mountain)] is u 0000111]. Please refer to Figure 3. The high-order data in the register [d7d6 d5] is Π 00]. After the first decoding @ 31 is decoded, the above-mentioned endpoint voltage selection device 30 is controlled to output the endpoint voltage%. And% are used as the first voltage VB and the second voltage ντ, respectively. μ is then controlled by a timing control circuit (not shown), and the displacement register 36 sequentially outputs [d0 0], [d2 mountain], and ⑷tun] for the above-mentioned decoder decoding. After the conversion between the first voltage% and the second electrical and analog voltages is obtained, refer to the steps shown in Table 1 below. ^ 'I' means that the switch is on, and 0, means that the switch is off. Yiliang's paper standards are in accordance with Chinese National Standard (CNS) M specifications (2 丨 GO7 nm nm-II »I I- n I. ^ -— —— — ^ — I __ 丁 1, ",-'° (Please Read the notes on the back before filling this page) A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (8) Table 1: Step S1 S2 S3 S4 S5 S6 Decoding ---- id〇〇1 1 0 1 1 1 1 0 2 1 0 0 1 1 0 3 0 1 1 0 1 0 fd7 dil 4 1 0 0 1 1 0 5 0 1 1 0 1 0 \ dd dl 6 0 0 0 1 0 1 Step 1 Close The first and sixth switches SI and S6 turn on the second to fifth switches S2 to S5 to discharge the potentials of the first to third capacitors ci to c3 to the same level as the ground reference point. At this time, the second decoder 32 also decodes the data set [d00] = [l0] and outputs / enables the voltage-dividing selection device 34 to output the corresponding voltage Vb2. Step 2 Turn on the first, fourth, and fifth switches (SI, S4, and S5), and turn off the second, third, and sixth switches (S2, S3, and S6). At this time, the voltage VB2 output by the voltage division selection device 34 is The first capacitor C1 is charged, so the voltage of the first capacitor C1 is VB2. Step 3 Turn off the first, fourth, and sixth switches (SI, S4, S6), and enable the second, third, and fifth switches (S2, S3, S5) is turned on, and the charge stored in the above-mentioned first capacitor C1 will be the same as the above-mentioned second and third capacitors (c2, the size of this paper is suitable) Α4 "Τ ^ χ297 公 楚) nn ^^^ 1 ml nn n — ^ n J ml tn ^ — mm ^^^ 1 1 OJ (please read the notes on the back before filling this page) ΑΊ ΑΊ Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. ) C3) charge redistribution, because ci: C2: C3 = l: l: 2, so the voltage of the second capacitor C2 V_ = VB2 X C1 / (C1 + C2 + C3) = VB2 / 4. At this time, the second decoder 32 also decodes and outputs the next data group [d2dl] = [1 ', so that the voltage division selecting device 34 outputs its corresponding voltage VT. Step 4 Turn on the first, fourth, and fifth switches (S1, S4, and S5), and turn off the second, third, and sixth switches (S2, S3, and S6). At this time, the voltage Vt output by the voltage division selection device 34 is The first capacitor C1 is charged, so the voltage of the first capacitor C1 is Vt. Step 5 Turn off the first, fourth, and sixth switches (SI, S4, and S6), and turn on the first, second, and fifth switches (S2, S3, and S5), and store the electricity stored in the first valleyr C1. Will perform charge redistribution with the second and third capacitors (c., C3), so the voltage of the second capacitor C2 at this time is Vsum = (Cl X VT + C2 X VB2 / 4) / (Cl + C2-hC3 ) = VT / 4 + vB2 / 16 c At this time, the second decoder 32 also decodes and outputs the next data group [(14 山] = [〇〇], so that the above-mentioned partial voltage selection device 34 outputs the basin phase voltage VB. Eight steps 6 Five switches (SI, S2, S3, S5) to turn on the fourth and sixth (S4, S6) above, the corresponding voltage% of the highest M material group data set [d4 d3] will be the above The fourth capacitor $ a is charged to the potential of VB ', so the voltage Vy of the output terminal γ will be pushed up to 11 --- 1---II-II- I-. 1 ^ 1 I — |--in -in n ^ i (Please read the notes on the back before filling out this page) A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (10)

Vsum+VB=VB+Vi74+VB2/16。 \ 最後Y端點電壓值VY經一輸出缓衝器37輸出，即為 上述數位類比轉換器之類比電壓輸出。 考量在256灰階下，8段Gamma校正曲線，在電路實 作上，應用本發明之C-DAC電路面積與傳統R-DAC及2-divided C-DAC之比較如表二所示。 表二： ’ 電阻器數目 電容器數目 MOS 數 g 電源線數目 R-DAC 256 4096 256 2-divided 16 400 9 本發明 4 5 300 9 由上表可知本發明電路所使用之元件數目最少，又本 發明電路中所使用之電阻器佔用之面積比一個電容器所用 之面積為小，所以可以有效改進2-divided C-DAC之缺點。 請參照第4圖，其顯示256灰階DAC之轉換曲線。第 4圖係為8段階梯狀之Gamma校正曲線，曲線之各端點 N〇〜N8主要是對應於上述端點電壓V〇〜V8之選擇。若調整 上述端點電壓V〇〜V8為等差級數，則Gamma校正曲線將可 成為傳統DAC之線性轉換曲線。所以本發明之DAC更可 提供由使者自行定義其所需之Gamma校正曲線之功能，進 而提高應用之彈性。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟悉本項技藝者，在不脫離本發明之精神和 範圍内，當可應用本發明之特性，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準 12 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -ie 丁Vsum + VB = VB + Vi74 + VB2 / 16. \ Finally, the Y terminal voltage value VY is output through an output buffer 37, which is the analog voltage output of the digital analog converter described above. Considering the 8-segment Gamma correction curve under 256 gray levels, the circuit implementation of the present invention is compared with the conventional R-DAC and 2-divided C-DAC. Table 2: 'Number of resistors, number of capacitors, number of MOSs, number of power lines R-DAC 256 4096 256 2-divided 16 400 9 The present invention 4 5 300 9 As can be seen from the above table, the circuit of the present invention has the least number of components and the present invention The area occupied by the resistor used in the circuit is smaller than that used by a capacitor, so the disadvantages of the 2-divided C-DAC can be effectively improved. Please refer to Figure 4, which shows the conversion curve of a 256 gray-scale DAC. Figure 4 is an eight-step stepped gamma correction curve. The end points of the curve No. to N8 are mainly corresponding to the selection of the above-mentioned end point voltages V0 to V8. If the above-mentioned endpoint voltages V0 ~ V8 are adjusted to equal difference stages, the gamma correction curve can become a linear conversion curve of a conventional DAC. Therefore, the DAC of the present invention can further provide the function of allowing the messenger to define the gamma correction curve required by himself, thereby improving the flexibility of the application. Although the present invention is disclosed as above with the preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art can apply the characteristics of the present invention without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. 12 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page) -ie 丁

Claims (1)

申5青專利範圍 經濟部中央標準局員工消費合作社印裝 選擇接一㈣ 節二：:=:述第，及*二_之連接 之、查：：二電容器之一端耦接於上述第三開關及第二開關 :即點’另一端耦接於上述第六開關及第五開關之連 接即點； —第三電容器與上述第四開關並聯；以及 - h電容㈣接於上述分壓選擇裝置之輸出端和上 述接地參考點之間； 其中’藉由㈣上述第—至第六開關之時序導通動 W得上述第-至第四電容器進行電荷重分配之動作， 而將每上述m位疋資料組其相對應之電壓合成一類比輸 出電壓’而由上述第二電容器與上述第二、第三開關之連 接節點輸出。 2.如申請專利範圍第i項所述之數位類比轉換器，其 中上述第—至第六開關之時序導通動作如下步驟： 、a.關閉上述第一、第六開關’將上述第二至第五開關 導通’藉以將上述第-至第三電容器之電位放電至與上述 接地參考點相同之位準，此時上述第二解碼器也對上述m 位元資料組中之最低位元組加以解碼輸出，使得上述分壓 選擇裝置輸出其相對應之電壓； b.將上述第一、四、五開關導通，關閉上述第二、三、 六開關，此時上述分壓選擇裝置輸串之電壓對上述第一電 本紙張尺度適用中國國家標準（CNS ) A4現格（210 X 297公董） ----1---f :裝------訂 (請先閲讀背面之注意事項再填寫本頁)The scope of application for the patent scope of the 5th Patent of the Central People ’s Bureau of the Ministry of Economic Affairs of the Consumers ’Cooperatives is to choose one of them. Section 2: Connections of the two capacitors are connected to the third switch. And the second switch: the other end of the point is coupled to the connection between the sixth switch and the fifth switch; the third capacitor is connected in parallel with the fourth switch; and the h capacitor is connected to the voltage dividing device. Between the output terminal and the above-mentioned ground reference point; where 'the first-to-fourth capacitors are used to perform the redistribution of charge through the timing operation of the first-sixth to sixth switches, and each of the m-bits of The corresponding voltages are combined into an analog output voltage and output by the connection node of the second capacitor and the second and third switches. 2. The digital analog converter as described in item i of the scope of patent application, wherein the sequential conducting actions of the first to sixth switches are as follows: a. Turn off the first and sixth switches' to switch the second to first Five switches are turned on 'to discharge the potentials of the first to third capacitors to the same level as the ground reference point. At this time, the second decoder also decodes the lowest byte in the m-bit data set. Output, so that the voltage-dividing selection device outputs its corresponding voltage; b. Turn on the first, fourth, and fifth switches and turn off the second, third, and sixth switches; The paper size of the first paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 public directors) ---- 1 --- f: installed ------ order (please read the precautions on the back first) (Fill in this page again)