經濟部中央搮隼局員工消費合作社印裝 A7 B7__, 五、發明説明（I ) 發明領域： 本發明係關於一種積體電路中製作互補式金氧半導體 (CMOS)雙井(Twin Wells)結構的方法，特別是關於一種僅 利用一層光罩，進行CMOS中p井(p well)與η井(n well) 之離子佈植（Ion Implantation)的方法。 發明背景： 雙井CMOS是一種結合p井與η井的綜合性設計。它使 得PM0S與NM0S都可以在經適當微摻雜的井(well)區內製 作，因此並不需要像單井設計一般，讓其中一種電晶體建 築在高摻雜的底材上，所以CMOS裡的電晶體將在最適當條 件下操作。當半導體的積集度使元件設計小於1微米之後， 因爲通道長度縮短，通道內的電場強度增加，PM0S內的電 洞與NM0S內的電子漂移率(Mobility)都將趨於飽和，使得 P通道與η通道的電流相當。因爲PM0S與NM0S此時的執行 性能相近，因此當元件小於1微米之後，雙井CMOS將成爲 一種很合適的CMOS選擇，尤其將雙井CMOS結構與渠溝隔 離一併使用，將使PM0S與NM0S間的隔距(Spacing)，大大 的縮短，以增加積集度（Integration)。 傳統雙井CMOS的製程是在矽底材上，以二次以上的光 罩(Photo Mask)步驟，以光阻爲護罩，分別先後進行p井 區及η井區的離子佈植（l〇n implantation)，由於所須的 光阻較厚，會產生曝光時焦距深度(Depth of Focus; D0F) 的問題’亦會因爲多次光罩而造成雙井重疊的問題；另外， 因爲多次光罩步驟，使光阻剝落問題更加嚴重，而影響離 ---------装—τ-------訂------線 (請先閱護背面_之注意事項再蟥寫本頁) ^紙張尺度適用肀國國家標準（CNS >八4規格（210X 297公釐） A7 B7 經濟部中央樣準局員工消費合作社印装 五、發明説明（> ) 子佈植製程，造成產品良率降低。本發明即是針對習知技 藝之缺點，改良CMOS雙井結構製程，以期降低生產成本並 提昇良率。 發明之概述： 本發明的主要目的是提供一種僅以一次光罩，進行 CMOS雙井結構之離子佈植的方法，可節省光罩，避免習知 技藝中因多次光罩而造成雙井重疊的問題。 本發明的另一目的是提供一種僅以一次光罩，進行 CMOS雙井結構之離子佈植的方法，可使所用的光阻厚度減 小’可改善曝光時的焦距深度(Depth of Focus; D0F)。 本發明的再一目的是提供一種僅以一次光罩，進行 CMOS雙井結構之離子佈植的方法，可減少光阻的使用，並 避免因光阻剝落問題而影響離子佈植製程。 本發明是以下列製程步驟來達到上述之各項目的：首 先’於半導體基板上形成一層墊氧化層及一層氮化矽層； 接著’利用光罩，在氮化矽層上定義出p井的光阻圖案， 並以電漿蝕刻法去除未被光阻覆蓋的氮化矽層，以氮化矽 爲護罩，將離子植入基板形成p井；再接著，形成一層氧 化層，並進行CMP表面平坦化處理；最後，以濕蝕刻移除 氮化矽層後，以氧化層爲護罩，將離子植入基板形成η井， 再移除氧化層，則利用本發明所形成之CMOS雙井結構於焉 完成。 圖式簡要說明： 圖一是本發明實施例中，半導體基板形成墊氧化層、 ___— (請先閱I背面之注意事項再填寫本頁) 本紙張尺度適用中國國豕標準（CNS ) A4規格（210X297公釐） A7 A7 2-墊氧化層 4-光阻 10- Ρ井區 100- Ρ井離子佈植 五、發明説明（j ) 氮化矽層及光阻圖案之剖面示意圖。 圖二是本發明實施例中，乾蝕刻氮化矽層後，以離子植 入形成P井之剖面示意圖。 圖三是本發明實施例中，形成氧化層之剖面示意圖。 圖四是本發明實施例中，進行CMP後之剖面示意圖。 圖五是本發明實施例中，濕蝕刻氮化矽層後，以離子植 入形成η井之剖面示意圖。 圖號說明： 1-半導體基板 3-氮化矽層 5-氧化層 20- η井區 200- η井離子佈植 發明詳細說明： 本發明揭露一種積體電路中形成CMOS雙井結構的方 法，僅以一次光罩，進行CMOS雙井結構之離子佈植。首先， 請參考圖一，提供一半導體基板1，在所述半導體基板i 上陸續形成一層墊氧化(Pad Oxide)層2及一層氮化矽 (Si«層3，其中所述墊氧化層2係爲二氧化矽(Si〇2)，其 厚度係介於2G0埃到400埃之間，而氮化矽層3的厚度係 介於4000埃到6000埃之間。接著以一個光罩(Photo Mask) ’在所述氮化矽層3上定義出ρ井位置的光阻圖案4。 接著，請參考圖二，利用非均向性電槳蝕刻法(Plasma Etching)進行氮化矽蝕刻，去除未被光阻4覆蓋的氮化砂 „ 訂 線 (t先閱請'""之注意事項再¥寫本頁) 經濟部中央標準局員工消费合作社印装 經濟部中央標隼局員工消費合作社印裝 A7 ____B7 五、發明説明（$ ) 層3 ;然後以氮化砂層3爲離子佈植護罩（I〇n implantation Mask)，進行p井區離子佈植1 GO，在未被氮化矽覆蓋的所 述半導體基板1上，形成P井10，其中p井離子佈植100 的P型離子種類可採用硼(B)，也可以是二氟化硼(BFO，而 p井離子佈植1GG的劑量(dosage)係介於1E13到2Ε13αΓ2 之間，離子佈植100的能量係介於150KeV到180KeV之間。 接著，請參考圖三，去除光阻4後，於表面沉積一層 填充氧化層(Fi 1 led 0xide)5，以填滿所述氮化矽層3於表 面所形成之渠溝(Trench)，其中所述填充氧化層5係爲二 氧化矽(Si〇2)，其厚度係介於6000埃到8G0Q埃之間。 隨後，請參考圖四，利用化學機械研磨法(Chemical Mechanical Polishing; CMP)進行表面平坦化處理，除去 粗糙不平整的填充氧化層表面，並使所述氮化矽層3完全 裸露，而不被所述填充氧化層5覆蓋。 再接著，請參考圖五，先採用濕蝕刻法(Wet Etching)， 移除氮化矽層3，本實施例中係採用磷酸(H3P〇4)溶液爲蝕 刻配方；之後，以填充氧化層5爲離子佈植的護罩，進行η 井區離子佈植200，在未被所述填充氧化層5覆蓋的所述 半導體基板1上，形成與先前形成之Ρ井區10相鄰的η井 區20，其中η井離子佈植200的η型離子種類是採用磷 (Ρ)，而η井離子佈植200的劑量係介於1Ε13到2E13cnf2 之間，離子佈植200的能量係介於400KeV到480KeV之間。 最後，移除所述填充氧化層5及所述墊氧化層2，即完成 本發明實施例之CMOS雙井結構。 _5 _ 本纸張尺度適用中國國家揉準（CNS )八4規格（210X297公釐） ---------------1T-------^ (請先聞讀背"之注意事項再> 寫本頁) A7 _B? 五、發明説明（j ) 藉由上述方法’僅以一次光罩步驟，由氮化矽層3及填 充氧化層5，先後分別做爲p井區及η井區離子佈植的護 罩’可解決習知技藝中’因多次光罩步驟而造成雙井重疊 的問題；並且’不以光阻做爲離子佈植的護罩，可使用以 定義圖案的光阻厚度減小，以改善其曝光時的焦距深度， 並因光阻使用的減少，可避免因光阻剝落問題而影響離子 佈植製程。 以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明的範圍，其中ρ井與η井離子佈植的先後順序， 可視製程的需要調整之。因此熟知此技藝的人士應能明 瞭，適當而作些微的改變與調整，仍將不失本發明之要義 所在，亦不脫離本發明之精神和範圍，故都應視爲本發明 的進一步實施狀況。謹請貴審査委員明鑑，並祈惠准， 是所至禱。 (請先閱讀肾面之注意事項再鲈\本頁) .裝. *1Τ 線 經濟部中夬榡準局員工消資合作枉印製 本紙張尺度遥用中國國家標準（CNS ) Α4規格（210X297公釐）A7 B7__ printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs, V. Description of the Invention (I) Field of the Invention: The present invention relates to the production of complementary metal-oxide-semiconductor (CMOS) Twin Wells structures in integrated circuits. The method, in particular, relates to a method for performing ion implantation of p wells and n wells in CMOS using only one layer of a mask. BACKGROUND OF THE INVENTION: Dual-well CMOS is a comprehensive design that combines p-well and η-well. It allows both PM0S and NMOS to be fabricated in appropriately micro-doped well regions, so there is no need to design like a single well, and one of the transistors is built on a highly doped substrate, so CMOS The transistor will operate under the most appropriate conditions. When the semiconductor integration makes the element design smaller than 1 micron, the channel length is shortened and the electric field strength in the channel is increased. The holes in PM0S and the electron mobility (Mobility) in NMOS will tend to saturate, making the P channel It is equivalent to the current of the n channel. Because the performance of PM0S and NM0S is similar at this time, when the component is smaller than 1 micron, double-well CMOS will become a very suitable CMOS option. Especially, the use of dual-well CMOS structure and trench isolation will make PM0S and NM0S Spacing is greatly shortened to increase integration. The traditional dual-well CMOS process uses ion masking on the silicon substrate with more than two photo mask steps and photoresist as the shield. n implantation), because the required photoresist is thick, it will cause the problem of the depth of focus (Depth of Focus; D0F). It will also cause the problem of double well overlap due to multiple photomasks; in addition, because of multiple light The masking step makes the problem of photoresistance peeling more serious, and affects the separation of --------- installation—τ ------- order ------ line (please read the back of _ first attention Matters are reproduced on this page) ^ The paper size is subject to the national standards of China (CNS > 8 4 specifications (210X 297 mm) A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Procurement, Ministry of Economic Affairs 5. Description of inventions) The implantation process results in lower product yield. The present invention is to improve the CMOS dual-well structure process in order to reduce the production cost and improve the yield. The main purpose of the present invention is to provide a kind of Ion implantation of CMOS double-well structure with one-time photomask can save photomask and avoid The problem of double-well overlap caused by multiple photomasks in the conventional art. Another object of the present invention is to provide a method for performing ion implantation of a CMOS double-well structure with a single photomask, which can make the photoresist used. 'Thickness reduction' can improve the depth of focus (DepF) during exposure. Another object of the present invention is to provide a method for performing ion implantation of a CMOS double-well structure with only one photomask, which can reduce photoresistance. And avoids affecting the ion implantation process due to the problem of photoresist peeling. The present invention uses the following process steps to achieve the above-mentioned objectives: first, a layer of a pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate; Next, using a photomask, a photoresist pattern of the p-well is defined on the silicon nitride layer, and the silicon nitride layer not covered by the photoresist is removed by plasma etching. The silicon nitride is used as a shield to implant the ion implantation. Into the substrate to form a p-well; then, an oxide layer is formed and the CMP surface is flattened; finally, after the silicon nitride layer is removed by wet etching, the ion implantation substrate is used to form an n-well , Then remove The oxide layer is completed by using the CMOS double-well structure formed by the present invention. Brief description of the drawings: Figure 1 is an embodiment of the present invention, the semiconductor substrate forms a pad oxide layer, ___— (Please read the notes on the back of I first (Fill in this page again) This paper size is in accordance with China National Standard (CNS) A4 specification (210X297 mm) A7 A7 2-pad oxide layer 4-photoresist 10-P well area 100-P well ion implantation (J) A schematic cross-sectional view of a silicon nitride layer and a photoresist pattern. FIG. 2 is a schematic cross-sectional view of a P well formed by ion implantation after dry-etching the silicon nitride layer in an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of an oxide layer formed in an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view after performing CMP in the embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of an n-well formed by ion implantation after wet-etching a silicon nitride layer in an embodiment of the present invention. Description of drawing number: 1-semiconductor substrate 3-silicon nitride layer 5-oxide layer 20-η well region 200-η well ion implantation Detailed description of the invention: The present invention discloses a method for forming a CMOS double-well structure in an integrated circuit. Ion implantation of CMOS double-well structure is performed with only one photomask. First, please refer to FIG. 1, a semiconductor substrate 1 is provided, and a pad oxide layer 2 and a silicon nitride (Si «layer 3) are successively formed on the semiconductor substrate i. It is silicon dioxide (SiO2), the thickness of which is between 2 G0 and 400 Angstroms, and the thickness of the silicon nitride layer 3 is between 4000 and 6000 Angstroms. Then a photo mask (Photo Mask) is used. ) 'Define a photoresist pattern 4 at the position of ρ well on the silicon nitride layer 3. Next, referring to FIG. 2, a silicon nitride etching is performed by using an anisotropic electric pad etching method (Plasma Etching) to remove Nitrided sand covered by photoresist 4 „Ordering line (t read first, please read the“ " " precautions, and then write this page) Employees ’Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs printed the employees’ cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Print A7 ____B7 V. Description of the invention ($) Layer 3; then use the nitrided sand layer 3 as an ion implantation mask to perform ion implantation 1 GO in the p-well area. On the covered semiconductor substrate 1, a P-well 10 is formed, and the P-type ion species of the p-well ion implantation 100 can be adopted. (B), it can also be boron difluoride (BFO, and the p-well ion implantation 1GG dose is between 1E13 and 2E13αΓ2, and the energy of the ion implantation 100 is between 150KeV and 180KeV. Next, please refer to FIG. 3, after removing the photoresist 4, a layer of filled oxide (Fi 1 led 0xide) 5 is deposited on the surface to fill the trench formed by the silicon nitride layer 3 on the surface, where The filling oxide layer 5 is silicon dioxide (SiO2), and its thickness is between 6000 Angstroms and 8G0Q Angstroms. Subsequently, referring to FIG. 4, a chemical mechanical polishing (CMP) method is used. The surface is flattened to remove the rough and uneven surface of the filled oxide layer, and the silicon nitride layer 3 is completely exposed without being covered by the filled oxide layer 5. Then, referring to FIG. 5, wet etching is used first. Method (Wet Etching), the silicon nitride layer 3 is removed. In this embodiment, a phosphoric acid (H3P04) solution is used as the etching formula. Then, the oxide layer 5 is used as an ion implanted shield to perform the η well area. Ion implantation 200 on the semiconductor substrate not covered by the filling oxide layer 5 1, an n-well region 20 adjacent to the previously formed P-well region 10 is formed. The n-type ion species of the n-well ion implantation 200 is phosphorus (P), and the dose of the n-well ion implantation 200 is introduced. Between 1E13 and 2E13cnf2, the energy of the ion implantation 200 is between 400KeV and 480KeV. Finally, the filling oxide layer 5 and the pad oxide layer 2 are removed to complete the CMOS double well of the embodiment of the present invention. structure. _5 _ This paper size is applicable to China National Standards (CNS) 8-4 (210X297 mm) --------------- 1T ------- ^ (Please read first (Read the "Precautions to Read Again" and write this page) A7 _B? V. Description of the invention (j) Using the above method 'only one photomask step, the silicon nitride layer 3 and the oxide layer 5 are filled, one by one As a shield for ion implantation in p-well area and η-well area, it can solve the problem of overlap of double wells caused by multiple photomask steps in the conventional art; and 'do not use photoresist as a shield for ion implantation. The mask can be used to reduce the thickness of the photoresist to define a pattern to improve the focal depth during exposure, and to reduce the use of the photoresist to avoid affecting the ion implantation process due to the problem of photoresist peeling. The above description uses the preferred embodiments to describe the present invention in detail, but not to limit the scope of the present invention. The sequence of ion implantation in the ρ well and the η well can be adjusted according to the needs of the process. Therefore, those who are familiar with this technique should be able to understand that appropriate and slight changes and adjustments will still not lose the essence of the invention, nor depart from the spirit and scope of the invention, so they should be regarded as the further implementation of the invention . I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. (Please read the precautions for the kidney side first, and then this page). Packing. * 1T printed by Chinese National Standards (CNS) Α4 size (210X297) for paper size remote use, printed by the staff of China Central Standards Bureau, Ministry of Economic Affairs, China. Mm)