TW380313B - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
TW380313B
TW380313B TW085109692A TW85109692A TW380313B TW 380313 B TW380313 B TW 380313B TW 085109692 A TW085109692 A TW 085109692A TW 85109692 A TW85109692 A TW 85109692A TW 380313 B TW380313 B TW 380313B
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Taiwan
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aforementioned
voltage
circuit
transistor
pair
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TW085109692A
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Chinese (zh)
Inventor
Yukihide Suzuki
Noriaki Kubota
Koji Arai
Tsugio Takahashi
Shunichi Sukegawa
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Hitachi Ltd
Texas Instruments Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

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  • Dram (AREA)

Abstract

The invention relates to a kind of differential amplifier circuit of semiconductor integrated circuit driven by overdrive method which is applied to DRAM as highly integrated and low working voltage. The purpose of this invention is to prevent excess overdrive even the power supply voltage provided to sense amplifier is high. The features are that the control circuit employs the power voltage (VDD) as the working power to supply the first control signal of initial activation in the activation timing of sense amplifier; and to supply a lower step-down voltage (VDL) that is smaller than the previous power voltage which functioned as the working voltage to activate the second control signal. The delay means as regulating the activation of the first control signal to the activation of the second control signal that employs an inverter mechanism using the power voltage (VDD) as the working power so the delay time of delay circuit has negative independence of the power voltage.

Description

^Γ^ϋν-··'·""合 y;;·1".-'·. · A7 ' 1 B7____— 五、發明説明（13 ) 號，並與控制信號¢) X所指示之字線驅動定時同步，將以 字線選擇信號所應選擇之字線驅動至選擇電平。字線驅動 器WD 〇〜WD 7所形成之字線選擇電平，乃定爲較前述 降壓電壓VD L電平爲髙之昇壓電壓V P P。昇壓電壓 V P P乃在使降壓電壓VD L昇壓之昇壓電路所生成。昇 壓電路2之詳細情形雖未圖示，但可適用周知之供給泵（ charge pump)電路來輕易形成。 SA01、SA23、SA45、SA67 乃爲感測 .放大器區塊（sense amplifier block); C SW〇 1、 CSW23、CSW45、CSW67則爲行開關電路區 塊（c ο 1 u in n s w i t c h c i r c u i t b 1 〇 c k )，被配置在左右一對 之記憶墊塊之間，由鄰接之左右一對之記億墊塊所共有。 挾有感測放大器區塊SA01、SA23、SA45、 SA67與行開關電路區塊CSW01、CSW23、 C SW4 5、C SW6 7加以配置之左右一對之記憶墊塊 ，乃採用共用資料線（shared dataline)構造，形成任 何一方之記憶墊塊之動作將被選擇之狀態•各個感測放大 器區塊之動作控制及共用感測放大器區塊之記憶墊塊@之 資料線共用開關電路（sharing switch circuit)(參照 圖9 )之控制等之記憶墊塊之動作選擇控制，乃由每一成 對之記憶墊塊所設之墊塊控制器（mat contro1er) MCNT01、MCNT23、MCNT45、MCNT 6 7等來進行。 在墊塊控制器MCNT01、MCNT23、 木纸沭尺度it .ii; I丨‘\| i'U.打彳（rNS ) Λ侦L柁（2 10 X 297公漦) " ' ~ ~ (計先閱讀背而之注意事項再楨寫本頁)^ Γ ^ ϋν- ·· '· " " Total y ;; 1 " .-' ·. · A7 '1 B7 ____— V. Description of the invention (13), and the control signal ¢) X indicates The word line driving timing is synchronized, and the word line to be selected by the word line selection signal is driven to a selection level. The word line selection level formed by the word line drivers WD 0 to WD 7 is set to a step-up voltage V P P which is higher than the aforementioned step-down voltage VD L level. The boosted voltage V P P is generated by a boost circuit that boosts the buck voltage V D L. Although the detailed situation of the booster circuit 2 is not shown, it can be easily formed by applying a well-known charge pump circuit. SA01, SA23, SA45, SA67 are sensing. Amplifier block (sense amplifier block); C SW〇1, CSW23, CSW45, CSW67 are row switch circuit blocks (c ο 1 u in nswitchcircuitb 1 〇ck), It is placed between the left and right pair of memory pads and is shared by the adjacent left and right pair of billion pads.左右 A pair of left and right memory pads configured with sense amplifier blocks SA01, SA23, SA45, SA67 and row switch circuit blocks CSW01, CSW23, C SW4 5, C SW6 7, use a shared data line. ) Structure, forming a state where the motion of any one of the memory blocks will be selected • The motion control of each sense amplifier block and the sharing of the memory block @ of the sense amplifier block @ sharing switch circuit (Refer to Fig. 9) The operation selection control of the memory blocks such as the control is performed by the mat contro1er MCNT01, MCNT23, MCNT45, MCNT 6 7 etc. of each pair of memory blocks. . In the block controllers MCNT01, MCNT23, wood and paper scales it .ii; I 丨 '\ | i'U. Snoring (rNS) Λ Detecting L 柁 (2 10 X 297 males) "' ~ ~ (Count (Read the precautions before writing this page)

經濟部中央標準局員工消費合作社印製 A7 &gt; ‘ __, B7_____ 五、發明説明（1 ) &lt;發明所屬之技術部門&gt; 本發明乃關於：備有以過激勵（overdrive)方式被 驅動之差動放大電路之半導體積體電路者，例如，適用於 :爲高積體化，工作電壓被低電平化之DRAM ( Dynamic Random Accees Memory) 而有效之技術者。 &lt;以往之技術&gt; 爲增大D RAM之記憶容量，記億格電晶體（memor-y cell transistor)等之M OS電晶體（以下又簡稱 MOSFET)將被小型化；由此，隨MOS電晶體之閘 極長之縮小化，閘極氧化膜將被薄膜化；故工作電壓之低 電平化研究在進行中。尤其是D RAM，在不致降低高電 平之讀出動作效率（或者使髙電平之讀出動作範圍成爲比 較大）之情況，擬進行高電平之寫入（對記憶格之儲存容 量之充電動作）時，.乃以提昇字線之選擇，抑或降低結合 有記憶格之資料輸出入端子之字線之電壓（感測放大器之 放大動作所帶來之資料線之達到電平）較爲有效。惟如上 述，隨電晶體之高積體化，Μ 0 S電晶體之閘極氧化膜被 薄膜化時，若隨意提高字線之電壓水平，則閘極氧化膜將 成爲容易被破壞，而在D RAM之可靠性方面將極爲欠佳 。由此種情形，將被迫不得不降低資料線之電壓。如此， 將資料線之電壓加以低電壓化，則勢將妨害感測放大器之 高速動作》亦即，若感測放大器之工作電源之電壓被降低 *則流入感測放大器之電流將減少，而當記憶格之電荷資 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇Χ2ί&gt;7公釐） » »^^1 —^^1 - —^ϋ m· , m _ (讀先閱讀背面之注意事項再填寫本頁) ---ix---------„-----1----- -4 - &quot;'••&quot;'t^u^^n-1消 A 合 c&quot;· 補无 A7 .' __——一_B7 五、發明説明（30 ) .· 差之輸入信號S A 2，將被變換爲信號振幅成爲接地電 位VS S與前述昇壓電壓VP P之電位差之輸出信號 VSAN2 &gt;而雙方之信號V&gt;SA2 、VSAN2之邏輯 值將被成爲一般。昇壓電壓VPP將成爲例如4. 0V。 圖6乃表示：由圖5之電路構成對傳動線路SDN、 SDP供給工作電源所用之控制信號pSAN， ^8八？18，识3八1^2之波形。 當規定感測放大器3之活性化期間之控制信號 VSAEB變化爲低電平之有效電平（active level)， 則首先，控制信號P SAP 1 B將變化爲低電平（接地電 位VSS之電平），並經由MOS電晶體Q41，電源電 壓VDD將被供給至傳動線路SD P。由此，因被供給至 感測放大器3之P溝道型MO S電晶體Q 1 3、Q 1 4之 電流較大，故由記憶格之選擇動作顯現在互補資料線 DLO «DLOB之微小電位差將迅速被放大。接著，控 制信號¢) SAP 1 B將被倒相成髙電平（電源電壓VDD 之電平），同時控制信號PSAN2亦被成爲高電平（昇 壓電壓VPP之電平）；由此，經由MOS電晶體 Q42 ~，降壓電壓VDL將被供給至傳動線路SDP » 控制信號？&gt; SAN則與控制信號p SAEB之低電平期間 同步，被成爲髙電平。由此，由感測放大器3所驅動之互 補資料線之到達電平，將被規定成：一方爲接地電位 VSS，另一方爲降壓電壓VDL之狀態。 此時，MOS電晶體Q4 2 &gt;乃爲N溝道型，將其控 本紙乐尺度4扪ί （) 圯柁（2]〇X 297公浼） ~ • .-' -- I - 1、1 -- .*-1 —- - - - 1-»-」\5J (&quot;先閱讀背而之注意事項再&quot;寫本頁) 經漪部中央標準局K工消費合作社印聚 A7 B7 五、發明説明（2 ) 訊被讀出於資料線時，將形成處於互補關係之資料線之微 小電位差予以放大之速度將被降低。 在此，作爲可使感測放大器在低電壓下來高速動作之 技術，乃有感測放大器之過激勵（over drive)技術。例 如，感測放大器以Μ 0 S靜態鎖存形態被構成者，在P溝 道型MO S電晶體之源極，乃於感測放大器激活化定時之 最初給與外部電源電壓VDD，接著給與將外部電源電壓 V D D加以降壓之電壓V D L，來使感測放大器動作。作 爲感測放大器之過激勵技術之一，亦已在： ISSCC950A〇29ns 6 4MbDRAM with Hierachical Array Architecture/PA14.2有報告被 提出。並且，在日本特開平5 — 6 2 4 6 7號專利公報， 亦刊載有：爲控制外部電源電壓供給至感測放大器之期間 (過激勵時間），利用假資料線（dummy dataline)之技 術。. 〈本發明擬解決之問題&gt; 本發明人對上述感測放大器之過激勵加以檢討之結果 ’發現了以下之各問題。亦即，構成感測放大器之P溝道 型MO S電晶體之源極，乃經由開關元件被供給外部電源 電壓VDD，並經由其他之開關元件，被結合在降壓電路 之輸出端子。外部電源電壓VD D及降壓電至壓VD L之 供給線，乃由多數之感測放大器所共有。當感測放大器被 供給，則因其乃爲較電源電壓VD L爲高之工作電壓，故 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） III- ϊ----.,_&quot;^-- (請先閲讀背面之注意事項再填寫本筲) -丁 、-'° m f： &lt;, w A7 B7 五、發明説明（31 ) 制爲ON狀態之控制信號¢) SAN 2之髙電平，則成爲較 其汲極電壓（降壓電壓VD L )爲大之電壓，例如字線昇 壓電壓YPP;故該MOS電晶體Q42/之閘極•源極 間電壓將被成爲較大*而且，載流子遷移率乃Ν溝道型 MO S電晶體較Ρ溝道型MO S電晶體約大約3倍左右。 因此，如圖1之實施例，與使用Ρ溝道型MO S電晶體 Q42，以接地電位VSS將其控制爲ON狀態時比較， 可在MO S電晶體Q 4 2 &gt;獲得較大之電流供給能力。結 果，工作電源被低電壓化之狀況下，亦可使感測放大器3 進行髙速動作· N溝道型MOS電晶體Q4 2 &gt;之閘極電壓假定與汲 極電壓（降壓電壓VDL)相等時，此MOS電晶體 &lt;3 4 2 &quot;之源極電壓將等於較閘極電壓被降低MO S電晶 體Q42 /之臨限值電壓之份量。爲減少此電壓降低，在 本發明之實施例，前述閘極電壓乃被設定成較前述汲極電 壓爲髙。使前述閘極電壓成爲汲極電壓與前述臨限值電壓 之和以上，則可完全取消（cancel )前述臨限值電壓之降 低部分：故可進一步有效防止：對感測放大器之被低寧壓 化之電壓（VDL)之供給能力降低。 例如，假定 VSS = 〇V，VDDi3. 3V， V D L = 2 . 2 V · V P = 4 . 〇V，將 N 溝道型MOS 電晶體Q42,以VPP=4. 〇V之閘極電壓使成爲 ON狀態時之閘極•源極間電壓乃爲1 . 8 V ;假定 MO S電晶體Q4 2 /爲P溝道型’則以0V之閘極電壓 (誚先閱讀背1δ之注意事項再瑣苟本頁) &quot; 、τ 木纸張尺政延 β'ΐ. ( ('NS ) ΛΊίί# ( 210X 297公從） 經&quot;部中央標冰局員工消费合作社印^ A7 , B7 五、發明説明（3 ) 將使感測放大器高速動作。亦即，感測放大器之放大動作 中之初始性過渡響應（transient response)動作將被高 速化。接著，感測放大器之工作電源將被切換爲降壓電壓 VD L。在此情形下，被多數感測放大器共有之前述工作 電源之供給線或資料線，將存在不期望之電容成分；放在 外部電源電壓VDD爲容許範圍之上限之電平，或者爲測 驗動作範圍供給有較通常爲高電平之外部電源電壓之狀態 下，感測放大器之工作電源被切換爲降壓電壓VD L時， 將可預測：從感測放大器向降壓電路之輸出端子將有電流 倒流。 此時，作爲降壓電路採用：結合於在外部電源電壓之 電流源串聯連接高電阻之電路*擬將在降壓電路之貫通電 流抑制於最小限度，則從前述感測放大器側向降壓電路之 輸出端子倒流之電流，將爲前述高電阻所阻而無法迅速洩 漏至接地電位；結果降壓電壓VD L有上昇之虞；此等現 象終爲本發明人所發現。 前述降壓電壓VD L之不期望之電平上昇，將在以下 各點有不良之後果。亦即，降壓電壓VD L之上昇，將使 感測放大器之放大動作所生資料線之到達電壓上昇；由此 ，將使字線之選擇電平與資料線之高電平間之電位差趨小 ，在向記憶格之高電平寫入時，在儲存容量，將無法外加 資料線之該高電平電壓。並且，因前述降壓電壓VD L之 不期望之電平上昇，若感測放大器所引起之資料線之到達 電壓被上昇，則隨之，在晶片（chip)非選擇期間被補償 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) {請先閱讀背面之注意事項再填寫本頁) 裝. *-° -6 -Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 &gt; '__, B7_____ V. Description of the invention (1) &lt; Technical department to which the invention belongs &gt; The present invention is about: having been driven by overdrive The semiconductor integrated circuit of the differential amplifier circuit is, for example, suitable for a technical person who is effective in DRAM (Dynamic Random Accees Memory) whose operating voltage is low for high integration. &lt; Previous technology &gt; In order to increase the memory capacity of D RAM, M OS transistors (hereinafter referred to as MOSFETs) such as memor-y cell transistors will be miniaturized; The reduction of the gate length of the transistor will reduce the thickness of the gate oxide film; therefore, research on the low level of the operating voltage is ongoing. In particular, D RAM is intended to perform high-level writes (to the storage capacity of memory cells without reducing the high-level read operation efficiency (or to make the high-level read operation range larger)). Charging action), is to increase the selection of the word line, or reduce the voltage of the word line combined with the data input and output terminals of the memory cell (the level of the data line brought by the amplification action of the sense amplifier) is relatively effective. However, as described above, with the increase of the transistor, when the gate oxide film of the M 0 S transistor is thinned, if the voltage level of the word line is increased arbitrarily, the gate oxide film will be easily damaged. The reliability of D RAM will be extremely poor. In this case, you will be forced to lower the voltage of the data line. In this way, lowering the voltage of the data line will hinder the high-speed operation of the sense amplifier. That is, if the voltage of the working power of the sense amplifier is reduced *, the current flowing into the sense amplifier will be reduced, and when The scale of the charge capital paper of the memory cell is applicable to the Chinese National Standard (CNS) A4 specification (21〇 × 2ί &gt; 7 mm) »» ^^ 1 — ^^ 1-— ^ ϋ m ·, m _ (Read the notes on the back first Please fill in this page for more information) --- ix --------- „----- 1 ----- -4-&quot; '•• &quot;' t ^ u ^^ n-1 Elimination of A and C &quot; · Compensation without A7. '__—— 一 _B7 V. Description of the invention (30). · The difference of the input signal SA 2 will be converted into a signal amplitude to the ground potential V S and the aforementioned boosted voltage VP The output signal VSAN2 &gt; of the potential difference between P and the logical values of the signals V &gt; SA2 and VSAN2 of both sides will be general. The boosted voltage VPP will be, for example, 4.0V. The line SDN and SDP supply the control signal pSAN used for working power, ^ 8-8? 18, and the waveform of ^ 3 ^ 1 ^ 2. When specifying the control signal VS during the activation period of the sense amplifier 3 AEB changes to a low level active level. First, the control signal P SAP 1 B will change to a low level (the level of the ground potential VSS), and via the MOS transistor Q41, the power supply voltage VDD will It is supplied to the transmission line SD P. As a result, since the currents of the P-channel type MO S transistors Q 1 3 and Q 1 4 supplied to the sense amplifier 3 are large, the selection actions of the memory cells appear complementary. The tiny potential difference of the data line DLO «DLOB will be quickly amplified. Then, the control signal ¢) SAP 1 B will be inverted to a 髙 level (the level of the power supply voltage VDD), and the control signal PSAN2 will also be high ( The level of the boosted voltage VPP); Therefore, the step-down voltage VDL will be supplied to the transmission line SDP via the MOS transistor Q42. »The control signal? &Gt; The SAN is synchronized with the low level period of the control signal p SAEB, Therefore, the reaching level of the complementary data line driven by the sense amplifier 3 will be defined as one state of the ground potential VSS and the other of the step-down voltage VDL. At this time, the MOS Transistor Q4 2 &gt; is an N-channel type Scale 4 扪 ί () 圯 柁 (2) 〇X 297 公 浼) ~ • .- '-I-1, 1-. *-1 —----1-»-" \ 5J (&quot; Read the precautions before writing this page, and then write this page) Printing and Printing A7 B7, K Industrial Consumer Cooperative, Central Standards Bureau of the Ministry of Economic Affairs V. Invention Description (2) When the information is read on the data line, it will form a complementary relationship. The speed at which the small potential difference of the data lines is amplified will be reduced. Here, as a technology that enables the sense amplifier to operate at high speed at a low voltage, there is an over drive technology of the sense amplifier. For example, if the sense amplifier is constructed in the form of M 0 S static latch, the source of the P-channel MOS transistor is given the external power supply voltage VDD at the beginning of the activation timing of the sense amplifier, and then given The external power supply voltage VDD is stepped down to a voltage VDL to operate the sense amplifier. As one of the over-excitation technologies of the sense amplifier, it has also been reported in: ISSCC950A029ns 6 4MbDRAM with Hierachical Array Architecture / PA14.2. In addition, Japanese Patent Laid-Open No. 5-6 2 4 6 7 also discloses a technique of using a dummy data line to control the period (over-excitation time) during which the external power supply voltage is supplied to the sense amplifier. <Problems to be Solved by the Present Invention> As a result of reviewing the over-excitation of the above-mentioned sense amplifier by the present inventors, 'the following problems were found. That is, the source of the P-channel type MOS transistor constituting the sense amplifier is supplied with an external power supply voltage VDD via a switching element, and is coupled to the output terminal of the step-down circuit via other switching elements. The supply lines for the external power supply voltage VD D and the step-down voltage VD L are shared by most sense amplifiers. When the sense amplifier is supplied, because it is a higher working voltage than the power supply voltage VD L, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) III- ϊ ----., _ &quot; ^-(Please read the notes on the back before filling in this note) -D,-'° mf: &lt;, w A7 B7 V. Description of the invention (31) Control signal with ON status ¢) SAN 2 The voltage level of the MOS transistor Q42 / will be a voltage greater than its drain voltage (step-down voltage VD L), such as the word line boost voltage YPP; Larger * Moreover, the carrier mobility is about 3 times that of the N-channel MOS transistor compared to the P-channel MOS transistor. Therefore, as shown in the embodiment of FIG. 1, compared with the case where the P-channel type MO S transistor Q42 is used and it is controlled to the ON state with the ground potential VSS, a larger current can be obtained at the MO S transistor Q 4 2 &gt; Supply capacity. As a result, even when the operating power is reduced, the sense amplifier 3 can be operated at a high speed. The gate voltage of the N-channel MOS transistor Q4 2 is assumed to be the same as the drain voltage (step-down voltage VDL). When equal, the source voltage of this MOS transistor &lt; 3 4 2 &quot; will be equal to the weight of the MOS transistor Q42 / threshold voltage which is lower than the gate voltage. In order to reduce this voltage drop, in the embodiment of the present invention, the gate voltage is set to be larger than the drain voltage. If the gate voltage is equal to or more than the sum of the drain voltage and the threshold voltage, the reduction of the threshold voltage can be completely canceled: so it can further effectively prevent: low voltage of the sense amplifier. The supply capacity of the reduced voltage (VDL) is reduced. For example, suppose VSS = 0V, VDDi3. 3V, VDL = 2.2V · VP = 4. 0V, and turn on the N-channel MOS transistor Q42 with a gate voltage of VPP = 4. 0V. The gate-to-source voltage in the state is 1.8 V; assuming that the MOS transistor Q4 2 / is a P-channel type, a gate voltage of 0 V is used (read the precautions for 1δ before reading it carefully (This page), τ wooden paper ruler political extension β'ΐ. (('NS) ΛΊίί # (210X 297 public obedience) Printed by the Ministry of Central Standard Ice Bureau employee consumer cooperative ^ A7, B7 V. Description of the invention (3) The sense amplifier will operate at high speed. That is, the initial transient response action in the amplification operation of the sense amplifier will be accelerated. Then, the operating power of the sense amplifier will be switched to step-down. Voltage VD L. In this case, the supply line or data line of the aforementioned operating power supply, which is shared by most sense amplifiers, will have an undesired capacitance component; placed at a level where the external power supply voltage VDD is the upper limit of the allowable range, or When an external power supply voltage, which is generally high, is supplied to the test operation range, When the working power of the sense amplifier is switched to the step-down voltage VD L, it can be predicted that a current will flow from the sense amplifier to the output terminal of the step-down circuit. At this time, as a step-down circuit, it is used: combined with the external power supply voltage The current source is connected in series with a high-resistance circuit * It is intended to suppress the through current in the step-down circuit to a minimum. The current flowing back from the sense amplifier side to the output terminal of the step-down circuit will be blocked by the high-resistance. It cannot leak to the ground potential quickly; as a result, the step-down voltage VD L may rise; these phenomena were eventually discovered by the inventors. The aforementioned unexpected rise in the step-down voltage VD L will be defective at the following points That is, the rise of the step-down voltage VD L will increase the arrival voltage of the data line generated by the sense amplifier's amplifying action; thus, the word line selection level and the high level of the data line will increase. The potential difference becomes smaller, and when writing to the high level of the memory cell, the high level voltage of the data line cannot be applied to the storage capacity. Moreover, due to the aforementioned undesired step-down voltage VD L Level rise, if the arrival voltage of the data line caused by the sense amplifier is increased, it will be compensated during the non-selection period of the chip. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) { (Please read the precautions on the back before filling out this page). *-° -6-

經濟部中央標丰局負工消f合作杜印製 A7 , , _ _-__B7_五、發明説明（4 ) (equalize)之資料線之初始性電平（預充電電平（precharge level) 亦上昇 ：在此種狀態 下被寫入之資料被讀 出時，對預充電電平之高電平之讀出電壓容限亦將趨小。 進一步，形成字線選擇電平之昇壓電路若利用前述降壓電 壓VD L時，释壓電壓VD L之不期望之電平上昇將使字 線選擇電平上昇，將有使記憶格選擇電晶體之閘極氧化膜 破損之虞。 以上之各問題乃爲外部電源電壓在容許範圍上限之電 平時之問題；但外部電源電壓爲容許範圍下限之電平時， 則有：感測放大器之放大動作中之前述起始性過渡響應動 作之高速化無法充分獲得等之問題。 如上述，採用過激勵技術時之上述問題，終爲本發明 人所發現。在前述之日本特開平5 — 6 2 4 6 7號專利公 報，乃刊載有：檢測出假資料線之充放電狀況，配合此狀 況來控制過激勵時間之方法；惟在此情形下乃需要形成假 資料線所用之區域。並且，爲撿測出假資料線之電位水平 ’亦有必需重新設置：其所需之檢測電路等之問題。此外 &quot;被配置在記憶陣列（memory array)之最外側之資料線 在製造工程中成爲不良之可能性極高；因此，作爲通常之 資料線未被一般所使用》因之，亦可考慮：將此未被使用 之資料線作爲假資料線來利用；惟將不良之可能性甚高之 .資料線作爲上述假資料線來利用*亦無法期望確實之動作 &quot;因此，利用假資料線來調整過激勵時間之技術，將在晶 之積體度及動作之確實性等方面成爲問題，此種情形亦爲 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） . -7 - ' (請先閱讀背面之注意事項再填寫本頁) 掌 訂 經濟部中央標準局E〈工消費合作社印製 A7 ' 1 __B7____________ 五、發明説明（5 ) 本發明人所發現。 進一步，依據本發明人之檢討研究，在CMO S靜態 問鎖（cmos staticlatch)形態之感測放大器中，在其P 溝道型MOS電晶體之傳動線路（drive line)供給驅動 電壓之電源開關MO S電晶體，因以以往之P溝道型所構 成；故在感測放大器之工作電壓被低電壓化之狀況下，在 工作電壓之供給時，該電源開關M 〇 S電晶體閘極•源極 間電壓（VGS)將被趨小。由此，電源開關MOS電晶 體所作電流供給能力將降低，感測放大器之高速動作亦將 受妨害。此等事實亦爲本發明人所發現。尤其是感測放大 器被前述過激勵時，在降壓電壓之供給時，前述感測放大 器之高速動作之遭受妨害，將更爲顯著，吾人推測：此種 問題不僅在對感測放大器之過激勵之情形如此，對於工作 電壓被低電壓化之差動放大電路，一般而言，亦將被顯著 化。 本發明之目的乃在提供：即使對於如以過激勵形成被 驅動之感測放大器之差動放大電路之高電位側驅動電壓被 提高，亦可有效防止：對差動放大電路之過剩之過激勵等 之被高積體化之半導體積體電路者。 進一步，本發明之其他目的亦在提供：對於以過激勵 \ 形式被驅動之如感測放大器之差動放大電路，將降壓電壓 作爲一個工作電源來供給之降壓電路之前述降壓電壓，不 期望地發生電平上昇之虞，能防止於未然之半導體積體電 路者。 本紙張尺度適用中國园家標準（CNS_) A4規格（210X297公釐) (讀先閱讀背面之注意事項再填寫本頁) 裝The Ministry of Economic Affairs, Central Bureau of Standards and Commerce, Bureau of Labor and Economic Cooperation, Du printed A7,, _ _-__ B7_V. The initial level of the data line of the invention description (4) (equalize) (the precharge level is also Rise: When the data written in this state is read, the read voltage margin to the high level of the precharge level will also become smaller. Further, a boost circuit forming a word line selection level If the aforementioned step-down voltage VD L is used, an undesired rise in the release voltage VD L will increase the word line selection level, which may cause the gate oxide film of the memory cell selection transistor to be damaged. Each problem is a problem when the external power supply voltage is at the level of the upper limit of the allowable range; but when the external power supply voltage is at the level of the lower limit of the allowable range, there are: the acceleration of the aforementioned initial transient response action in the amplification operation of the sense amplifier Problems such as inability to obtain sufficient information. As mentioned above, the above problems when using over-excitation technology were finally discovered by the inventors. In the aforementioned Japanese Patent Application Laid-Open No. 5-6 2 4 6 7, it was published that: Charge and discharge of fake data lines Method to control the over-excitation time in accordance with this situation; however, in this case, the area used by the fake data line needs to be formed. And, to detect the potential level of the fake data line, it must also be reset: its required Problems such as detection circuits, etc. In addition, "the data line arranged on the outermost side of the memory array is highly likely to be defective during manufacturing; therefore, it is not commonly used as a normal data line" Therefore, you can also consider: using this unused data line as a fake data line; but the possibility of bad is high. The data line is used as the above fake data line * and you ca n’t expect a real action &quot; Therefore, the technology of adjusting the over-excitation time by using fake data lines will become a problem in terms of crystal integrity and movement reliability. This situation also applies the Chinese National Standard (CNS) A4 specification (210X297) for this paper standard. (Mm). -7-'(Please read the notes on the back before filling out this page) Order the Central Standards Bureau of the Ministry of Economic Affairs E <Printed by Industrial and Consumer Cooperatives A7' 1 __B7____________ V. Description of the invention (5) Discovered by the inventor. Further, according to the review and study by the inventor, among the sense amplifiers in the form of CMOS static latch (cmos static latch), among the P-channel MOS transistors, The power switch MO S transistor that supplies the drive voltage to the drive line is composed of the conventional P-channel type; therefore, when the operating voltage of the sense amplifier is lowered, when the operating voltage is supplied, The gate-source voltage (VGS) of the power switch MOS transistor will be reduced. As a result, the current supply capability of the power switch MOS transistor will be reduced, and the high-speed operation of the sense amplifier will be hindered. These facts were also discovered by the inventors. Especially when the sense amplifier is over-excited, the high-speed operation of the aforementioned sense amplifier is hindered when the step-down voltage is supplied. I speculate that this problem is not only over-excitation of the sense amplifier. In this case, the differential amplifier circuit whose operating voltage is lowered will generally be significantly improved. The object of the present invention is to provide: even if the high potential side driving voltage of a differential amplifier circuit that is driven by an over-excitation sense amplifier is increased, it can effectively prevent: excessive over-excitation of a differential amplifier circuit Wait for semiconductor integrated circuits that have been integrated. Further, another object of the present invention is also to provide the aforementioned step-down voltage of a step-down circuit that uses a step-down voltage as a working power supply for a differential amplifier circuit such as a sense amplifier that is driven in an over-excitation mode, An undesired level rise may occur, and a semiconductor integrated circuit can be prevented in advance. This paper size is applicable to China Garden Standard (CNS_) A4 specification (210X297 mm) (read the precautions on the back before filling this page)

•IT -8 - A7 - ， ____B7 五、發明説明（6 ) 本發明之其他目的亦在提供：可防止對被低電壓化之 差動放大電路供給工作電源所用之MO S電晶體所引起工 作電壓供給能力之降低之技術者。本發明之其他目的亦在 提供：即使工作電壓被低電壓化，亦可使如感測放大器之 差動放大電路高速動作之半導體積體電路者》 本發明之進一步其他之目的亦在提供：在過激勵技術 中，可將資料線之電位放大至高速且確實之電平之半導體 積體電路者。 本發明之前述以及其他之目的及新穎之特徵，將由本 說明書之記述及附圖，獲得明確之觀念及瞭解》 &lt;解決上述問題之方法&gt; 在本申請所揭示之本發明之中代表性者之概要簡單說 明如下。 經漭部中央標準局貝工消費合作社印製 . -'y. --Γ--,-----Γ 裝！ (請先閱讀背面之注意事項再填寫本頁) 〔1〕在元件之細微化或隨高積體化之工作電壓之低電壓 化時，爲保證被低電壓驅動之電路部分所含之差動放大電 路（3 )之高速動作，在前述差動放大電路之激活化定時 中，最初作爲前述差動放大電路之工作電源，形成供給第 1驅動電壓（VDD)之第1驅動控制信號（^ SA 1 B )，同時之第1驅動控制信號被激活化後，將較該第1驅 動控制信號被非激活化相呼應被激活化之前述第1驅動電 壓電平爲低之第2驅動電壓（VDL)，作爲差動放大電 路之工作電壓進行供給控制之第2驅動控制信號（ ¢) S A 2 B )，加以形成之過激勵（over drive)技術， 本紙張尺度適用中國國家標準（CN'S ) A4規格（210X297公釐） -9 - 經浐部中央標浓局負工消费合作社印裝 A7 1 __________B7_______ 五、發明説明（7 ) 採用於控制電路（TG)時；作爲規定第1驅動控制信號 被激活化之期間（亦即過激勵時間）之延遲機構（1 2 ) ，使用將上述第1驅動電壓作爲工作電源來接納之反相器 電路；而上述第1驅動控制信號被激活化之期間，將對前 述第1驅動電壓具有負之依賴性。 前述過激勵技術，將可作爲對於在備有動態記憶格（ dynamic memory cell)之DRAM等含有多數之如感測放 大器之差動放大電路之驅動技術來採用。亦即，在隨記億 陣列之高積體化之工作電壓之低電壓化時，爲保證如感測 放大器之差動放大電路（3 )之高速動作之故。此時，記 億陣列之工作電源，乃爲將外部電源電壓（VDD)在降 壓電路（1)加以降壓之降壓電壓（VDL);而在驅動 如感測放大器之差動放大電路時，外部電源電壓將作爲前 述第1驅動電壓，降壓電壓則作爲前述第2驅動電壓。 作爲如感測放大器之差動放大電路之驅動方式採用過 激勵技術時，在外部電源電壓爲容許範圍之上限電平，或 者，爲測驅動作容限被供給較通常爲高之電平之電源電壓 等之狀態下：差動放大電路之工作電源從外部電源電壓（ VDD)被切換爲降壓電路（VDL )時，將可預測：從 差動放大電路向降壓電路之輸出端子將有電流倒流。例如 ，作爲降壓電路，採用在被結合於電源電壓之電流源串聯 連接高電阻之電路，擬將降壓電路中之貫通電流抑制在最 小限度時：從前述感測放大器側向降壓電路之輸出端子倒 流之電流，將被前述高電阻所阻擋而將不致迅速被泄漏至• IT -8-A7-, ____B7 V. Description of the invention (6) Another object of the present invention is to provide: to prevent the operating voltage caused by the MO S transistor used for supplying the operating power to the differential amplifier circuit with a low voltage Technologists with reduced supply capacity. Another object of the present invention is also to provide: a semiconductor integrated circuit capable of causing a differential amplifier circuit such as a sense amplifier to operate at high speed even if the operating voltage is reduced. A further object of the present invention is also to provide: In the over-excitation technology, a semiconductor integrated circuit that can amplify the potential of the data line to a high-speed and reliable level. The foregoing and other objects and novel features of the present invention will be clearly understood and understood from the description and drawings of the present specification. &Lt; Methods for Solving the Problems above &gt; Representative among the inventions disclosed in this application The summary is briefly explained below. Printed by Shellfish Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs. -'Y. --Γ-, ----- Γ Install! (Please read the precautions on the back before filling in this page) [1] When the components are miniaturized or the operating voltage is lowered with higher integration, the differential included in the circuit part driven by the low voltage is guaranteed The high-speed operation of the amplifier circuit (3), in the activation timing of the aforementioned differential amplifier circuit, is initially used as the working power source of the aforementioned differential amplifier circuit to form a first drive control signal (^ SA) that supplies a first drive voltage (VDD). 1 B), after the first driving control signal is activated, the second driving voltage (VDL) which is lower than the first driving voltage level corresponding to the activation of the first driving control signal is deactivated. ), Which is the second drive control signal (¢) SA 2 B) for the supply control of the working voltage of the differential amplifier circuit, and the over drive technology is formed. This paper size applies the Chinese National Standard (CN'S) A4 specification (210X297 mm) -9-Printed on the A7 Consumer Cooperative of the Central Bureau of Standards and Economics of the People's Republic of China, printed A7 1 __________B7_______ V. Description of the invention (7) When used in the control circuit (TG); as the first drive control signal During the activation period (that is, overexcitation time), the delay mechanism (12) uses an inverter circuit that receives the first driving voltage as a working power source; and during the period when the first driving control signal is activated, It will have a negative dependency on the aforementioned first driving voltage. The aforementioned over-excitation technique can be adopted as a driving technique for a differential amplifier circuit including a large number of sense amplifiers, such as a DRAM equipped with a dynamic memory cell. That is, in order to ensure the high-speed operation of the differential amplifier circuit (3) such as a sense amplifier when the operating voltage of the high-integrated array is reduced. At this time, the working power supply of the Billion Array is a step-down voltage (VDL) that reduces the external power supply voltage (VDD) in the step-down circuit (1); and when driving a differential amplifier circuit such as a sense amplifier The external power supply voltage will be used as the aforementioned first driving voltage, and the step-down voltage will be used as the aforementioned second driving voltage. When the overdrive technology is used as a driving method of a differential amplifier circuit such as a sense amplifier, a power supply with a higher level than usual is supplied when the external power supply voltage is the upper limit level of the allowable range Under voltage and other conditions: When the working power of the differential amplifier circuit is switched from the external power supply voltage (VDD) to the step-down circuit (VDL), it can be predicted that there will be current from the differential amplifier circuit to the output terminal of the step-down circuit Backflow. For example, as a step-down circuit, a high-resistance circuit connected in series with a current source coupled to the power supply voltage is used. When the through current in the step-down circuit is to be minimized: from the aforementioned sense amplifier side to the step-down circuit. The current flowing backward at the output terminal will be blocked by the aforementioned high resistance and will not be quickly leaked to

本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） J (請先閱讀背面之注意事項再填寫本頁) 裝. 經濟部中央標準局員工消費合作社印笨 A7 ' ____ B7 _____ 五、發明説明（8 ) 接地電位。此時，依據上述之機構，規定過激勵時間之如 前述CMO S反相器之MO S電路，因其工作電源電壓愈 高，過渡響應時間則愈趨短，故外部電源電壓（VDD ^ 較低時，過激勵時間亦將相對地趨長：而外部電源電壓（ VDD )較高時，則過激勵時間將相對地趨短•因此，延 遲電路之延遲時間將對外部電源電壓（VDD)具有負之 依賴性；由此，將可防止差動放大電路過剩地被過度激勵 〇 由於可防止對差動放大電路過剩地被過度激勵，由此 亦可防止：從多數之如感測放大器之差動放大電路向降壓 電路倒流電流之事態發生：由此，將可防止：降壓電壓不 期望地發生電平上昇之事態。 〔2〕向差動放大電路（3 )之髙電位側之傳動線路 (driveline)(S D P)供給工作電壓（V D L )之 MO S電晶體（Q 4 2 )定爲N溝道型，而其閘極供給之 開關控制信號（¥ SAN 2 )之髙電平電位，定爲較其汲 極電壓爲高電平之昇壓電壓（VP P )之電位。作爲前述 昇壓電壓，則可利用形成字線選擇電平之內部昇壓電路（ 2 )之輸出電壓。 依據其他之觀點，則將對差動放大電路（3 )之高電 位側之傳動線路（SDP)供給工作電壓（VDL)之Μ 〇 S電晶體（Q 4 3 )定爲Ρ溝道型，而將被供給至其閘 極之開關控制信號（4 S ΑΪ5 2 Β )之低電平電位定爲與 前述電源電壓（VDD)極性相反之負電壓（VBB)。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐) ~ &quot; (請先閱讀背面之注意事項再填寫本頁) 裝. 、-0 L·' 經濟部中央標準局工消費合作社印製 A7 ' __B7______ 五、發明説明（9 ) 作爲負電壓’則可利用基板偏壓發生電路（5 )之輸出電 壓。 即使如感測放大器之差動放大電路之工作電壓之低電 平化有進展’但若向其高電位側傳動線路供給工作電源之 Μ ◦ S電晶體爲N溝道型，則使其成爲〇 N狀態所需之閘 極•源極電壓，將可按照該MO S電晶體之閘極氧化膜之 耐壓等要因來決定。因此，將無隨著差動放大電路之工作 電壓被低電壓化，使前述閘極•源極電壓趨小之趨勢。並 且，以載流子（carrier)遷移率言’與Ρ溝道型MO S 電晶體比較，N溝道型MO S電晶體將大3倍左右；即使 是與P溝道型M〇S電晶體之情形同等之閘極•源極間電 壓，或其以下之閘極•源極間電壓，亦可獲得比較大之電 流供給能力。結果，將能夠避免：隨著工作電壓被低電壓 化而使向高電位側傳動線路之工作電源供給用Μ 0 S電晶 體之閘•源極間電壓被趨小之現象；即使在工作電壓被低 電壓化之狀況下，亦可使差動放大電路作高速動作。 並且，即使向如感測放大器之差動放大電路之高電位 側之傳動線路供給工作電路之MO S電晶體，定爲Ρ溝道 型之情形，若將對其作開關控制之信號電壓定爲負電壓， 亦可將該M〇 S電晶體之閘極•源極電壓定爲較大；結果 ，在工作電壓被低電壓化之狀況下亦可使差動放大電路作 高速動作。 藉由將對前述高電位側之傳動線路供給工作電源之Ν 溝道型MO S電晶體，做爲訂定開關控制之信號振幅的昇 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 -12 - 經滴部中央標準局負工消f合作社印製 A7 . _ B7 五、發明説明（10 ) 壓電壓，利用形成字線選擇電平之昇壓電路之輸出；或將 對前述傳動線路供給動作電源之P溝道型MO S電晶體， 做爲訂定開關控制之信號振幅之負電壓，利用基板偏壓發 生電路所形成之負電壓；於前述差動放大電路之工作速度 之高速化時，可極力抑制電路規模之增大。 〔3〕而且，關於過激勵（over drive)，亦可採用 以下之方法。亦即，半導體積體電路，將含有：一對之資 料線；及備有一對之P溝道型MOS電晶體及一對之N溝 道型MO S.電晶體等之CMO S閂鎖電路，而將放大前述 —對之資料線之電位差之感測放大器（.sense amplifier );及承接第1電壓之第1端子；及承接較前述第1電壓 爲低之第2電壓之第2端子；及被設於：在前述一對之p 溝道型MO S電晶體中被共同結合之一對源極與前述第1 端子之間之第1開關MO S電晶體；及被設在前述被共同 結合之一對源極與前述第2端子之間之N溝道型MO S之 第2開關MO S電晶體：及向前述第1及第2開關MO S 電晶體之閘極輸出信號成爲：在第1期間前述第1開關 MO S電晶體將成ON狀態，而在前述第1期間後之第2 期間則前述第1開關M〇 S電晶體將成爲0 F F狀態，且 前述第2開關MO S電晶體亦將成爲ON狀態等之控制電 路等；而在前述第2期間，前述第2開關MO S電晶體之 閘極電壓，乃爲較前述第2電壓爲高之之電壓；等爲構成 者。 前述控制電路乃含有規定前述第1期間之延遲電路’ 本紙張尺度適用中國囤家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. -6 -13 - 經潢部中央標洚局兵工消费合作社印繁 A7 ' _B7____ _ 五、發明説明（11 ) 而前述第1期間之變動則對前述第1電壓之變動具有負之 依存性(dependency) 〇 依據此方法’在過激勵（over drive)技術中，因可 將過激勵時間（第1期間）按過激勵用之電壓（第1電壓 )來控制；故不僅可防止感測放大器之過剩激勵，同時亦 能使供給較低電壓（第2電壓）之第2開關MOS電晶體 之ON阻抗趨小，來提高由此所帶來之電流供給能力。因 此，在過激勵技術中，感測放大器將可使資料線之電壓水 平高速且確賓被放大至所希望之水平。 將前述延遲電路，以將前述第1電壓作爲工作電源來 承接之反相器電路來構成；由此即可以簡單構成來確實控 制過激勵時間。 在前述第2期間，將前述第2開關MO S電晶體之閘 極電壓，定爲前述第2電壓與前述第2開關Μ Ο S電晶體 之閾值電壓之和之電壓相等，或較其爲高之電壓；由此即 可使在前述第2開關Μ 0 S電晶體之前述閾值電壓份量之 降低（drop )，將不致發生。 &lt;發明之實施形態&gt; 圖8乃表示本發明之一例之D RAM之方塊圖者。該 圖所示之D RAM，雖未特別之限制，但乃由周知之半導 體積體電路之製造技術，被形成爲：如單晶矽之1個半導 體基板。在圖8乃代表性地表示有2個之記億陣列 MARYO，MARY1。 ϋ张尺度適用中國國家標準（CNS ) A4規210X29*7公楚1 (請先閲讀背面之注意事項再填寫本頁) 裝. *-β ri. -14 - 經濟部中央標4,-局貝工消費合作社印製 A7 ' ____ B7 五、發明説明（12 ) 如圖8所示之DRAM，乃由外部電源端子承接如 3，3V之外部電源電壓VDD，如〇V之接地電位 VSS。此DRAM爲記億容量之增大，在記憶陣列 MARYO ，MARY1之MOS電晶體乃被小型化；由 此，隨此等Μ 0 S電晶體之閘極長之縮小化.，閘極氧化膜 已被薄膜化。爲此，在記憶陣列MARYO，MARY1 之工作電壓亦已被低電壓化，而將例如2 . 2 V之降壓電 壓VD L作爲基本之工作電源來利用。降壓電壓VD L乃 在使外部電源電壓VDD降壓之降壓電路生成。在圖中， 5乃爲基板偏壓VBB之發生電路。基板偏壓發生電路5 亦可以周知之電路來構成；例如，圖示雖省略，由電容器 與二極管元件所構成；由於接受正極性之周期性信號，將 形成負極性之基板偏壓VBB。 各記億陣列MARYO，MARY1乃被分割成各8 個之記憶塾塊（memory mat)MMAT〇 〜MMAT7。 各個記憶墊塊MMAT0〜MMAT7，乃含有多數之選 擇端子被結合在字線，而資料輸出入端子則被結合在互補 資料線之1電晶體型之動態記憶格（dynamic memory ceil) 。 每個記憶墊塊亦設有字驅動器 （word driver ) WD 〇 〜WD 7，及列址解碼器（row adderss decorde-r) XD〇〜XD7。列址解碼器XD〇〜XD7在其動 作被選擇後即將內部內部內部互補列址信號A X加以解碼 以形成字線選擇信號，來選擇響應內部互補列址信號A X 之1條字線。字驅動器WD 0〜WD 7乃接受字線選擇信 本纸張尺度適用中國园家標準（CNS ) Α4規格（210X297公釐） — 一：— — L—IΙΓ 裝------訂.-----—ϋ (請先Μ讀背面之注意事項再填寫本頁) 15This paper size applies to Chinese National Standard (CNS) A4 (2 丨 0X297 mm) J (Please read the precautions on the back before filling out this page). Packing. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 '____ B7 _____ 5. Description of the invention (8) Ground potential. At this time, according to the above-mentioned mechanism, the MO S circuit of the CMO S inverter such as the aforementioned CMO S inverter with over-excitation time, because the higher the operating power voltage, the shorter the transient response time, so the external power voltage (VDD ^ is lower Time, the over-excitation time will also be relatively long: when the external power supply voltage (VDD) is high, the over-excitation time will be relatively short • Therefore, the delay time of the delay circuit will have a negative effect on the external power supply voltage (VDD) This will prevent the differential amplifier circuit from being excessively excited. As it can prevent the differential amplifier circuit from being excessively excited, it can also prevent: from the majority of the sense amplifier differential The state that the current is reversed by the amplifier circuit to the step-down circuit occurs: As a result, the situation in which the step-down voltage rises unexpectedly can be prevented. [2] The transmission line to the 髙 potential side of the differential amplifier circuit (3) (driveline) (SDP) The MO S transistor (Q 4 2) that supplies the operating voltage (VDL) is set to N-channel type, and the high-level potential of the switch control signal (¥ SAN 2) supplied by its gate is set to For its drain The potential of the step-up voltage (VP P) which is at a high level. As the aforementioned step-up voltage, the output voltage of the internal step-up circuit (2) forming the word line selection level can be used. According to other viewpoints, then The MOS transistor (Q 4 3) that supplies the operating voltage (VDL) to the high-potential side transmission line (SDP) of the differential amplifier circuit (3) is set to a P-channel type and will be supplied to its gate. The low-level potential of the pole switch control signal (4 S ΑΪ5 2 Β) is set to a negative voltage (VBB) with the opposite polarity to the aforementioned power supply voltage (VDD). This paper size applies the Chinese National Standard (CNS) Α4 specification (210X297) (%) ~ &Quot; (Please read the precautions on the back before filling this page). -0 L · 'Printed by A7 of the Central Standards Bureau of Industry and Consumer Cooperatives of the Ministry of Economic Affairs __B7______ 5. Description of the invention (9) as negative voltage' The output voltage of the substrate bias generating circuit (5) can be used. Even if the working voltage of the differential amplifier circuit of the sense amplifier is lowered, but if the working power is supplied to the high-potential side transmission line, ◦ S transistor is N-channel type. The gate and source voltage required for the ON state will be determined according to factors such as the withstand voltage of the gate oxide film of the MOS transistor. Therefore, the operating voltage of the differential amplifier circuit will not be lowered. As the voltage becomes smaller, the aforementioned gate-source voltage tends to decrease. In addition, in terms of carrier mobility, compared with the P-channel MOS transistor, the N-channel MOS transistor will be larger. About 3 times; even the gate-source voltage equivalent to that of the P-channel MOS transistor, or a gate-source voltage below or below, can obtain a relatively large current supply capacity. As a result, it is possible to avoid the phenomenon that the gate-source voltage of the M 0 S transistor for working power supply to the high-potential side transmission line is reduced as the operating voltage is reduced; even when the operating voltage is reduced, Under the condition of low voltage, the differential amplifier circuit can also be operated at high speed. In addition, even if the MO S transistor of the working circuit is supplied to the transmission line on the high potential side of a differential amplifier circuit such as a sense amplifier, the case is determined as a P-channel type. If the signal voltage for switching control is set to Negative voltage can also make the gate and source voltage of this MOS transistor larger; as a result, the differential amplifier circuit can also be operated at high speed when the operating voltage is reduced. The N-channel MOS transistor that supplies working power to the high-potential side transmission line is used as the rise of the signal amplitude for the predetermined switch control. The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm). (%) (Please read the precautions on the reverse side before filling out this page) Binding. Order-12-printed by the Central Standards Bureau of the Ministry of Standards and Technology Co., Ltd. printed A7. _ B7 V. Description of the invention (10) The voltage and voltage are used to form The output of the step-up circuit of the word line selection level; or the P-channel type MO S transistor which supplies the operating power to the aforesaid transmission line as a negative voltage for setting the amplitude of the signal to be controlled by the switch. The negative voltage formed by the circuit; when the operating speed of the aforementioned differential amplifier circuit is increased, the increase of the circuit scale can be suppressed as much as possible. [3] For over drive, the following method can also be used. That is, the semiconductor integrated circuit will include: a pair of data lines; and a CMO S latch circuit including a pair of P-channel type MOS transistors and a pair of N-channel type MO S. transistors, etc. And a sense amplifier (.sense amplifier) that amplifies the potential difference of the aforementioned-pair of data lines; and a first terminal that receives a first voltage; and a second terminal that receives a second voltage that is lower than the aforementioned first voltage; and It is provided in the first switching MO S transistor which is commonly coupled between a pair of the source and the first terminal in the aforementioned p-channel type MO S transistor; One pair of the second switching MO S transistor of the N-channel type MO S between the source and the second terminal: and the output signal to the gate of the first and second switching MO S transistors becomes: In the first period, the first switch MO S transistor will be turned on, and in the second period after the first period, the first switch MO S transistor will be in the 0 FF state, and the second switch MO S will be turned on. The crystal will also become the control circuit of the ON state, etc .; during the aforementioned second period, the gate voltage of the aforementioned second switching MO S transistor is , Is compared to the sum of the second voltage to a high voltage; configuration as the person. The aforementioned control circuit contains the delay circuit that stipulates the first period mentioned above. 'This paper size is applicable to the Chinese standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page). -6. -13-Printed A7 '_B7____ _ by the Central Bureau of Standards, Ministry of Economic Affairs and Military Cooperatives Consumer Cooperatives V. Description of the Invention (11) The changes in the aforementioned first period have a negative dependency on the aforementioned changes in the first voltage 〇According to this method, in the overdrive technology, the overdrive time (the first period) can be controlled according to the overdrive voltage (the first voltage); therefore, it can not only prevent the overdrive of the sense amplifier. At the same time, the ON resistance of the second switching MOS transistor that supplies a lower voltage (second voltage) can also be made smaller to improve the current supply capability. Therefore, in the over-excitation technique, the sense amplifier will make the voltage level of the data line high and the amplifier will be amplified to the desired level. The aforementioned delay circuit is constituted by an inverter circuit which receives the aforementioned first voltage as an operating power source; thus, a simple configuration can be used to surely control the over-excitation time. During the second period, the gate voltage of the second switch MO S transistor is set to be equal to or higher than the sum of the threshold voltages of the second voltage and the second switch M 0 S transistor. Therefore, the threshold voltage drop of the second switching M 0 S transistor can be prevented from occurring. &lt; Embodiment of Invention &gt; Fig. 8 is a block diagram showing a D RAM according to an example of the present invention. Although the D RAM shown in the figure is not particularly limited, it is formed by a well-known manufacturing technology of a semiconductor volume circuit, such as a semiconductor substrate of single crystal silicon. Fig. 8 shows two representative arrays MARYO and MARY1. ϋ Zhang scale is applicable to Chinese National Standard (CNS) A4 Regulation 210X29 * 7 Gong Chu 1 (Please read the precautions on the back before filling this page). * -β ri. -14-Central Standard of the Ministry of Economic Affairs A7 '____ B7 printed by the industrial and commercial cooperatives V. Description of the invention (12) As shown in Figure 8, the DRAM shown in Figure 8 receives external power supply voltage VDD such as 3, 3V, and ground potential VSS such as 0V. This DRAM is an increase in memory capacity. In the memory array MARYO, the MOS transistor of MARY1 is miniaturized; therefore, with the reduction of the gate length of these M 0 S transistors, the gate oxide film has been reduced. Be thinned. For this reason, in the memory array MARYO, the operating voltage of MARY1 has also been reduced, and a step-down voltage VD L of, for example, 2.2 V is used as a basic working power source. The step-down voltage VD L is generated in a step-down circuit that steps down the external power supply voltage VDD. In the figure, 5 is a circuit for generating the substrate bias VBB. The substrate bias generating circuit 5 can also be constructed by a well-known circuit; for example, although not shown in the figure, it is composed of a capacitor and a diode element. Since it receives a positive periodic signal, a negative substrate bias VBB will be formed. Each memory array MARYO, MARY1 is divided into 8 memory mats MMAT0 to MMAT7 each. Each memory pad MMAT0 ~ MMAT7 contains most of the optional terminals combined on the word line, and the data input / output terminals are combined on the dynamic memory ceil of a transistor type of the complementary data line. Each memory pad is also provided with a word driver WD 〇 ～ WD 7 and a row adderss decorde-r XD〇 ～ XD7. The column address decoders XD0 to XD7 decode the internal internal internal complementary column address signal A X to form a word line selection signal after selecting its action to select a word line that responds to the internal complementary column address signal A X. The word drive WD 0 ~ WD 7 accepts the word line selection letter. The paper size is applicable to the Chinese Gardener Standard (CNS) Α4 specification (210X297 mm). ----— ϋ (Please read the notes on the back before filling in this page) 15

^Γ^ϋν-··'·&quot;&quot;合 y;;·1&quot;.-'·. · A7 ' 1 B7____— 五、發明説明（13 ) 號，並與控制信號¢) X所指示之字線驅動定時同步，將以 字線選擇信號所應選擇之字線驅動至選擇電平。字線驅動 器WD 〇〜WD 7所形成之字線選擇電平，乃定爲較前述 降壓電壓VD L電平爲髙之昇壓電壓V P P。昇壓電壓 V P P乃在使降壓電壓VD L昇壓之昇壓電路所生成。昇 壓電路2之詳細情形雖未圖示，但可適用周知之供給泵（ charge pump)電路來輕易形成。 SA01、SA23、SA45、SA67 乃爲感測 .放大器區塊（sense amplifier block); C SW〇 1、 CSW23、CSW45、CSW67則爲行開關電路區 塊（c ο 1 u in n s w i t c h c i r c u i t b 1 〇 c k )，被配置在左右一對 之記憶墊塊之間，由鄰接之左右一對之記億墊塊所共有。 挾有感測放大器區塊SA01、SA23、SA45、 SA67與行開關電路區塊CSW01、CSW23、 C SW4 5、C SW6 7加以配置之左右一對之記憶墊塊 ，乃採用共用資料線（shared dataline)構造，形成任 何一方之記憶墊塊之動作將被選擇之狀態•各個感測放大 器區塊之動作控制及共用感測放大器區塊之記憶墊塊@之 資料線共用開關電路（sharing switch circuit)(參照 圖9 )之控制等之記憶墊塊之動作選擇控制，乃由每一成 對之記憶墊塊所設之墊塊控制器（mat contro1er) MCNT01、MCNT23、MCNT45、MCNT 6 7等來進行。 在墊塊控制器MCNT01、MCNT23、 木纸沭尺度it .ii; I丨‘\| i'U.打彳（rNS ) Λ侦L柁（2 10 X 297公漦) &quot; ' ~ ~ (計先閱讀背而之注意事項再楨寫本頁)^ Γ ^ ϋν- ·· '· &quot; &quot; Total y ;; 1 &quot; .-' ·. · A7 '1 B7 ____— V. Description of the invention (13), and the control signal ¢) X indicates The word line driving timing is synchronized, and the word line to be selected by the word line selection signal is driven to a selection level. The word line selection level formed by the word line drivers WD 0 to WD 7 is set to a step-up voltage V P P which is higher than the aforementioned step-down voltage VD L level. The boosted voltage V P P is generated by a boost circuit that boosts the buck voltage V D L. Although the detailed situation of the booster circuit 2 is not shown, it can be easily formed by applying a well-known charge pump circuit. SA01, SA23, SA45, SA67 are sensing. Amplifier block (sense amplifier block); C SW〇1, CSW23, CSW45, CSW67 are row switch circuit blocks (c ο 1 u in nswitchcircuitb 1 〇ck), It is placed between the left and right pair of memory pads and is shared by the adjacent left and right pair of billion pads.左右 A pair of left and right memory pads configured with sense amplifier blocks SA01, SA23, SA45, SA67 and row switch circuit blocks CSW01, CSW23, C SW4 5, C SW6 7, use a shared data line. ) Structure, forming a state where the motion of any one of the memory blocks will be selected • The motion control of each sense amplifier block and the sharing of the memory block @ of the sense amplifier block @ sharing switch circuit (Refer to Fig. 9) The operation selection control of the memory blocks such as the control is performed by the mat contro1er MCNT01, MCNT23, MCNT45, MCNT 6 7 etc. of each pair of memory blocks. . In the block controllers MCNT01, MCNT23, wood and paper scales it .ii; I 丨 '\ | i'U. Snoring (rNS) Λ Detecting L 柁 (2 10 X 297 males) &quot;' ~ ~ (Count (Read the precautions before writing this page)

經濟部中央標隼局貝工消f合作社印製 A7 , &gt; __B7______ 五、發明説明（14 ) MCNT4 5、MCNT6 7，乃有墊塊選擇信號MS、 感測放大器控制信號#SAN、0SAN2、 0SAP1B等被供給。墊塊選擇信號MS，乃爲指示從 8個之記億墊塊MMAT 〇〜MMAT 7究竟選擇哪一個 之3數元（3 bi t)之信號。實際上，乃與被保持在列 址緩衝器RAB之列址信號之上位3數元之資訊相對應。 墊塊控制器MCNT01、MCNT23、MCNT45 、MCNT 6 7乃將墊塊選擇信號MS加以解碼，進行感 測放大器區塊之動作控制或列址解碼器之活性化控制成爲 :使其所指定之記憶墊塊動作之狀態。例如，墊塊選擇信 號M S若指定記憶墊塊Μ M A T 0，則列址解碼器X D 〇 將被活性化，同時感測放大器區塊SA〇 1將經由資料線 共用開關電路被連接在記億墊塊MMATO;而在記偉墊 塊MMATO，記憶格之選擇動作亦成爲可能。對於感測 放大器控制信號05八1^、0SAN2、0SAP1B ; 其詳細情形容後再說明。 各個行開關電路區塊C SWn乃承接來自行址解碼器 Y D之行選擇信號，由此來從記憶墊塊中選擇各4組之互 補資料線，並導通至互捕共用資料線CDO〜CD3。行 址解碼器Y D乃在讀出動作中字線選擇動作確定後，由被 \ 成爲致能電平（enable level)之定時信號必Y成爲動作 可能之狀態；由此，來對內部互補行址信號AY進行解碼 ，以生成行選擇信號》 由前述字線選擇動作及行選擇動作，以墊塊選擇信號 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） {請先閱讀背面之注意事項再填寫本頁).Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Co., Ltd., A7, &gt; __B7______ V. Description of the invention (14) MCNT4 5, MCNT6 7, with the pad selection signal MS and the sense amplifier control signal #SAN, 0SAN2, 0SAP1B And so on. The pad selection signal MS is a signal indicating which one of the three pads MMAT 0 to MMAT 7 is selected from 3 bit. Actually, it corresponds to the information which is 3 digits above the address signal of the address buffer RAB. The pad controllers MCNT01, MCNT23, MCNT45, and MCNT 6 7 decode the pad selection signal MS to control the operation of the sense amplifier block or the activation control of the address decoder to make its designated memory pad The state of the block action. For example, if the pad selection signal MS specifies a memory pad M MAT 0, the address decoder XD 〇 will be activated, and at the same time, the sense amplifier block SA 〇1 will be connected to the memory pad through the data line shared switch circuit. Block MMATO; and in the block MMATO of Jiwei, the choice of memory cells is also possible. Regarding the control signals of the sense amplifier 05, 8 ^, 0SAN2, 0SAP1B; the details will be described later. Each row switch circuit block C SWn receives a row selection signal from the row address decoder Y D, thereby selecting each of four sets of complementary data lines from the memory pad, and leads to the mutual capture common data lines CDO ~ CD3. The row address decoder YD is a state in which the timing signal that has been turned into an enable level must be Y enabled after the word line selection action is determined in the read operation; thus, the internal complementary row address signal AY decodes to generate a row selection signal. "The aforementioned word line selection action and row selection action are used to select signals by pads. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). {Please read the back first (Please fill out this page).

-17 - 經濟部中央標準局男工消资合作社印^ A7 B7 五、發明説明（l5 ) MS、內部互補列址信號ΑΧ、以及內部互補行址信號 ΑΥ被指定之4個記億格，將被導通至互補共用資料線 CDO〜CD3。記憶陣列MARY1側雖未特加圖示， 亦與上述同樣被構成，而在記億陣列M A R Υ 1側則配置 有互補共用資料線CD4〜CD7。 前述互捕共用資料線CD 0〜CD 7雖未有特別之限 制，但亦被結合在資料輸出入電路D I 〇。在資料輸入電 路D I 〇，乃含有放大器（main amplifier )、寫入放大 器、以及資料輸出入緩衝器等，由定時信號0 W之被成爲 促成電平來進行寫入所需之資料輸入動作；而由定時信號 0 R之被成爲促成電平來進行讀出所需之資料輸出動作。 本實施例之動態RAM，乃以8數元單位來進行資料之寫 入及讀出，而由記憶陣列MARYO來擔負下位4數元， 以記憶陣列MA RY 1來擔負上位4數元者。 前述列址緩衝器RAB，乃將從外部位址輸入端子 A 0〜A i被輸入之列址信號，經由位址多工器（ 8(1打633 1111111；丨。士6\61')厶^1又被取入來加以保持。此取 入動作，乃由從定時發生電路TG所供給之定時信號 必X L之高電平來作指示。 位址多工器A Μ X，雖未特別限制，但亦在動態 RAM成爲通常動作模態時，從定時發生電路TG有：使 禁能電平（disable levei)之定時信號¢5 R E F被供給 ;由此將經由外部端子A 〇〜A i被供給之列址信號傳達 至列址緩衝器RAB。並且，動態RAM被作爲CBR ( 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公笼） (請先閱讀背面之注意事碩再填寫本頁) '裝. 訂 -18 - 經濟部中央標準局貝工消費合作社印製 A 7 , ^ _____ B7______ 五、發明説明（16 ) CAS before RA S )再新循環（refresh cycle)時， 上述定時信號# R E F被成爲促成電平，則將選擇從再新 位址計數器（refresh address counter) R E C 所供給 之再新位址信號，並將此傳達至列址緩衝器RAB。 再新位址計數器RF C，雖未有特別之限制，但動態 RAM 被成爲 CBR 再新模態（CBR refresh mode ) 時，將與從定時發生電路TG每按規定週期（CyCie)被供 給之定時信號0RC同步進行計數動作，以生成再新位址 〇 前述行址緩衝器CAB，乃將經由前述外部位址輸入 端子A 〇〜A i被供給之行址信號，與定時發生電路TG 所供給之控制信號《YL被成爲致能（enable)之定時同 步，加以取入保持。 前述定時發生電路TG，將作爲來自外部之接達信號 ’被供給：列址問控信號（ROW address strobe signal )RAS* (符號*乃意味：附有此號之信號爲row enable列致能應信號者）、行址閂控CAS*、寫入致能 (write enable )信號WE *、以及輸出促成信號Ο E * 等；而根據此等電平及變化定時來判定動態RAM之動作 模態，同時亦形成上述各種之定時信號，以控制動態RA Μ之內部動作·列址閂控信號R A S *乃由其低電平來指 示晶片（chip)選擇，並且通知列址信號爲有效。由此， 定時控制器TG將取入列址信號，然後順次生成：字線選 擇動作或記錄墊塊選擇所需之前述控制信號•行址閂控 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事碩再填商本頁) 訂 -19 - A7 B7 經演部中央標準局賀工消費合作社印製 五、 發明説明（Π ) 1 C A S * 乃 爲 通 知 行 址 信 號 爲 有 效 之 信 號 0 當 此 被 成爲 致 1 I 能 電 平 ( enable 1 eve 1 ) * 則 定 時 控 制 器 T G 將 順 次生 成 1 I 行 址 信 號 之 取 代 9 以 及 行 選 擇 動 作 所 需 之 前 述 控 制 信號 0 1 1 1 寫 入 致 能 信 W Ε 氺 則 由 其 致 能 電 平 來 對 D R A Μ 指示 寫 討 先 1 1 入 gCJ. 勤 作 輸 出 促 成 信 號 D E 氺 亦 由 其 促 成 電 平 來 對 閣 讀 背 ] 1 D R A Μ 指 示 讀 出 動 作 〇 C B R 再 新 模 態 乃 在 列 址 閂控 信 面 \ I 號 1 I R A S *成 爲 促 成 之 刖 &gt; 由 於 行 址 閂 控 C A S 氺 被成 爲 事 項 1 致 能 電 平 而 被 指 定 〇 再 填 在 寫 本 裝 园 圖 9 乃 表 示 有 ..1 /. 刖 述 記 憶 墊 塊 Μ Μ A T 0 、 頁 1 I Μ Μ A Τ 1 感 測 放 大 器 1^ 塊 S A 0 1 、 及 行 開 關 電路 區 1 1 塊 C S W 0 1 之 局 部 電 路 圖 〇 尤 其 在 該 圖 亦 有 接 受1 個 1 行 選 擇 信 號 Y S 0 0 之 電 路 部 分 代 表 性 地 被 表 示 。在 1 ci.i 圖 1 訂 中 通 道 ( 反 閘 ) 部 附 有 箭 頭 之 Μ 0 S 電 晶 體 乃 爲 P溝 道 1 1 型 亦 未 附 有 刖 頭 之 N 溝 道 型 之 Μ 0 S 電 晶 體 加 以 區別 〇 1 I 在 圖 9 中 代 表 性 表 示 之 W L 0 W L i 乃 爲 字 線， 1 fL D L 0 、 D L 0 Β 、 D L 1 、 D L 1 Β 則 爲 互 補 資 料線 » I Μ C 乃 爲 動 態 記 憶 格 ( dy nam i C memo ry cel 1 ) C 動態記 1 1 I 憶 格 Μ C 乃 由 被 連 接 在 資 料 線 之 選 擇 Μ 0 S 電 晶 體 Q 1 與 I τ· 1 內 儲 容 量 ( stored capac ity ) s c之串聯電路被連接於 ! 板 極 ( pi at e ) 電位Ρ &gt; L 〔V D L / 2 ) 所成^ Q 2 7， 1 Q 3 4 乃 爲 r~Hr 構 成 資 料 線 共 用 開 關 ( s h a r in g S W it ch )電 路 1 I 之 一 部 分 之 共 用 開 關 Μ 0 S 電 晶 體 〇 被 配 置 在 與 記 憶墊 塊 1 Μ Μ A T 0 之 間 之 被 代 表 性 表 示 之 共 用 開 關 Μ 0 S 電晶 體 1 1 I Q 2 7 Q 3 0 乃 以 控 制 信 ψ S Η R L 被 進 行 開 關控 制 1 1 1 本纸張尺度適用中國國家標率（CNS ) A4規格（210X297公楚） -20 - 經&quot;-部中央標準局員工消&quot;合作社印製 A7 ' ____B7___ 五、發明説明（18 ) ;被配置在與記億墊塊MMA T 1之間之被代表性表示之 共用開關MOS電晶體Q3 1〜Q34，則以控制信號 0 S HRR來進行開關控制。例如，墊塊選擇信號MS選 擇記憶墊塊MMATO時，前述墊塊控制器MCNTO 1 則將控制信號0 S HRR控制成高電平。未以墊塊選擇信 號MS來選擇之有關記憶墊塊之共用開關MO S電晶體， 乃以與該記億墊塊相對應之墊塊控制器被控制爲0 F F狀 態。 由P溝道型MOS電晶體Q9、Q1 0及P溝道型 Μ 0 S電晶體Q 1 3、Q 1 4所構成之靜態閂鎖（stati-c latch )形態之差動放大電路，乃爲由CMO S閂鎖電 路所成之一個感測放大器3;感測放大器3乃每按互捕資 料線各被設置。感測放大器3之工作電源乃經由傳動線路 SDN、SDP被供給。傳動線路SDN、SDP亦各對 感測放大器3爲共用者。關於向傳動線路SDN、SDP 之工作電源之供給控制，請容後說明。並且，在各個之互 補資料線，除上述感測放大器3外，亦備有：動態RAM 等待時’使互補資料線均衡（equalize)之MO S電晶體 Q21=MOS電晶體Q21，乃由控制信號0PCSB 來進行開關控制。進一步，亦設有與互捕資料線之均衡調 整’同時對互捕資料線供給預充電電位所用之MO S電晶 體Q 1 7、Q 1 8。預充電電位乃爲降壓電壓VDL之一 半之電平，將經由配線HVC來供給。MOS電晶體 Q1 7、Q1 8乃由控制信號0PCB來進行開關控制。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐) &quot; -21 - -— ΙΓ I L— I - 士民--- - - n T I I - - n L, ^ ! US. 、-Jp (請先閲讀背面之注意事項再填寫本頁) 經漭部中央標準局員工消費合作社印製 A7 B7 五、發明説明（19 ) 前述控制信號0 P C B、# P C S B則從定時控制器TG 被輸出。預充電電壓VD L/2乃在預充電電壓形成電路 4所形成，例如由承接降壓電壓VD L之電阻分壓電路等 所構成。 在圖9中，Q2 3、Q2 4乃爲被設在互補資料線 DLO'DLOB與互補共用資料線CD〇 (cd〇、 cd〇B)之間之行開關；Q2 5、Q26則爲被設在互 補資料線DL1、DL1B與互補共用資料線CD1 ( cdl 、cdlB)之間之行開關。同樣之行開關亦被設 在各互補資料線，以4對之互捕資料線爲一組被共同連接 於四對之互補共.用資料線CD〇(cd〇、cd〇B)、 CD1 (cdl ' cdlB) &gt; C D 2 ( c d 2 ' c d 2 B ) ，CD3(cd3、cd3B)。 e 下面說明向感測放大器3之傳動線路SDN、SDP 供給工作電源之電路構成。 圖1乃表示有：向感測放大器3之傳動線路SDN、 S D P供給工作電源之電路。在該圖乃代表性地表示有：-17-Printed by Male Workers' Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ^ A7 B7 V. Description of the Invention (l5) MS, internal complementary column address signal AX, and internal complementary row address signal ΑΥ are assigned 4 billion grids. It is conducted to the complementary common data line CDO ~ CD3. Although the memory array MARY1 is not shown in the figure, it is constructed in the same manner as above, and complementary common data lines CD4 to CD7 are arranged on the memory array M A R Υ 1 side. Although the aforementioned mutual capture common data lines CD 0 to CD 7 are not particularly limited, they are also incorporated in the data input / output circuit D I 0. The data input circuit DI 〇 includes an amplifier (main amplifier), a write amplifier, and a data input / output buffer, and the data input operation required for writing is performed by the timing signal 0 W being set to an enable level; and The data output operation required for reading is performed by the timing signal 0 R being an enable level. The dynamic RAM of this embodiment writes and reads data in 8-digit units, and the memory array MARYO is responsible for the lower 4 digits, and the memory array MAR RY 1 is responsible for the upper 4 digits. The aforementioned address buffer RAB is an address signal input from the external address input terminals A 0 to A i via an address multiplexer (8 (1 dozen 633 1111111; 丨. 6 \ 61 ') 厶^ 1 is again taken in for holding. This taking action is instructed by the high level of the timing signal XL supplied from the timing generating circuit TG. The address multiplexer A M X, although not particularly limited However, when the dynamic RAM becomes the normal operation mode, the timing generator circuit TG has: a timing signal ¢ 5 REF that disables the level (disable levei) is supplied; thus, it will be supplied via the external terminals A 0 to A i The supplied address signal is transmitted to the address buffer RAB. In addition, the dynamic RAM is used as the CBR (This paper size applies the Chinese national standard (CNS> A4 specification (210X297 male cage)) (Please read the precautions on the back before filling in this Page) 'Equipment. Book-18-Printed by A7, ^ __ B7______, Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (16) CAS before RA S) When the refresh cycle is refreshed, the above timing signal # REF is set to the enable level, the new address counter will be selected refresh address counter) The re-new address signal provided by the REC is transmitted to the column buffer RAB. The re-new address counter RF C, although there are no special restrictions, dynamic RAM has become the new mode of CBR. (CBR refresh mode), it will perform a counting operation in synchronization with the timing signal 0RC supplied from the timing generation circuit TG every predetermined cycle (CyCie) to generate a new address. The aforementioned line address buffer CAB will pass the aforementioned The row address signals supplied from the external address input terminals A 0 to A i are synchronized with the timing of the control signal "YL" provided by the timing generation circuit TG, and are fetched and held. The aforementioned timing generation circuit TG , Will be supplied as an external access signal ': ROW address strobe signal RAS * (symbol * means: the signal with this number is the row enable column enable signal), row Address latch control CAS *, write enable signal WE *, and output enable signal 0E *, etc .; and based on these levels and change timings to determine the operation mode of the dynamic RAM, and also form the above Various timing signals to control the internal operation of the dynamic RAM. The column address latching signal RAS * indicates the chip selection by its low level, and notifies that the address signal is valid. Therefore, the timing controller TG The address signals will be taken in, and then generated in sequence: the aforementioned control signals required for the word line selection action or recording pad selection • Row address latch control This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (please Please read the notice on the back of the page and then fill in this page) Order -19-A7 B7 Printed by He Gong Consumer Cooperative, Central Standards Bureau of the Ministry of Performing Industry 5. Description of Invention (Π) 1 CAS * It is effective to notify the address signal Signal 0 When this is set to 1 I enable level (enable 1 eve 1) *, the timing controller TG will sequentially generate 1 I row address signal instead of 9 and the aforementioned control signal 0 1 1 1 required for row selection The input enable letter W Ε 由 writes the DRA Μ instruction according to its enable level. 1 1 Enter gCJ. The output enable signal DE氺 It also reads back to the cabinet by its enabling level] 1 DRA Μ indicates the readout action. The new mode of CBR is in the address latching control plane \ I 1 IRAS * Become the enabler &gt; The control CAS is designated as the enable level of item 1 and then filled in the writing book. Figure 9 shows that there is .. 1 /. The memory block Μ Μ AT 0, page 1 Μ Μ A Τ 1 sense The partial circuit diagram of the sense amplifier 1 ^ block SA 0 1 and the row switch circuit area 1 1 block CSW 0 1 is particularly representative of the circuit part that accepts a 1-row selection signal YS 0 0 in this figure. In 1 ci.i figure 1, the M 0 S transistor with an arrow attached to the channel (reverse brake) part is a P channel 1 1 type N channel M 0 S transistor without a hoe. Difference 〇1 I WL 0 WL i represented in FIG. 9 is a word line, 1 fL DL 0, DL 0 Β, DL 1, DL 1 Β are complementary data lines »I Μ C is a dynamic memory cell (dy nam i C memory cel 1) C dynamic record 1 1 I memory grid MC is selected by the data line connected M 0 S transistor Q 1 and I τ · 1 internal storage capacity (stored capac ity) sc The series circuit is connected to the plate electrode (pi at e) potential P &gt; L (VDL / 2) ^ Q 2 7, 1 Q 3 4 is a data line shared switch (shar in g SW for r ~ Hr) it ch) The common switch M 0 S transistor, which is a part of the circuit 1 I, is a common switch M 0 S transistor 1 1 IQ 2 7 Q, which is arranged between the memory pad 1 and M AT 0. 3 0 is The letter ψ S Η RL is switched on and off 1 1 1 This paper size is applicable to China National Standards (CNS) A4 specifications (210X297 Gongchu) -20-Printed by &quot; -Ministry Central Bureau of Standards Consumers &quot; A7 '____B7___ V. Description of the invention (18); The representatively represented common switch MOS transistor Q3 1 ~ Q34, which is arranged between the block 100 million and MMA T 1, is switched by the control signal 0 S HRR control. For example, when the pad selection signal MS selects the memory pad MMATO, the pad controller MCNTO 1 controls the control signal 0 S HRR to a high level. The common switch MOS transistor of the memory pad which is not selected by the pad selection signal MS is controlled to the 0 F F state by a pad controller corresponding to the 100 million pad. The differential amplifier circuit in the form of a static latch (stati-c latch) composed of P-channel MOS transistors Q9, Q1 0 and P-channel MOS transistor Q 1 3, Q 1 4 is A sense amplifier 3 formed by a CMO S latch circuit; the sense amplifiers 3 are set for each press data acquisition line. The working power of the sense amplifier 3 is supplied via the transmission lines SDN and SDP. The transmission lines SDN and SDP are also paired with the sense amplifier 3 as a sharer. Regarding the supply control of the drive line SDN and SDP, please explain later. In addition, in addition to the above-mentioned sense amplifier 3, each complementary data line also has a MO S transistor Q21 = MOS transistor Q21 that equalizes the complementary data line when the dynamic RAM waits, which is controlled by a signal 0PCSB for switch control. Further, there are also provided MOS electric crystals Q 1 7 and Q 1 8 for supplying the pre-charging potential to the inter-capture data line at the same time. The precharge potential is a half of the step-down voltage VDL and will be supplied via the wiring HVC. The MOS transistors Q1 7, Q1 8 are controlled by the control signal 0PCB. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) &quot; -21--ΙΓ IL- I-Shimin -----n TII--n L, ^! US., -Jp (Please read the precautions on the back before filling in this page) A7 B7 printed by the Ministry of Standards, Bureau, and Consumer Cooperatives V. Invention Description (19) The aforementioned control signals 0 PCB and # PCSB are output from the timing controller TG. The precharge voltage VD L / 2 is formed in the precharge voltage forming circuit 4, for example, a resistor divider circuit that receives the step-down voltage VD L and the like. In Fig. 9, Q2 3 and Q2 4 are switches installed between the complementary data line DLO'DLOB and the complementary common data line CD0 (cd〇, cd〇B); Q2 5, Q26 are set Switch between the complementary data lines DL1, DL1B and the complementary common data lines CD1 (cdl, cdlB). The same line switch is also set on each complementary data line, with 4 pairs of mutual capture data lines as a group that are commonly connected to four pairs of complementary common lines. Use data lines CD〇 (cd〇, cd〇B), CD1 ( cdl 'cdlB) &gt; CD 2 (cd 2' cd 2 B), CD3 (cd3, cd3B). e The following describes the circuit configuration for supplying operating power to the drive lines SDN and SDP of the sense amplifier 3. FIG. 1 shows a circuit that supplies working power to the transmission lines SDN and S D P of the sense amplifier 3. The figure is representative of:

1隊列份量之感測放大器3，但圖中所示代表性之傳動線 路SDN、SDP乃包含在本實施例之DRAM之所有感 測放大器3所用之傳動線路SDN、SDP之總稱者。在 傳動線路SDN，乃經由以控制信號0SA1B來進行開 關控制之P溝道型MO S電晶體Q 4 1 ，供給有外部電源 電壓；並且’經由以控制信號^ SA2 B來進行開關控制 之P溝道型MOS電晶體Q42，供給有降壓電壓VDL 本紙張尺度適用中國國家標準（CNS ) A4規格（210_X297公釐） (請先閲讀背面之注意事項再填寫本頁)The sense amplifiers 3 of one queue weight, but the representative transmission lines SDN and SDP shown in the figure are the general term of the transmission lines SDN and SDP used in all the sense amplifiers 3 included in the DRAM of this embodiment. In the transmission line SDN, a P-channel type MO S transistor Q 4 1 for switching control by a control signal 0SA1B is supplied with an external power supply voltage; and a P-channel for switching control through a control signal ^ SA2 B Dome MOS transistor Q42, supplied with step-down voltage VDL This paper size is applicable to China National Standard (CNS) A4 specification (210_X297 mm) (Please read the precautions on the back before filling this page)

A7 . __^_____B7__.__ 五、發明説明（20) 。控制信號0SAN，？）SA1B 、0SA2B則由前述 定時控制器TG碎輸出。 有關此一例子之DRAM，乃如前述，將從外部電源 端子承接如3. 3V之外部電電源電壓VDD;但爲記憶 容量之增大，在記憶陣列MARYO，MARY1之 MO S電晶體將被小型化；由此，隨此等MO S電晶體之 閘極長之縮小化閘極氧化膜已被薄膜化；放在記憶陣列 M A R Y 0，M A R Y 1之工作電壓將被低電壓化，例如 乃以如2 . 2 V之降壓電壓VD L作爲基本之工作電源。 此時，對傳動線路S D P僅供給降壓電壓VD L，則感測 放大器3之工作速度將趨慢；故對傳動線路S D P乃適用 :在感測放大器活性化定時之最初給與外部電源電壓 VDD，接著再給與降壓電壓VDL，使感測放大器動作 等之感測放大器過激勵技術。 好濟部中央標準局負工消费合作社印製 ^^^1 —«I (H I - - In n^i .*义 I (請先閱讀背面之注意事項再填寫本頁) 亦即，如圖2所示，當規定感測放大器2之活性化期 間之控制信號0SAEB (定時控制器TG之內部控制信 號，圖1中未圖示），被變化爲低電平之有效電平（3£：1:-ive level );則首先，控制信號必S A 1 B將被變化爲 低電平，而經由MOS電晶體Q41 ，電源電壓VDD將A7. __ ^ _____ B7 __.__ 5. Description of the invention (20). Control signal 0SAN? ) SA1B and 0SA2B are output by the aforementioned timing controller TG. As for the DRAM of this example, the external electric power supply voltage VDD such as 3.3V will be received from the external power supply terminal as described above; but to increase the memory capacity, the MOS transistor of the memory array MARYO, MARY1 will be small As a result, the gate oxide films of these MOS transistors have been reduced in size; the operating voltages placed in the memory arrays MARY 0 and MARY 1 will be lowered, for example, such as The 2.2 V step-down voltage VD L is used as the basic working power supply. At this time, only the step-down voltage VD L is supplied to the transmission line SDP, the working speed of the sense amplifier 3 will become slower; therefore, it is applicable to the transmission line SDP: the external power supply voltage VDD is initially given at the timing of the activation of the sense amplifier Then, a step-down voltage VDL is given to the sense amplifier over-excitation technology to make the sense amplifier operate. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of Ho Chi Minh City As shown, when the control signal 0SAEB (the internal control signal of the timing controller TG, not shown in Figure 1) is specified during the activation period of the sense amplifier 2, it is changed to a low level effective level (3 £: 1 : -ive level); First, the control signal SA 1 B will be changed to a low level, and the power supply voltage VDD will be changed via the MOS transistor Q41.

被供給至傳動線路SDP。由此，因從感測放大器3之P \ 溝道型MO S電晶體Q 1 4所供給之電流較大，由記憶格 之選擇動作顯現在互補資料線D L 0、D L Ο B之微小電 位差，將迅速被放大。接著，控制信號0 SA 1 B將反轉 至高電平，同時控制信號0SA2B亦被成爲低電平；由 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ' -23 - 經滴部中央標4'-局si工消费合作杜印製 A7 ' ___B7 ____^_ 五、發明説明（21 ) 此，將經由MO S電晶體Q 4 2向傳動線路s D P供給降 壓電壓。控制信號0 SAN將控制信號¢) S AE B之低電 平期間同步被成爲高電平。由此，由感測放大器3被驅動 之互補資料線之到達電平，將被規定成一方爲接地電位， 另一方爲降壓電壓VD L。如此，將記憶陣列之低電壓驅 動下之感測放大器3之放大動作加以高速化。在圖2中， 0 D T將作爲過激勵（over drive )時間。此外，因開關 M〇 S電晶體Q4 1及Q4 2乃被結合成並聯形態，故電 源電壓VD.D及降壓電壓VD L將各經由一個開關MO S 電晶體被供給至傳動線路SDP。因此，與開關MOS電 晶體被結合成串聯形態之情形比較，可將開關電路之Ο N 阻抗減小。 降壓電路1乃備有：被結合於外部電源電壓VDD之 P溝道型之MO S電晶體Q 5 0與被結合在接地電位 VS S之高電阻R 1之串聯連接點，作爲輸出端子N o u t ;並備有：.該輸出端子N 〇 u t反饋至非倒相輸入端子 (+)，基準電壓VLR則被供給至倒相輸入端子（一） ，以對前述MO S電晶體Q 5 0進行開關控制乏運算放大 器（operational amplifier) AMP 1 ;等所構成。前 述運算放大器AMP 1 ，將進行負反饋控制成爲：在輸出 \ 端子No u t之電位成爲較基準電位VLR爲低，則使 M0S電晶體Q50之電導增大（使ON阻抗減小）：而 輸出端子N 〇 u t之電位成爲較基準電位VLR爲高，則 使M0S電晶體Q 5 0之電導減小（使ON阻抗增大）， 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） &quot;&quot; _ 24 _ (請先聞讀背面之注意事項再填寫本頁) 裝It is supplied to the transmission line SDP. Therefore, because the current supplied from the P \ channel type MO S transistor Q 1 4 of the sense amplifier 3 is large, the selection action of the memory cell appears on the small potential difference of the complementary data lines DL 0 and DL Ο B, Will be zoomed in quickly. Then, the control signal 0 SA 1 B will be reversed to a high level, and at the same time, the control signal 0SA2B will also be changed to a low level; this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) '-23-Jing Dibu Central standard 4'- bureau SI industrial consumer cooperation Du printed A7 '___B7 ____ ^ _ V. Description of the invention (21) Therefore, the step-down voltage will be supplied to the transmission line s DP via the MO S transistor Q 4 2. Control signal 0 The SAN will control the signal ¢) S AE B during the low level to be synchronized to a high level. Therefore, the reach level of the complementary data line driven by the sense amplifier 3 will be defined as one of the ground potentials and the other of the step-down voltage VD L. In this way, the amplification operation of the sense amplifier 3 driven by the low voltage of the memory array is accelerated. In Figure 2, 0 D T will be used as the over drive time. In addition, since the switches MOS transistors Q4 1 and Q4 2 are combined in parallel, the power supply voltage VD.D and the step-down voltage VD L are each supplied to the transmission line SDP via a switch MOS transistor. Therefore, compared with the case where the switching MOS transistor is combined in a series configuration, the ON resistance of the switching circuit can be reduced. The step-down circuit 1 is provided with a series connection point of a P-channel type MO S transistor Q 50 connected to an external power supply voltage VDD and a high resistance R 1 connected to a ground potential VS S as an output terminal N. out; and provided: the output terminal No is fed back to the non-inverting input terminal (+), and the reference voltage VLR is supplied to the inverting input terminal (1) to perform the aforementioned MO S transistor Q 50 Operational control amplifier (operational amplifier) AMP 1; and so on. The aforementioned operational amplifier AMP 1 will perform negative feedback control such that at the output \ terminal No ut potential becomes lower than the reference potential VLR, the conductance of the M0S transistor Q50 is increased (the ON impedance is reduced): and the output terminal The potential of No ut becomes higher than the reference potential VLR, so that the conductance of the M0S transistor Q 50 is reduced (the ON impedance is increased). This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 male) Li) &quot; &quot; _ 24 _ (Please read the notes on the back before filling in this page)

*1T* 1T

Q 經漪部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（22 ) 以使將輸出端子N 〇 u t之電壓保持在基準電壓V L R等 狀態。如此被形成在輸出端子N 〇 u t之電壓將作爲降壓 電壓VDL。尤其爲將流入MOS電晶體Q 5 0及電阻 R 1以及串聯電路之貫通電流抑制於最小限度，電阻R 1 之值將被設定成非常大之值。在前述負反饋控制中，經由 高電阻R1流入輸入端子No u t之電流，將被減少至實 質上可忽視之程度。此外，基準電壓V L R乃爲由例如未 圖示之周知之基準電壓發生電路所形成之控制電壓，被定 爲例如2 . 2 V » 在此，外部電源電壓VDD乃爲例如3. 3V，惟利 用可能之電源電壓，通常乃容認有± 1 0%左右之容許範 圍。因此，爲了作爲外部電源電壓VDD被供給其容許範 圍之下限電平時，亦能夠謀求感測放大器3之瞬態響應（ transient response)動作之_高速化，將需設定前述控制 信號必S A 1 B之有效（active)期間（過激勵時間 ODT)。因此，僅以如此觀點來固定前述過激勵時間， 則因被供給之外部電源電壓V D D在容許範圍之上限電平 ，或因電源電壓VDD側之動作容限試驗等被供給特別高 之外部電源電壓VDD時，而當感測放大器3之工作電源 從外部電源電壓VD D被轉換爲降壓電壓VD L時，電流 \ 將從傳動線路SDP向降壓電路1之輸出端子No u t倒 流。倒流之電流將無法期望如前述經由高電阻R 1立即被 放電至接地電位VSS。而來自傳動線路S D P之倒流電 流將逐漸使降壓電壓V D L之電平上昇，隨之亦使互補資 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —^—-L— Γ1')裝----；—訂------^w (許先閲讀背面之注意事項再填鸾本頁) -25 - 鳑济.部中央標革局t貝工消费合作社印^ A7 B7 五、發明説明（23 ) 料線之預充電電平（VDL/ 2)上昇。 在此種例子中，，乃將過激勵時間ODT按電源電壓 VDD之電平，可變地控制成：能阻止電流如上述之傳動 線路S D P向降壓電路1倒流般之過剩之過激勵狀態爲構 成。 爲此所需之定時形成電路，乃作爲圖1所示之定時控 制器TG之一部分來表示。亦即，在規定前述感測放大器 3之活性化期間之控制信號# S A E B之低電平期間，乃 最初將前述控制信號0 S A 1 B加以活性化，接著再將前 述控制信號0 S A 2 B加以活性化，如此將雙方之控制信 號《SA1B、0SA2B互補地使其變化；故此乃各設 有2輸入形式之NAND閘10及NOR閘1 1 ，而 NAN D閘1 〇與NOR閘1 1之一方之輸入端子亦互相 結合，並且在NAND閘1 0之其一方之輸入端子與另一 方之輸入端子之間，則配置有：將奇數個之CMO S反相 器INV0〜INVi (i=2n — 1)加以串聯連接之 延遲電路1 2。圖4乃表示延遲電路之具體之一例電路者 。在前述NAND閘1 〇之另一方之輸入端子，乃經由 CMOS反相器13，供給有控制信號0SAEB，而 Ν Ο R閘1 1之另一方之輸入端子’亦供給有控制信號 0SAEB 。控制信號0SA1B乃從NAND閘10被 輸出，控制信號0SA2B則將NOR閘11之輸出以 MO S反相器1 4來倒相後所形成。控制信號0 S AN亦 將前述控制信號0 SAE B通過串聯3段之CMO S反相 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） * - - /、' 11 If . ^衣 . 訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局吳工消#合作社印？木 A7 B7 五、發明説明（24 ) 器15、16來形成。 包含在定時控制信號TG之電路之工作電源，乃爲外 部電源電壓VDD及接地電位VS S。前述延遲電路1 2 所含之CMOS反相器I NVO〜I NV i之串聯段數， 乃被決定成：在外部電源電壓VDD於其容許範圍之下限 電平時，亦可獲得能謀求感測放大器3之瞬態響應動作之 高速化之充分之過激勵時間〇 D T之狀態。在此，規定過 激勵時間ODT之前述延遲電路12之CMOS反相器 I NV0〜.1 NV i ，乃如圖4所示，作爲電源電壓將承 接外部電源電壓V D D »各反相器因其工作電源電壓愈高 ，瞬態響應時間亦成爲愈短，放在外部電源電壓（VD D )較低時，過激勵時間相對地將成較長，外部電源電壓（ VDD)較高時，則過激勵時間將相對地成爲較短。因此 ，延遲電路之延遲時間將對外部電源電壓（VDD)具有 負之依存性。所以，供給之外部電源電壓VD D爲容許範 圍之上限電平，或爲了電源竃壓VDD側之動作範圍試驗 ，供給特別高之外部電源電壓VDD時，延遲電路1 2之 延遲時間將相對地被趨短，而相對地電平較高之外部電源 電壓VDD經由MOS電晶體Q41被供給至傳動線路 SD P之時間亦將趨短。由此，將可防止：由相對地電平 較高之外部電源電壓，使感測放大器3被過剩地進行過激 勵之現象。 因此，作爲構成延遲電路之反相器之電源電壓’使用 過激勵用之電壓（VD D )，由此即可以簡單構成來確實 本紙張尺度適用中國S家標準（CNS ) A4規格（210X 297公釐） (諳先閩讀背面之注意事項再填寫本頁) 裝_ 訂 -27 - 經濟部中央樣準局貝工消費合作社印製 A7 ' ___ B7___________ 五、發明説明（25 ) 控制過激勵時間。 由於對感測放大器3能過防止過激勵趨於過剩，故亦 可阻止從多數之感測放大器3向降壓電路1電流倒流之事 態發生；因此，由此亦可防止：降壓電壓VD L被不希望 地無限制上昇電平之事態發生。因此，將可阻止：工作電 壓向低電壓化時之電路可靠性，因降壓電壓VDL不按所 求地被昇高電平而被迫降低之事態發生。例如，因感測放 大器3之放大動作所引起資料線之到達電壓，使降壓電壓 VD L之昇高電平因此趨高；由此將可防止：字線之選擇 電平與資料線之高電平之間之電位差趨小，因而，在向記 憶格之高電平寫入中，存儲容量S C可防止無法被外加資 料線之該高電平之電壓。而且，因前述降壓電壓VDL之 不希求之電平上昇，若使感測放大器3所生資料線之到達 電壓被昇高，則與此相應，於晶片非選擇期間被補償（ equalize)之資料線之初始性電平之預充電電平亦將上昇 :在此狀態下被寫入之資料若被讀出時，亦可防止：對預 充電之高電平之讀出電壓容限將被縮小等現象。進一步， 形成字線選擇電平之昇壓電路2，乃利用前述降壓電壓 VD L時，降壓電壓VD L之不希求之電平高昇，即使將 使字線選擇電平V P P上昇，惟亦無記憶格M C之選擇 MO S電晶體q 1之閘極氧化膜被破壞之虞。 圖3乃表示：生成感測放大器控制所需之控制信號 0SAN、0SA1B、0SA2B之電路之其他例子者 。該圖所示電路，乃在2輸入NOR閘2 0之一方輸入端 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝. 訂Q Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (22) In order to keep the voltage of the output terminal No ot at the reference voltage V L R and so on. The voltage thus formed at the output terminal No. will be taken as the step-down voltage VDL. In particular, in order to minimize the through current flowing into the MOS transistor Q 50 and the resistor R 1 and the series circuit, the value of the resistor R 1 will be set to a very large value. In the aforementioned negative feedback control, the current flowing into the input terminal No ut via the high resistance R1 will be reduced to a practically negligible level. In addition, the reference voltage VLR is a control voltage formed by, for example, a well-known reference voltage generating circuit (not shown), and is set to, for example, 2.2 V. Here, the external power supply voltage VDD is, for example, 3.3 V, but using The possible power supply voltage is usually within the tolerance range of ± 10%. Therefore, in order to increase the speed of the transient response operation of the sense amplifier 3 when the external power supply voltage VDD is supplied to the lower limit level of its allowable range, it is necessary to set the aforementioned control signal to SA 1 B. Active period (over-excitation time ODT). Therefore, to fix the over-excitation time only from such a viewpoint, a particularly high external power supply voltage is supplied because the supplied external power supply voltage VDD is at the upper limit level of the allowable range, or due to an operation tolerance test on the power supply voltage VDD side. At VDD, and when the operating power of the sense amplifier 3 is converted from the external power voltage VD D to the step-down voltage VD L, the current \ will be reversed from the transmission line SDP to the output terminal No ut of the step-down circuit 1. The reverse current cannot be expected to be immediately discharged to the ground potential VSS via the high resistance R 1 as described above. The reverse current from the SDP of the transmission line will gradually increase the level of the step-down voltage VDL, which will also make the complementary capital paper scale apply the Chinese National Standard (CNS) A4 specification (210X297 mm) — ^ —- L— Γ1 ' ) Installed ----;-ordered ------ ^ w (Xu first read the precautions on the back and then fill out this page) -25-Relief. Printed by the tbeigong consumer cooperative of the Central Bureau of Standard Leather Industry ^ A7 B7 V. Description of the Invention (23) The precharge level (VDL / 2) of the material line rises. In this example, the over-excitation time ODT is variably controlled according to the level of the power supply voltage VDD so that the excessive over-excitation state that can prevent the current from flowing backward as the above-mentioned transmission line SDP to the step-down circuit 1 is Make up. The timing forming circuit required for this purpose is shown as part of the timing controller TG shown in FIG. That is, during the low-level period of the control signal #SAEB that defines the activation period of the aforementioned sense amplifier 3, the aforementioned control signal 0 SA 1 B is initially activated, and then the aforementioned control signal 0 SA 2 B is applied. Activation, so that the two control signals "SA1B, 0SA2B complement each other to change; therefore, each of them is provided with a NAND gate 10 and a NOR gate 1 1 of 2 inputs, and one of the NAN D gate 1 0 and the NOR gate 1 1 The input terminals are also combined with each other, and between one input terminal of the NAND gate 10 and the other input terminal, it is configured: an odd number of CMO S inverters INV0 ~ INVi (i = 2n — 1 ) Add a delay circuit 12 connected in series. FIG. 4 is a circuit example showing a specific example of the delay circuit. The other input terminal of the aforementioned NAND gate 10 is supplied with a control signal 0SAEB via the CMOS inverter 13, and the other input terminal of the NR gate 11 is also supplied with a control signal 0SAEB. The control signal 0SA1B is output from the NAND gate 10, and the control signal 0SA2B is formed by inverting the output of the NOR gate 11 with the MO S inverter 14. The control signal 0 S AN also reverses the aforementioned control signal 0 SAE B through the CMO S of 3 segments in series. The paper size applies the Chinese National Standard (CNS) A4 (210X297 mm) *--/, '11 If. ^ Order (please read the notes on the back before filling out this page) Wu Gongxiao #college seal of the Central Standards Bureau of the Ministry of Economic Affairs? Wood A7 B7 V. Description of the invention (24) The devices 15, 16 are formed. The working power supply of the circuit included in the timing control signal TG is the external power supply voltage VDD and the ground potential VSS. The number of series sections of the CMOS inverters I NVO to I NV i included in the aforementioned delay circuit 12 is determined as follows: When the external power supply voltage VDD is below the lower limit of its allowable range, a sense amplifier can also be obtained. The state of the transient response action of 3 is the state of sufficient over-excitation time 0DT. Here, the CMOS inverters I NV0 ~ .1 NV i of the aforementioned delay circuit 12 that specify the over-excitation time ODT are as shown in FIG. 4. As the power supply voltage, they will take the external power supply voltage VDD. The higher the power supply voltage, the shorter the transient response time. When the external power supply voltage (VD D) is low, the over-excitation time will be relatively long. When the external power supply voltage (VDD) is high, the over-excitation will be Time will be relatively short. Therefore, the delay time of the delay circuit will have a negative dependency on the external power supply voltage (VDD). Therefore, when the supplied external power supply voltage VD D is the upper limit of the allowable range, or for the test of the operating range of the power supply VDD side, when a particularly high external power supply voltage VDD is supplied, the delay time of the delay circuit 12 will be relatively It will become shorter, and the time when the external power supply voltage VDD, which has a relatively high ground level, is supplied to the transmission line SD P via the MOS transistor Q41, will also become shorter. As a result, the excessive excitation of the sense amplifier 3 by the external power supply voltage having a relatively high ground level can be prevented. Therefore, as the power supply voltage of the inverter constituting the delay circuit, an over-excitation voltage (VD D) is used, so that it can be simply constructed to ensure that this paper size is compatible with the Chinese Standard (CNS) A4 specification (210X 297 mm) (%) (I read the notes on the reverse side before filling out this page) Binding_Order-27-Printed A7 '___ B7___________ printed by the Shellfish Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs 5. Description of the invention (25) Control over the incentive time. Since the over-excitation of the sense amplifier 3 can be prevented too much, it can also prevent the current from flowing back from the majority of the sense amplifiers 3 to the step-down circuit 1; therefore, it can also prevent: the step-down voltage VD L Undesirably rising levels occur. Therefore, the reliability of the circuit when the operating voltage is lowered can be prevented from being forced to decrease because the step-down voltage VDL is not raised as required. For example, the arrival voltage of the data line caused by the amplification action of the sense amplifier 3 causes the rising level of the step-down voltage VD L to become higher; thus, it can prevent: the selection level of the word line and the high data line The potential difference between the levels becomes smaller. Therefore, in writing to the memory cell at a high level, the storage capacity SC can prevent the high level voltage from being applied to the data line. Moreover, because the undesired level of the aforementioned step-down voltage VDL rises, if the arrival voltage of the data line generated by the sense amplifier 3 is increased, correspondingly, the data is equalized during the non-selection period of the chip. The precharge level of the initial level of the line will also rise: if the data written in this state is read, it can also prevent: the read voltage tolerance for the high level of precharge will be reduced And other phenomena. Further, the step-up circuit 2 forming the word line selection level utilizes the undesired level of the step-down voltage VD L when the step-down voltage VD L is used, even if the word line selection level VPP is increased, but There is also no possibility that the gate oxide film of the MO S transistor q 1 is destroyed by the memory cell MC. Figure 3 shows other examples of circuits that generate the control signals 0SAN, 0SA1B, and 0SA2B required for the control of the sense amplifier. The circuit shown in the figure is installed on one side of the 2 input NOR gate and 2 0 side. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Order

L -28 - 經濟部中夾標準局員工消费合作社印製 A7 ' ， B7 ______ 五、發明説明（26 ) 子被供給有前述控制信號4 SAEB，而在該NOR閘 2 0之一方輸入端子與另一方輸入端子之間，則配置有決 定過激勵時間所用之延遲電路2 1。前述控制信號 沴SAN乃將控制信號# SAE B以CMO S反相器2 2 來加以倒相所形成，控制信號0 S A 1 B則將N 0 R閘 2 0之輸出以CMO S反相器2 3來加以倒相所形成，而 控制信號0SA2B則將延遲電路2 1之輸出以CMOS 反相器2 4來加以倒相所形成。由該圖所示之邏輯構成， 基本上亦可形成圖2所示之波形之控制信號$ SAN、 0SA1B、0SA2B。尤其是圖3之情形，前述延遲 電路2 1亦由奇數段之CMOS反相器I NV0、 INV1、INV3與CR延遲電路25之串聯電路所構 成。CR延遲電路2 5乃爲由如電容元件或電阻元件等之 從動電路元件所構成之延遲要素；與CMO S反相器不同 ，其延遲時間乃對電源電壓未具有負之依存性。如圖1所 示之延遲電路1 2，僅以CMO S反相器來構成時，若延 遲時間之電源電壓依存性過大而不方便時，乃如圖3將延 遲時間不具有電源電壓依存性之C R延遲電路與CMO S 反相器加以組合來構成延遲電路，方爲良策。此外，在圖 1之邏輯構成中，採用圖3之延遲電路2 1 ，亦當然爲可 \ 能。 上述之例子僅爲其一例，在不脫離本發明之要旨之範 圍內將可作種種變更，亦爲不必贅言者。例如，降壓單元 1 0之電流源不限定於利用運算放大器來進行負反饋控制 本紙張尺度適用中國S家標準（CNS ) A4規格（210X 297公釐) ~~~ -29 - (計先閱讀背面之注意項再填窍本頁) 裝· 丁 -ο -k 經濟部中央標來局S(工消费合作社印製 A7 · ___B7____ 五、發明説明（27 ) 之構成。並且，DRAM之記億墊塊構成、墊塊選擇之邏 輯構成、資料之並聯輸出入數元數等’亦不限定於上述實 施例，可作適宜之變更。並且，生成感測放大器控制所用 之控制信號0SAN、&lt;^SA1B.、&lt;]&amp;SA2B之電路之 邏輯構成，亦不限定於圖1及圖3，而可作適宜之變更。 作爲延遲機構，MO S鼋路亦不限定於CMO S反相器， 可以NAND、NOR等等邏輯閘來構成。延遲時間對電 源電壓具有負之依存性之電路，亦不限定於僅具有MO S 電晶體之電.路，含有雙極性電晶體_( bipolar transistor )等其他之電路元件來構成亦可。 圖5乃表示對感測放大器之傳動線路SDN、SDP 供給工作電源所用之其他例子之電路者。在圖5及前述圖 _ 1中，共同之部份乃附有相同之符號。 傳動線路S D N乃被供給在N溝道型MO S電晶體 &lt;99及Q 1 0之共用汲極，傳動線路SDP則被結合在P 溝道型MO S.電晶體Q 1 3及Q 1 4之共用汲極。在該圖 亦代表性地表示有1隊列份量之感測放大器3，惟在圖中 代表性地被表示之傳動線路SDN，SDP，乃爲本實施 例之D R A Μ所含之所有感測放大器3所用之傳動線路 SDN、SD. Ρ之總稱者。在傳動線路SDN，乃經由以 \L -28-Printed A7 ', B7 by the Consumer Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs 5. The invention description (26) is supplied with the aforementioned control signal 4 SAEB, and the input terminal of one of the NOR gates 20 and another Between one input terminal, a delay circuit 21 for determining the overexcitation time is arranged. The aforementioned control signal 沴 SAN is formed by inverting the control signal # SAE B with the CMO S inverter 2 2, and the control signal 0 SA 1 B uses the output of the N 0 R gate 2 0 with the CMO S inverter 2 3 is formed by inverting, and the control signal 0SA2B is formed by inverting the output of the delay circuit 21 with a CMOS inverter 24. By the logic structure shown in the figure, the control signals $ SAN, 0SA1B, 0SA2B of the waveform shown in FIG. 2 can basically be formed. Particularly in the case of FIG. 3, the aforementioned delay circuit 21 is also constituted by a series circuit of the odd-numbered CMOS inverters I NV0, INV1, INV3, and the CR delay circuit 25. The CR delay circuit 25 is a delay element composed of a passive circuit element such as a capacitor element or a resistance element; unlike the CMO S inverter, its delay time does not have a negative dependence on the power supply voltage. When the delay circuit 12 shown in FIG. 1 is constituted only by a CMO S inverter, if the power supply voltage dependency of the delay time is too large and inconvenient, the delay time does not have the power supply voltage dependency as shown in FIG. 3 It is a good idea to combine a CR delay circuit with a CMO S inverter to form a delay circuit. In addition, in the logical configuration of FIG. 1, it is of course possible to use the delay circuit 2 1 of FIG. 3. The above examples are just examples, and various changes can be made without departing from the spirit of the present invention, and needless to say. For example, the current source of the step-down unit 10 is not limited to the use of an operational amplifier for negative feedback control. The paper size is applicable to China Standard S (CNS) A4 specifications (210X 297 mm) ~~~ -29-(count first read Note on the back, fill in this page again.) Ding-o-k Central Bureau of the Ministry of Economic Affairs, Bureau S (printed by Industrial and Consumer Cooperatives A7 · ___B7____ V. Composition of the invention description (27). And, DRAM is worth 100 million pads. The block configuration, the logical configuration of the block selection, the parallel input and output numbers of data, etc. are not limited to the above-mentioned embodiment, and can be changed as appropriate. In addition, the control signal 0SAN used for controlling the sense amplifier is generated, &lt; ^ SA1B., &Lt;] &amp; SA2B The logical structure of the circuit is not limited to Figures 1 and 3, but can be changed as appropriate. As a delay mechanism, the MO S circuit is not limited to the CMO S inverter It can be composed of logic gates such as NAND, NOR, etc. Circuits whose delay time has a negative dependency on the power supply voltage are not limited to circuits with only MO S transistors. Circuits include bipolar transistors, etc. Other circuit elements may be used. 5 is a circuit that represents other examples of the circuit used to supply working power to the drive circuit SDN and SDP of the sense amplifier. In Figure 5 and the previous figure _1, the common parts are attached with the same symbols. The drive circuit SDN is The common drains of N-channel type MO S transistors &lt; 99 and Q 1 0 are supplied, and the drive line SDP is incorporated in the common drains of P-channel type MO S. transistors Q 1 3 and Q 1 4. In this figure, the sense amplifiers 3 with 1 queue are representatively shown. However, the transmission lines SDN and SDP represented in the figure are representative of all the sense amplifiers 3 included in the DRA M of this embodiment. The general name of the transmission line SDN and SD. P. The transmission line SDN is based on \

控制信號4 S AN來進行開關控制之Ν溝道型MO S電晶 體Q 4 0，有接地電位V S S被供給其中。在傳動線路 SDP，亦經由以控制信號0 SAP 1 B來進行開關控制 之P溝道型MO S電晶體Q 4 1 ，有外部電源電壓VD D 义法尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 -30 - 經濟部中央標聿局員工消f合作社印製 A7 ' ________ B7 _ 五、發明説明（28 ) 被供給其中；並且經由以控制信號0 s AN 2來進行開關 控制之N溝道型MOS電晶體Q42 —，亦有降壓電壓 VDL被供給其中。控制信號0SAN、0SAP1B、 0 S AN 2及從前述定時控制器TG被輸出。The N-channel MOS transistor Q 4 0 which is controlled by the control signal 4 S AN for switching control is supplied with a ground potential V S S. In the transmission line SDP, the P-channel type MO S transistor Q 4 1 which is controlled by the control signal 0 SAP 1 B is also used. There is an external power supply voltage VD D. The legal standard applies to the Chinese National Standard (CNS) A4 specification ( 210X 297mm) (Please read the notes on the back before filling out this page) Pack. Book-30-Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs, F7, A7 '________ B7 _ V. Description of the invention (28) was provided Among them, and through the N-channel MOS transistor Q42-which is controlled by the control signal 0 s AN 2, a step-down voltage VDL is also supplied. The control signals 0SAN, 0SAP1B, 0 S AN 2 and the aforementioned timing controller TG are output.

形成控制信號0SAN、0SAP1B 、0SAN2 之電路，乃作爲圖1所示定時控制器TG之一部分被表示 。亦即，爲能在規定前述感測放大器3之活性化期間之控 制信號0SAEB (定時控制器TG之內部控制信號，在 圖1未圖示.）之低電平期間，最初將前述控制信號 4 SAP 1 B加以活性化，接著再將前述控制信號 4 SAB 2加以活性化，乃各設有2輸入形式之NAND 閘10及NOR閘11 ;並且，NAND閘10及NOR 閘1 1之一方之輸入端子亦互相結合，而在NAND閘 1 0之其一方之輸入端子與另一方輸入端子之間，亦配置 有：將奇數個之CMOS反相器INV0〜INVi ( i =2 η — 1 )加以串聯連接之延遲電路1 2。在前述 NAND閘10之另一方輸入端子，亦經由CMO S反相 器1 3，供給有控制信號0SAEB，在NOR閘1 1之 另一方輸入端子則供給有控制信號0 S A E B。控制信號 0 S A P 1 B乃從前述NA ND閘1 〇被輸出，控制信號 Λ # S AN則將前述控制信號0 s ΑΕ Β通過串聯3段之 CMOS反相器15、16、17所形成。前述NOR閘 1 1之輸出0SA2乃被供給至電平變換電路6，而電平 變換電路6之輸出即成爲前述控制信號0 SAN 2。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (讀先閱讀背面之注意事項再填寫本頁) 裝· -31 - A7 B7 五、發明説明（29 ) 前述電平變換電路6乃爲將輸入信號之信號振幅加以 放大後傳達以輸出之電路，有P溝道型MO S電晶體 Q60、Q6 1與N溝道型MOS電晶體Q6 2之串聯電 路，以及P溝道型MOS電晶體Q6 3、Q6 4與N溝道 型MO S電晶體Q 6 5之串聯電路，被並聯配置在昇壓電 壓VP P與接地電位VS S之間。在MO S電晶體Q6 1 、Q6 2之閘極乃有輸入信號4.SA2被供給其中， MOS電晶體Q64、Q6 5之閘極則有輸入信號 0SA2以CMOS反相器18倒相後被供給其中。 經濟部中央標隼局員工消费合作社印裝 (讀先閱讀背面之注意事項再填寫本頁) MO S電晶體Q 6 1與Q 6 2之結合點乃被結合在MO S 電晶體6 3之閘極，而MOS電晶體Q 64與Q 6 5之結 合點則被結合在MO S電晶體Q 6 0之閘極。輸入信號. 0SA2之信號振幅乃爲接地電位VSS與電源電壓 VDD之電位差。亦即，NOR閘1·1之工作電源乃爲 VDD、VS S »控制信號？5 S A2爲電源電壓VDD 之電平時，將由MOS電晶體Q63、Q64之ON狀態 ，Μ 0 S電晶體Q6 5之OFF狀態，MOS電晶體Q6 3、&lt;36 4之〇&gt;1狀態，使控制信號03人1^2成爲昇壓 電壓V P P之電平。當控制信號0 S A 2成爲接地電位 V S S之電平，則由Μ 0 S電晶體&lt;362之0卩？狀態， ν MOS電晶體Q65之ON狀態，MOS電晶體Q60、 Q6 1之ON狀態，MOS電晶體Q6 3之OF F狀態， 控制信號？5 SAN2將成爲接地電位VS S之電平。因此 ，信號振幅成爲接地電位VS S與電源電壓VDD之電位 本紙張尺度適用中國囷家標準（CNS ) A4規格（210X297公釐） -32 - &quot;'••&quot;'t^u^^n-1消 A 合 c&quot;· 補无 A7 .' __——一_B7 五、發明説明（30 ) .· 差之輸入信號S A 2，將被變換爲信號振幅成爲接地電 位VS S與前述昇壓電壓VP P之電位差之輸出信號 VSAN2 &gt;而雙方之信號V&gt;SA2 、VSAN2之邏輯 值將被成爲一般。昇壓電壓VPP將成爲例如4. 0V。 圖6乃表示：由圖5之電路構成對傳動線路SDN、 SDP供給工作電源所用之控制信號pSAN， ^8八？18，识3八1^2之波形。 當規定感測放大器3之活性化期間之控制信號 VSAEB變化爲低電平之有效電平（active level)， 則首先，控制信號P SAP 1 B將變化爲低電平（接地電 位VSS之電平），並經由MOS電晶體Q41，電源電 壓VDD將被供給至傳動線路SD P。由此，因被供給至 感測放大器3之P溝道型MO S電晶體Q 1 3、Q 1 4之 電流較大，故由記憶格之選擇動作顯現在互補資料線 DLO «DLOB之微小電位差將迅速被放大。接著，控 制信號¢) SAP 1 B將被倒相成髙電平（電源電壓VDD 之電平），同時控制信號PSAN2亦被成爲高電平（昇 壓電壓VPP之電平）；由此，經由MOS電晶體 Q42 ~，降壓電壓VDL將被供給至傳動線路SDP » 控制信號？&gt; SAN則與控制信號p SAEB之低電平期間 同步，被成爲髙電平。由此，由感測放大器3所驅動之互 補資料線之到達電平，將被規定成：一方爲接地電位 VSS，另一方爲降壓電壓VDL之狀態。 此時，MOS電晶體Q4 2 &gt;乃爲N溝道型，將其控 本紙乐尺度4扪ί （) 圯柁（2]〇X 297公浼） ~ • .-' -- I - 1、1 -- .*-1 —- - - - 1-»-」\5J (&quot;先閱讀背而之注意事項再&quot;寫本頁) m f： &lt;, w A7 B7 五、發明説明（31 ) 制爲ON狀態之控制信號¢) SAN 2之髙電平，則成爲較 其汲極電壓（降壓電壓VD L )爲大之電壓，例如字線昇 壓電壓YPP;故該MOS電晶體Q42/之閘極•源極 間電壓將被成爲較大*而且，載流子遷移率乃Ν溝道型 MO S電晶體較Ρ溝道型MO S電晶體約大約3倍左右。 因此，如圖1之實施例，與使用Ρ溝道型MO S電晶體 Q42，以接地電位VSS將其控制爲ON狀態時比較， 可在MO S電晶體Q 4 2 &gt;獲得較大之電流供給能力。結 果，工作電源被低電壓化之狀況下，亦可使感測放大器3 進行髙速動作· N溝道型MOS電晶體Q4 2 &gt;之閘極電壓假定與汲 極電壓（降壓電壓VDL)相等時，此MOS電晶體 &lt;3 4 2 &quot;之源極電壓將等於較閘極電壓被降低MO S電晶 體Q42 /之臨限值電壓之份量。爲減少此電壓降低，在 本發明之實施例，前述閘極電壓乃被設定成較前述汲極電 壓爲髙。使前述閘極電壓成爲汲極電壓與前述臨限值電壓 之和以上，則可完全取消（cancel )前述臨限值電壓之降 低部分：故可進一步有效防止：對感測放大器之被低寧壓 化之電壓（VDL)之供給能力降低。 例如，假定 VSS = 〇V，VDDi3. 3V， V D L = 2 . 2 V · V P = 4 . 〇V，將 N 溝道型MOS 電晶體Q42,以VPP=4. 〇V之閘極電壓使成爲 ON狀態時之閘極•源極間電壓乃爲1 . 8 V ;假定 MO S電晶體Q4 2 /爲P溝道型’則以0V之閘極電壓 (誚先閱讀背1δ之注意事項再瑣苟本頁) &quot; 、τ 木纸張尺政延 β'ΐ. ( ('NS ) ΛΊίί# ( 210X 297公從） 經濟部中央標準局員工消费合作社印掣 A7 _ B7 _ 五、發明説明（32 ) 使成爲ON狀態時之閘•源極間電壓乃爲2 · 2 V。表面 上，P溝道型MO S電晶體之閘•源極間電壓雖較大，但 在此情形下，若考慮載流子移動度之差，則將MO S.電晶 體Q 4 2 /以N溝道型來構成，將相對地獲得較大之電流 供給能力。尤其是將MOS電晶體Q42/作爲Ρ溝道型 以接地電位V S S來使其成爲ON狀態時，將成爲：閘· 源極間電壓（VGS)=降壓電壓V.DL而採取：感測放 大器3之工作電源愈被低電壓化，V G S則愈趨小之傾向 。與此相對·，如本實施例，將N溝道型Μ ◦ S電晶體 Q42 ζ成爲ON狀態所用之閘•源極間電壓，將可按 該MOS電晶體Q42/之閘極膜之耐壓等要因來決定， 將未具有隨工作電源之低電壓化，VG S被變小之傾向。 因此，工作電源之低電壓化今後預測可能有進展之狀況下 ，MO S電晶體Q 4 2 &gt;採用N溝道型，將其以昇壓電壓 來控制成爲ON狀態之構成，在對感測放大器之高速化之 對應方面實較優越。並且，利用形成字線選擇電平之昇壓 電路2之輸出VPP，來生成MOS電晶體Q4 2 &gt;之開 關控制信號0SAN2 ;由此即可在感測放大器3之動作 速度之高速化時，極力抑制電路規模之增大。 在圖5之例子中，亦與前述圖1之實施例同樣，作爲 構成延遲電路12之反相器之之電源電壓使用過激勵用之 電IB(VDD)，則由此可以簡單構成來確實控制過激勵 時間。 因此，依據圖5所示例子，在過激勵技術中，不僅可 本紙張尺度適用中國國家標準（CMS ) Α4規格（2丨0Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝·The circuits forming the control signals 0SAN, 0SAP1B, 0SAN2 are shown as part of the timing controller TG shown in FIG. That is, in order to define the control signal 0SAEB (the internal control signal of the timing controller TG, which is not shown in FIG. 1) during the activation period of the aforementioned sense amplifier 3, the aforementioned control signal 4 is initially SAP 1 B is activated, and then the aforementioned control signal 4 SAB 2 is activated, each of which is provided with a two-input NAND gate 10 and a NOR gate 11; and, one of the NAND gate 10 and the NOR gate 11 is input The terminals are also combined with each other, and between one input terminal of the NAND gate 10 and the other input terminal, an odd number of CMOS inverters INV0 to INVi (i = 2 η — 1) are connected in series. Connected delay circuit 1 2. The other input terminal of the aforementioned NAND gate 10 is also supplied with a control signal 0SAEB via the CMO S inverter 13, and the other input terminal of the NOR gate 11 is supplied with a control signal 0 S A E B. The control signal 0 S A P 1 B is output from the aforementioned NA ND gate 1 〇, and the control signal Λ # S AN is formed by passing the aforementioned control signal 0 s Α Β through a series of three-stage CMOS inverters 15, 16, and 17. The output 0SA2 of the foregoing NOR gate 11 is supplied to the level conversion circuit 6, and the output of the level conversion circuit 6 becomes the aforementioned control signal 0 SAN2. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) (read the precautions on the back before filling this page). ······································ The aforementioned level shift circuit 6 is a circuit that amplifies the signal amplitude of the input signal and transmits it to the output. There are a series circuit of P-channel MOS transistors Q60, Q6 1 and N-channel MOS transistor Q6 2, and a P-channel type. A series circuit of the MOS transistors Q6 3, Q6 4 and the N-channel MOS transistor Q 6 5 is arranged in parallel between the boosted voltage V P P and the ground potential V S. The gates of the MO transistors Q6 1 and Q6 2 are provided with an input signal 4.SA2, and the gates of the MOS transistors Q64 and Q6 5 are provided with an input signal 0SA2, which is supplied after being inverted by the CMOS inverter 18. among them. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (read the precautions on the back before filling out this page) The junction of the MO S transistor Q 6 1 and Q 6 2 is combined at the gate of the MO S transistor 6 3 The junction of the MOS transistor Q 64 and Q 6 5 is combined with the gate of the MO S transistor Q 6 0. Input signal. The signal amplitude of 0SA2 is the potential difference between the ground potential VSS and the power supply voltage VDD. That is, the working power of NOR gate 1.1 is VDD, VS S »control signal? When 5 S A2 is at the power supply voltage VDD level, the ON state of MOS transistors Q63 and Q64, the OFF state of MOS transistor Q6 5 and the MOS transistor Q6 3, &lt; 36 4 of 0 &gt; 1 state, The control signals 03 and 1 ^ 2 are set to the level of the boosted voltage VPP. When the control signal 0 S A 2 becomes the level of the ground potential V S S, then the M 0 S transistor &lt; 362 of 0? State, ν MOS transistor Q65 ON state, MOS transistor Q60, Q6 1 ON state, MOS transistor Q6 3 OF F state, control signal? 5 SAN2 will be at the ground potential VS S level. Therefore, the signal amplitude becomes the potential of the ground potential VS S and the power supply voltage VDD. The paper size is applicable to the Chinese family standard (CNS) A4 specification (210X297 mm) -32-&quot; '•• &quot;' t ^ u ^^ n -1 eliminates A and c &quot; · Compensation without A7. '__—— 一 _B7 V. Description of the invention (30). · The difference of the input signal SA 2 will be converted into a signal amplitude to become the ground potential V S and the aforementioned boost The output signal VSAN2 &gt; of the potential difference between the voltages VP P and the logic values of the signals V &gt; SA2 and VSAN2 of both sides will be general. 0V。 Boost voltage VPP will become, for example, 4.0V. FIG. 6 shows that the control signal pSAN used to supply the working power to the transmission lines SDN and SDP is constituted by the circuit of FIG. 5. 18. Recognize the waveform of 3-8 1 ^ 2. When the control signal VSAEB during the activation period of the sense amplifier 3 is specified to change to an active level of a low level, first, the control signal P SAP 1 B will change to a low level (the level of the ground potential VSS ), And via the MOS transistor Q41, the power supply voltage VDD will be supplied to the transmission line SD P. Therefore, since the current of the P-channel MOS transistors Q 1 3 and Q 1 4 supplied to the sense amplifier 3 is large, the selection action of the memory cell appears on the small potential difference of the complementary data line DLO «DLOB Will be zoomed in quickly. Then, the control signal ¢) SAP 1 B will be inverted to a 髙 level (the level of the power supply voltage VDD), and the control signal PSAN2 will also be set to a high level (the level of the boosted voltage VPP); MOS transistor Q42 ~, step-down voltage VDL will be supplied to the drive line SDP »Control signal? &gt; The SAN is synchronized with the low level period of the control signal p SAEB, and becomes a high level. As a result, the reach level of the complementary data line driven by the sense amplifier 3 will be defined as one state is the ground potential VSS and the other is the state of the step-down voltage VDL. At this time, the MOS transistor Q4 2 &gt; is an N-channel type, and it is controlled to the paper scale 4 扪 ί () 圯 柁 (2] 〇X 297 公 浼) ~ • .- '-I-1, 1-. *-1 —----1-»-" \ 5J (&quot; Read the precautions and write this page) mf: &lt;, w A7 B7 V. Description of the invention (31 ) Control signal in the ON state ¢) The high level of SAN 2 becomes a voltage greater than its drain voltage (step-down voltage VD L), such as the word line boost voltage YPP; therefore, the MOS transistor Q42 The gate-to-source voltage will be larger *, and the carrier mobility is about 3 times that of the N-channel MOS transistor compared to the P-channel MOS transistor. Therefore, as shown in the embodiment of FIG. 1, compared with the case where the P-channel type MO S transistor Q42 is used and it is controlled to the ON state with the ground potential VSS, a larger current can be obtained at the MO S transistor Q 4 2 &gt; Supply capacity. As a result, even when the operating power is reduced, the sense amplifier 3 can be operated at a high speed. The gate voltage of the N-channel MOS transistor Q4 2 is assumed to be the same as the drain voltage (step-down voltage VDL). When equal, the source voltage of this MOS transistor &lt; 3 4 2 &quot; will be equal to the weight of the MOS transistor Q42 / threshold voltage which is lower than the gate voltage. In order to reduce this voltage drop, in the embodiment of the present invention, the gate voltage is set to be larger than the drain voltage. If the gate voltage is equal to or more than the sum of the drain voltage and the threshold voltage, the reduction of the threshold voltage can be completely canceled: so it can further effectively prevent: low voltage of the sense amplifier. The supply capacity of the reduced voltage (VDL) is reduced. For example, suppose VSS = 0V, VDDi3. 3V, VDL = 2.2V · VP = 4. 0V, and turn on the N-channel MOS transistor Q42 with a gate voltage of VPP = 4. 0V. The gate-to-source voltage in the state is 1.8 V; assuming that the MOS transistor Q4 2 / is a P-channel type, a gate voltage of 0 V is used (read the precautions for 1δ before reading it carefully (This page), τ wooden paper ruler political extension β'ΐ. (('NS) ΛΊίί # (210X 297 public)) The Central Consumers Bureau of the Ministry of Economic Affairs, the Consumer Cooperatives, printed A7 _ B7 _ V. Description of the invention (32 ) The gate-source voltage when it is turned on is 2 · 2 V. On the surface, the gate-source voltage of the P-channel MOS transistor is large, but in this case, if you consider The difference in the carrier mobility will make the MO S. transistor Q 4 2 / N-channel type, and relatively large current supply capacity will be obtained. Especially, the MOS transistor Q42 / will be used as the P channel. When the model is turned on with the ground potential VSS, the gate-source voltage (VGS) = step-down voltage V.DL is adopted: The lower the operating voltage of the sense amplifier 3, the VGS On the contrary, as in this embodiment, the gate-source voltage used to turn the N-channel type M ◦ S transistor Q42 ζ into the ON state will be based on the MOS transistor Q42 / The factors such as the breakdown voltage of the gate film are determined, and there is no tendency that VGS will be reduced with the lower voltage of the operating power supply. Therefore, under the situation that the lowering of the operating power supply may be progressed in the future, MO S The transistor Q 4 2 is an N-channel type, which is controlled by the boosted voltage to be in the ON state. It is superior in the response to the high speed of the sense amplifier. In addition, the word line is used to select a transistor. The output VPP of the flat boost circuit 2 is used to generate the switching control signal 0SAN2 of the MOS transistor Q4 2 &gt; Therefore, when the operating speed of the sense amplifier 3 is increased, the increase of the circuit scale can be suppressed as much as possible. In the example of FIG. 5, as in the embodiment of FIG. 1 described above, as the power supply voltage of the inverter constituting the delay circuit 12, the over-excitation electric power IB (VDD) is used, so that it can be simply constructed to confirm Control over-excitation time. Therefore, according to Figure 5 Son, in overdrive technology, not only can scale this paper applies China National Standard (CMS) Α4 specification (2 Shu 0Χ297 mm) (Please read the back of the precautions to fill out this page) installed ·

、1T -35 - A7 B7 經漪部中央標準局負工消費合作社印製 五、 發明説明 (33 ) 1 將 過 激 勵 時 間按 過 激 勵 用 之 電 壓 ( V D D ) 加 以 控 制 同 1 厂 時 因 降 壓 電 壓 供 給 用 之 Μ 0 S 電 晶 體 Q 4 2 之 電 流 供 給 1 1 能 力 較高 » 故 亦 可 將 資 料 線 之 電 平 高 速 且 確 實 放 大 至 所 希 /--V 1 1 诗 1 I 望 之 電 平 〇 先 閱 1 J 讀 1 I 圖 7 乃 表 示 • 對 感 測 放 大 器 3 之 傳 動 線 路 供給 降 壓 電 背 面 1 壓 V D L 所 用 之 其 他 例 子 者 • 在 此 例 子 中 t 乃 代 替 前 述 注 意 1 事 1 Μ 0 S 電 晶 體 Q 4 2 〆 採 用 P 溝 道 型 Μ 0 S 電 晶 體 Q 4 3 項 再 填 、 t 並 將 對 其 進 行 開 開 控 制 之 信 號 振 幅 定 爲 基 板 偏 壓 為 本 裝 1 V Β Β 與 電 滴 電 壓 V D D 之 範 圍 t 由 此 擬 使 該 Μ 0 S 電 晶 頁 1 體 Q 4 3 之 閘 • 源 極 間 電 壓 成 爲 較大 者 〇 在 圖 4 中 1 1 Μ 0 S 電 晶 體 tuaL Q 4 3 之 開 關 控 制 信 號 乃 爲 Φ S A Ρ 2 B t 1 其 信 號 振 幅 則 爲 電 源 電 壓 V D D 與 基 板 偏 壓 V Β Β 之 間 之 訂 I 電 位 差 0 1 I 在 圖 7 中 7 乃 爲 電 平 變 換 .電 路 〇 此 電 平 變 換 電 路 7 1 1 I 乃 爲 將 刖 述 控 制 信 號 Φ S A 2 以 C Μ 0 S 反 相 器 1 9 來 倒 1 相 並 輸 入 將 输 入 信 號 之 信 號 振 幅 加 以 擴 大 後 傳 達 至 輸 出 1 之 電 路 有 P 溝 道 型 Μ 0 S 電 晶 體 Q 7 0 與 N 溝 道 型 1 Μ 0 S 電 晶 體 Q 7 1 、 Q 7 2 之 串 聯 電 路 及 Ρ 溝 道 型 1 ! Μ 0 S 電 晶 體 Q 7 3 與 Ν 溝 道 型 Μ 0 S 電 晶 體 Q 7 4 I Q 7 5 之 串 聯 電 路 被 並 聯 配 置 在 電 源 電 壓 V D D 與 基 板 I 偏 壓 V B B 之 間 〇 在 Μ 0 S 電 晶 體 Q 7 0 Q 7 1 之 閘 極 1 1 &gt; 乃 有 輸 入 信 號 Φ S A 2 之 倒相 信 號 被 供 給 其 中 t 在 1 1 Μ 0 S 電 晶 體 Q 7 3 « Q 7 4 之 閘 極 則 有 輸 入 信 號 1 1 Φ S A 2 經 由 C Μ 0 S 反 相 器 1 9 、 2 0 被 供 給 其 中 〇 1 1 準 標 家 國 國 中 用 適 度 尺 張 紙 本 釐 公 A7 B7 經漭部中央標準局員工消費合作社印製 五、 發明説明（34 ) Μ 0 S 電晶體 Q 7 0 與 Q 7 1 之 結 合 點 乃 被 結 合 在 Μ 0 S 1 I 電 晶 體 Q 7 5 之 閘 極 * 而 Μ 0 S 電 晶 體 Q 7 3 與 Q 7 4 之 Γ | 結 合 點 則被結 合 在 Μ 0 S 電 晶 體 Q 7 2 之 閘 極 〇 輸 入 信 號 1 1 Φ S A 2之信 號 振 幅 乃 爲 接 地 電 位 V S S 與 電 源 電 壓 請 先 I 1 V D D 之電位 差 ( 反 相 器 1 9 \ 2 0 之 工 作 電 源 乃 爲 閱 讀 背 1 V S S ，V D D ) t 當 控 制 信 號 Φ S A 2 被 成 爲 電 源 電 壓 面 — 1 V D D 之電平 時 ， 乃 由 Μ 0 S 電 晶 體 Q 7 0 之 0 Ν 狀 態 » 事 項 Μ 0 S 電晶體 7 3 之 0 F F 狀 態 Μ 0 S 電 晶 體 IUZ. Q 7 4 、 再 填 本 裝 Q 7 5 之0 N 狀 態 使 控 制 信 號 Φ S A P 2 Β 被 成 爲 基 板 頁 1 I 偏 壓 V B B之 電 平 〇 當 控 制 信 號 Φ S A 2 被 成 爲 接 地 電 位 1 1 1 V S S 之電平 則 由 Μ 0 S 電 晶 體 Q 7 0 之 0 F F 狀 態 9 1 Μ 0 S 電晶體 Q 7 1 之 0 Ν 狀 態 Μ 0 S 電 晶 體 Q 7 3 % 1 訂 Q 7 2 之0 N 狀 態 9 Μ 〇 S 電 晶 體 Q 7 5 之 0 F F 狀 態 &gt; 1 使 控 制 信號Φ S A P 2 Β 被 成 爲 電 源 電 壓 Υ D D 之 電 平 〇 I 1 因 此 » 信號振 幅 成 爲 接 地 電 位 V S S 與 電 源 電 壓 V D D 之 1 上' 電 位 差 ，而輸 入 信 號 Φ S A 2 則 將 被 變 換 爲 ： 邏 輯 值 被 倒 vJ I 置 9 信 號振幅 被 成 爲 基 板 偏 壓 V B Β 與 電 源 電 壓 V D D 之 1 1 電 位 差 之輸出 信 號 Φ S A P 2 B 〇 1 1 由 圖7之 構 成 &gt; 即 使 在 對 傳 動 線 路 S D Ρ 之 降 壓 電 壓 1 V D L 之供給 採 用 Ρ 溝 道 型 之 Μ 0 S 電 晶 體 Q 4 3 » 若 1 將 對 其 作開關 控 制 之 信 號 振 幅 定 爲 基 板 偏 壓 V Β Β 與 電 1 源 電 壓 V D D 之 範 圍 » 則 由 此 亦 可 使 該 Μ 0 S 電 晶 體 ΙΧ3Ζ. I Q 4 3 之閘· 源 極 間 電 壓 成 爲 較 大 * 結 果 « 在 工 作 電 源 被 1 I 低 電 壓 化之狀 況 下 9 亦 可 使 感 測 放 大 器 3 進 行 高 速 動 作 〇 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -37 - 經济部中央標準局員工消f合作社印製 A7 ______B7_________ 五、發明説明（35 ) 惟在工作電源之低電壓化有進展之狀況下，隨降壓電壓 VDL之低電壓化，MOS電晶體Q4 3之閘極•源極電 壓將具有趨小之傾向。作爲基板偏壓VB B，由於利用基 板偏壓所形成之負電壓，將可在感測放大器3之動作速度 之高速化時，極力抑制電路規模之增大。 對於上述之例子，亦可在不趨越本發明之要旨之範圍 內作種種之變更，此亦爲不必贅言之事。例如，在上述之 例子中，乃將感測放大器進行過激勵之情形加以說明；惟 對於未採用過激勵時，對於向感測放大器之高電位側之傳 動線路供給工作電源之MO S電晶體，亦可同樣採用有關 042、Q4 3之構成。進一步，在採用過激勵時，對 於MOS電晶體Q4 1 ，亦同樣可採用關於Q 4 2、 Q43之構成。並且，DRAM之記憶墊塊構成、墊塊選 擇之邏輯構成、資料之並聯輸出入數元數等，亦不限定於 上述實施例，可適宜加以變更。而且，生成感測放大器控 制所用之控制信號0SAN、0AP1B 、&lt;^SAN2之 電路之邏輯構成，亦不限定於圖1者，可適宜加以變更。 在以上之說明中，主要乃將本發明人所作發明，適用 於成爲其背景之利用部門之D R AM時之情形加以說明者 :惟本發明亦不限定於此，將可廣泛適用於：與時鐘信號 同步動作之同步性DRAM (synchronous DRAM)、虛擬 靜態RAM (pseudo static RAM)，進一步，則在微電 腦等之資料處理L S I之晶片上（on chip)之此等記憶 體等，備有資料傳送所用之接受器（receiver)用差動放 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X297公釐） 一 38 _ I - ---------'士氏一I I I n n - τ _ 1 - n ! L·,- 0¾ i ,- - k (讀先閣讀背而之注意事邛再填两本頁) A7 ______B7______ 五、發明説明（36 ) 大電路之半導體積體電路等。 &lt;發明之效果） 本申請案所揭示之本發明之中代表性者所能獲得之效 果簡單說明如下。 亦即，作爲如感測放大器之差動放大電路之驅動方式 ，採用過激勵（over drive)技術時，由於規定過激勵時 間之延遲機構之延遲時間，對外部電源電壓具有負之依存 性；故在被供給之外部電源電壓爲容許範圍之上限電平， 或者因電源電壓側之動作容限試驗等被供給特別高之外部 電源電壓時，延遲機構之延遲時間將相對地被縮短；換言 之，過激勵時間（OD T)將相對地被縮短，而相對地電 平較高之外部電源電壓被供給差動放大電路之傳動線路（ driveline) ( S D P )之時間，亦將被縮短。由此*將可 防止由相對性電平較高之外部電源電壓使差動放大電路被 過剩地過激勵之現象。 經濟部中央標準局員工消费合作社印製 (請先閱讀背而之注意事項再填艿本頁) 由於可防止對差動放大電路之過激勵成爲過剩，故亦 可防止從多數之差動放大電路向降壓電路有電流倒流之事 態發生；由此，亦可防止：工作電源被低電壓化之電路， 例如被供給至DRAM之記憶陣列之降壓電壓（VDL) ，不冀求地被昇高電平之事態。因此，將可阻止被用於工 作電壓之低電壓化之電路之可靠性，因降壓電壓不冀求地 被昇高電壓而降低之事態。例如，將可防止：如感測放大 器之差動放大電路之放大動作所引起之資料線之到達電壓 本纸法尺度適用中國國家標準（CNS ) A4規格（210X297公釐) -39 - A7 _ B7 五、發明説明（37 ) ，因降壓電壓之上昇被提高，由此使字線之選擇電平與資 料線之高電平之電位差趨小，而在向記億格之高電平寫入 時，不能將資料線之該高電平之電壓外加於存儲容量等之 事態。而且，因降壓電壓之不冀求之電平高昇若使如感測 放大器之差動放大電路所作資料線之到達電壓上昇，則與 此相應，被補償平衡之資料線之預充電電平亦將上昇，在 此種狀態下被寫入之資料若被讀出時，亦可防止：對預充 電電平之高電平之讀出電壓容限亦將趨小之現象。並且， 形成字線選摞電平之昇壓電路乃利用前述降壓電壓時，則 降壓電壓之不冀求之電平上昇將使字線選擇電平上昇，而 損害記億格選擇電晶體之閘極氧化膜之虞亦不致發生。 經濟部中央標隼局員工消费合作社印製 將在延遲時間無電源電壓依賴性之如C R延遲電路之 無源元件所成之延遲要件，與Μ 0 S電晶體電路加以併用 以構成前述延遲機構，由此擬僅以如CM O S反相器之 Μ 0 S電晶體電路來確保必要之延遲時間時，若延遲時間 之電源電壓依存性過大，亦可加以因應，故可較容易將必 需之延遲時間及延遲時間之電源電壓依存性之雙方加以最 適化。 將對差動放大電路之高電位側傳動線路供給電源電壓 或降壓電壓之MO S電晶體定爲Ν溝道型，其開關控制信 號之振幅則定爲較電源電壓被昇壓之電壓，由此，則可避 :工作電源隨著被低電化，使對高電位側傳動線路之工作 電壓供給用Μ ◦ S電晶體之閘·源極間電壓被變小；而工 作電壓被低電壓化之狀況下亦可使差動放大電路高速工作 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X29*7公釐） 一 40 _ (讀先閱讀背面之注意事領再填&quot;本頁) 經濟部中央樣準局S工消費合作社印裝 Μ _ Β7 五、發明説明（38 ) 〇 並且，即使將對差動放大電路之高電位側之傳動線路 供給工作電源之MO S電晶體定爲P溝道型時，若將對其 作開關控制之信號振幅定爲負電壓與電源電壓之範圍，則 可使該MO S電晶體之閘•源極間電壓成爲較大；結果， 即使在工作電源被低電壓化之狀況下，亦可使差動放大電 路高速工作。 作爲對前述高電位側之傳動線路供給工作電源之N溝 道型Μ 0 S電晶體加以進行開關控制之信號振幅予以規定 所需之昇壓電壓，利用形成字線選擇電平之昇壓電路之輸 出；並且，作爲對前述傳動線路供給工作電壓之Ρ溝道型 Μ ◦ S電晶體加以進行開關控制之信號振幅予以規定所需 之負電壓，利用基板偏壓發生電路所形成之負電壓；則由 此，在前述差動放大電路之動作速度之高速化時，將可極 力抑制電路規模之增大。 &lt;附圖之簡單說明&gt; 〔圖1〕表示以過激勵形式來驅動控制感測放大器所 用之一例之電路圖。 〔圖2〕驅動控制圖1所示感測放大器之控制信號之 一例之波形圖。 〔圖3〕表示以過激勵形式來驅動感測放大器之控制 信號之其他生成邏輯之邏輯電路圖。 〔圖4〕表示延遲電路之一例之電路圖。 本纸張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (锖先閱讀背面之注意事項再填寫本頁) 訂 i Λ -41 - A7 B7 五、發明説明（39 ) 〔圖5〕對感測放大器之傳動線路SDN、SDP供 給工作電源所用之一例之電路圖· 〔圖6〕由圖5之電路構成對傳動線路SDN、SD P供給工作電源所用之控制信號WSAN、0 SAP 1 B 、^SAN2之波形圖。 〔圖7〕對感測放大器之傳動線路S D P供給降壓電 壓VD L所用之其他例之電路圖· 〔圖8〕本發明之一例之DRAM之全體性方塊圖。 〔圖9〕圖8所示DRAM之記憶墊塊、感測放大器 區塊、以及行開關電路區塊之局部電路圖· (附圖中符號之說明） MARYO 'MARY1 .........記憶陣列， Μ M A T 〇〜Μ M A T 7 .........記憶墊塊， ο A s 經濟部中央標準局員工消費合作社印製 ο Dw、 1T -35-A7 B7 Printed by the Central Standards Bureau of the Central Bureau of Standards and Labor Co-operative Consumer Cooperatives V. Description of the invention (33) 1 Control the over-excitation time according to the over-excitation voltage (VDD). The supply of M 0 S transistor Q 4 2 has a high current supply capacity 1 1 »so the level of the data line can be quickly and surely amplified to the desired level --- V 1 1 Poem 1 I desired level. Read 1 J Read 1 I Figure 7 shows: • Other examples used to supply the voltage reduction back of the sensor amplifier 3 to the back 1 VDL • In this example, t is used instead of the previous note 1 thing 1 Μ 0 S electricity The crystal Q 4 2 〆 uses the P-channel type M 0 S transistor Q 4 3 and then fills in t, and sets the signal amplitude of the open / closed control to the substrate bias. This device is 1 V Β Β The range t of the drop voltage VDD is therefore intended to make the gate of the M 0 S transistor 1 body Q 4 3 • the source-to-source voltage becomes larger. In FIG. 1 1 1 M 0 S transistor tuaL Q 4 3 The switching control signal is Φ SA Ρ 2 B t 1 and its signal amplitude is the predetermined I potential difference between the power supply voltage VDD and the substrate bias voltage V Β Β 0 1 I In Figure 7 7 is a level shift. Circuit. This level conversion circuit 7 1 1 I is a circuit for inverting the described control signal Φ SA 2 with a C M 0 S inverter 1 9 and inputting the signal. The signal amplitude of the input signal is amplified and transmitted to the output 1. There are series circuits of P channel M 0 S transistor Q 7 0 and N channel 1 M 0 S transistor Q 7 1, Q 7 2 and P channel 1! M 0 S transistor Q 7 3 and The serial circuit of the Ν channel type M 0 S transistor Q 7 4 IQ 7 5 is arranged in parallel at the power supply voltage VDD and the substrate I Between the bias voltage VBB, the gate 1 1 of the M 0 S transistor Q 7 0 Q 7 1 is provided with an inverted signal of the input signal Φ SA 2 where t is at 1 1 M 0 S transistor Q 7 3 «The gate of Q 7 4 has an input signal 1 1 Φ SA 2 is supplied through C M 0 S inverters 1 9 and 2 0 〇 1 1 The standard standard of the country and the country uses a moderate rule of paper Acm B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China. 5. Description of the Invention (34) The junction of the M 0 S transistor Q 7 0 and Q 7 1 is combined at the gate of the M 0 S 1 I transistor Q 7 5 Pole * and the Γ | junction of the M 0 S transistor Q 7 3 and Q 7 4 is combined at the gate of the M 0 S transistor Q 7 2 〇 Input signal 1 1 Φ SA 2 The signal amplitude is the ground potential The potential difference between VSS and the power supply voltage should be I 1 VDD (the operating power of the inverter 1 9 \ 2 0 is for reading back 1 VSS, VDD) t When the control signal Φ SA 2 is turned on Voltage plane — 1 VDD level is determined by M 0 S transistor Q 7 0 0 Ν state »Matter M 0 S transistor 7 3 0 FF state M 0 S transistor IUZ. Q 7 4 The 0 N state of Q 7 5 causes the control signal Φ SAP 2 Β to become the level of the substrate page 1 I bias VBB. 0 When the control signal Φ SA 2 is set to the ground potential 1 1 1 VSS level is changed from Μ 0 S Transistor Q 7 0 0 FF State 9 1 Μ 0 S Transistor Q 7 1 0 0 N State M 0 S Transistor Q 7 3% 1 Order Q 7 2 0 N State 9 Μ0S Transistor Q 7 5 0 FF state &gt; 1 makes the control signal Φ SAP 2 Β to be the level of the power supply voltage Υ DD Ⅰ 1 Therefore »the signal amplitude becomes the potential difference between the ground potential VSS and the power supply voltage VDD, and the input signal Φ SA 2 Will be transformed into: logic value is inverted vJ I set to 9 signal amplitude is output as potential difference between substrate bias VB Β and power supply voltage VDD 1 1 No. Φ SAP 2 B 〇1 1 is composed of FIG. 7 &gt; Even if the step-down voltage 1 VDL of the transmission line SD P is supplied with a P-channel type M 0 S transistor Q 4 3 »If 1 will be The amplitude of the signal for switching control is set to the range of the substrate bias voltage V Β Β and the power supply voltage VDD », so that the gate and source voltage of the M 0 S transistor I × 3Z. IQ 4 3 can be made larger. * Result «9 can make sense amplifier 3 operate at high speed even when working power is reduced by 1 I. 1 1 1 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) -37- Printed by the staff of the Central Bureau of Standards, Ministry of Economic Affairs, Cooperative Cooperative A7 ______B7_________ V. Description of the Invention (35) However, under the condition that the low voltage of the working power has progressed, with the lower voltage of the step-down voltage VDL, The gate and source voltages tend to decrease. As the substrate bias voltage VB B, the negative voltage formed by the substrate bias voltage can be used to suppress the increase of the circuit scale at a high speed when the operating speed of the sense amplifier 3 is increased. It is needless to say that various changes can be made to the above examples without departing from the scope of the present invention. For example, in the above example, the case where the sense amplifier is over-excited is explained; but when the over-excitation is not used, for the MOS transistor that supplies the operating power to the high-potential side transmission line of the sense amplifier, Structures related to 042 and Q4 3 can also be used in the same manner. Furthermore, when over-excitation is used, the structure regarding Q 4 2 and Q 43 can also be adopted for the MOS transistor Q 4 1. In addition, the memory pad structure of the DRAM, the logical structure of the pad selection, and the number of parallel input / output digits of data are not limited to the above-mentioned embodiments, and can be appropriately changed. In addition, the logic configuration of the circuits for generating the control signals 0SAN, 0AP1B, &lt; ^ SAN2 used for the control of the sense amplifier is not limited to those in Fig. 1 and can be appropriately changed. In the above description, it is mainly the case where the invention made by the present inventor is applicable to the DR AM which is the utilization department of its background: However, the present invention is not limited to this, and will be widely applicable to: Synchronous DRAM (synchronous DRAM) and pseudo static RAM (synchronous DRAM) for signal synchronization operation. Furthermore, these memories, such as on chips, of data processing LSIs such as microcomputers, etc. are provided for data transmission. The paper size of the receiver for the receiver is applicable to the Chinese National Standard (CNS) A4 specification (2I0X297 mm)-38 _ I---------- 'Shishi III III nn-τ _ 1-n! L ·,-0¾ i,--k (read the notes of the first cabinet and fill in two more pages) A7 ______B7______ 5. Description of the invention (36) Semiconductor integrated circuits for large circuits. &lt; Effects of the invention) The effects obtained by the representative of the present invention disclosed in this application can be briefly described as follows. That is, as a driving method of a differential amplifier circuit such as a sense amplifier, when an over drive technique is used, the delay time of a delay mechanism that specifies the over-excitation time has a negative dependency on the external power supply voltage; When the supplied external power supply voltage is the upper limit level of the allowable range, or when a particularly high external power supply voltage is supplied due to an operation tolerance test on the power supply voltage side, the delay time of the delay mechanism will be relatively shortened; in other words, excessive The excitation time (OD T) will be relatively shortened, and the time when the external power supply voltage with a relatively high ground level is supplied to the driveline (SDP) of the differential amplifier circuit will also be shortened. This * will prevent excessive amplification of the differential amplifier circuit by an external power supply voltage with a high relative level. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back and then fill out this page). Since it can prevent the excessive excitation of the differential amplifier circuit from becoming excessive, it can also prevent the majority of differential amplifier circuits. A state of current backflow to the step-down circuit occurs; as a result, it is also possible to prevent: a circuit whose working power is lowered, such as the step-down voltage (VDL) of the memory array supplied to the DRAM, undesirably being increased Level matters. Therefore, the reliability of a circuit used for lowering the operating voltage can be prevented, and a situation in which the step-down voltage is undesirably lowered due to an increase in voltage can be prevented. For example, it can prevent: the arrival voltage of the data line caused by the amplifying action of the differential amplifier circuit of the sense amplifier. The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -39-A7 _ B7 V. Description of the invention (37), due to the rise of the step-down voltage, the potential difference between the selection level of the word line and the high level of the data line becomes smaller, and it is written to the high level of the billionth grid. At this time, the high-level voltage of the data line cannot be applied to the storage capacity. Moreover, if the undesired level rise due to the step-down voltage increases the arrival voltage of the data line such as the differential amplifier circuit of the sense amplifier, the precharge level of the data line being compensated and balanced is corresponding to this. It will rise, and if the data written in this state is read, it can also prevent: the read voltage tolerance to the high level of the precharge level will also become smaller. In addition, when the step-up circuit forming the word line selection level uses the aforementioned step-down voltage, an undesired level increase of the step-down voltage will cause the word line selection level to rise, and damage the billion-line selection voltage. The gate oxide film of the crystal does not occur. The Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs will print the delay elements formed by passive components such as CR delay circuits that have no dependency on the power supply voltage during the delay time, and combine them with the M 0S transistor circuit to form the aforementioned delay mechanism. Therefore, it is planned to only use the M 0 S transistor circuit such as the CM OS inverter to ensure the necessary delay time. If the power supply voltage dependency of the delay time is too large, it can also be responded, so it is easier to set the necessary delay time. And both the power supply voltage dependency of the delay time are optimized. The MO S transistor that supplies the power supply voltage or the step-down voltage to the high-potential side transmission line of the differential amplifier circuit is set as the N-channel type, and the amplitude of the switching control signal is set to a voltage that is boosted compared to the power supply voltage. , It can be avoided: as the working power is lowered, the working voltage supply for the high-potential side transmission line M is reduced. The voltage between the gate and the source of the S transistor is reduced; and the operating voltage is reduced. The differential amplifier circuit can also work at a high speed. The paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X29 * 7 mm)-40 _ (read the precautions on the back and fill in this page again) Printed by the Central Bureau of Prototype, S and Consumer Cooperatives _ B7 V. Description of the Invention (38) 〇 Furthermore, even if the MO S transistor which supplies working power to the high-potential side transmission line of the differential amplifier circuit is set as the P-channel In the model, if the amplitude of the signal to be controlled by the switch is within the range of the negative voltage and the power supply voltage, the voltage between the gate and the source of the MO S transistor can be made larger. As a result, even when the operating power is low, Voltage state Next, the differential amplifier circuit can operate at high speed. As the boost voltage required to regulate the signal amplitude of the N-channel type M 0 S transistor that supplies working power to the drive line on the high potential side, the boost voltage is selected by forming a word line. And the negative voltage required as the signal amplitude for switching control of the P-channel type M ◦ S transistor that supplies the operating voltage to the aforementioned transmission line, using the negative voltage formed by the substrate bias generating circuit; Therefore, when the operation speed of the differential amplifier circuit is increased, the increase in circuit scale can be suppressed as much as possible. &lt; Brief description of the drawings &gt; [Fig. 1] A circuit diagram showing an example of driving and controlling the sense amplifier in an over-excitation mode. [Fig. 2] A waveform diagram of an example of a control signal for driving and controlling the sense amplifier shown in Fig. 1. [Fig. [Fig. 3] A logic circuit diagram showing other generation logic of a control signal for driving a sense amplifier in an over-excitation form. [Fig. 4] A circuit diagram showing an example of a delay circuit. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) (锖 Please read the precautions on the back before filling this page) Order i Λ -41-A7 B7 V. Description of the invention (39) [Figure 5 ] Circuit diagram of an example of supplying working power to the transmission line SDN and SDP of the sense amplifier. [Fig. 6] The control signal WSAN, 0 SAP 1 B for supplying working power to the transmission line SDN and SD P is composed of the circuit of FIG. 5 , ^ SAN2 waveform. [Fig. 7] A circuit diagram of another example for supplying the step-down voltage VD L to the drive circuit S D P of the sense amplifier. [Fig. 8] An overall block diagram of a DRAM according to an example of the present invention. [Figure 9] Partial circuit diagram of the memory pad block, sense amplifier block, and row switch circuit block of the DRAM shown in Figure 8 · (Description of symbols in the drawing) MARYO 'MARY1 ......... Memory array, Μ MAT 〇 ～ Μ MAT 7 ......... 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IX (讀先閱讀背面之注意事項再填寫本頁) 裝. --0 經濟部中央標準局員工消费合作社印製 本紙乐尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 44 -IX (Read the precautions on the back before filling in this page) Pack. --0 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs This paper scale is applicable to the Chinese National Standard (CNS) Α4 specification (210X 297 mm) 44-

Claims (1)

B8 ‘ 1 C8 D8 六、申請專利範圍___________________ — 第881 091 92號專利申請案 中文申請專利範圍修正本 ' 民國87年12月修正 1 . 一種半導體積體電路，其特徵爲： 備有：放大互補信號線之電位差之差動放大電路；及 形成供給作爲前述差動放大電路之工作電源之第1驅動電 壓之第1驅動控制信號，同時在第1驅動控制信號被活性 化（activation)後’該第1驅動控制信號亦與被非活性 化相呼應被活性化，而將較前述第1驅動電壓電平爲低之 第2驅動電壓，作爲前述差動放大電路之工作電源來供給 之第2驅動控制信號加以形成之控制電路等； 而前述控制電路亦含有規定第1驅動控制信號被活性 化之期間之延遲電路； 前述延遲電路則含有將前述第1驅動電壓作爲工作電 源來承接之反相器電路；前述第1驅動控制信號被活性化 之期間亦對前述第1驅動電壓具有負之依存性（depende-nbcy );等爲構成者。 經濟部中央標準局員工消費合作社印製 2.如申請專利範圍第1項所述之半導體積體電路中 ;前述反相器電路乃爲CMO S反相器電路者。 3 . —種半導體積體電路，其特徵爲： 備有選擇端子被結合在字線（word line)之複數個之 記億格（memory cell);及被連接在記憶格之資料輸出入 端子之互補信號線（complementary signal l.ine);及 放大器互補信號線之電位差之差動放大電路（different- 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） B8 ‘ 1 C8 D8 六、申請專利範圍___________________ — 第881 091 92號專利申請案 中文申請專利範圍修正本 ' 民國87年12月修正 1 . 一種半導體積體電路，其特徵爲： 備有：放大互補信號線之電位差之差動放大電路；及 形成供給作爲前述差動放大電路之工作電源之第1驅動電 壓之第1驅動控制信號，同時在第1驅動控制信號被活性 化（activation)後’該第1驅動控制信號亦與被非活性 化相呼應被活性化，而將較前述第1驅動電壓電平爲低之 第2驅動電壓，作爲前述差動放大電路之工作電源來供給 之第2驅動控制信號加以形成之控制電路等； 而前述控制電路亦含有規定第1驅動控制信號被活性 化之期間之延遲電路； 前述延遲電路則含有將前述第1驅動電壓作爲工作電 源來承接之反相器電路；前述第1驅動控制信號被活性化 之期間亦對前述第1驅動電壓具有負之依存性（depende-nbcy );等爲構成者。 經濟部中央標準局員工消費合作社印製 2.如申請專利範圍第1項所述之半導體積體電路中 ;前述反相器電路乃爲CMO S反相器電路者。 3 . —種半導體積體電路，其特徵爲： 備有選擇端子被結合在字線（word line)之複數個之 記億格（memory cell);及被連接在記憶格之資料輸出入 端子之互補信號線（complementary signal l.ine);及 放大器互補信號線之電位差之差動放大電路（different- 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐）B8 '1 C8 D8 6. Scope of Patent Application _________________ — Patent Application No. 881 091 92 Amendment to Chinese Application for Patent Scope' Amendment Dec. 87, Republic of China 1. A semiconductor integrated circuit, which is characterized by: A differential amplifier circuit with a potential difference of complementary signal lines; and a first drive control signal that supplies a first drive voltage that is a working power source of the differential amplifier circuit, and at the same time after the first drive control signal is activated The first drive control signal is also activated in response to being inactivated, and a second drive voltage lower than the first drive voltage level is supplied as a second power supply for the operating power of the differential amplifier circuit. A control circuit formed by driving control signals; and the aforementioned control circuit also includes a delay circuit which specifies a period during which the first driving control signal is activated; the aforementioned delay circuit includes an inversion which uses the first driving voltage as an operating power source Circuit; the period during which the first drive control signal is activated also has a negative dependency on the first drive voltage (Depende-nbcy); etc. are the constituents. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 2. In the semiconductor integrated circuit described in item 1 of the scope of patent application; the aforementioned inverter circuit is a CMO S inverter circuit. 3. A semiconductor integrated circuit, which is characterized by: a plurality of memory cells provided with a selection terminal combined with a word line; and a data input / output terminal connected to a memory cell Complementary signal line (complementary signal l.ine); and differential amplifier circuit of the potential difference of the amplifier's complementary signal line (different- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) B8 '1 C8 D8 6 Scope of patent application ___________________ — Patent application No. 881 091 92 Amendment to Chinese patent application scope 'Amendment Dec. 87 of the Republic of China 1. A semiconductor integrated circuit characterized by: having: amplifying the potential difference between complementary signal lines A differential amplifier circuit; and a first drive control signal forming a first drive voltage to be supplied as a working power source of the differential amplifier circuit, and at the same time after the first drive control signal is activated, the first drive control signal Also in response to being inactivated, the second driving voltage, which is lower than the first driving voltage level, is used as the differential amplifier. The control circuit for forming the second driving control signal supplied by the working power of the circuit; and the aforementioned control circuit also includes a delay circuit which specifies the period during which the first driving control signal is activated; the aforementioned delay circuit includes the aforementioned first drive The inverter circuit that voltage is used as the working power source; the period during which the first drive control signal is activated also has a negative dependence on the first drive voltage (depende-nbcy); etc. are the constituents. Central Standard of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative 2. In the semiconductor integrated circuit described in item 1 of the scope of patent application; the aforementioned inverter circuit is a CMO S inverter circuit. 3. A semiconductor integrated circuit with characteristics For: a plurality of memory cells with selective terminals combined in a word line; and a complementary signal l.ine connected to data input and output terminals of a memory cell; And the amplifier's complementary signal line potential difference between the differential amplifying circuit (different- this paper size applies to China's national ladder standard (CNS) A4 specifications (210X297 mm) A8 B8 1 C8 D8 六、申請專利範圍 ial amplifier circuit);及將從.外.部所供給之外部電 (請先間讀背面之注意事項再填寫本頁) 源電壓加以降壓，以形成前述字線之選擇電平以下之降壓 電壓之降壓電1路_ :及形成：在前述差動放大電路之活性化 定時（activation timing)最初將前述外部電源.電Μ作 爲工作電源供給至前述差動放大電路之第1驅動控制信號 ，同時之第1L·驅動控制信號被活性化後與該第1驅動控制 f 信號被非活g化柑呼應被活性化，並將在前述降壓電路所 生成之降壓電壓作爲差動放大電路之工作電源被供給之第 2驅動控制信號之控制電路等； 而前述控制電路亦含有規定前述第1驅動控制信號被 活性化之期間之延遲雪路； 前述延遲電路則含有作爲工作電源來承接前述外部電 源電壓之反相器電路，而前述第1驅動控制信號被活性化 之期間.亦對前述外部電源電壓具有負之依存性；等爲構成 者。 4. 如申請專利範圍第3項所述之半導體積體電路中 ;前述降壓電路乃在電流源與髙電阻之串聯連接點形成前 經濟部中央標準局員工消費合作社印製 述降壓電壓之電路者。 5. 如申請專利範圍第4項所述之半導體積體電路中 :前述記憶格乃爲動態型之記億格，而備有：將前述降壓 電路之輸出端子之電壓之大致一半之電壓，作爲前述互捕 信號線之預充電電壓來形成之電路；及將前述互補信號線 加以選擇性地導通之補償（equalize)電路；及與前述補 償電路所生互補信號線之導通定時相呼應，對互補信號線 本紙張尺度逋用中國國家棵準（CNS ) A4規格（21〇Χ297公釐）A8 B8 1 C8 D8 VI. Patent application scope (ial amplifier circuit); and external power supplied from the external department (please read the precautions on the back first and then fill out this page) to reduce the source voltage to form the aforementioned Step 1 of the step-down voltage below the selection level of the word line: and formation: The aforementioned external power supply is initially supplied to the aforementioned activation timing at the activation timing of the aforementioned differential amplifier circuit. The first drive control signal of the differential amplifier circuit is activated at the same time as the first L · drive control signal is activated and the first drive control f signal is inactivated and activated, and will be activated in the aforementioned step-down circuit. The generated step-down voltage is a control circuit for the second drive control signal to which the working power of the differential amplifier circuit is supplied; and the aforementioned control circuit also includes a delay snow path which specifies the period during which the aforementioned first drive control signal is activated; The delay circuit includes an inverter circuit that receives the external power supply voltage as a working power source, and a period during which the first drive control signal is activated. Dependence of the voltage source having a negative; and the like are to constitute. 4. In the semiconductor integrated circuit as described in item 3 of the scope of the patent application; the aforementioned step-down circuit is formed at the series connection point of the current source and the rubidium resistor. Circuit person. 5. As described in the semiconductor integrated circuit described in item 4 of the scope of the patent application: the aforementioned memory cell is a dynamic type of a hundred million cells, and is provided with a voltage of approximately half of the voltage of the output terminal of the aforementioned step-down circuit, A circuit formed as a precharge voltage of the aforementioned mutual capture signal line; and an equalize circuit which selectively conducts the aforementioned complementary signal line; and corresponds to the turn-on timing of the complementary signal line generated by the aforementioned compensation circuit, corresponding to Complementary signal cable This paper uses China National Standard (CNS) A4 (21〇 × 297 mm) A8 B8 1 C8 D8 六、申請專利範圍 ial amplifier circuit);及將從.外.部所供給之外部電 (請先間讀背面之注意事項再填寫本頁) 源電壓加以降壓，以形成前述字線之選擇電平以下之降壓 電壓之降壓電1路_ :及形成：在前述差動放大電路之活性化 定時（activation timing)最初將前述外部電源.電Μ作 爲工作電源供給至前述差動放大電路之第1驅動控制信號 ，同時之第1L·驅動控制信號被活性化後與該第1驅動控制 f 信號被非活g化柑呼應被活性化，並將在前述降壓電路所 生成之降壓電壓作爲差動放大電路之工作電源被供給之第 2驅動控制信號之控制電路等； 而前述控制電路亦含有規定前述第1驅動控制信號被 活性化之期間之延遲雪路； 前述延遲電路則含有作爲工作電源來承接前述外部電 源電壓之反相器電路，而前述第1驅動控制信號被活性化 之期間.亦對前述外部電源電壓具有負之依存性；等爲構成 者。 4. 如申請專利範圍第3項所述之半導體積體電路中 ;前述降壓電路乃在電流源與髙電阻之串聯連接點形成前 經濟部中央標準局員工消費合作社印製 述降壓電壓之電路者。 5. 如申請專利範圍第4項所述之半導體積體電路中 :前述記憶格乃爲動態型之記億格，而備有：將前述降壓 電路之輸出端子之電壓之大致一半之電壓，作爲前述互捕 信號線之預充電電壓來形成之電路；及將前述互補信號線 加以選擇性地導通之補償（equalize)電路；及與前述補 償電路所生互補信號線之導通定時相呼應，對互補信號線 本紙張尺度逋用中國國家棵準（CNS ) A4規格（21〇Χ297公釐） 8^1\4修正.. 補无 A8 , B8 1 C8 D8 六、申請專利範圍 供給前述預充電電壓之預充電電路；等所成奢。 6 . —種半導體積體電路，其特徵爲： (請先閱讀背面之注意事項再填寫本頁) 含有：一對之資料線（,data 1 i ne ); 及備有一對P溝道型MO S電晶體及一對N溝道型 M〇 S電晶體之CM〇 S閂鎖電路（CMOS latch circui-t)，而放大前述—對之資料線之電位差之感測放大器； 及承接第1電壓之第1端子.： 及承接較前述第1電壓爲低之第2電壓之第2端子； 及在前述一對之P溝道型MO S電晶體被設在共同結 合之一對之源極與前述第1端子之間之第1開關M〇S電 晶體； 及被設在前述共同結合之一對源極與前述第2端子之 間之第2開關M0S電晶體； 經濟部中央標準局員工消費合作社印製 及將前述第1及第2開關MOS電晶體控制成：在第 1期間前述第1開關MOS電晶體被成爲ON狀態，在前 述第1期間.後之第2.期間Μ述第1開關Μ 0 S電晶體被成 爲0 F F狀態，且前述第2開關MO S電晶體被成爲ON 狀.B等之控制電路等； · 而前述控制電路亦含有規定前述第1期間之延遲電路 » 前述延遲電路則含有將前述第1電壓作爲工作電源來 承接之反相器電路：等爲構成者· 7.如申請專利範圍第6項所述之半導體積，體電路中 ;前述第1及第2開關MO S電晶體乃被結合成並聯形態 本紙張尺度適用中國國家操準（CNS ) A4規格（210X297公釐） 8^1\4修正.. 補无 A8 , B8 1 C8 D8 六、申請專利範圍 供給前述預充電電壓之預充電電路；等所成奢。 6 . —種半導體積體電路，其特徵爲： (請先閱讀背面之注意事項再填寫本頁) 含有：一對之資料線（,data 1 i ne ); 及備有一對P溝道型MO S電晶體及一對N溝道型 M〇 S電晶體之CM〇 S閂鎖電路（CMOS latch circui-t)，而放大前述—對之資料線之電位差之感測放大器； 及承接第1電壓之第1端子.： 及承接較前述第1電壓爲低之第2電壓之第2端子； 及在前述一對之P溝道型MO S電晶體被設在共同結 合之一對之源極與前述第1端子之間之第1開關M〇S電 晶體； 及被設在前述共同結合之一對源極與前述第2端子之 間之第2開關M0S電晶體； 經濟部中央標準局員工消費合作社印製 及將前述第1及第2開關MOS電晶體控制成：在第 1期間前述第1開關MOS電晶體被成爲ON狀態，在前 述第1期間.後之第2.期間Μ述第1開關Μ 0 S電晶體被成 爲0 F F狀態，且前述第2開關MO S電晶體被成爲ON 狀.B等之控制電路等； · 而前述控制電路亦含有規定前述第1期間之延遲電路 » 前述延遲電路則含有將前述第1電壓作爲工作電源來 承接之反相器電路：等爲構成者· 7.如申請專利範圍第6項所述之半導體積，體電路中 ;前述第1及第2開關MO S電晶體乃被結合成並聯形態 本紙張尺度適用中國國家操準（CNS ) A4規格（210X297公釐） 8T 12. ί〇，ί f' Jt： Α8 Β8 C8 D8 六、申請專利範園 ，而在前述第1期間前述第2開關MO S電晶體乃被成爲 ◦甘F狀態者· 8.如_請專利範圍第7項所述之半導體積體電路中 ;前[述反相器電路乃爲CMOS反相器電路者。 9 ..如申請專利範圍第8項所述之半導體積體電路中 ;前述第1端子乃爲外部電源電壓者· 10.如申請專利範圍第9項所述之半導體積體電路 中；前述一對之P溝道型S電晶體乃具有：承接前述 一對之資料線之電位之一對閘極及一對之汲極’而將前述 一對之P溝道型Μ 0 S電晶體之一方之Μ 0 S電晶體之汲 極與另一方之閘極互相加以結合所成；前述一對之Ν溝道 型Μ 0 S電晶體則具有：被共同結合之一對之源極及承接 前述一對之資料線之電位之一對閘極及一對之汲極等；而 ，將前述一對之Ν溝道型MO S電晶體之一方之M.OS電晶 體之汲」極與另一方之閘極互相加以結合所成者。 1 1 一種半導體積體電路，其特.徵爲·· 備有放大互補信號線之電位差之差動放大電路；及在 前述差動放大電路之髙電位倾之傳動線路（drive liire) 供給第1驅動電壓之第1開關MO S電晶體；及對前述傳 動線路供給第1驅動電壓之第1開關MO S電晶體；及對 前述傳動線路供.給較前述第1驅動電壓爲低電平之第2驅 動電壓之第2開關MO S電晶體；及在前述差動放大電路 之活性化期間’最初經由前述第1開關MO S電晶體將第 1驅動電壓供給傳動線路，接著經由第2開關MO S電晶 本紙張尺度適用中國國家標準（CNS &gt; A4規格（210X297公釐） 請 先 閱 背 ιέ 之 注 意 項 經濟部中央標準局負工消費合作社印裝 4 8T 12. ί〇，ί f' Jt： Α8 Β8 C8 D8 六、申請專利範園 ，而在前述第1期間前述第2開關MO S電晶體乃被成爲 ◦甘F狀態者· 8.如_請專利範圍第7項所述之半導體積體電路中 ;前[述反相器電路乃爲CMOS反相器電路者。 9 ..如申請專利範圍第8項所述之半導體積體電路中 ;前述第1端子乃爲外部電源電壓者· 10.如申請專利範圍第9項所述之半導體積體電路 中；前述一對之P溝道型S電晶體乃具有：承接前述 一對之資料線之電位之一對閘極及一對之汲極’而將前述 一對之P溝道型Μ 0 S電晶體之一方之Μ 0 S電晶體之汲 極與另一方之閘極互相加以結合所成；前述一對之Ν溝道 型Μ 0 S電晶體則具有：被共同結合之一對之源極及承接 前述一對之資料線之電位之一對閘極及一對之汲極等；而 ，將前述一對之Ν溝道型MO S電晶體之一方之M.OS電晶 體之汲」極與另一方之閘極互相加以結合所成者。 1 1 一種半導體積體電路，其特.徵爲·· 備有放大互補信號線之電位差之差動放大電路；及在 前述差動放大電路之髙電位倾之傳動線路（drive liire) 供給第1驅動電壓之第1開關MO S電晶體；及對前述傳 動線路供給第1驅動電壓之第1開關MO S電晶體；及對 前述傳動線路供.給較前述第1驅動電壓爲低電平之第2驅 動電壓之第2開關MO S電晶體；及在前述差動放大電路 之活性化期間’最初經由前述第1開關MO S電晶體將第 1驅動電壓供給傳動線路，接著經由第2開關MO S電晶 本紙張尺度適用中國國家標準（CNS &gt; A4規格（210X297公釐） 請 先 閱 背 ιέ 之 注 意 項 經濟部中央標準局負工消費合作社印裝 4A8 B8 1 C8 D8 VI. Patent application scope (ial amplifier circuit); and external power supplied from the external department (please read the precautions on the back first and then fill out this page) to reduce the source voltage to form the aforementioned Step 1 of the step-down voltage below the selection level of the word line: and formation: The aforementioned external power supply is initially supplied to the aforementioned activation timing at the activation timing of the aforementioned differential amplifier circuit. The first drive control signal of the differential amplifier circuit is activated at the same time as the first L · drive control signal is activated and the first drive control f signal is inactivated and activated, and will be activated in the aforementioned step-down circuit. The generated step-down voltage is a control circuit for the second drive control signal to which the working power of the differential amplifier circuit is supplied; and the aforementioned control circuit also includes a delay snow path which specifies the period during which the aforementioned first drive control signal is activated; The delay circuit includes an inverter circuit that receives the external power supply voltage as a working power source, and a period during which the first drive control signal is activated. Dependence of the voltage source having a negative; and the like are to constitute. 4. In the semiconductor integrated circuit as described in item 3 of the scope of the patent application; the aforementioned step-down circuit is formed at the series connection point of the current source and the rubidium resistor. Circuit person. 5. As described in the semiconductor integrated circuit described in item 4 of the scope of the patent application: the aforementioned memory cell is a dynamic type of a hundred million cells, and is provided with a voltage of approximately half of the voltage of the output terminal of the aforementioned step-down circuit, A circuit formed as a precharge voltage of the aforementioned mutual capture signal line; and an equalize circuit which selectively conducts the aforementioned complementary signal line; and corresponds to the turn-on timing of the complementary signal line generated by the aforementioned compensation circuit, corresponding to Complementary signal cables The paper size of the paper uses the Chinese National Standard (CNS) A4 specification (21〇 × 297 mm) 8 ^ 1 \ 4 amendments: No A8, B8 1 C8 D8 No. 6, the scope of patent application for the aforementioned pre-charge voltage Pre-charging circuit; waiting for luxury. 6. A semiconductor integrated circuit, characterized by: (Please read the precautions on the back before filling out this page) Contains: a pair of data lines (, data 1 i ne); and a pair of P-channel MO CMOS latch circui-t of S transistor and a pair of N-channel MMOS transistor, and amplifying the aforementioned-pair of data line potential difference sense amplifier; and receiving the first voltage The first terminal: and the second terminal for receiving a second voltage lower than the aforementioned first voltage; and the P-channel type MOS transistor of the aforementioned pair is provided at the source and The first switch M0S transistor between the aforementioned first terminal; and the second switch M0S transistor provided between the pair of the source and the aforementioned second terminal in a common combination; consumption by employees of the Central Standards Bureau of the Ministry of Economic Affairs The cooperative prints and controls the first and second switching MOS transistors such that the first switching MOS transistor is turned on during the first period, and the first period is described in the second period. The switch M 0 S transistor is brought to the 0 FF state, and the aforementioned second switch MO S transistor is turned to the ON state. Control circuit, etc .; and the control circuit also includes a delay circuit that specifies the first period of time »The delay circuit includes an inverter circuit that uses the first voltage as the working power source: etc. as the constituent. The semiconductor product and body circuit described in item 6 of the patent scope; the aforementioned first and second switch MO S transistors are combined into a parallel configuration. This paper is applicable to China National Standards (CNS) A4 specifications (210X297 mm) 8 ^ 1 \ 4 amendments: No A8, B8 1 C8 D8. 6. The scope of patent application for the pre-charging circuit for the aforementioned pre-charging voltage; 6. A semiconductor integrated circuit, characterized by: (Please read the precautions on the back before filling out this page) Contains: a pair of data lines (, data 1 i ne); and a pair of P-channel MO CMOS latch circui-t of S transistor and a pair of N-channel MMOS transistor, and amplifying the aforementioned-pair of data line potential difference sense amplifier; and receiving the first voltage The first terminal: and the second terminal for receiving a second voltage lower than the aforementioned first voltage; and the P-channel type MOS transistor of the aforementioned pair is provided at the source and The first switch M0S transistor between the aforementioned first terminal; and the second switch M0S transistor provided between the pair of the source and the aforementioned second terminal in a common combination; consumption by employees of the Central Standards Bureau of the Ministry of Economic Affairs The cooperative prints and controls the first and second switching MOS transistors such that the first switching MOS transistor is turned on during the first period, and the first period is described in the second period. The switch M 0 S transistor is brought to the 0 FF state, and the aforementioned second switch MO S transistor is turned to the ON state. Control circuit, etc .; and the control circuit also includes a delay circuit that specifies the first period of time »The delay circuit includes an inverter circuit that uses the first voltage as the working power source: etc. as the constituent. The semiconductor product and body circuit described in item 6 of the patent scope; the aforementioned first and second switch MO S transistors are combined into a parallel configuration. This paper is applicable to China National Standards (CNS) A4 specifications (210X297 mm) 8T 12. ί〇, ί f 'Jt: Α8 Β8 C8 D8 VI. Apply for a patent garden, and during the aforementioned first period, the aforementioned second switch MO S transistor has become a state of “F”. 8. If _ please In the semiconductor integrated circuit described in item 7 of the patent scope; the aforementioned inverter circuit is a CMOS inverter circuit. 9 .. In the semiconductor integrated circuit described in item 8 of the scope of patent application; the aforementioned first terminal is an external power supply voltage; 10. In the semiconductor integrated circuit described in item 9 of the scope of patent application; The opposite P-channel type S transistor has one of the following: a pair of gates and a pair of drains that receive one of the potential of the data line of the aforementioned pair, and one of the P-channel M 0 S transistor of the aforementioned pair The drain of the M 0 S transistor and the gate of the other are combined; the N-channel M 0 S transistor of the aforementioned pair has: the source of a pair that is combined together and the aforementioned one One of the potentials of the pair of data lines is a pair of a gate electrode and a pair of a drain electrode, and the drain of the M.OS transistor of one of the aforementioned pair of N-channel MOS transistors and the other The gates are combined with each other. 1 1 A semiconductor integrated circuit, characterized in that: a differential amplifier circuit provided with amplifying a potential difference of a complementary signal line; and a drive liire of a potential tilt of the differential amplifier circuit is provided to the first The first switching MO S transistor of the driving voltage; and the first switching MO S transistor of the first driving voltage supplied to the aforementioned transmission line; and the first switching MO S transistor of a lower driving level than the aforementioned first driving voltage. 2 driving voltage of the second switch MO S transistor; and during the activation period of the aforementioned differential amplifier circuit, the first driving voltage is first supplied to the transmission line via the first switching MO S transistor, and then via the second switch MO S The paper size of the transistor is applicable to the Chinese national standard (CNS &gt; A4 size (210X297mm). Please read the note below. Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 4 8T 12. ί〇, ί f 'Jt ： Α8 Β8 C8 D8 VI. Apply for patents, and during the aforementioned first period, the aforementioned second switch MO S transistor is made into a “F” state. 8. As described in the patent scope, please refer to the semiconductor product Body circuit The aforementioned [inverter circuit is a CMOS inverter circuit. 9 .. In the semiconductor integrated circuit described in item 8 of the scope of patent application; the aforementioned first terminal is an external power supply voltage. 10. Such as In the semiconductor integrated circuit described in item 9 of the scope of the patent application, the P-channel S transistor of the aforementioned pair has: a pair of gates and a pair of drains that receive the potential of the data line of the aforementioned pair. The drain of one M 0 S transistor of one of the aforementioned P-channel M 0 S transistors and the gate of the other one are combined; the N-channel M 0 S of one of the aforementioned pair is formed The crystal has: a pair of source electrodes and a pair of gate electrodes and a pair of drain electrodes that are connected to the potential of the data line of the aforementioned pair; and an N-channel type MO S of the aforementioned pair One of the crystals is a combination of the drain of the M.OS transistor and the gate of the other. 1 1 A semiconductor integrated circuit whose characteristics are as follows: Amplified potential difference between complementary signal lines A differential amplifier circuit; and a drive liire for the potential tilt of the aforementioned differential amplifier circuit The first switch MO S transistor of the first drive voltage; and the first switch MO S transistor of the first drive voltage that supplies the first drive voltage; and the first drive voltage that is lower than the first drive voltage. The second switch MO S transistor of the second drive voltage; and during the activation period of the differential amplifier circuit, the first drive voltage is first supplied to the transmission line via the first switch MO S transistor, and then via the second switch The paper size of the MO S transistor is in accordance with the Chinese national standard (CNS &gt; A4 size (210X297 mm). Please read the cautionary note first. Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 D8_；__ 六、申請專利範圍 體將第2驅動電壓供給傳動線路之開關控制信號之發生機 構等；而前述第1開關MOS電晶體乃爲P溝道型，而其 .· · ··- . 開關控制信‘之髙電平電位乃爲第1驅動電壓之電位；前 述第2開關MO S電晶體則爲N溝道型，而其開關控制信 號之髙電平電位亦爲較第2驅動電壓被昇壓之電位；等爲 構成者* 1 2 . —種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電路之降壓電路；及選擇端子被結合在字線之複數個之 記憶格；及被連接在前述記憶格之資料輸出入端子之互捕 信號線；及放大互補信號線之電位差之差動放大電路；及 對前述孝動放大電路之高電位側之、傳動線路供給前述電源 電壓之第1開關Μ 0 S電晶體；及對前述傳動線路供給前 述降壓電壓之第2開關MO S電晶體；及在前述差動放大 電路之活性化期間，最初經由前述第1開關MOS電晶體 將電源電壓供給傳動線路，接著經由第2開關Μ 0 S電晶 體，將降壓電壓供給傳動線路之開關控制信號之發生機構 一等一;_而前述第1開關MOS電晶體乃爲Ρ溝道型_，且其開 關控制信號之髙電平電位亦爲從前述外部所供給之電源電 壓之電位，前述第2開關MO S電晶體則爲Ν溝道型，且 其開關控制信號之髙電平電位則爲較前述降壓電壓被昇壓 之電位：等-爲—構成者· 1 3 .如申請專利範圍第1 2項所述之半導體積體電 路中；前述被昇壓之電位乃爲與較前述降壓電壓髙出等於 本^張尺度逋用中國國家標準（CNS ) Α4規格（210X297公釐） 装 訂 - - f (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装D8_; __ VI. The scope of the patent application is to generate the second drive voltage to the switch control signal generating mechanism of the drive circuit, etc .; and the first switch MOS transistor is a P-channel type, and its ... The 髙 level potential of the switch control signal is the potential of the first drive voltage; the aforementioned second switch MO S transistor is an N-channel type, and the 髙 level potential of the switch control signal is also higher than the second drive voltage. Boosted potential; etc. are the constituents * 1 2. A semiconductor integrated circuit characterized by: having a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down circuit; and A plurality of memory cells whose selection terminals are combined with the word line; and mutual capture signal lines connected to the data input / output terminals of the memory cell; and a differential amplifier circuit that amplifies the potential difference of the complementary signal lines; and The first switch M 0 S transistor of the high potential side of the amplifying circuit, the drive line supplying the aforementioned power supply voltage; and the second switch MO S transistor of the aforementioned step-down voltage supplying the drive line; and the differential amplifier circuit During activation, the power supply voltage is first supplied to the transmission line via the first switch MOS transistor, and then the step-down voltage is supplied to the transmission control signal generation mechanism of the transmission line via the second switch M 0 S transistor; _ The first switch MOS transistor is a P-channel type, and the level potential of the switch control signal is also the potential of the power supply voltage supplied from the outside. The second switch MO S transistor is N. Channel type, and the 髙 level potential of its switching control signal is a potential that is boosted compared to the aforementioned step-down voltage: Equal-to-constructor · 1 3. The semiconductor product described in item 12 of the scope of patent application In the body circuit; the aforementioned boosted potential is equal to the above-mentioned step-down voltage, which is equal to this standard. It uses the Chinese National Standard (CNS) A4 specification (210X297 mm). Binding--f (Please read the back first (Please note this page before filling in this page) D8_；__ 六、申請專利範圍 體將第2驅動電壓供給傳動線路之開關控制信號之發生機 構等；而前述第1開關MOS電晶體乃爲P溝道型，而其 .· · ··- . 開關控制信‘之髙電平電位乃爲第1驅動電壓之電位；前 述第2開關MO S電晶體則爲N溝道型，而其開關控制信 號之髙電平電位亦爲較第2驅動電壓被昇壓之電位；等爲 構成者* 1 2 . —種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電路之降壓電路；及選擇端子被結合在字線之複數個之 記憶格；及被連接在前述記憶格之資料輸出入端子之互捕 信號線；及放大互補信號線之電位差之差動放大電路；及 對前述孝動放大電路之高電位側之、傳動線路供給前述電源 電壓之第1開關Μ 0 S電晶體；及對前述傳動線路供給前 述降壓電壓之第2開關MO S電晶體；及在前述差動放大 電路之活性化期間，最初經由前述第1開關MOS電晶體 將電源電壓供給傳動線路，接著經由第2開關Μ 0 S電晶 體，將降壓電壓供給傳動線路之開關控制信號之發生機構 一等一;_而前述第1開關MOS電晶體乃爲Ρ溝道型_，且其開 關控制信號之髙電平電位亦爲從前述外部所供給之電源電 壓之電位，前述第2開關MO S電晶體則爲Ν溝道型，且 其開關控制信號之髙電平電位則爲較前述降壓電壓被昇壓 之電位：等-爲—構成者· 1 3 .如申請專利範圍第1 2項所述之半導體積體電 路中；前述被昇壓之電位乃爲與較前述降壓電壓髙出等於 本^張尺度逋用中國國家標準（CNS ) Α4規格（210X297公釐） 装 訂 - - f (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装D8_; __ VI. The scope of the patent application is to generate the second drive voltage to the switch control signal generating mechanism of the drive circuit, etc .; and the first switch MOS transistor is a P-channel type, and its ... The 髙 level potential of the switch control signal is the potential of the first drive voltage; the aforementioned second switch MO S transistor is an N-channel type, and the 髙 level potential of the switch control signal is also higher than the second drive voltage. Boosted potential; etc. are the constituents * 1 2. A semiconductor integrated circuit characterized by: having a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down circuit; and A plurality of memory cells whose selection terminals are combined with the word line; and mutual capture signal lines connected to the data input / output terminals of the memory cell; and a differential amplifier circuit that amplifies the potential difference of the complementary signal lines; and The first switch M 0 S transistor of the high potential side of the amplifying circuit, the drive line supplying the aforementioned power supply voltage; and the second switch MO S transistor of the aforementioned step-down voltage supplying the drive line; and the differential amplifier circuit During activation, the power supply voltage is first supplied to the transmission line via the first switch MOS transistor, and then the step-down voltage is supplied to the transmission control signal generation mechanism of the transmission line via the second switch M 0 S transistor; _ The first switch MOS transistor is a P-channel type, and the level potential of the switch control signal is also the potential of the power supply voltage supplied from the outside. The second switch MO S transistor is N. Channel type, and the 髙 level potential of its switching control signal is a potential that is boosted compared to the aforementioned step-down voltage: Equal-to-constructor · 1 3. The semiconductor product described in item 12 of the scope of patent application In the body circuit; the aforementioned boosted potential is equal to the above-mentioned step-down voltage, which is equal to this standard. It uses the Chinese National Standard (CNS) A4 specification (210X297 mm). Binding--f (Please read the back first (Please note this page before filling in this page) 經濟部中央標準局員工消费合作社印裝 六、申請專利範園 前述第2開關MO S電晶體之/閎值之電壓份量之電位相等 ，或亦較其爲髙之電位者。 14.如申請專利範圍第13項所述之半導體積體電 路中；備有承接前述降壓電壓並輸出前述被昇壓之電位之 昇壓電路，而前述昇壓電路之輸出電平乃爲字線選擇電平 者。 1 5 . —種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電路之降壓電路；及選擇端子被結合在字線之複數個之 記憶格；及被連接在前述記憶格之資料輸出入端子之互捕 信轉線；及放大互捕信號線之電位差之差動放大電路；及 對前述差動放大電路之髙電位側之傳動線路供給前述電滬 電壓之第1開關MO S電晶體；及對前述傳動線路供給前 述降壓電壓之第2開關MO S電晶體；及在前述差動放大 電路之活性化期間，最初經由前述第1開關MO S電晶體 將電源電壓供給傳動線路，接著經由第2開關MO S電晶 體，將降壓電懕供給傳動線路之開關控制信號之發生機構 等；及對前述外部所供給之電源電壓具有負之極性之負電 壓之發生電路等，•而前述第1開關MO S電晶體乃爲P溝 道型，且其開關控制信號之髙電平電壓亦爲從前述外部被 供給之電源電壓之電平，前述第2開關MO S電晶體則爲 P溝道型，且其開關控制信號之低電平電壓則爲較前述負 電歷之電平；等爲構成者。 本紙張尺度適用中國國家揉準（CNS ) 規格（210X297公嫠） (請先閱讀背面之注意事項再填寫本頁) 、τPrinted by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 6. Patent Application Fanyuan. The potential of the voltage component of the second switch MO S transistor is equal to or equal to the potential of 髙. 14. The semiconductor integrated circuit according to item 13 of the scope of application for a patent; a booster circuit is provided to receive the aforementioned step-down voltage and output the aforementioned boosted potential, and the output level of the aforementioned booster circuit is Select level for word line. 1 5. A semiconductor integrated circuit, characterized in that: it is provided with a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down circuit; and a plurality of selection terminals are connected to a plurality of word lines. A memory cell; and a mutual capture signal transfer line connected to the data input and output terminals of the memory cell; and a differential amplifier circuit that amplifies the potential difference of the mutual capture signal line; and a transmission line on the pseudo-potential side of the differential amplifier circuit The first switch MO S transistor which supplies the aforementioned power-supply voltage; and the second switch MO S transistor which supplies the aforementioned step-down voltage to the transmission line; and during the activation of the differential amplifier circuit, the first The switch MO S transistor supplies the power supply voltage to the transmission line, and then, through the second switch MO S transistor, supplies the step-down voltage to the transmission circuit's switching control signal generation mechanism, etc .; and has a negative effect on the aforementioned externally supplied power supply voltage. The polarity of the negative voltage generation circuit, etc., and the first switch MO S transistor is a P-channel type, and the 髙 level voltage of its switch control signal is also The level of the supplied power supply voltage is the P-channel type of the second switching MOS transistor, and the low-level voltage of the switching control signal is a level lower than the aforementioned negative calendar; etc. are the constituents. This paper size applies to China National Standards (CNS) specifications (210X297 cm) (Please read the precautions on the back before filling this page), τ 經濟部中央標準局員工消费合作社印裝 六、申請專利範園 前述第2開關MO S電晶體之/閎值之電壓份量之電位相等 ，或亦較其爲髙之電位者。 14.如申請專利範圍第13項所述之半導體積體電 路中；備有承接前述降壓電壓並輸出前述被昇壓之電位之 昇壓電路，而前述昇壓電路之輸出電平乃爲字線選擇電平 者。 1 5 . —種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電路之降壓電路；及選擇端子被結合在字線之複數個之 記憶格；及被連接在前述記憶格之資料輸出入端子之互捕 信轉線；及放大互捕信號線之電位差之差動放大電路；及 對前述差動放大電路之髙電位側之傳動線路供給前述電滬 電壓之第1開關MO S電晶體；及對前述傳動線路供給前 述降壓電壓之第2開關MO S電晶體；及在前述差動放大 電路之活性化期間，最初經由前述第1開關MO S電晶體 將電源電壓供給傳動線路，接著經由第2開關MO S電晶 體，將降壓電懕供給傳動線路之開關控制信號之發生機構 等；及對前述外部所供給之電源電壓具有負之極性之負電 壓之發生電路等，•而前述第1開關MO S電晶體乃爲P溝 道型，且其開關控制信號之髙電平電壓亦爲從前述外部被 供給之電源電壓之電平，前述第2開關MO S電晶體則爲 P溝道型，且其開關控制信號之低電平電壓則爲較前述負 電歷之電平；等爲構成者。 本紙張尺度適用中國國家揉準（CNS ) 規格（210X297公嫠） (請先閱讀背面之注意事項再填寫本頁) 、τ 87. 12. 1〇 年月 ,.，家ί.匕丨A8 Β8 C8 D8 經濟部中央標準局員工消費合作社印製 々、申請專利範圍 16.如申請專利範圍第15項所述之半導體積體電 路中；前述負電壓之發生電路乃爲基板偏壓之發生電路者 A 0 1 7 . —種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電壓之降壓電路；及形成字線之選擇電平之昇壓電路； 及選擇端子被結合在字線之複數個之記億格；及被連接在 前述記憶格之資料輸出入端子之互補信號線；及放大互補 信號線之電位差之差動放大電路；及對前述差動放大電路 之髙電位側之傳動線路供給前述降壓電壓之開關MO S電 晶體；及在前述差動放大電路之活性化期間，經由前述開 關MO S電晶體；將降壓電壓供給傳動線路之開關控制信 號之發生機構等，而前述開關MO S電晶體乃爲N溝道型 ’且其開關控制#號之低電平電位乃爲接地電位.，高電平 電位則爲以前述昇壓電路所形成之字線選擇電平之電位； 等爲構成者。 1 8 .—種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電路之降壓電路；及選.擇端子被結合在字線之複數個之 記憶格；及被連接在前述記憶格之資料輸_入端子之互捕 信號線：及放大互補信號線之電位差之差動放大電路：及 對前述差動放大電路之髙電位側之傳動線路供給降壓電壓 之第2開關MO S電晶體及在前述差動放大電路之活性 化期間*經由開關M〇 S電晶體將降壓電壓供給傳動線路 本紙張尺度適用中國國家標準（CNS_) A4規格（210X297公釐） ---------1 裝 Li &gt; “ i -· (請先閱讀背面之注意事項再填寫本頁) 訂 -7 - 87. 12. 1〇 年月 ,.，家ί.匕丨A8 Β8 C8 D8 經濟部中央標準局員工消費合作社印製 々、申請專利範圍 16.如申請專利範圍第15項所述之半導體積體電 路中；前述負電壓之發生電路乃爲基板偏壓之發生電路者 A 0 1 7 . —種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電壓之降壓電路；及形成字線之選擇電平之昇壓電路； 及選擇端子被結合在字線之複數個之記億格；及被連接在 前述記憶格之資料輸出入端子之互補信號線；及放大互補 信號線之電位差之差動放大電路；及對前述差動放大電路 之髙電位側之傳動線路供給前述降壓電壓之開關MO S電 晶體；及在前述差動放大電路之活性化期間，經由前述開 關MO S電晶體；將降壓電壓供給傳動線路之開關控制信 號之發生機構等，而前述開關MO S電晶體乃爲N溝道型 ’且其開關控制#號之低電平電位乃爲接地電位.，高電平 電位則爲以前述昇壓電路所形成之字線選擇電平之電位； 等爲構成者。 1 8 .—種半導體積體電路，其特徵爲： 備有：將從外部所供給之電源電壓加以降壓以形成降 壓電路之降壓電路；及選.擇端子被結合在字線之複數個之 記憶格；及被連接在前述記憶格之資料輸_入端子之互捕 信號線：及放大互補信號線之電位差之差動放大電路：及 對前述差動放大電路之髙電位側之傳動線路供給降壓電壓 之第2開關MO S電晶體及在前述差動放大電路之活性 化期間*經由開關M〇 S電晶體將降壓電壓供給傳動線路 本紙張尺度適用中國國家標準（CNS_) A4規格（210X297公釐） ---------1 裝 Li &gt; “ i -· (請先閱讀背面之注意事項再填寫本頁) 訂 -7 -Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 6. Patent Application Fanyuan. The potential of the voltage component of the second switch MO S transistor is equal to or equal to the potential of 髙. 14. The semiconductor integrated circuit according to item 13 of the scope of application for a patent; a booster circuit is provided to receive the aforementioned step-down voltage and output the aforementioned boosted potential, and the output level of the aforementioned booster circuit is Select level for word line. 1 5. A semiconductor integrated circuit, characterized in that: it is provided with a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down circuit; and a plurality of selection terminals are connected to a plurality of word lines. A memory cell; and a mutual capture signal transfer line connected to the data input and output terminals of the memory cell; and a differential amplifier circuit that amplifies the potential difference of the mutual capture signal line; and a transmission line on the pseudo-potential side of the differential amplifier circuit The first switch MO S transistor which supplies the aforementioned power-supply voltage; and the second switch MO S transistor which supplies the aforementioned step-down voltage to the transmission line; and during the activation of the differential amplifier circuit, the first The switch MO S transistor supplies the power supply voltage to the transmission line, and then, through the second switch MO S transistor, supplies the step-down voltage to the transmission circuit's switching control signal generation mechanism, etc .; and has a negative effect on the aforementioned externally supplied power supply voltage. The polarity of the negative voltage generation circuit, etc., and the first switch MO S transistor is a P-channel type, and the 髙 level voltage of its switch control signal is also The level of the supplied power supply voltage is the P-channel type of the second switching MOS transistor, and the low-level voltage of the switching control signal is a level lower than the aforementioned negative calendar; etc. are the constituents. This paper size applies to China National Standards (CNS) specifications (210X297 cm) (Please read the precautions on the back before filling out this page), τ 87. 12.10,., Jia ί. A8 Β8 C8 D8 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, applying for patents 16. In the semiconductor integrated circuit described in item 15 of the scope of applying for patents; the aforementioned negative voltage generating circuit is the substrate bias generating circuit A 0 1 7. — A semiconductor integrated circuit, characterized in that: it is provided with a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down voltage; and raises a selection level of a word line Voltage circuit; and a plurality of hundreds of millions of grids where the selection terminal is combined with the word line; and a complementary signal line connected to the data input and output terminals of the aforementioned memory grid; and a differential amplifier circuit that amplifies the potential difference of the complementary signal line; And the switch MO S transistor which supplies the aforementioned step-down voltage to the transmission line on the pseudo-potential side of the differential amplifier circuit; and during the activation period of the differential amplifier circuit, via the switch MO S transistor ; The step-down voltage is supplied to the switching control signal generating mechanism of the transmission line, etc., and the aforementioned switch MO S transistor is an N-channel type, and the low-level potential of its switch control # is the ground potential. The flat potential is a potential selected by the word line formed by the aforementioned booster circuit; 18. A semiconductor integrated circuit, characterized in that: it is provided with a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down circuit; and a plurality of optional terminals that are combined with the word line. Each memory cell; and the mutual capture signal line connected to the data input terminal of the aforementioned memory cell: and a differential amplifier circuit that amplifies the potential difference of the complementary signal line: and the transmission to the pseudo-potential side of the differential amplifier circuit The second switch MO S transistor that supplies the step-down voltage to the line and during the activation period of the aforementioned differential amplifier circuit * supplies the step-down voltage to the transmission line via the switch M 0S transistor. This paper applies the Chinese national standard (CNS_) A4 Specifications (210X297mm) --------- 1 Install Li &gt; "i-· (Please read the precautions on the back before filling this page) Order -7-87. 12. January, 2010 . ， Home. A8 Β8 C8 D8 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, applied for patent scope 16. In the semiconductor integrated circuit described in item 15 of the scope of patent application; the aforementioned negative voltage generating circuit Is for the generation of substrate bias A 0 1 7. A semiconductor integrated circuit, which is characterized by: a step-down circuit that steps down a power supply voltage supplied from the outside to form a step-down voltage; and a selection level that forms a word line Step-up circuit; and several hundred million grids with selection terminals combined in word lines; and complementary signal lines connected to the data input and output terminals of the aforementioned memory grid; and differential amplifier circuits that amplify potential differences of complementary signal lines ; And the switch MO S transistor that supplies the aforementioned step-down voltage to the transmission line on the pseudo-potential side of the differential amplifier circuit; and during the activation of the differential amplifier circuit, via the switch MO S transistor; A mechanism for generating a switching control signal for a voltage supply transmission circuit, and the aforementioned switch MO S transistor is an N-channel type, and the low-level potential of the switch control # is a ground potential. The high-level potential is The potential of the word line selection level formed by the aforementioned booster circuit; etc. are the constituents. 1 8. A semiconductor integrated circuit, characterized in that: it is provided with: a power supply voltage supplied from the outside is added Step-down circuit that steps down to form a step-down circuit; and select multiple memory cells whose terminals are combined with the word line; and mutual capture signal lines connected to the data input_input terminals of the aforementioned memory cell: and amplification Differential amplifier circuit of potential difference of complementary signal line: and the second switch MO S transistor which supplies a step-down voltage to the transmission line on the potential side of the differential amplifier circuit and during the activation period of the differential amplifier circuit * The switch M0S transistor supplies the step-down voltage to the drive circuit. The paper size applies the Chinese National Standard (CNS_) A4 specification (210X297 mm) --------- 1 Li &gt; "i-· (Please (Please read the notes on the back before filling out this page) Order -7- A8 B8 C8 D8 六、申請專利範圍 之開關控制信號之發生機構；及對前述電源電壓具有負之 / · 極性之基板偏壓之發生電路等；而前述開關MO S電晶體 乃爲p溝道Μ ’且其開關控制信號之低電平電位乃爲前述 基板偏壓’高電平電位則爲前述降摩電壓以上之電位；等 爲構成者。 19,τ種半導體積體電路，其特徵爲： 含有：一對之資料線； 荩備有一對之Ρ溝道型MO S電晶體及一對之Ν溝道 型MO S電晶體之CMO S閂鎖電路，而將前述一對之資 料線之電位差.加以放大之感測放大器（sen s.e ampl ifier )； 及承接第1電壓之第1端子； 及承接較前述第1電壓爲低之第2電壓之第2端子； 及被設在前述一對之P溝道型Μ 0 S電晶體.中被共同 結合之一對源極與前述第1端子之間之第1開關MO S電 晶體； 及被設在前述共同結合之一對之源極與前述第2端子 之間k：N溝道型之第2開關MOS電晶體； - 及向前述第1及第2開關MO S電晶體MO S電晶體 之閘極輸出信號成爲：在第1期間前述第1開關1^105電 晶體被成爲ON狀態，在前述第1期間後之第2期間’前 述第1開關MO S電晶體被成爲◦ F F狀態，且前述第2 開關MO S、電晶體被成爲ON狀態等之控制電路等； 而在前述第2期間，前述第2開關！^〇 s電晶體之鬧 本紙張尺度適用中國國家揉準（CNS)A4規格（210x297公釐）_ R _ ^^1 tv 1^1 nn am I,---- .1^1 —^ϋ —^il· J \,J· nn I , .. &gt; &gt; 、 « (請先閲讀背面之注意事項再填寫本頁) 經 濟 部 中 央 標 準 員 工 消 費 合 作 社 印 製A8 B8 C8 D8 VI. Patent-applying switch control signal generating mechanism; and a substrate bias generating circuit with negative / polarity to the aforementioned power supply voltage; and the aforementioned switching MO S transistor is a p-channel M 'And the low-level potential of its switch control signal is the aforementioned substrate bias.' The high-level potential is the potential above the aforementioned friction reduction voltage; etc. are the constituents. 19, τ semiconductor integrated circuits, which are characterized by: Containing: a pair of data lines; (1) a CMO S latch with a pair of P-channel MOS transistors and a pair of N-channel MOS transistors Lock the circuit and increase the potential difference between the data lines of the aforementioned pair. A sense amplifier (sen se amplifier) that amplifies; and a first terminal that receives the first voltage; and a second voltage that is lower than the first voltage A second terminal; and a first switch MO S transistor which is provided in the aforementioned pair of P-channel type M 0 S transistor and is combined with a pair of source and the first terminal; and K: N-channel type second switching MOS transistor provided between the source of a pair of the common pair and the second terminal; and to the first and second switching MO S transistors MO S transistors The gate output signal is: the first switch 1 ^ 105 transistor is turned on in the first period, and the second switch MOS transistor is turned into the FF state in the second period after the first period. In addition, the aforementioned second switch MO S, the transistor is turned on, and the control circuit, etc .; and in the aforementioned second period, the The second switch! ^ 〇s Noise of transistor This paper size is applicable to China National Standard (CNS) A4 (210x297 mm) _ R _ ^^ 1 tv 1 ^ 1 nn am I, ---- .1 ^ 1 — ^ ϋ — ^ Il · J \, J · nn I, .. &gt; &gt;, «(Please read the notes on the back before filling out this page) Printed by the Central Standard Staff Consumer Cooperative of the Ministry of Economic Affairs A8 B8 C8 D8 六、申請專利範圍 之開關控制信號之發生機構；及對前述電源電壓具有負之 / · 極性之基板偏壓之發生電路等；而前述開關MO S電晶體 乃爲p溝道Μ ’且其開關控制信號之低電平電位乃爲前述 基板偏壓’高電平電位則爲前述降摩電壓以上之電位；等 爲構成者。 19,τ種半導體積體電路，其特徵爲： 含有：一對之資料線； 荩備有一對之Ρ溝道型MO S電晶體及一對之Ν溝道 型MO S電晶體之CMO S閂鎖電路，而將前述一對之資 料線之電位差.加以放大之感測放大器（sen s.e ampl ifier )； 及承接第1電壓之第1端子； 及承接較前述第1電壓爲低之第2電壓之第2端子； 及被設在前述一對之P溝道型Μ 0 S電晶體.中被共同 結合之一對源極與前述第1端子之間之第1開關MO S電 晶體； 及被設在前述共同結合之一對之源極與前述第2端子 之間k：N溝道型之第2開關MOS電晶體； - 及向前述第1及第2開關MO S電晶體MO S電晶體 之閘極輸出信號成爲：在第1期間前述第1開關1^105電 晶體被成爲ON狀態，在前述第1期間後之第2期間’前 述第1開關MO S電晶體被成爲◦ F F狀態，且前述第2 開關MO S、電晶體被成爲ON狀態等之控制電路等； 而在前述第2期間，前述第2開關！^〇 s電晶體之鬧 本紙張尺度適用中國國家揉準（CNS)A4規格（210x297公釐）_ R _ ^^1 tv 1^1 nn am I,---- .1^1 —^ϋ —^il· J \,J· nn I , .. &gt; &gt; 、 « (請先閲讀背面之注意事項再填寫本頁) 經 濟 部 中 央 標 準 員 工 消 費 合 作 社 印 製 87. 19 }- 衫'JJ 一 補充 A8 B8 C8 D8 六、申請專利範圍 極電壓乃被成爲較前述第2電壓爲髙之電壓；等爲構成者 〇 (請先閲讀背面之注意事項再填寫本頁) 2 0 ·茹申請專利範圍第1 9項所述之半導體積體電 路中；前述控制電路乃含有規定前述第1期間之延遲電路 ，而前述第1期間之變動乃對前述第1電壓之變動具有負 之依存性者。 2 1 .如申請專利範圍第2 0項所述之半導體積體電 路中；前述延遲電路乃含有將前述第1電壓作爲工作電源 來接受之反相器電路者· 2 2.如申請專利範圍第2 1項所述之半導體積體電 路中；在前述第2期間，前述第2開fMO s電晶體之閘 極電壓’乃與前述第2電壓與前述第2開關MO S電晶體 之臨限值電壓之和之電壓相等，或較其爲、髙之電壓者。 2 3 如申請專利範圍第2 2項所述之半導體積體電 路中；前述第1及第2開關MO S電晶體乃被結合成並聯 形態，而在前述第1期間前述第2開關M 0S電晶體將成 爲0 F F狀態者· 經濟部中央標準局員工消費合作社印製 24·—種半導體積體電路，其特徵爲： 含有：一對之資料線； 及複數之字線； 及各被結合在前述一對之資料線之一方及前述複數之 字線之一個之複數之動態型記憶格； 及備有一對之Ρ溝道型MO S電晶體及一對之Ν溝道 型MO S電晶體之CMO S閂鎖電路，而放大前述一對之 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） 87. 19 }- 衫'JJ 一 補充 A8 B8 C8 D8 六、申請專利範圍 極電壓乃被成爲較前述第2電壓爲髙之電壓；等爲構成者 〇 (請先閲讀背面之注意事項再填寫本頁) 2 0 ·茹申請專利範圍第1 9項所述之半導體積體電 路中；前述控制電路乃含有規定前述第1期間之延遲電路 ，而前述第1期間之變動乃對前述第1電壓之變動具有負 之依存性者。 2 1 .如申請專利範圍第2 0項所述之半導體積體電 路中；前述延遲電路乃含有將前述第1電壓作爲工作電源 來接受之反相器電路者· 2 2.如申請專利範圍第2 1項所述之半導體積體電 路中；在前述第2期間，前述第2開fMO s電晶體之閘 極電壓’乃與前述第2電壓與前述第2開關MO S電晶體 之臨限值電壓之和之電壓相等，或較其爲、髙之電壓者。 2 3 如申請專利範圍第2 2項所述之半導體積體電 路中；前述第1及第2開關MO S電晶體乃被結合成並聯 形態，而在前述第1期間前述第2開關M 0S電晶體將成 爲0 F F狀態者· 經濟部中央標準局員工消費合作社印製 24·—種半導體積體電路，其特徵爲： 含有：一對之資料線； 及複數之字線； 及各被結合在前述一對之資料線之一方及前述複數之 字線之一個之複數之動態型記憶格； 及備有一對之Ρ溝道型MO S電晶體及一對之Ν溝道 型MO S電晶體之CMO S閂鎖電路，而放大前述一對之 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） A8 , 1 B8 C8 D8 ___ 六、申請專利範圍 資料線之電位差之感測放大器： 及承接第1電壓之第1端子； 及承接較4前述第1電壓爲低之第2電壓之第2端子； 及被設在前述一對之P溝道型MO S電晶體中被共同 結合之一對源極與前述第1端子之間之第1開關MO S® 晶體； 及被設在前述被共同結合之一對之源極與前述第2端 子之間之N溝道型之第2開關MO S電晶體； 及對前述第1及第2開關MOS電晶體之閘極輸出信 號成爲：在第1期間，前述第1開關MO S電晶體被成爲 ON狀態，在前述第1期間後之第2期間，前述第1開關 MO S電晶體被成爲OFF狀態，且前述第2開關MOS 電晶體被成爲0 N狀態等之控制電路； 及使前述第2電壓昇壓以輸出屏壓電壓之昇壓電路等 t 而在前述第2期間，前述昇壓電壓乃被供給前述第2 開關MO S電晶體之閘極；等爲搆成者。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 2 5.如申請專利範圍第2 4項所述之半導體積體電 路中；前述昇壓電壓乃被供給選擇字線者· 2 6.如申請專利範圍第2 5項所述之半導體積體電 路中；前述昇壓電壓乃被成爲與從前述第2電壓被昇壓等 於前述第2開關MO S電晶體之閾值份量之電壓相等，或 較其髙之電壓者· 2 7.如申請專利範圍第2 6項所述之半導體镡體電 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） -10 - A8 , 1 B8 C8 D8 ___ 六、申請專利範圍 資料線之電位差之感測放大器： 及承接第1電壓之第1端子； 及承接較4前述第1電壓爲低之第2電壓之第2端子； 及被設在前述一對之P溝道型MO S電晶體中被共同 結合之一對源極與前述第1端子之間之第1開關MO S® 晶體； 及被設在前述被共同結合之一對之源極與前述第2端 子之間之N溝道型之第2開關MO S電晶體； 及對前述第1及第2開關MOS電晶體之閘極輸出信 號成爲：在第1期間，前述第1開關MO S電晶體被成爲 ON狀態，在前述第1期間後之第2期間，前述第1開關 MO S電晶體被成爲OFF狀態，且前述第2開關MOS 電晶體被成爲0 N狀態等之控制電路； 及使前述第2電壓昇壓以輸出屏壓電壓之昇壓電路等 t 而在前述第2期間，前述昇壓電壓乃被供給前述第2 開關MO S電晶體之閘極；等爲搆成者。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 2 5.如申請專利範圍第2 4項所述之半導體積體電 路中；前述昇壓電壓乃被供給選擇字線者· 2 6.如申請專利範圍第2 5項所述之半導體積體電 路中；前述昇壓電壓乃被成爲與從前述第2電壓被昇壓等 於前述第2開關MO S電晶體之閾值份量之電壓相等，或 較其髙之電壓者· 2 7.如申請專利範圍第2 6項所述之半導體镡體電 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） -10 -A8 B8 C8 D8 VI. Patent-applying switch control signal generating mechanism; and a substrate bias generating circuit with negative / polarity to the aforementioned power supply voltage; and the aforementioned switching MO S transistor is a p-channel M 'And the low-level potential of its switch control signal is the aforementioned substrate bias.' The high-level potential is the potential above the aforementioned friction reduction voltage; etc. are the constituents. 19, τ semiconductor integrated circuits, which are characterized by: Containing: a pair of data lines; (1) a CMO S latch with a pair of P-channel MOS transistors and a pair of N-channel MOS transistors Lock the circuit and increase the potential difference between the data lines of the aforementioned pair. A sense amplifier (sen se amplifier) that amplifies; and a first terminal that receives the first voltage; and a second voltage that is lower than the first voltage A second terminal; and a first switch MO S transistor which is provided in the aforementioned pair of P-channel type M 0 S transistor and is combined with a pair of source and the first terminal; and K: N-channel type second switching MOS transistor provided between the source of a pair of the common pair and the second terminal; and to the first and second switching MO S transistors MO S transistors The gate output signal is: the first switch 1 ^ 105 transistor is turned on in the first period, and the second switch MOS transistor is turned into the FF state in the second period after the first period. In addition, the aforementioned second switch MO S, the transistor is turned on, and the control circuit, etc .; and in the aforementioned second period, the The second switch! ^ 〇s Transistor size This paper is suitable for China National Standard (CNS) A4 (210x297 mm) _ R _ ^^ 1 tv 1 ^ 1 nn am I, ---- .1 ^ 1 — ^ ϋ — ^ Il · J \, J · nn I, .. &gt; &gt;, «(Please read the notes on the back before filling out this page) Printed by the Central Standard Staff Consumer Cooperative of the Ministry of Economic Affairs 87. 19} -shirt 'JJ A supplement A8 B8 C8 D8 VI. Patent application scope The extreme voltage is regarded as a voltage that is 较 higher than the second voltage mentioned above; etc. are the constituents 0 (Please read the precautions on the back before filling out this page) 2 0 · Ru apply for a patent In the semiconductor integrated circuit described in item 19 of the scope, the control circuit includes a delay circuit that specifies the first period, and the change in the first period is a negative dependency on the change in the first voltage. 2 1. The semiconductor integrated circuit as described in item 20 of the scope of patent application; the delay circuit includes an inverter circuit that accepts the aforementioned first voltage as a working power supply. 2 2. 2 In the semiconductor integrated circuit described in item 1; during the aforementioned second period, the gate voltage 'of the aforementioned second ON fMO s transistor is the threshold value between the aforementioned second voltage and the aforementioned second switching MO S transistor The sum of the voltages is equal to or more than the voltage of 髙. 2 3 In the semiconductor integrated circuit described in item 22 of the scope of the patent application; the aforementioned first and second switching MO S transistors are combined in parallel, and during the aforementioned first period, the aforementioned second switch M 0S is electrically connected. The crystal will become 0 FF. · 24 · printed semiconductor integrated circuits by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, which are characterized by: containing: a pair of data lines; and plural zigzag lines; One of the aforementioned one pair of data lines and one of the aforementioned plural word lines of a dynamic memory cell; and a pair of P-channel MOS transistors and one pair of N-channel MOS transistors CMO S latch circuit, and the paper size of the aforesaid pair is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 87. 19} -shirt 'JJ supplement A8 B8 C8 D8 The voltage is considered to be a voltage that is higher than the second voltage mentioned above; etc. are the constituents. (Please read the precautions on the back before filling this page.) 2 0 · Rules for semiconductor integrated circuits described in item 19 of the scope of patent application Medium; the aforementioned control circuit contains The predetermined period of the first delay circuit, and the period of change is the first person has a negative dependence of the variation of the first voltage. 2 1. The semiconductor integrated circuit as described in item 20 of the scope of patent application; the delay circuit includes an inverter circuit that accepts the aforementioned first voltage as a working power supply. 2 2. 2 In the semiconductor integrated circuit described in item 1; during the aforementioned second period, the gate voltage 'of the aforementioned second ON fMO s transistor is the threshold value between the aforementioned second voltage and the aforementioned second switching MO S transistor The sum of the voltages is equal to or more than the voltage of 髙. 2 3 In the semiconductor integrated circuit described in item 22 of the scope of the patent application; the aforementioned first and second switching MO S transistors are combined in parallel, and during the aforementioned first period, the aforementioned second switch M 0S is electrically connected. The crystal will become 0 FF. · 24 · printed semiconductor integrated circuits by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, which are characterized by: containing: a pair of data lines; and plural zigzag lines; One of the aforementioned one pair of data lines and one of the aforementioned plural word lines of a dynamic memory cell; and a pair of P-channel MOS transistors and one pair of N-channel MOS transistors CMO S latch circuit, and the paper size of the aforementioned pair is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A8, 1 B8 C8 D8 ___ Six. Patent application range data line potential difference sense amplifier : And the first terminal for receiving the first voltage; and the second terminal for receiving the second voltage which is lower than the aforementioned first voltage of 4; and are combined together in the pair of P-channel type MO S transistors One pair of source and the first terminal The first switch MO S® crystal between the two; and the second channel MO S transistor of the N-channel type provided between the source of a pair of the pair to be combined together and the second terminal; and The gate output signals of the first and second switching MOS transistors are: during the first period, the first switching transistor MOS is turned on, and in the second period after the first period, the first switching transistor MOS is turned on. The transistor is turned off, and the second switching MOS transistor is turned into a 0 N state, and the like; and a boosting circuit that boosts the second voltage to output the screen voltage is t. In the meantime, the boosted voltage is supplied to the gate of the second switch MOS transistor; etc. are the constituents. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 2 5. In the semiconductor integrated circuit described in item 24 of the scope of patent application; the aforementioned boosted voltage is supplied Select word line · 2 6. In the semiconductor integrated circuit as described in item 25 of the scope of patent application; the aforementioned boosted voltage is equal to that of the aforementioned second switching MO S transistor which is boosted from the aforementioned second voltage The voltage of the threshold weight is equal to or higher than that of the voltage. 2 7. The size of the semiconductor chip as described in item 26 of the patent application scope applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). ) -10-A8, 1 B8 C8 D8 ___ 6. Sensing amplifier for the potential difference of the patent application data line: and the first terminal that receives the first voltage; and the second voltage that is lower than the first voltage above 4 A second terminal; and a first switching MO S® crystal provided between a pair of sources in the aforementioned pair of P-channel type MO S transistors which are commonly combined with each other; and The source of a pair that is combined with the aforementioned The N-channel type second switching MOS transistor between two terminals; and the gate output signal to the first and second switching MOS transistors is: during the first period, the first switching MOS transistor A control circuit that is turned on, and that the first switch MOS transistor is turned off, and that the second switch MOS transistor is turned on, etc., in a second period after the first period; The second voltage step-up is a step-up circuit or the like that outputs the screen voltage. During the second period, the step-up voltage is supplied to the gate of the second switch MO S transistor; and so on. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 2 5. In the semiconductor integrated circuit described in item 24 of the scope of patent application; the aforementioned boosted voltage is supplied Select word line · 2 6. In the semiconductor integrated circuit as described in item 25 of the scope of patent application; the aforementioned boosted voltage is equal to that of the aforementioned second switching MO S transistor which is boosted from the aforementioned second voltage The voltage of the threshold weight is equal to or higher than that of the voltage. 2 7. The size of the semiconductor chip as described in item 26 of the patent application scope applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). ) -10- A8 B8 C8 D8 六、申請專利範圍 路中；前述第1端子乃爲外部電源電壓端子者》 (請先閲讀背面之注意事項再填寫本頁) 2 8 .如申請專利範圍第2 7項所述之半導體積體電 路中；前述运制電路乃含有規定前述第1期間之延遲電路 ，而前述第1期間之變動乃對前述第1電壓之變動具有負 之依存性者。 2 9.如申請專利範圍第2 8項所述之半導體積體電 路中；前述延遲電路乃含有將前述第1電壓作爲工作電壓 來接受之反相器電路者。 3 0 .如申請專利範圍第2 9項所述之半導體積體電 路中：前述第1及第2開關MO S電晶體乃被結合成並聯 狀態，而在前述第1期間前述第2開關MO S電晶體乃被 成爲OFF狀態者· 經濟部中央標準局員工消費合作社印策 3 1 .如申請專利範圍第3 0項所述之半導體積體電 路中；前述一對之P溝道型MOS電晶體乃具有承接前述 一對之資料線之電位之一對閘極及一對汲極，而將前述一 對之P溝道型MO S電晶體之一方之Μ 0 S電晶體之汲極 與他方之閘極互相加以結合所成；前述一對之Ν溝道型 MO S電晶體則具有共同被結合之一對源極及承接前述一 之資料線之電位之一對閘極及一對汲極，並將前述一對之 Ν溝道型MO S電晶體之一方之M〇 S電晶體之汲極與他 方之閘極互相加以結合所成；等爲構成者。 3 2 . —種半導體積體電路，其特徵爲： 含有：一對之資料線； 及備有一對之Ρ溝道型M0S電晶體及一對之Ν溝道 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） -11 -A8 B8 C8 D8 6. The scope of patent application is on the way; the aforementioned first terminal is an external power voltage terminal "(please read the precautions on the back before filling this page) 2 8. As described in item 27 of the scope of patent application In the semiconductor integrated circuit, the operation circuit includes a delay circuit that specifies the first period, and the change in the first period is a negative dependency on the change in the first voltage. 2 9. The semiconductor integrated circuit as described in item 28 of the scope of patent application; the aforementioned delay circuit includes an inverter circuit which accepts the aforementioned first voltage as an operating voltage. 30. In the semiconductor integrated circuit described in item 29 of the scope of the patent application: the aforementioned first and second switching MO S transistors are combined in a parallel state, and during the aforementioned first period, the aforementioned second switch MO S Transistors have been turned off. • Consumer Cooperative Cooperative Mark 3 of the Central Standards Bureau of the Ministry of Economic Affairs. 1. In semiconductor integrated circuits as described in item 30 of the scope of patent application; the aforementioned pair of P-channel MOS transistors It has one pair of gates and one pair of drains that receive the potential of the data line of the aforementioned pair, and the drain of the M 0 S transistor of one of the aforementioned pair of P-channel MOS transistors and the other The gates are combined with each other; the aforementioned N-channel MOS transistor has a pair of a source and a pair of a drain and a pair of drains that are connected to the potential of the data line that is connected to the aforementioned one. It is formed by combining the drain of one MOS transistor of one of the aforementioned pair of N-channel MOS transistors and the gate of the other; and the like. 3 2. — A semiconductor integrated circuit, which is characterized by: containing: a pair of data lines; and a pair of P-channel M0S transistors and a pair of N-channels This paper applies Chinese national standards (CNS) ) Α4 size (210 × 297 mm) -11- A8 B8 C8 D8 六、申請專利範圍 路中；前述第1端子乃爲外部電源電壓端子者》 (請先閲讀背面之注意事項再填寫本頁) 2 8 .如申請專利範圍第2 7項所述之半導體積體電 路中；前述运制電路乃含有規定前述第1期間之延遲電路 ，而前述第1期間之變動乃對前述第1電壓之變動具有負 之依存性者。 2 9.如申請專利範圍第2 8項所述之半導體積體電 路中；前述延遲電路乃含有將前述第1電壓作爲工作電壓 來接受之反相器電路者。 3 0 .如申請專利範圍第2 9項所述之半導體積體電 路中：前述第1及第2開關MO S電晶體乃被結合成並聯 狀態，而在前述第1期間前述第2開關MO S電晶體乃被 成爲OFF狀態者· 經濟部中央標準局員工消費合作社印策 3 1 .如申請專利範圍第3 0項所述之半導體積體電 路中；前述一對之P溝道型MOS電晶體乃具有承接前述 一對之資料線之電位之一對閘極及一對汲極，而將前述一 對之P溝道型MO S電晶體之一方之Μ 0 S電晶體之汲極 與他方之閘極互相加以結合所成；前述一對之Ν溝道型 MO S電晶體則具有共同被結合之一對源極及承接前述一 之資料線之電位之一對閘極及一對汲極，並將前述一對之 Ν溝道型MO S電晶體之一方之M〇 S電晶體之汲極與他 方之閘極互相加以結合所成；等爲構成者。 3 2 . —種半導體積體電路，其特徵爲： 含有：一對之資料線； 及備有一對之Ρ溝道型M0S電晶體及一對之Ν溝道 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） -11 -A8 B8 C8 D8 6. The scope of patent application is on the way; the aforementioned first terminal is an external power voltage terminal "(please read the precautions on the back before filling this page) 2 8. As described in item 27 of the scope of patent application In the semiconductor integrated circuit, the operation circuit includes a delay circuit that specifies the first period, and the change in the first period is a negative dependency on the change in the first voltage. 2 9. The semiconductor integrated circuit as described in item 28 of the scope of patent application; the aforementioned delay circuit includes an inverter circuit which accepts the aforementioned first voltage as an operating voltage. 30. In the semiconductor integrated circuit described in item 29 of the scope of the patent application: the aforementioned first and second switching MO S transistors are combined in a parallel state, and during the aforementioned first period, the aforementioned second switch MO S Transistors have been turned off. • Consumer Cooperative Cooperative Mark 3 of the Central Standards Bureau of the Ministry of Economic Affairs. 1. In semiconductor integrated circuits as described in item 30 of the scope of patent application; the aforementioned pair of P-channel MOS transistors It has one pair of gates and one pair of drains that receive the potential of the data line of the aforementioned pair, and the drain of the M 0 S transistor of one of the aforementioned pair of P-channel MOS transistors and the other The gates are combined with each other; the aforementioned N-channel MOS transistor has a pair of a source and a pair of a drain and a pair of drains that are connected to the potential of the data line that is connected to the aforementioned one. It is formed by combining the drain of one MOS transistor of one of the aforementioned pair of N-channel MOS transistors and the gate of the other; and the like. 3 2. — A semiconductor integrated circuit, which is characterized by: containing: a pair of data lines; and a pair of P-channel M0S transistors and a pair of N-channels This paper applies Chinese national standards (CNS) ) Α4 size (210 × 297 mm) -11- 六、申請專利範園 型MO S電晶體之CMO S閂鎖電路，而將前述之一對資 料線之電位差加以放大之感測放大器： 及承接對前述一對之資料線之髙電平側之資料線之驅 動電壓之端子； 及在前述一對之P溝道型MO S電晶體中•具有共通 被結合之一對之被源極結合之源極及被結合在前述端子之 汲極及接受控制信號之閘極等之N溝道型之開關MO S電 晶體等； 而前述控制信瞵之髙電平電壓乃被定爲較前述驅動電 壓爲髙之電壓；等爲構成者。 3 3 .如申請專利範圍第3 2項所述之半導體積體電 路中；前述控制信號之髙電平電壓乃被定爲：與該髙電平 電壓與前述開關Μ 0 S電晶體之臨限值電壓之和之電壓相 等，或較其爲髙之電壓者· 請 先 閲 % 背 ιέ 之 注 I6. A CMO S latch circuit that applies for a patented Fan MOS transistor, and a sense amplifier that amplifies the potential difference of one of the aforementioned data lines: The terminal of the driving voltage of the data line; and in the aforementioned one pair of P-channel type MOS transistors, a source having a common pair and a source coupled to one pair and a drain coupled to the aforementioned terminal and receiving N-channel type switching transistors such as gates of the control signals, etc., and the 髙 level voltage of the aforementioned control signal is set to a voltage which is higher than the aforementioned driving voltage; etc. are the constituents. 3 3. In the semiconductor integrated circuit as described in item 32 of the scope of the patent application; the threshold voltage of the aforementioned control signal is determined as: the threshold of the threshold voltage and the threshold value of the switch M 0 S transistor The voltage is equal to the sum of the voltages, or the voltage that is higher than the voltage. Please read the% note first. I 責 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） -12 -Responsibility This paper size applies to China National Standard (CNS) Α4 size (210X297 mm) -12- 六、申請專利範園 型MO S電晶體之CMO S閂鎖電路，而將前述之一對資 料線之電位差加以放大之感測放大器： 及承接對前述一對之資料線之髙電平側之資料線之驅 動電壓之端子； 及在前述一對之P溝道型MO S電晶體中•具有共通 被結合之一對之被源極結合之源極及被結合在前述端子之 汲極及接受控制信號之閘極等之N溝道型之開關MO S電 晶體等； 而前述控制信瞵之髙電平電壓乃被定爲較前述驅動電 壓爲髙之電壓；等爲構成者。 3 3 .如申請專利範圍第3 2項所述之半導體積體電 路中；前述控制信號之髙電平電壓乃被定爲：與該髙電平 電壓與前述開關Μ 0 S電晶體之臨限值電壓之和之電壓相 等，或較其爲髙之電壓者· 請 先 閲 % 背 ιέ 之 注 I6. A CMO S latch circuit that applies for a patented Fan MOS transistor, and a sense amplifier that amplifies the potential difference of one of the aforementioned data lines: The terminal of the driving voltage of the data line; and in the aforementioned one pair of P-channel type MOS transistors, a source having a common pair and a source coupled to one pair and a drain coupled to the aforementioned terminal and receiving N-channel type switching transistors such as gates of the control signals, etc., and the 髙 level voltage of the aforementioned control signal is set to a voltage which is higher than the aforementioned driving voltage; etc. are the constituents. 3 3. In the semiconductor integrated circuit as described in item 32 of the scope of the patent application; the threshold voltage of the aforementioned control signal is determined as: the threshold of the threshold voltage and the threshold value of the switch M 0 S transistor The voltage is equal to the sum of the voltages, or the voltage that is higher than the voltage. Please read the% note first. I 責 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） -12 -Responsibility This paper size applies to China National Standard (CNS) Α4 size (210X297 mm) -12-
TW085109692A 1995-08-18 1996-08-09 Semiconductor integrated circuit TW380313B (en)

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