TW379366B - Semiconductor circuit apparatus - Google Patents

Abstract

A semiconductor integrated circuit device comprising a first circuit block operated by a supply voltage applied from an external terminal and a second circuit block operated by an internal voltage generated by a power supply circuit, characterized in that a voltage that is higher than the internal voltage in absolute value is generated by a charge pump circuit, that a variable impedance means is provided between the output voltage of the charge pump circuit and the internal voltage, and that the internal voltage is generated by controlling the variable impedance means so that the internal voltage coincides with a reference voltage by allowing a differential amplifier circuit operated by the output voltage of the charge pump circuit to compare both voltages.

Description

經濟部中央揉準局貝工消费合作社印製 A7 B7 五、發明説明（彳） 技術領域 本發明關於半導體積體電路裝置，主要關於動態型 (Dynamic) RAM (Random Access Memory)中之電源供 給控制之有效技術。 一 背景技術 爲增長動態型RAM中之記憶格之資訊保持時間’需 使基板之雜質濃度變薄，縮小位址選擇MO S F E T之源 極、汲極擴散層與基板間之Ρ η接合之電場。如此般降低 基板之雜質濃度，則上述MO S F Ε Τ之臨界値電壓變低 ，閘極電壓設爲接地電位等非選擇位準時之源極、汲極間 之漏電流將增加。因此，有人建議將連接閘極之字元線之 非選擇位準設爲負電壓。該負電壓，係使用充電泵電路， 爲使其安定化藉位準感知器使振盪電路間歇地動作。如此 般使字元線之非選擇位準爲負電壓，以改善資訊保持時間 之動態型RAM之仍有例如特開平2 — 5 2 9 0號公報、 特開平6 — 255566、特開平7 — 5746 1號公報 及特開平7 — 30709 1號公報。 基板電壓，因與位元線或字元線間之容量結合，在位 元線或字元線於選擇位準與非選擇位準之間變化位準時， 會產生1 0%〜3 0%之較大之電位變動。因此，於充電 泵電路令供至基板電壓之負偏壓利用於上述字元線之非選 擇位準時，藉由使上述容量結合與字元線之選擇位準變化 爲非選擇位準用之電流而進行放電，字元線之非選擇位準 ^紙佚尺度適用中國國家揉準（CNS ) A4規格（210X297公釐)Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of the Ministry of Economic Affairs V. INTRODUCTION (彳) TECHNICAL FIELD The present invention relates to semiconductor integrated circuit devices, and mainly relates to power supply control in Dynamic RAM (Random Access Memory). Effective technology. Background Art In order to increase the information retention time of a memory cell in a dynamic RAM, it is necessary to thin the impurity concentration of the substrate and reduce the address to select the electric field of the junction between the source and drain diffusion layers of the MO S F E T and the substrate. By reducing the impurity concentration of the substrate in this way, the critical threshold voltage of the above MO S F ET becomes lower, and the leakage current between the source and the drain when the gate voltage is set to a non-selected level such as the ground potential will increase. Therefore, it is suggested to set the non-selection level of the word line connected to the gate to a negative voltage. This negative voltage uses a charge pump circuit, and the oscillation circuit is intermittently operated by a level sensor in order to stabilize it. In this way, the non-selection level of the word line is set to a negative voltage to improve the information retention time. There are still dynamic RAMs such as Japanese Patent Application Laid-Open No. 2-5 2990, Japanese Patent Application Laid-Open No. 6-255566, Japanese Patent Application Laid-Open No. 7-5746 Bulletin No. 1 and Japanese Patent Application Laid-Open No. 7-30709. Due to the combination of the substrate voltage and the bit line or word line capacity, when the bit line or word line is changed between the selection level and the non-selection level, 10% to 30% will be generated. Large potential changes. Therefore, when the charge pump circuit uses the negative bias voltage supplied to the substrate voltage to use the non-selection level of the word line, by changing the capacity combination and the selection level of the word line to the current for the non-selection level, For the discharge, the non-selection level of the character line ^ paper size is applicable to China National Standard (CNS) A4 (210X297 mm)

In m n ^^1 —II In I-I HI ^^1 I ^^1 I I ^^1 U3-° (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（2 ) - 暫時不足致使資訊保持特性惡化之最大原因，此點被判明 。因此，有必要實現穩定動作之內部電源電路之改良。 本發明目的在於提供具穩定動作之內部電源電路的半 導體積體電路裝置。本發明另=目的在於提供包含可保持 大記憶容量，且改善資訊保持特性的動態型ram的半導 體積體電路裝置。本發明再另一目的在於提供可實現信賴 性及高速動作、低消費電力的半導體積體電路裝置、本發 明之目的及新穎技術特徵可由參照圖面說明如下。 發明之開示 本發明爲具備：藉由外部端子供給之電源電壓動作之 第1電路方塊及藉由電源電路所形成內部電壓動作之第2 電路方塊的半導體積體電路裝置，令相對於上述內部電壓 爲絕對値較大之電壓由充電泵電路形成，於該輸出電壓與 內部電壓之間設可變阻抗裝置，藉由以上述充電泵電路形 成之輸出電壓爲動作電壓的差動放大電路來比較基準電壓 及上述內部電壓，俾控制上述可變阻抗裝置使兩者成爲一 致。 實施發明之最佳形態。 以下，參照圖面說明本發明。 圖1及圖2爲本發明之動態型RAM之一部分之一實 施例之槪略電路圖。於圖1中，圖示記憶陣列部，圖2圖 示電源電路，構成動態型RAM之位準或資料之輸出入介 面、列系之選擇電路及控制電路等被省略。 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） -5- r ^ n I d n n n 丁 (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央橾率局貝工消费合作社印装 五 、發明説明（3 ) 1 1 圖1中，動 態 型 記 憶 格 f 係 作 爲 代 表 圖 示 出 之 1 個 記 1 | 憶 陣 列M A C上 所 設 之 字 元 線 W 1 W 3 > … … W η > 及 1 I 2 對 互補位元線 b i t 、 * / b i t之- -方t )i t 或 請 1 1 / b i t間所設 之 作 爲 代 表 之 圖 示 之 8 個 0 動 態 型 記 憶 格 先 閲 讀 1 1 係 由 位址選擇Μ 0 S F E T Q m 及 記 憶 電 容 量 C S 構 成 〇 背 δ 之 1 1 位 址 選擇Μ 0 S F E T Q m 之 閘 極 接 於 對 應 之 字 元 線 W 1 注 意 審 1 I 等 Μ 0 S F Ε T Q m 之 汲 極 接 對 m 之 位 元 線 b i t 等 > 項 再 1 源 *·. 極¥記憶電容 器 C S 0 記 憶 電 容 量 C S 之 另 一 電 極 爲 共 寫 本 裝 I 用 供至有屏極 ® J 堅 〇 頁 1 1 於此實施例 之 動 態 型 R A Μ 中 上 述 字 元 線 W 1 等 之 1 1 選 擇 位準係設定 爲 相 對 於 上 述 位 元 線 b 1 t 等 之 Η ( 尚 1 1 ) 位 準高出位址 選 擇 Μ 〇 S F Ε T Q m 之 臨 界 値 電 壓 分 的 訂 I 高 電 壓 V C Η。 因 此 上 述 字 元 線 之 非 公BB 进 擇 位 準 係 設 定 1 I 成相 對於電路之 接 地 電位 V S S爲低的負電壓V N N 〇 1 1 令後述之感 測 放 大 器 於 內 部 降 壓 電 壓 V D L 動 作 時 > 1 1 藉 以 下說明之感 測 放 大 器 S A 放 大 供 至 位 元 線 之 上 述 Η 位 i·-，· 1 準 係設定爲上 述 內 部 電 壓 V D L 對 l/iff 應 之 位 準 〇 因 此 上 1 I 述 字 元線之選擇 位 準 對 應 之 高 電 壓 V C Η 設 定 爲 V D L 1 I + V t h之高電 壓 0 感 測 放 大 器 S A 之 輸 出 入 節 點 9 接 於 1 1 上 述 一對互補位 元 線 b i t 及 / b i t 〇 上 述 互 補 位 元 線 1 1 b i t 及 / b i t 係 如 同 圖 所 示 配 置 成 向 平 行 方 向 延 伸 1 1 » 爲 求容量平衡 » J 要時使適當交叉。 該互補位元 ;線 1 I b i t 及 / b i t 當 上 述 感 測 放 大 器 採 共 用 感 測 方 式 時 1 | 係 經由共用開 關 Μ 0 S F E Τ 與 感 測 放 大 器 S A 之 單 位 1 1 1 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明u ) 電路之輸出入節點連接。 感測放大器S A之單位電路’係由閘極與汲極交叉連 接成閂鎖形態之N通道型放大MOSFET Q4、 Q5 及P通道型放大M0SFET—Q6、 Q7構成。N通道 型MOSFET Q4及Q5之源極接於共用源極線，於 該共同源極線，在感測放大器之動作時序，介由N通道型 功率開關MOSFET Q8供給有電路之接地電位 VSS。P通道型MOSFET Q6及Q7之源極，接 共用源極線，於該共用源極線，在感測放大器之動作時序 ，介由P通道型功率開關MOSF ET Q9供給有上述 內部降壓電壓V D L。 雖未特別限制，但上述感測放大器之Η位準側之動作 電壓，爲達感測放大器之高速動作，可於放大動作開始起 算至位元線之放大信號到達上述電壓VD L前之間暫時供 給V CH之高電壓，即所謂過驅動。即，與上述 MOSFET Q9並聯設P通道型MOSFET，令該 P通道型MO S F E T於感測放大器之放大動作開始時暫 時爲ON狀態以供給上述高電壓VCH。 於上述感測放大器之單位電路之輸出入節點設有由， 令互補位元線短路之等化器MOSFET Q1，及供給 半預充電電壓VDL/2於互補位元線b i t、/b i t 之開關MOSFET Q2與Q3所構成之預充電電路。 於該MOSFET Q1〜Q3之閘極供至有共用之等化 (或預充電）信號EQ。形成該等化信號EQ之驅動電路 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） .^ϋ _1 - - ! —^1 - n «η r'*R· - -I - - n Τ» 、-° (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消费合作杜印製 A7 ____B7_· _ 五、發明説明（5 ) ，係和驅動上述字元線W 1〜W3……W η之字元驅動器 WD 1等相同，將選擇位準設爲VCH，非選擇位準設爲 V Ν Ν之負電壓。 相對地，供給電路之接地電位至上述感測放大器S A 之功率開關MOSFET Q8之驅動用驅動器SAND ，係於上述內部電壓VD L及上述負電壓VNN動作，又 形成由內部降壓電壓之Η位準，及負電壓VNN之L位準 構成之驅動信號S AN。供給上述感測放大器S Α之內部 降壓電壓VDL之功率開關MOSFET Q9之驅動用 驅動器SAPD，係形成由上述高電壓VCH之Η位準及 電路之接地電位V S S之L位準構成之驅動信號S A Ρ。 雖未特別限制，於記憶陣列M A C之形成之P型井領 域施加有較上述負電壓VNN爲低之電位之基板電壓 VB B，上述P型井領域與形成較深之N型井領域結合， 於構成上述感測放大器之P通道型MO S F E T之形成之 N型井領域，施加有較上述高電壓V C Η爲高之高電壓 VP Ρ。上述電壓VB Β及電壓VP Ρ，如後述係由充電 泵電路形成。 於形成上述字元線W1等之選擇信號之X解碼器 XD E C及字元驅動器WD，包含於陣列電路A C，用於 形成上述預充電信號E Q之驅動器，及用以形成感測放大 器之驅動信號之驅動器SAND、 SANP上，供給有 VCH、 VDL、 VSS、 VNN作爲動作電壓。於構成 各驅動器之P通道型MO S F E T之形成之N型井領域施 本紙張尺度適用中國國家揉準（CNS ) A4规格（210 X 297公釐）_ · n - - - _ —^1 n m , · m urn ^^1 HI HI U3 ,T (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作杜印裝 A7 B7 五、發明説明（6 ) 加有高壓V C P P作爲偏壓，在N通道型MO S F E T之 形成之P型井領域或P型基板施加負壓VBB。 於圖2，高電壓VPP係由高壓產生電路VPPG形 成。高壓產生電路VPPG係由，振盪電路1 ，充電泵電 路2，又位準感知器3構成，充電泵電路2，接受振盪電 路1形成之振盪脈衝，藉由充電泵動作產生高電壓。 藉位準感知器3進行位準感測以使高電壓V P P穩定 於所要之高電壓，俾間歇控制振盪電路1之動作。即，當 高電壓VP P到達所要高電壓時停止振盪動作，當高電壓 VP P降低時使上述振盪電路1動作。 上述高電壓V P P設定爲較字元線W 1等之選擇位準 之對應高電壓V C Η爲高。例如，如圖3之動作波形圖所 示，設定字元線之選擇電壓VCH爲2 . 25V，設定高 電壓VPP爲2.6V之高電壓。形成較上述必要之電壓 V C Η爲高之電壓，依該高電壓V Ρ Ρ使基準電壓產生電 路RGFP動作。該基準電壓產生電路RGFP，係使定 電流Ip，介由Ρ通道型MOSFET Q10及Q11 構成之電流鏡電路，流經以上述內部電壓VD L (或外部 電源電壓V e X t )爲基準之電阻器Rp ，以產生相當於 上述位準選擇用MOSFET Qm之臨界値電壓Vt h 之電壓。據此，使基準電壓VRH設定爲上述VDL (或 Vext)+Vth對應之電壓。 定電壓產生電路RGP係由，設於上述高電壓VP P 與內部高電壓V C Η間之作爲可變電阻元件之P通道型Μ II _ HI _ - - - I - HI - ! — - - - In -- - - {請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） -9- 經濟部中央標準局貝工消费合作杜印製 A7 B7 五、發明説明（7 ) OSFET Q1 2，及接受基準電壓VRH與內部高電 壓V C Η之差動放大電路4構疼，差動放大電路4之輸出 信號供至M〇SFET Q12之閘極。當內部高電壓 VCH相對於基準電壓VRH變低時，形成變化爲L位準 之信號、縮小MOSFET Q12之電阻値以使兩者一 致，反之，內部高電壓VCH相對基準電壓VRH變高時 ，形成變爲Η位準之信號，增大MOSFET Q12之 電阻値以使兩者一致。 負電壓VB B由負電壓產生電路VB B G形成。負電 壓產生電路VBBG係由上述之振盪電路6、負充電泵 (Negative Charge pump circuit) 7 及位準感知器 8 構成， 充電泵電路7，係接受振盪電路6形成之振盪脈衝，藉充 電泵動作產生負電壓。位準感知器8進行位準感測使該負 電壓VB B穩定於所要之負高壓，俾間歇地控制振盪電路 6之動作。即，當負電壓VB B到達所要負電壓時停止振 盪動作，負電壓低於絕對値時使振盪電路6再度動作。 上述負電壓V B B設爲絕對値大於字元線W 1等非選 擇位準對應之負電壓V N N。例如，如圖3之動作波形圖 所示，字元線之非選擇電壓VNN設爲—〇 . 75V，負 電壓VB B設爲一 1 . 1 V。形成相對於上述必要之電壓 VNN於負方向爲較大之電壓，依該負電壓VB B使基準 電壓產生電路RG F N動作》該基準電壓產生電路 RGFN，係使定電流介由N通道型MOSFET Q 1 3及Q 1 4構成之電流鏡電路，流經以電路接地電位 n- n·* a^—9 t· 1^1 m . ^^1 It· ai.^ In (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家揉準（CNS ) A4規格（2丨0X297公釐） -10- 經濟部中央橾準局貝工消费合作杜印製 A7 B7 五、發明説明（8 ) V S S爲基準之電阻R η，以產生施加於位址選擇用 MOSFET Qm之閘極、源極間之逆偏壓VRN。於 此實施例，係將電壓VRN設爲一〇.75V之負電壓者 〇 定電壓產生電路RGN係由，設於負電壓VB B與內 部負電壓V N N之間作爲可變電阻元件之N通道型 MOSFET Q1 5 ，及接受上述基準電壓VRN與內 部負電壓VNN之差動放大電路9構成，差動放大電路9 之輸出信號供至MOSFET Q15之閘極。係控制成 ，當內部高電壓VNN之絕對値小於基準電壓VRN時， 形成變化爲Η位準之信號，縮小MOSFET Q1 5之 電阻値以使兩者一致。反之，內部負電壓VNN之絕對値 大於基準電壓VRN時，形成變化爲L位準之信號，增大 MOSFET Q15之電阻値以使兩者一致。 定電壓產生電路5，係接受來自外部端子之外部電壓 Vext ，藉由和上述定電壓產生電路RGP相同之電路 來產生內部降壓電壓VDL者。定電壓產生電路5，不一 定爲必要者。上述感測放大器或位址選擇電路等周邊電路 亦可爲藉由外部端子供給之外部電壓V e X t而動作者。 此情況下，如上述般，以外部電壓V e X t爲基準形成內 部高電壓V C Η之位準。即使設有定電壓產生電路5時， 以該定電壓VD L作爲感測放大器之動作電壓使用，使位 址緩衝器或位址解碼器等內部電路依上述外部電壓 V e X t動作亦可。 本紙張尺度適用中國國家揉率（CNS ) A4規格（210X297公釐） •11 - --------.裝-- <請先閲讀背面之注意事項再填寫本頁)In mn ^^ 1 —II In II HI ^^ 1 I ^^ 1 II ^^ 1 U3- ° (Please read the notes on the back before filling out this page) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (2)-The biggest reason for the temporary lack of information deterioration characteristics is identified. Therefore, it is necessary to improve the internal power supply circuit for stable operation. An object of the present invention is to provide a semiconductor volume circuit device having an internal power supply circuit with stable operation. Another object of the present invention is to provide a semiconductor volume semiconductor circuit device including a dynamic ram capable of maintaining a large memory capacity and improving information retention characteristics. Still another object of the present invention is to provide a semiconductor integrated circuit device capable of realizing reliability, high-speed operation, and low power consumption. The object of the present invention and novel technical features can be explained as follows with reference to the drawings. DISCLOSURE OF THE INVENTION The present invention is a semiconductor integrated circuit device including a first circuit block operated by a power supply voltage supplied from an external terminal and a second circuit block operated by an internal voltage formed by a power supply circuit. The absolute larger voltage is formed by the charge pump circuit. A variable impedance device is set between the output voltage and the internal voltage. The reference is compared by a differential amplifier circuit that uses the output voltage formed by the charge pump circuit as the operating voltage. The voltage and the internal voltage are controlled so that the variable impedance device becomes the same. The best mode for carrying out the invention. Hereinafter, the present invention will be described with reference to the drawings. 1 and 2 are schematic circuit diagrams of an embodiment of a part of a dynamic RAM according to the present invention. In FIG. 1, a memory array section is shown, and FIG. 2 shows a power supply circuit, a level or data input / output interface constituting a dynamic RAM, a selection circuit of a line system, and a control circuit are omitted. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -5- r ^ n I dnnn D (Please read the precautions on the back before filling this page) A7 B7 The Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumption Cooperative cooperative printing V. Description of the invention (3) 1 1 In FIG. 1, the dynamic memory cell f is shown as a representative figure 1 | The character line W 1 W 3 provided on the memory array MAC >… … W η > and 1 I 2 pairs of complementary bit lines bit, * / bit--square t) it Reading 1 1 is composed of the address selection M 0 SFETQ m and the memory capacitance CS. 1 of the back δ 1 1 The address selection M 0 SFETQ m is connected to the corresponding word line W 1 Attention review 1 I etc. M 0 SF Ε TQ The drain of m is connected to the bit line of m bit etc. > term and 1 source * .. pole ¥ memory capacitor CS 0 The other electrode of the memory capacitance CS is a co-write device I is used to Youjiji J Page 1 1 In the dynamic type RA of this embodiment, the 1 1 selection level of the above character line W 1 etc. is set to be relative to the above bit line b 1 t etc. (still 1 1) The level is higher than the address selection, and the order of the threshold voltage points of the MCSF E TQ m is set to a high voltage VC. Therefore, the non-common BB advance selection level of the word line is set to 1 I to a negative voltage VNN that is low relative to the ground potential VSS of the circuit 〇1 1 to make the sense amplifier described later operate at the internal step-down voltage VDL > 1 1 Use the sense amplifier SA described below to amplify the above-mentioned bits i ·-, · 1 supplied to the bit line. The level is set to the level corresponding to the above-mentioned internal voltage VDL to l / iff. Therefore, the characters described in 1I above High voltage VC corresponding to line selection level Η High voltage set to VDL 1 I + V th 0 I / O node 9 of sense amplifier SA Connected to 1 1 The above pair of complementary bit lines bit and / bit 〇 The above complementary The bit lines 1 1 bit and / bit are arranged to extend in the parallel direction 1 1 as shown in the figure »To balance the capacity» J If necessary, make appropriate crossovers. The complementary bit; line 1 I bit and / bit When the above-mentioned sensing amplifier adopts the common sensing method 1 | It is a unit through the common switch M 0 SFE Τ and the sensing amplifier SA 1 1 1 This paper size is applicable to the country of China 橾Standard (CNS) A4 (210X297 mm) A7 B7 printed by Beige Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention u) The input and output nodes of the circuit are connected. The unit circuit of the sense amplifier SA is composed of N-channel type amplification MOSFETs Q4, Q5 and P-channel type amplification MOSFETs Q6, Q7 which are connected in a latched manner with a gate and a drain cross-connected. The sources of the N-channel MOSFETs Q4 and Q5 are connected to a common source line. At this common source line, the ground potential VSS of the circuit is supplied via the N-channel power switch MOSFET Q8. The sources of the P-channel MOSFETs Q6 and Q7 are connected to a common source line. The common source line is used to supply the above-mentioned internal step-down voltage VDL via the P-channel power switch MOSF ET Q9 during the operation timing of the sense amplifier. . Although it is not particularly limited, the operating voltage of the above-mentioned sense amplifier on the quasi-level side is for high-speed operation of the sense amplifier. It can be temporarily calculated from the start of the amplification operation until the amplification signal of the bit line reaches the above-mentioned voltage VD L The high voltage supplied to V CH is the so-called overdrive. That is, a P-channel type MOSFET is provided in parallel with the above-mentioned MOSFET Q9, so that the P-channel type MO S F E T is temporarily turned on at the start of the amplification operation of the sense amplifier to supply the high voltage VCH. The input and output nodes of the unit circuit of the above-mentioned sense amplifier are provided with an equalizer MOSFET Q1 that short-circuits the complementary bit line, and a switching MOSFET that supplies a half precharge voltage VDL / 2 to the complementary bit lines bit and / bit. Q2 and Q3 pre-charge circuit. The gates of the MOSFETs Q1 to Q3 are supplied to a shared equalization (or precharge) signal EQ. The driving circuit that forms the equalization signal EQ This paper size is applicable to China National Standard (CNS) A4 (210X297 mm). ^ Ϋ _1--! — ^ 1-n «η r '* R ·--I- -n Τ »,-° (Please read the notes on the back before filling out this page) Printed by A7 ____ B7_ · _ 5. The description of the invention (5), which drives and drives the above words The element drivers WD 1 of the element lines W 1 to W 3... W η are the same, and the selection level is set to VCH, and the non-selection level is set to a negative voltage of V Ν Ν. In contrast, the driver SAND that supplies the ground potential of the circuit to the power switch MOSFET Q8 of the sense amplifier SA described above operates on the internal voltage VD L and the negative voltage VNN, and forms the level of the internal step-down voltage. And the driving signal S AN formed by the L level of the negative voltage VNN. The driver SAPD for driving the power switch MOSFET Q9 of the internal step-down voltage VDL supplied to the above-mentioned sense amplifier SA is to form a driving signal SA composed of the high level of the high voltage VCH and the L level of the ground potential VSS of the circuit. P. Although not particularly limited, a substrate voltage VB B having a lower potential than the above-mentioned negative voltage VNN is applied to the P-well field formed by the memory array MAC. The above-mentioned P-well field is combined with a deeper N-well field. In the field of the N-type well formed by the P-channel type MO SFET constituting the above-mentioned sense amplifier, a higher voltage VP P than the above-mentioned high voltage VC is applied. The voltage VB B and the voltage V P are formed by a charge pump circuit as described later. The X decoder XD EC and the character driver WD forming the selection signal of the word line W1 and the like are included in the array circuit AC, a driver for forming the precharge signal EQ, and a driving signal for forming a sense amplifier. The drivers SAND and SANP are supplied with VCH, VDL, VSS, VNN as the operating voltage. In the field of N-type wells formed by the P-channel type MO SFETs constituting each driver, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) _ · n---_ — ^ 1 nm, · M urn ^^ 1 HI HI U3, T (Please read the notes on the back before filling this page) The Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperation Du printed A7 B7 V. Description of the invention (6) High voltage VCPP is added as Bias, a negative voltage VBB is applied to the P-well area or P-type substrate formed by the N-channel type MO SFET. As shown in Fig. 2, the high-voltage VPP is formed by a high-voltage generating circuit VPPG. The high-voltage generating circuit VPPG is composed of an oscillating circuit 1, a charging pump circuit 2, and a level sensor 3. The charging pump circuit 2 receives an oscillating pulse formed by the oscillating circuit 1, and generates a high voltage by the operation of the charging pump. Level sensing is performed by the level sensor 3 to stabilize the high voltage V P P at a desired high voltage, and the operation of the oscillation circuit 1 is intermittently controlled. That is, when the high voltage VP P reaches a desired high voltage, the oscillation operation is stopped, and when the high voltage VP P decreases, the oscillation circuit 1 is operated. The high voltage V P P is set to be higher than the corresponding high voltage V C Η of the selection level of the word line W 1 and the like. For example, as shown in the operation waveform diagram of FIG. 3, the selection voltage VCH of the word line is set to 2.25V, and the high voltage VPP is set to a high voltage of 2.6V. A voltage higher than the necessary voltage V C Η is formed, and the reference voltage generating circuit RGFP is operated in accordance with the high voltage V P P. The reference voltage generating circuit RGFP is a constant current Ip, a current mirror circuit composed of P-channel MOSFETs Q10 and Q11, and flows through a resistor based on the internal voltage VD L (or external power supply voltage V e X t). Rp to generate a voltage corresponding to the threshold voltage Vt h of the above-mentioned level selection MOSFET Qm. Accordingly, the reference voltage VRH is set to a voltage corresponding to the above-mentioned VDL (or Vext) + Vth. The constant voltage generating circuit RGP is a P-channel type M II as a variable resistance element provided between the above-mentioned high voltage VP P and the internal high voltage VC _ HI _----I-HI-!----In ---{Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297mm) -9- Printed by Shellfisher Consumer Cooperation, Central Standards Bureau, Ministry of Economic Affairs A7 B7 V. Description of the invention (7) OSFET Q1 2 and the differential amplifier circuit 4 receiving the reference voltage VRH and the internal high voltage VC VC, the output signal of the differential amplifier circuit 4 is supplied to the gate of the MOSFET Q12 . When the internal high voltage VCH becomes lower than the reference voltage VRH, a signal that changes to the L level is formed, and the resistance of the MOSFET Q12 is reduced to make the two coincide. On the contrary, when the internal high voltage VCH becomes higher than the reference voltage VRH, it forms The signal becomes Η level, and the resistance of MOSFET Q12 is increased to make them coincide. The negative voltage VB B is formed by a negative voltage generating circuit VB B G. The negative voltage generating circuit VBBG is composed of the oscillation circuit 6, the negative charge pump circuit 7 and the level sensor 8 described above. The charge pump circuit 7 receives the oscillation pulse formed by the oscillation circuit 6 and operates by the charge pump. Generate a negative voltage. The level sensor 8 performs level sensing to stabilize the negative voltage VB B at a desired negative high voltage, and controls the operation of the oscillation circuit 6 intermittently. That is, the oscillation operation is stopped when the negative voltage VB B reaches the desired negative voltage, and the oscillation circuit 6 is operated again when the negative voltage is lower than the absolute value. The negative voltage V B B is set to be absolutely larger than the negative voltage V N N corresponding to a non-selection level such as the word line W 1. For example, as shown in the operation waveform diagram of FIG. 3, the non-selection voltage VNN of the word line is set to -0.75V, and the negative voltage VB B is set to 1.1V. A relatively large voltage in the negative direction is formed relative to the necessary voltage VNN, and the reference voltage generating circuit RG FN is operated according to the negative voltage VB B. The reference voltage generating circuit RGFN is a constant current through an N-channel MOSFET Q The current mirror circuit composed of 1 3 and Q 1 4 flows through the circuit ground potential n- n · * a ^ —9 t · 1 ^ 1 m. ^^ 1 It · ai. ^ In (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to China National Standards (CNS) A4 (2 丨 0X297mm) ) A resistor R η with VSS as a reference to generate a reverse bias VRN applied between the gate and the source of the address selection MOSFET Qm. In this embodiment, the voltage VRN is set to a negative voltage of 10.75V. The fixed voltage generating circuit RGN is an N-channel type that is set as a variable resistance element between the negative voltage VB B and the internal negative voltage VNN. The MOSFET Q1 5 is composed of a differential amplifier circuit 9 that receives the reference voltage VRN and the internal negative voltage VNN. The output signal of the differential amplifier circuit 9 is supplied to the gate of the MOSFET Q15. It is controlled so that when the absolute value of the internal high voltage VNN is smaller than the reference voltage VRN, a signal that changes to a level is formed, and the resistance of the MOSFET Q1 5 is reduced to make the two coincide. Conversely, when the absolute value of the internal negative voltage VNN is greater than the reference voltage VRN, a signal that changes to the L level is formed, and the resistance of the MOSFET Q15 is increased to make the two coincide. The constant voltage generating circuit 5 receives the external voltage Vext from the external terminal, and generates the internal step-down voltage VDL by the same circuit as the above-mentioned constant voltage generating circuit RGP. The constant voltage generating circuit 5 is not necessarily required. The peripheral circuits such as the above-mentioned sense amplifier or address selection circuit may be operated by an external voltage V e X t supplied from an external terminal. In this case, as described above, the level of the internal high voltage V C Η is formed based on the external voltage V e X t as a reference. Even when the constant voltage generating circuit 5 is provided, the constant voltage VD L is used as the operating voltage of the sense amplifier, so that internal circuits such as an address buffer or an address decoder can operate according to the external voltage V e X t. This paper size is applicable to China National Kneading Rate (CNS) A4 (210X297mm) • 11---------. Loading-< Please read the precautions on the back before filling this page)

••IT A7 ___B7_· 五、發明説明（9 ) 上述充電泵電路2或7形成之電壓VPP或VBB， 係保持於寄生容量等所蓄積之電荷，例如當字元線由非選 擇位準切爲選擇位準時，或反之由選擇位準切爲非選擇位 準時，因連接多數記憶格，藉由具較大寄生容量之字元線 之充電或放電之電流而如上述般作較大之變動。預估此種 電壓變動，設定字元線之選擇位準及非選擇位準，則有必 要於字元線連接之位址選擇用MO S F E T之閘極絕緣膜 ，或於構成上述字元線驅動用之字元線驅動器的輸出 MO S F E T之閘極絕緣膜上施予耐高壓化，俾對應於上 述位準變動分增加之預估値之電壓。 經濟部中央標隼局貝工消费合作社印装 (請先聞讀背面之注意事項再填寫本頁) 相對於此，本案發明中設計成介由定電壓電路RG P 或RGN形成字元線之選擇位準、非選擇位準，則如上述 當字元線由非選擇位準切爲選擇位準，或反之由選擇位準 切爲非選擇位準時，因連接多數記憶格，即因具較大寄生 容量之字元線之充電或放電之電流致使V P P及V B B產 生變動。但因，定電壓電路RGP或RGN之可變電阻之 MOSFET Q12及Q15之電阻値亦變化而吸收該 電壓變動，故可確保大致一定之電壓V C Η及VNN。 上述內部高電壓VCH及高電壓VP Ρ之電壓差，及 內部負電壓V ΝΝ與負電壓VB Β之電壓差，係形成爲分 別補正上述字元線之驅動電流對應之充電泵電路2及7之 輸出電壓變動者。如此則施加於字元驅動器WD之輸出 MO S F Ε Τ或記億格之位址選擇MO S F Ε Τ之閘極絕 緣膜之電壓，成爲由上述穩定化電壓V C Η或VNN決定 本紙張尺度遑用中國困家標準（CNS ) Α4規格（210X297公釐） -12- 經濟部中央梯準局员工消费合作社印製 A7 B7 五、發明説明（10 ) 之較小電壓，故不必如上述般預估電壓變動並施予耐高壓 化。 圖3爲本發明之動態型R am之槪略動作說明之波形 圖》圖中主要圖示記憶格之選擇動作。上述等化信號E Q ，當記憶格處於資訊保持狀態時係設定爲上述內部高電壓 VCH之Η位準。如此則使MOSFET Q1〜Q3爲 ON狀態，使互補位元線b i t、/b i t短路之同時， 供給上述半預充電電壓VDL/2。因互補位元線b i t 、/b i t設爲半預電電壓VDL/2，等化信號EQ之 位準即使處於V D L之低電位亦會動作。但是，如本實施 例般藉由使用內部高電壓VCH ’可縮小MOSFET Q1之ON電阻，於短時間內使互補位元線b i t及 /b i t之Η位準與L位準短路而設定爲中間電位VDL / 2。 記憶體存取時，等化信號E Q由Η位準變爲L位準， 此時，等化信號E Q之L位準並非電路之接地電位，而是 負電壓VNN。其理由在於，爲使等化高速化而將臨界値 設爲較小，於MOSFET Q1〜Q3之閘極供給負電 壓V N N，以防止流經汲一源極間之漏電流。 和上述同樣地，感測放大器能動信號SAN，當感測 放大器處於非動作狀態時係設爲負電壓V N N，防止流經 功率開關MOSFET Q8之漏電流。亦即， MOSFET Q8，爲求感測放大器之高速化，其閘極 絕緣膜形成爲較薄，設定爲較低臨界値電壓。使用此種低 本紙張尺度適用中國國家梂準（CNS ) A4规格（210X297公釐） --------1.、裝-- (請先閲讀背面之注意#'項再填寫本頁) 訂 -13- 經濟部中央橾準局貝工消费合作社印装 A7 B7 五、發明説明（u) 臨界値電壓之Μ 0 S F E T，則於動作狀態時，可流經較 大之電流’使感測放大器之放大動作高速。此情況，於Ρ 通道型MOSFET Q9亦同樣，當感測放大器處於非 動作狀態時係設定爲內部高電壓VCH，以防止流經功率 開關MOSFET Q9之漏電流。 當等化信號E Q設定爲負電壓V Ν Ν之非選擇位準後 ，字元線W i成爲內部高電壓ν C Η之Η位準之選擇狀態 。如此則記憶格之位址選擇Μ 0 S F E T Q m成爲Ο Ν 狀態’資訊記憶電容器Cs與位元線b i t或/b i t之 設定爲上述半預充電電位VD L/2之寄生容量之間被進 行電荷分散。例如，當於資訊記億電容器C s不存在有電 荷之狀態時，如同圖所示與記憶格連接之位元線電位即降 下。 感測放大器能動作化信號S A N，如上述般由負電壓 VNN上昇爲內部降壓電壓VDL，令上述N通道型 MOSFET Q8爲ON狀態，並供給電路之接地電位 之L位準之動作電壓。感測放大器能動化信號SAP，由 內部高電壓V C Η下降爲電路接地電位V S S之L位準， 令Ρ通道型MOSFET Q9爲ON狀態，供給內部降 壓電壓VD L般之Η位準之動作電壓。如上述般 MOSFET Q8與Q9，其閘極絕緣膜形成較薄，設 定爲較低之臨界値電壓，故設定爲ON狀態時流通較大之 電流，使感測放大器之放大動作爲高速。該感測放大器之 放大動作使互補位元線b i t及/b i t之電位，因來自 -In· 1 I - I - n I- - --Ia^^1 - -*- -I In I 1^1 (請先閲讀背面之注意事項再填寫本育) 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14- 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（12 ) 上述記億格之讀出電位差被擴大，而放大爲內部降壓電壓 VD L般之Η位準，及電位接地電位般之L位準。 因上述感測放大器之放大動作，對應於互補位元線 b i t及/b i t之Η位準與L位準，藉由字元線Wi之 選擇動作使於位元線b i t及/ b i t所接記憶格之記億 電容器Cs ，再度寫入上述記憶電荷狀態對應之L位準。 記憶體存取終了後，字元線Wi由內部高電壓VCH 下降爲負電壓VNN，之後，等化信號E Q由負電壓 VNN上昇爲內部高電壓VCH，使互補位元線b i t及 /b i t之Η位準/L位準短路以設定爲半預充電電壓 VDL/2。爲防止如此形成之半預充電電壓VDL/2 之因漏電流而變動，設有MOSFET Q2及Q3，藉 由其ON狀態而將半預充電電壓VD L/2傳至互補位元 線 b i t 及 / b i t。 圖4爲本發明之動態型R AM之一實施例之槪略元件 斷面圖。此實施例之動態型RAM，各元件係藉由3重井 構造形成。亦即，在P型基板上形成較深之η型井領域 DWELL，於該η型井領域DWELL上形成ρ型井領 域PWE L L以形成記憶格之位址選擇MO S F E T及感 測放大器之N通道型MOS F ET。據此，則在形成有記 憶格之P型井領域PWELL施加基板負偏壓VBB ’以 提高位址選擇MO S F E T之臨界値電壓，增長資訊保持 時間之同時，可令α線等產生於P型井領域PWE L L之 小數載子吸收於基板負偏壓V Β Β側以增長資訊保持時間 1^1 ^^1 ^^1 In n^— In I— ^*之 n· ^^1 ml In 0¾ *ve (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） -15- 經濟部中央標準局貝工消费合作社印製 Α7 Β7 五、發明説明（13 ) 〇 η型井領域被形成包圍P型井領域PWE L L且與上 述D EWL L接合，形成構成感測放大器等之P通道型 MOSFET。X解碼器等周邊電路，係形成於上述P-基板上之P型井領域PWE L L。依此種構成’包含形成 有記憶格或感測放大器之N通道型M0 s F E T之 PWE L L在內，則可在不設置各別之元件分離領域之狀 態下將感測放大器、記億格及字元驅動器一齊形成於 DWE L L內，而實現高積體化。 此實施例中，MOSFET具2種閘極絕緣膜’記憶 格之位址選擇MO S F E T ’及構成字元驅動之輸出 MO S F E T，其閘極絕緣膜形成爲膜厚t ο X 2之較厚 者。感測放大器或構成周邊電路之MO S F E T ’係形成 爲閘極絕緣膜爲膜厚t oxl之較薄者。使用2種閘極絕 緣膜之膜厚之優點爲’可同時達成元件之信賴性與動作之 高速化。即，閘極絕緣膜爲1種時，爲了元件之信賴度確 保（閘極絕緣膜之耐壓確保）’於施加之最大電壓條件下 ，閘極絕緣膜之膜厚被限定，因而在未施加上述高電壓之 電路中，臨界値電壓變高，電流驅動能力降低，動作速度 變慢。特別是，周邊電路及感測放大器大受Μ 0 S F E T 之驅動能力之影響。 於本實施例中，閘極施加有如上述般之內部高電壓 V C Η及負電壓VNN般之大信號振幅的位址選擇 MO S F Ε Τ，及形成該信號振幅之輸出信號的功率驅動 本紙張尺度遢用中國國家梂率（CNS ) Α4规格（210X297公釐） ---------^-- (請先閲讀背面之注意事項再填寫本頁) 、βτ -16- 經濟部中央標準局貝工消费合作社印製 B7五、發明説明（14 ) 器之輸出MO S F E T，爲防止閘極絕緣膜之耐壓破壞而 設定爲較厚之t ο X 2，而僅施加有上述內部降壓電壓之 感測放大器或周邊電路之MO S F E T ’爲達動作之高速 化而設定爲較薄之t ο X 1，如此可兼顧元件之信賴性及 動作之高速化。 本實施例中，於P —基板介由其上形成之PWE L L 施加電路之接地電位V S S之偏壓，於上述DWE L L施 加充電泵電路形成之高電壓VP P。又’於DWE L L內 所形成PWE L L施加有充電泵電路形成之基板負偏壓 VBB。依此種構成，則DWELL之接合容量與 PWE L L之接合容量可分別利用爲充電泵電路2及7之 電壓保持容量。 上述DWE L L供給有內部高電壓V CH， DWE L L內形成之PWE L L亦可供給負電壓VNN。 依此構成，則DWE L L之接合容量及PWE L L之接合 容量，可利用作爲設於圖2所示定電壓電路RG P與 RGN之輸出的電壓穩定化之電容器CDH及CDN。因 此，如圖所示，於DWELL供給高電壓VPP ’於 DWE L L內形成之PWE L L供給負電壓VB B之構成 ，沒有必要於定電壓電路RGP與RGN之輸出以MOS 容量等形成電壓穩定用之電容器CDH及CDN。 圖5爲本發明之動態型R AM之另一實施例之槪略元 件斷面圖。於此實施例中，和上述同樣以三重井構造形成 各元件。即，在P -型基板上形成深之η型井領域 (請先閎讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家棣準（CNS ) Α4規格（210><297公嫠） -17- 經濟部中央揉隼局貞工消费合作社印装 A7 B7五、發明説明（15 ) DWELL，於該η型并領域DWELL上形成構成記億 格之位址選擇MOSFET的p型井領域PWELL。於 形成有記憶格之P型井領域PWE L L施加基板負偏壓 VB B，以提高位址選擇MO S F E T之臨界値電壓增長 資訊保持時間之同時，令α線等產生於p型井領域 PWE L L之小數載子吸收於基板負偏壓VB Β側以增長 資訊保持時間。 本實施例中，構成感測放大器之Ν通道型 MO S F Ε Τ係與記億格所形成之Ρ型WE L L，形成在 上述DWE L L分離出之Ρ型井領域。於此種構成，在感 測放大器之Ν通道型MO S F Ε Τ所形成之ρ型井領域 PWE L L上，並非如上述記憶格般供給基板負偏壓 VB Β，而是供給電路之接地電位V S S。結果，因負偏 壓，在不受基板效果之影響之狀況下’可縮小構成感測放 大器之Ν通道型MO S F Ε Τ之臨界値電壓’對同一元件 尺寸可提昇驅動能力’使感測放大器之動作高速化。 圖6爲字元驅動器WD之一實施例之電路圖。於圖中 僅以字元驅動器WD之中’字元線W i對應之1個字元驅 動器WD i爲代表圖示出。構成X解碼器D E c之邏輯電 路G 1、G 2等’係如上述般藉由內部降壓電壓70匕及 電路之接地電位V S S動作者’並對應其而形成Η位準/ L位準之非選擇/選擇之輸出信號1^ 1 ° 相對於此，字元線W i之選擇位準係對應內部電壓 VCH，非選擇位準係對應內部負電壓VNN之電壓’故 ^^^1 m 1^1 I m , . «^0^ n^— I- - ^^1 nn ilf 、T (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率（CNS > A4规格（210 X 297公釐）_ ] 8 _ A7 B7 經濟部中央樣準局貝工消費合作社印裝 五 、發明説明（16 ) 1 i 不 必 對 上 述 V D L 及 V S S 所 對 應 之 X 解 碼器 X D Ε C 之 1 1 輸 出 信 號 Ν 1進 行 位 準 轉換 〇 於 此 實 施 例 中， 爲 提 高 元 件 1 1 之 信 賴 度 需儘 力 縮 小 施加 於 輸 出 Μ 0 S F Ε Τ 之 閘 極 之 請 1 先 1 電 壓 〇 亦 即 ，上 述 輸 出 信號 Ν 1 係 經 由 2個 位 準 轉 換 電 聞 讀 1 換 電 背 1 路 L S Ρ 及 L S N 分 別 轉換 爲 2 個 不 同 位 準。 位 準 轉 面 之 1 路 L S Ρ 係形 成 信 號 Ν 5 用 於 供 至 輸 出 Μ 0 S F Ε Τ 注 意 事 1 1 P 1 之 閘 極 俾使 上 述 X 解碼 器 X D Ε C 之 輸出 信 號 Ν 1 形 項 再 ά 成 爲 高 電 壓 V C Η 之 選 擇位 準 位 址 轉 換 電路 L S Ν 係 % 本 百 裝 I 形 成 信 號 Ν 3用 於 供 至 輸出 Μ 0 S F Ε Τ Ν 1 之 閘 極 俾 只 届 1 I 將 上 述 X 解 碼器 X D Ε C之輸出信號Ν ] .形成爲負· :壓 1 1 V N N 之 非 選擇 位 準 〇 1 1 位 準 轉 換電 路 L S Ρ， 係 設 定 爲 以 接 地電 位 V S S 及 訂 I 高 電 壓 V C Η動 作 > 設 置有 由 Ρ 通 道 型 Μ 0 S F Ε Τ 1 I Q 1 8 、 Q 19 及 Ν 通道型Μ ( 〕S F Ε Τ Q 1 6 1 1 1 Q 1 7 構 成 之一 對 C Μ 0 S 換 流 器 電 路 及分 別 串 接 於 Ρ 1 1 通 道 型 Μ 0 S F Ε Τ Q 1 8 Q 1 9 閘極 互 相 供 給 有 1 另 一 方 之 C Μ 0 S 換 流 器電 路 之 輸 出 信 號 ，設 定 爲 閂 鎖 形 | 態 之 P 通 道 型Μ 〇 S F Ε Τ Q 2 0 及 Q 2 1 被 供 給 有 I 局 電 壓 V C Η » X 解 碼 器D Ε C 之 輸 出 信 號Ν 1 係 供 至 構 1 1 I 成 一 方之 C MO S 換 流; 器之Μ < 3 3 F Ε Τ Q 1 7 及 1 1 Q 1 9 之 閘 極， 經 由 換 流器 電 路 I V 1 反 轉供 至 構 成 另 一 1 1 方 C Μ 0 S 換流 器 電 路 之Μ 0 S F Ε Τ Q 1 6 及 Q 1 8 I 之 閘 極 〇 1 I — 方 之 換流 器 電 路 之輸 出 信 號 Ν 4 係供 至 作 爲 驅 動 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -19 · A7 B7 五、發明説明（17 ) 器動作之CMOS換流器電路I V2之輸入，換流器電路 I V2之輸出信號N5供至P通道型輸出MOSFET MP 1之閘極，以驅動該輸出MOSFET MP 1。換 流器電路I V 1係圖示爲位準轉換電路L S P之一部分， 但實際上僅作爲形成X解碼器D E C之輸出信號之反轉信 號。也因此，位準轉換電路L S P如上述般動作於高電壓 VCH及電路之接地電路，但是，換流器電路I V 1亦和 X解碼器XD E C同樣動作於內部降壓電壓VD L及接地 電位V S S。 經濟部中夬標率局員工消费合作社印装 (請先閲讀背面之注意事項再填寫本頁) 位準轉換電路L S N，電路構成係與位準轉換電路 LSP相同。於是不同點爲，P通道型MOSFET與N 通道型MOSFET爲相反，N通道型MOSFET側設 有閂鎖形態之Μ 0 S F E T，同時，Η位準側之動作電壓 以內部降壓電壓VDL取代內部高電壓VCH，L位準側 之動作電壓則以內部負電壓VNN取代電路之接地電路 VSS。亦即，位準轉換電路LSN，係設定爲以內部降 壓電壓VD L及內部負電壓VNN動作，設置有和上述同 樣之Ρ通道型MO S F Ε Τ及Ν通道型MO S F E Τ構成 之一對CMO S換流器電路，及分別串接於Ρ通道型 MO S F Ε Τ，閘極互相供給有另一 CMO S換流器電路 之輸出信號，設定爲閂鎖形態之Ν通道型MOSFET， 被供給有內部負電壓V Ν N。 X解碼器XDEC之輸出信號N1，係供至構成一方 之CMO S換流器電路之MO S F Ε T之閘極，經換流器 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） -20- 經濟部中央標準局貞工消费合作社印製 A7 _B7_ 五、發明説明（18 ) 電路反轉，供至構成另一方之CMO S換流器電路之 M〇S F E 丁之閘極。一方之換流器電路之輸出信號N 2 ，係供至作爲驅動器動作之CMO S換流器電路之輸入， 該換流器電路之輸出信號N 3狀至N通道型輸出 MOSFET MN1之閘極，以驅動輸出MOSFET Μ N 1。 本實施例中，爲縮小施加於輸出MO S F Ε Τ ΜΡ 1及ΜΝ 1之閘極與汲極間之電壓，換言之，爲緩和 施加於MOSFET ΜΡ1及MN1之閘極絕緣膜之應 力，在與字元線W i所連接輸出端子之間分別串接P通道 型MOSFET MP2及N通道型MOSFET MN2，在P通道型MOSFET MP2之閘極施加接 地電位V S S使常時設爲ON狀態，N通道型 MOSFET MN2之閘極則施加有內部降壓電壓 VD L以設爲常時ON狀態。 位準轉換電路LSP，用於形成VCH及VSS之信 號振幅之驅動信號N5，以控制輸出MOSFET MP1之ΟΝ/OFF狀態。P通道型MOSFET ΜΡ 2，即使字元線W i爲負電壓VNN時，亦可將輸出 MOSFET ΜΡ1之汲極電壓保持於接地電位VSS +VT(此處VT爲MOSFET MP2之臨界値電壓 )0 結果，如圖7之動作波形所示，即使輸出端因N通道 型輸出MOSFET MN1之ON狀態而爲字元線Wi 本紙承尺度適用中國國家梂準（CNS ) A4規格（210X297公釐） -21 - (請先閲讀背面之注意事項再填寫本頁) 裝. ，-'° A7 ____ B7 五、發明説明（19 ) 之非選擇位準對應之負電壓VNN時，於〇 F F狀態之P 通道型輸出MOS FET MP 1之閘極與汲極間，亦僅 施加VCH-(VSS+VT)之電壓。 位準轉換電路L S N，用於形成VD L及VNN之信 號之振幅之驅動信號N 3，以控制輸出MO S F E T MN1之ΟΝ/OFF狀態。因此，N通道型 MOSFET MN1，即使字元線Wi爲高電壓VCH 時，亦可將輸出MOSFET MN1之汲極電壓保持於 內部降壓電壓VDL — VT (VT爲MOSFET MN2之臨界値電壓）。結果，如圖7之動作波形圖所示 ，輸出端子因P通道型MOSFET MP1之ON狀態 而爲字元線W i之選擇位準對應之內部高電壓V c Η時， 於OFF狀態之Ν通道型輸出MOSFET MN1之閘 極與汲極之間，僅施加有（VDL-VT) — VNN之電 壓。 經濟部中央樣準局貝工消费合作杜印裝 (請先閲讀背面之注意事項再填寫本頁) 即，如圖7之動作波形圖所示，因2種類之位準轉換 電路L S P及L S N產生之驅動電壓N 5及N 3之信號振 幅之限制作用，與串接設置之MOSFET MP2及 MN 2產生之施加電壓分割作用之相乘效果，故儘管字元 線W i之選擇位準/非選擇位準爲內部高電壓V C Η及內 部負電壓VNN對應之較大電壓，但施加於輸出 MOSFET MP1及MN1之電壓乃可抑制於較小。 因此，就記憶格而言，內部降壓電壓VD L保持於記憶電 容器Cs ，故字元線Wi設爲非選擇之負電壓VNN時， 本紙張尺度遑用中國困家揉準（CNS } A4规格（210X297公釐） •22- 經濟部中央搮準局負工消费合作社印裝 A7 B7 五、發明説明（20 ) VNN — VD L之最大電壓被施加，而當字元線w i設爲 選擇電壓V CH之後，V S S _V CH之最大電壓被施加 〇 位準轉換電路L S P之位準轉換動作之槪略如下。當 構成X解碼器XD E C之閘極電路G 1之輸出信號N 1爲 接地電位V S S對應之L位準時，一方之CMO S換流器 電路（Q1 7與Q1 9)之P通道型MOSFET Q 1 9爲ON狀態。因換流器電路I V 1之輸出信號之Η 位準使Ν通道型MOSFET Q16爲ON狀態，故另 —方之CMOS換流器電路（Q 1 6與Q 1 8 )之輸出信 號爲L位準。依此，則p通道型MOSFET Q2 1設 爲〇N狀態，經由〇N狀態之MOSFET Q19使輸 出信號N 4設定爲高電壓VCH之Η位準。結果，可形成 高電壓V CH對應之Η位準，且Ρ通道型MO S F ΕΤ Q20設爲OFF狀態，使直流電流未流通於另一方之 C Μ 0 S換流器。 當構成X解碼器XDE C之閘極電路G 1之輸出信號 Ν 1爲內部降壓電壓VDL之Η位準時，一方之CMOS 換流器電路（Q 1 7及Q 1 9 )之N通道型MOS FET Q 1 7成爲ON狀態。於另一方之CMO S換流器電路 (Q16及Q18)，換流器電路IV1之輸出信號成爲 L位準，P通道型MOSFET Q18爲ON狀態。因 MOSFET Q17成爲ON狀態使輸出信號N4設定 爲L位準。P通道型MOSFET Q20爲ON狀態， 本紙張尺度適用中國國家搮準（CNS > A4规格（210X297公釐） -23- (請先閲讀背面之注意事項再填寫本頁) 裝.•• IT A7 ___ B7_ · V. Description of the invention (9) The voltage VPP or VBB formed by the above charge pump circuit 2 or 7 is maintained by the stored charge such as parasitic capacity, for example, when the word line is cut from a non-selection level to When selecting the level, or vice versa, when switching from the selection level to the non-selection level, as most of the memory cells are connected, the charge or discharge current of the word line with a larger parasitic capacity changes greatly as described above. To estimate such voltage changes and set the selection level and non-selection level of the word line, it is necessary to select the gate insulating film of MO SFET at the address where the word line is connected, or drive the word line The voltage of the gate insulation film of the output MO SFET of the zigzag line driver is high-voltage resistant, corresponding to the voltage estimated to increase in the above-mentioned level variation. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the precautions on the back, and then fill out this page). In contrast, the invention in this case is designed to select the word line through the constant voltage circuit RG P or RGN Level, non-selection level, as described above, when the character line is cut from the non-selection level to the selection level, or vice versa, the selection level is cut to the non-selection level. The charge or discharge current of the word line of parasitic capacity causes changes in VPP and VBB. However, since the resistances Q of the variable resistors MOSFETs Q12 and Q15 of the constant-voltage circuit RGP or RGN also change to absorb the voltage variation, approximately constant voltages V C Η and VNN can be ensured. The voltage difference between the internal high voltage VCH and the high voltage VP P and the voltage difference between the internal negative voltage V NN and the negative voltage VB Β are formed to correct the charge pump circuits 2 and 7 corresponding to the drive currents of the word lines, respectively. Output voltage changer. In this way, the voltage applied to the gate driver WD's output MO SF ΕΤ or the gate insulation film of MO SF ΕΤ is selected by the above-mentioned stabilization voltage VC Η or VNN to determine the paper size. China Standard for Households (CNS) A4 specification (210X297 mm) -12- Printed by A7 B7 of the Consumer Cooperatives of the Central Ladder Bureau of the Ministry of Economic Affairs 5. Small voltage of invention description (10), so it is not necessary to estimate the voltage as above Change and apply high pressure resistance. FIG. 3 is a waveform of a description of a rough operation of the dynamic Ram according to the present invention. The diagram mainly illustrates a selection operation of a memory cell. The equalization signal E Q is set to the level of the above-mentioned internal high voltage VCH when the memory cell is in the information holding state. In this way, the MOSFETs Q1 to Q3 are turned on, the complementary bit lines b i t and / b i t are short-circuited, and the above-mentioned half precharge voltage VDL / 2 is supplied. Since the complementary bit lines b i t and / b i t are set to a half pre-electric voltage VDL / 2, the level of the equalization signal EQ will operate even at a low potential of V D L. However, as in this embodiment, by using the internal high voltage VCH ', the ON resistance of the MOSFET Q1 can be reduced, and in a short time, the bit level of the complementary bit line bit and / bit can be short-circuited to the L level to set the intermediate potential. VDL / 2. When the memory is accessed, the equalization signal E Q changes from the Η level to the L level. At this time, the L level of the equalization signal E Q is not the ground potential of the circuit, but a negative voltage VNN. The reason is that the threshold value 较小 is set to be small in order to increase the equalization speed, and a negative voltage V N N is supplied to the gates of the MOSFETs Q1 to Q3 to prevent leakage current flowing between the drain and source. As described above, the active signal SAN of the sense amplifier is set to a negative voltage V N N when the sense amplifier is in an inactive state to prevent leakage current flowing through the power switch MOSFET Q8. That is, in order to increase the speed of the sense amplifier, the MOSFET Q8 has a thin gate insulating film and is set to a low threshold voltage. Use of this low paper size is applicable to China National Standard (CNS) A4 (210X297 mm) -------- 1. Loading-(Please read the Note # on the back before filling this page ) Order-13- Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (u) The threshold voltage M 0 SFET can flow a larger current during operation. The amplifier's amplification action is high speed. In this case, the same is true for the P-channel MOSFET Q9. When the sense amplifier is in the inactive state, it is set to the internal high voltage VCH to prevent the leakage current flowing through the power switch MOSFET Q9. When the equalization signal E Q is set to the non-selection level of the negative voltage V Ν Ν, the word line Wi becomes the selected state of the Η level of the internal high voltage ν C Η. In this way, the address selection of the memory cell M 0 SFETQ m becomes 0 Ν state. The charge dispersion is performed between the parasitic capacity of the information memory capacitor Cs and the bit line bit or / bit set to the above-mentioned semi-precharge potential VD L / 2 . For example, when there is no charge state in the capacitor C s recorded in the information, the potential of the bit line connected to the memory cell decreases as shown in the figure. The sense amplifier can actuate the signal S A N, which rises from the negative voltage VNN to the internal step-down voltage VDL as described above, so that the N-channel MOSFET Q8 is turned on and supplies the operating voltage of the L level of the ground potential of the circuit. The activation signal SAP of the sense amplifier drops from the internal high voltage VC to the L level of the circuit ground potential VSS, sets the P-channel MOSFET Q9 to the ON state, and supplies the operating voltage of the internal step-down voltage VD L to a high level. . As mentioned above, the MOSFET Q8 and Q9 have thin gate insulation films and are set to a lower threshold voltage. Therefore, when set to the ON state, a larger current flows to make the amplification of the sense amplifier at high speed. The amplifying action of the sense amplifier causes the potentials of the complementary bit lines bit and / bit, due to -In · 1 I-I-n I----Ia ^^ 1--*--I In I 1 ^ 1 (Please read the notes on the back before filling in this education.) The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -14- Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (12) The read potential difference in the above-mentioned billion grids is enlarged, and enlarged to the internal level of the step-down voltage VD L and the L level of the potential ground potential. Due to the amplification action of the above-mentioned sense amplifier, corresponding to the bit level and L level of the complementary bit line bit and / bit, the memory cell connected to the bit line bit and / bit is selected by the selection action of the word line Wi. One hundred million capacitors Cs are written into the L level corresponding to the state of the stored charge again. After the memory access is completed, the word line Wi drops from the internal high voltage VCH to the negative voltage VNN. After that, the equalization signal EQ rises from the negative voltage VNN to the internal high voltage VCH, making the complementary bit lines bit and / bit The level / L level is short-circuited to set the half precharge voltage VDL / 2. In order to prevent the half-precharge voltage VDL / 2 thus formed from changing due to leakage current, MOSFETs Q2 and Q3 are provided, and the half-precharge voltage VD L / 2 is transmitted to the complementary bit line bit and / by its ON state. bit. Fig. 4 is a cross-sectional view of a schematic element of an embodiment of a dynamic RAM according to the present invention. In the dynamic RAM of this embodiment, each element is formed by a triple-well structure. That is, a deeper n-well region DWELL is formed on the P-type substrate, and a p-well region PWE LL is formed on the n-well region DWELL to form the address of the memory cell. The N channel of the MO SFET and the sense amplifier is selected. MOS F ET. According to this, in the P-well area where the memory cell is formed, PWELL applies a substrate negative bias VBB 'to increase the threshold voltage of the address selection MO SFET and increase the information retention time. At the same time, the alpha line can be generated in the P-type. The decimal carriers in the well field PWE LL are absorbed on the substrate negative bias V Β Β side to increase the information retention time 1 ^ 1 ^^ 1 ^^ 1 In n ^ — In I— ^ * of n · ^^ 1 ml In 0¾ * ve (Please read the precautions on the back before filling this page) This paper size uses the Chinese National Standard (CNS) A4 size (210X297 mm) -15- Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 5 Description of the Invention (13) The η-type well field is formed to surround the P-well field PWE LL and is joined to the above D EWL L to form a P-channel MOSFET constituting a sense amplifier and the like. The peripheral circuits such as the X decoder are PWE L L formed in the P-well area on the P-substrate. According to this structure, including the PWE LL of the N-channel type M0 s FET with a memory cell or a sense amplifier, the sense amplifier, the memory cell, and the megacell can be recorded without setting separate component separation areas. The character driver is formed in the DWE LL at the same time, so as to achieve high integration. In this embodiment, the MOSFET has two types of gate insulating film 'MO SFET of memory cell address selection' and a character driven output MO SFET. The gate insulating film is formed as the thicker film thickness t ο X 2 . The sense amplifier or the MO S F E T ′ constituting the peripheral circuit is formed as a gate insulating film having a thinner film thickness t oxl. The advantage of using two kinds of gate insulation film thickness is that it can achieve both the reliability of the device and the high-speed operation. In other words, when there is one type of gate insulating film, in order to ensure the reliability of the device (guaranteed the withstand voltage of the gate insulating film) under the maximum applied voltage condition, the film thickness of the gate insulating film is limited. In the above-mentioned high-voltage circuit, the critical threshold voltage becomes higher, the current driving capability is lowered, and the operation speed becomes slower. In particular, peripheral circuits and sense amplifiers are greatly affected by the driving ability of M 0 S F E T. In this embodiment, the address selection MO SF Ε Τ with the large signal amplitude such as the internal high voltage VC Η and negative voltage VNN applied to the gate, and the power of the output signal forming the signal amplitude drive the paper size. Use China National Standard (CNS) Α4 specification (210X297 mm) --------- ^-(Please read the notes on the back before filling this page), βτ -16- Central Standard of the Ministry of Economic Affairs Printed by BPC Consumer Cooperative Co., Ltd. B7 V. Invention Description (14) The output MO SFET of the device is set to a thicker t ο X 2 in order to prevent the breakdown voltage of the gate insulation film, and only the above internal voltage drop is applied. The voltage sense amplifier or the MO SFET of the peripheral circuit is set to a thinner t ο X 1 for high-speed operation, so that both the reliability of the device and the high-speed operation can be considered. In this embodiment, a bias voltage of the ground potential V S S of the circuit is applied to the PWE substrate formed on the P-substrate, and a high voltage VP P formed by the charge pump circuit is applied to the aforementioned DWE L L. In addition, a substrate bias voltage VBB formed by the charge pump circuit is applied to the PWE L L formed in the DWE L L. With this configuration, the connection capacity of DWELL and the connection capacity of PWE L L can be used as the voltage holding capacity of the charge pump circuits 2 and 7, respectively. The above DWE L L is supplied with an internal high voltage V CH, and the PWE L L formed in the DWE L L may also supply a negative voltage VNN. According to this structure, the junction capacity of DWE L L and the junction capacity of PWE L L can use capacitors CDH and CDN, which are voltage stabilized outputs provided in the constant voltage circuits RG P and RGN shown in FIG. 2. Therefore, as shown in the figure, the structure of supplying high voltage VPP to DWELL and supplying negative voltage VB B to PWE LL formed in DWE LL is not necessary to stabilize the voltage of the constant-voltage circuits RGP and RGN with MOS capacity and other voltages. Capacitors CDH and CDN. Fig. 5 is a cross-sectional view of a schematic element of another embodiment of the dynamic RAM of the present invention. In this embodiment, each element is formed in a triple-well structure as described above. That is, a deep η-type well area is formed on the P-type substrate (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) Α4 standard (210 > < 297 cm) ) -17- A7 B7 printed by Zhengong Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 5. Description of the invention (15) DWELL, on the n-type parallel area DWELL, a p-type well field that constitutes an address selection MOSFET that constitutes a hundred million grid is formed. PWELL. In the P-well area where a memory cell is formed, a substrate negative bias voltage VB B is applied to improve the threshold of the address selection MO SFET and the voltage retention information retention time, so that alpha lines and the like are generated in the P-well area PWE LL The decimal carriers are absorbed on the negative bias VB B side of the substrate to increase the information retention time. In this embodiment, the P-type WE L L formed by the N-channel type MO S F E T forming the sense amplifier and the recording grid is formed in the P-well field separated from the D WE L L described above. With this configuration, in the p-well field PWE LL formed by the N-channel type MO SF Ε Τ of the sense amplifier, the substrate bias voltage VB Β is not supplied to the substrate as described above, but the ground potential VSS of the circuit is supplied. . As a result, due to the negative bias, the threshold voltage of the N-channel type MO SF Ε Τ constituting the sense amplifier can be reduced without being affected by the effect of the substrate. Speed up the operation. FIG. 6 is a circuit diagram of an embodiment of the character driver WD. In the figure, only one character driver WD i corresponding to the 'character line Wi' among the character drivers WD is shown as a representative illustration. The logic circuits G1, G2, etc. constituting the X decoder DE c are formed by the internal step-down voltage of 70 kΩ and the circuit's ground potential VSS as described above, and correspondingly form the Η level / L level. Non-selected / selected output signal 1 ^ 1 ° In contrast, the selection level of the word line Wi corresponds to the internal voltage VCH, and the non-selected level corresponds to the voltage of the internal negative voltage VNN ', so ^^^ 1 m 1 ^ 1 I m,. «^ 0 ^ n ^ — I--^^ 1 nn ilf, T (Please read the precautions on the back before filling this page) This paper size is applicable to China's national standard (CNS > A4 specifications (210 X 297 mm) _] 8 _ A7 B7 Printed by the Central Samples Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. 5. Description of the invention (16) 1 i It is not necessary to match the X decoder XD Ε C corresponding to the above VDL and VSS 1 1 The output signal N 1 undergoes level conversion. In this embodiment, in order to improve the reliability of the component 1 1, it is necessary to make every effort to reduce the voltage applied to the gate of the output M 0 SF Ε Τ. Output signal N 1 It reads the electric news through 2 level conversions, 1 power back, 1 channel LS P and LSN are respectively converted into 2 different levels. The 1 channel LS P on the level conversion surface forms a signal N 5 for supplying to the output M 0 SF Ε Τ Note 1 The gate of 1 P 1 makes the output signal Ν 1 of the X-decoder XD Ε C form a high-voltage VC Η The selection level address conversion circuit LS Ν is 100% installed The I formation signal N 3 is used to supply the gate of the output M 0 SF Ε Ν Ν 1 only at 1 I. The output signal N of the above X decoder XD Ε C is formed to be negative.: Negative pressure 1 1 VNN Selection level 〇1 1-level conversion circuit LS P is set to operate at ground potential VSS and set I high voltage VC > It is provided with P channel type M 0 SF Ε Τ 1 IQ 1 8, Q 19 and Ν Channel type M (] SF Ε Τ Q 1 6 1 1 1 Q 1 7 constitutes a pair of C Μ 0 S converter circuits and is connected in series to Ρ 1 1 channel type M 0 SF Ε Q Q 1 8 Q 1 9 The gates supply 1 output signal of the other C Μ 0 S inverter circuit to each other, which is set to a latch-shaped | state P channel type Μ 〇 SF Ε Τ Q 2 0 and Q 2 1 are supplied with I station voltage VC Η »X decoder D Ε C output signal N 1 is supplied to C 1 S I commutation; 1 M 1 <; The gates of 3 3 F Ε Q 1 7 and 1 1 Q 1 9 are reversed and supplied to inverter M 0 SF Ε Τ which constitutes the other 1 1 side C Μ 0 S inverter circuit via inverter circuit IV 1. Gates of Q 1 6 and Q 1 8 I 〇1 I — The output signal N 4 of the inverter circuit is supplied as the drive 1 1 1 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ) -19 · A7 B7 V. Description of the invention (17) Input of CMOS converter circuit I V2 of converter operation, output signal N5 of converter circuit I V2 is supplied to the gate of P-channel output MOSFET MP 1, Drive this output MOSFET MP1. The inverter circuit I V 1 is shown as a part of the level conversion circuit L S P, but it is actually only used as an inverted signal forming the output signal of the X decoder D EC. Therefore, the level conversion circuit LSP operates on the high-voltage VCH and the ground circuit of the circuit as described above, but the converter circuit IV 1 also operates on the internal step-down voltage VD L and the ground potential VSS like the X decoder XD EC. . Printed by the Consumer Standards Cooperative Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling out this page) The level conversion circuit L S N has the same circuit configuration as the level conversion circuit LSP. Therefore, the difference is that the P-channel MOSFET is the opposite of the N-channel MOSFET. The N-channel MOSFET is provided with a latching M 0 SFET. At the same time, the operating voltage on the level side is replaced by the internal step-down voltage VDL. The voltage VCH, the operating voltage on the L level side replaces the ground circuit VSS of the circuit with the internal negative voltage VNN. That is, the level conversion circuit LSN is set to operate with the internal step-down voltage VD L and the internal negative voltage VNN, and is provided with a pair of P-channel type MO SF ET and N-channel type MO SFE Τ which is the same as the above. The CMO S converter circuit and the P-channel type MO SF Ε Τ are connected in series, and the gates supply the output signals of another CMO S converter circuit to each other, and the N-channel type MOSFET set to the latching mode is supplied. There is an internal negative voltage V N N. The output signal N1 of the X decoder XDEC is supplied to the gate of MO SF Ε T which constitutes one CMO S converter circuit. The paper size of the converter applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ) -20- Printed by A7 _B7_ of the Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics. 5. Description of the invention (18) The circuit is reversed and supplied to the gate of the MOSFET of the other party ’s CMO S converter circuit. The output signal N 2 of one inverter circuit is supplied to the input of the CMO S inverter circuit acting as a driver. The output signal N 3 of the inverter circuit is to the gate of the N-channel output MOSFET MN1. To drive the output MOSFET MN 1. In this embodiment, in order to reduce the voltage applied between the gates and the drains of the outputs MO SF Ε Τ MP1 and MN1, in other words, to alleviate the stress applied to the gate insulating films of the MOSFETs MP1 and MN1, P-channel MOSFET MP2 and N-channel MOSFET MN2 are connected in series between the output terminals connected to the element line Wi. A ground potential VSS is applied to the gate of the P-channel MOSFET MP2 to always be turned on, and the N-channel MOSFET MN2 An internal step-down voltage VD L is applied to the gate to be always ON. The level conversion circuit LSP is used to form the driving signal N5 of the signal amplitude of VCH and VSS to control the ON / OFF state of the output MOSFET MP1. The P-channel MOSFET MP2 can keep the drain voltage of the output MOSFET MP1 at the ground potential VSS + VT (where VT is the critical threshold voltage of the MOSFET MP2) even when the word line Wi is a negative voltage VNN. 0 Result As shown in the operation waveform of Fig. 7, even if the output terminal is a character line Wi due to the ON state of the N-channel output MOSFET MN1, the paper bearing standard is applicable to China National Standard (CNS) A4 specification (210X297 mm) -21- (Please read the precautions on the back before filling out this page)..,-'° A7 ____ B7 V. Description of the invention (19) When the negative voltage VNN corresponding to the non-selection level, the P channel output at 0FF state Only the voltage of VCH- (VSS + VT) is applied between the gate and the drain of the MOS FET MP 1. The level conversion circuit L S N is used to form the driving signal N 3 of the amplitude of the signals of VD L and VNN to control the ON / OFF state of the output MO S F E T MN1. Therefore, even when the word line Wi is a high voltage VCH, the N-channel MOSFET MN1 can keep the drain voltage of the output MOSFET MN1 at the internal step-down voltage VDL — VT (VT is the threshold voltage of the MOSFET MN2). As a result, as shown in the operation waveform diagram of FIG. 7, when the output terminal is the internal high voltage V c 对应 corresponding to the selection level of the word line Wi due to the ON state of the P-channel MOSFET MP1, the N channel is in the OFF state. Only the voltage (VDL-VT)-VNN is applied between the gate and the drain of the output MOSFET MN1. Dumpling Packing for Shellfisher Consumer Co-operation, Central Bureau of Standards, Ministry of Economy The limiting effect of the signal amplitudes of the driving voltages N 5 and N 3 is multiplied by the applied voltage division effect of the MOSFETs MP2 and MN 2 arranged in series, so despite the selection level / non-selection of the word line Wi The level is a relatively large voltage corresponding to the internal high voltage VC Η and the internal negative voltage VNN, but the voltages applied to the output MOSFETs MP1 and MN1 can be suppressed to be small. Therefore, as far as the memory cell is concerned, the internal step-down voltage VD L is kept at the storage capacitor Cs. Therefore, when the character line Wi is set to a non-selected negative voltage VNN, the paper size is based on Chinese standards (CNS} A4). (210X297 mm) • 22- Printed by A7 B7 of the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs V. Description of the invention (20) The maximum voltage of VNN — VD L is applied, and when the character line wi is set to the selection voltage V After CH, the maximum voltage of VSS _V CH is applied to the level conversion operation of the level switching circuit LSP. The following is a summary. When the output signal N 1 of the gate circuit G 1 forming the X decoder XD EC corresponds to the ground potential VSS When the L level is on, the P channel MOSFET Q 1 9 of one CMO S converter circuit (Q1 7 and Q1 9) is ON. The 信号 level of the output signal of the inverter circuit IV 1 makes the N channel type The MOSFET Q16 is in the ON state, so the output signal of the other CMOS inverter circuits (Q 1 6 and Q 1 8) is at the L level. Accordingly, the p-channel MOSFET Q2 1 is set to the ON state, The MOSFET Q19 in the ON state sets the output signal N 4 to the high level of the high voltage VCH. As a result, the The high voltage V CH corresponds to the high level, and the P-channel type MO SF ET Q20 is set to the OFF state, so that the DC current does not flow through the other C Μ 0 S converter. When the X decoder C gate is formed When the output signal N 1 of the pole circuit G 1 is at the level of the internal step-down voltage VDL, the N-channel MOS FET Q 1 7 of one of the CMOS converter circuits (Q 1 7 and Q 1 9) becomes ON. On the other side of the CMO S inverter circuit (Q16 and Q18), the output signal of the inverter circuit IV1 becomes the L level, and the P-channel MOSFET Q18 is turned on. The output signal N4 is set to L because the MOSFET Q17 is turned on. Level. The P-channel MOSFET Q20 is ON, and this paper size is applicable to the Chinese National Standard (CNS > A4 size (210X297 mm) -23- (Please read the precautions on the back before filling this page).

*aT 經濟部中央揉準局負工消费合作社印装 Α7 Β7 五、發明説明（21 ) 故另一方之CMO S換流器電路之輸出信號設爲高電壓 VCH對應之Η位準。結果’ P通道型MOSFET Q 2 1爲0 F F狀態，使直流電流未流通於形成L位準輸 出信號Ν 4之一方之CMO S換流器電路。 位準轉換電路L S Ν之位準轉換動作之槪略與上述大 略相同，故以下僅說明構成X解碼器XD E C之閘極電路 G 1之輸出信號Ν 1爲接地電位VS S對應之L位準時之 動作。供給有輸出信號Ν 1之一方之CMO S換流器電路 之Ρ通道型MO S F Ε Τ設定爲Ο Ν狀態。於另一方之 CMO S換流器電路，供給有反轉之Η位準信號，故Ν通 道型MO S F ΕΤ成爲ON狀態。因一方之CMOS換流 器電路之P通道型MO S F Ε T之ON狀態，輸出信號 N 2成爲內部降壓電壓VD L之Η位準，使另一方之 CMO S換流器電路之Ν通道型MO S F Ε Τ成爲ON狀 態。結果，另一方之CMO S換流器電路之輸出信號，因 2個N通道型MO S F Ε T設爲ON狀態，而輸出負電壓 VNN。結果，可形成內部降壓電壓VD L對應之Η位準 之輸出信號Ν 2，具使其對應之負電壓VNN側之Ν通道 型Μ 0 S F Ε Τ成爲0 F F狀態，使直流電流不流經一方 之CMO S換流器電路。 圖8爲字元線驅動器WD之另一實施例之電路圖。於 此實施例，X解碼器分割成2個電路構成。於第1解碼器 XDEC形成字元線4條分之選擇信號Ν1。該選擇信號 係經由未圖示之第2解碼器所形成之選擇信號X 〇 〇、 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210Χ297公釐） -24- (請先閲讀背面之注意事項再填寫本頁) 裝_ 、1Τ 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（22 ) X01、 X10及XII作開關控制之開關MOSFET Ml 0〜Ml 3分別供至對應之字元驅動器WD i。 字兀驅動器WD i ’係以1個電路爲代表圖示，兼具 位準轉換功能及字元驅動功能》-P通道型輸出 MOSFET M3 及M4，N通道型MOSFET M6及M5，爲構成字元驅動器者。N通道型輸出 MOSFET M6.，係與 N 通道型 MOSFET Μ 7 成閂鎖形態，具有位準轉換功能。於MOSFET Μ 7 ，串接有耐壓緩和用之Ν通道型MOSFET M8，和 MOSFET M5同樣’於閘極供給有內部降壓電壓 V D L。 於P通道型輸出MOSFET M3，爲位準轉換設 有閂鎖形態之P通道型MOSFET M2，於輸出 MOSFET M3之閘極，介由預充電信號WPH控制 之P通道型MOSFET Ml預充電於高電壓VCH。 於其輸入點介由開關MOSFET Ml〇供給有選擇信 號N 5。 圖9爲字元驅動器之動作說明之時序圖。當預充電信 號WPH爲電路接地電位GND之L位準時，P通道型 MOSFET Ml成爲ON狀態，輸入端子預充電爲高 電壓VCH。因預充電動作使MOSFET M3成 OFF狀態，同時，介由ON狀態之MOSFET Μ 9 ’MOSFET M8 使 N 通道輸出MOSFET Μ 6 之閘極電位Ν 3設爲VD L — VT之Η位準。結果， 本紙張尺度適用中國國家標準（CNS M4规格（2〗0X297公嫠） -25- n n. I ϊ I n n I l·— , - -I - m n I an 丁 J3 言 (請先聞讀背面之注意事項再填寫本覓) A7 B7 五、發明説明（23 ) Μ 0 S F E T Μ6成爲ON狀態，使字元線Wi成爲負 電壓VNN之非選擇位準。 因MOSFET M6之ON狀態，使於設定爲閂鎖 形態之MO S F E T M7之閘極供給有負電壓VNN而 成〇 F F狀態。因此，可防止貫通電流流經由成爲0 N狀 態之預充電MOSFET Ml ，及電壓緩和用之常時爲 ON狀態之MOSFET M9及M8及MOSFET M7所形成之串接路徑。 經濟部中夬橾準局貝工消費合作杜印製 因X解碼器之動作，使第1解碼器XD E C 1之輸出 信號N 1成爲L位準。之後，4條字元線之中因選擇信號 X00爲Η位準使MOSFET M10成ON狀態，如 此則輸入端之選擇信號N 5或爲L位準。結果，輸出 MOSFET M3由OFF狀態轉化爲ON狀態，使字 元線W i由負電壓VNN上昇爲高電壓V CH。因該電壓 之上昇，使MOSFET M7成爲〇N狀態， MOSFET M6之閘極電壓N3由VDL — VT降爲 負電壓VNN。因此，MOSFET M6被設爲OFF 狀態，字元線W i之電位快速上昇爲高電壓v C Η。其他 非選擇字元線，於其對應之字元驅動器中維持預充電電壓 ，因此，Ρ通道型輸出MOSFET成爲OFF狀態，Ν 通道型輸出MO S F Ε Τ成ON狀態而維持負電壓VNN 之非選擇位準。 字元線W i之選擇動作之終了，使解碼器信號χ〇 〇 設爲L位準，MOSFET M10被設爲OFF狀態。 -26- (請先聞讀背面之注意事項再填寫本頁) 本纸張尺度適用中國S家棣準（CNS ) A4規格（210X297公釐） 經濟部中央樣準局貝工消费合作社印裝 A7 B7五、發明説明（24 ) 又，第1解碼器XDE C 1之輸出信號N 1復原爲Η位準 。之後，預充電信號WP Η變爲L位準，使MO S F Ε Τ Μ 1成爲O N狀態。因此，輸入端之電壓Ν 5預充電爲 高電壓VCH。因該預充電動作，使P通道型輸出 MOSFET M3成爲OFF狀態，同時，N通道型 MOSFET M6之閘極電壓\3因MOSFET M8而設定爲VDL — VT所限制之Η位準。因 MOSFET M6之ON狀態，使字元線Wi之選擇位 準（VCH)上昇爲非選擇位準對應之負電壓VNN。此 構成中，施加於輸出MOSFET M3或M6之電壓， 如上述般被限制，故可確保元件之高信賴性。 此實施例中，對第1 X解碼器電路XDE C，共用4 條字元線對應之字元驅動器。如此則可減少相當於1條線 必要之MO S F Ε T之數目。換言之，以高密度配置之字 元線節矩，及形成該選擇信號之X解碼器之節矩可一致’ 使高集積化爲可能。 .圖10爲本發明適用於階層化（分割字元線方式）字 元驅動器時之一實施例之構成圖。階層化字元線指，將字 元線區分爲主字元線及副字元線，於副字元線連接記億格 者。於此種階層化字元方式中，係令高電阻之字元線以低 電阻之金屬配線層作底層，以緩和所謂字元分流方式中之 金屬配線層之佈線節矩者。藉此種分割字元線’可實現大 記億容量化及高集積化。 圖中表示出記憶區塊之主字元線及副字元線之關係之 . =^^1 111 . In. -ii n^i I- 1 * ml -I I n I---- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家梯準（CMS ) A4規格（210X297公釐） -27- B7 五、發明説明（25 ) 槪略構成。於圖中，以2條主字元線MW〇及MW i爲代 表表示。主字元線MW〇、 MWi等，係由設於主字元驅 動器MWD之各驅動器MDRVO、 MDRVi等設爲選 擇/非選擇。於1個主字元線MWO，於其延長方向設有 多數組副字元線SWL。圖中，以3組副字元線SWL爲 代表圖示出。副字元線SWL，係以偶數〇〜6及奇數1 〜7之合計8條副字元線交互配置於1個記憶區塊 MATO及MAT 1。如此則對1個主字元線，於其配列 方向分配8條副字元線，據此可使主字元線之節矩緩衝爲 1 / 8。 經濟部中央棣準局貝工消費合作杜印裝 (請先閲讀背面之注意事項再填寫本頁} 除掉主字元驅動器MWD鄰接之偶數〇〜6，及未圖 示之主字元線MW0之遠端側（字元驅動器之反對側）所 配置之奇數1〜7之外，配置於記憶區塊間之副字元驅動 器S W D 1等，係用於形成以其爲中心之左右記憶區塊 MAT 〇及MAT 1等之一對副字元線之選擇信號。如此 般藉由使副字元線之長度相對於主字元線之延長方向作分 割，則可減少1條副字元線所連接記憶格之數目，使記憶 格之選擇動作高速化。 如上述將副字元線區分爲偶數0〜6及奇數1〜7， 分別於記憶區塊兩側配置副字元驅動器S W D 〇、 SWD 1之構成，可配合記憶格之配置，使高密度配置之 副字元線SWL之實質節矩，於副字元驅動器SWD0、 SWD 1中緩和爲2倍，可對設於副字元驅動器SWD 0 、SWD1之驅動器SDRV，及其所對應之副字元線 本紙張尺度適用中國國家棣準（CNS ) A4规格（210X297公釐） -28- 經濟部中央標準局貝工消费合作社印装 A7 _ B7 五、發明説明（26 ) SWL等作有效佈線設計。驅動器S DRV，係藉主字元 線MWi與副字元選擇線FX1之邏輯積（AND)將副 字元線SWL設爲選擇/非選擇者。 構成X解碼器XDEC之閘電路AN3、 AN4等所 形成之選擇信號被供至主字元驅動器MWD。主字元驅動 器MWD，係由接受選擇信號之驅動器MDRVO、 MDRV i等構成，用於將各記憶區塊MATO、 ΜΑΤΙ中各4條副字元線0〜6 (1〜7)所對應之作 爲選擇信號之主字元線MW〇、MWi等驅動於選擇/非 選擇。設有副字元線選擇線FX i用於從4條副字元線〇 〜6或1〜7中選擇1條副字元線。副字元選擇線FX i ，係由FX0〜FX7等8條構成，以X解碼器XDEC 所含之閘電極AN1、 AN2等形成選擇信號。 介由主字元驅動器MWD所包含驅動器F D RV 〇等 ，偶數副字元選擇線FX0〜FX 6被供至偶數劑之副字 元驅動器SDRV0〜6，介由驅動器FDRV1等，奇 數副字元選擇線F X 1〜F X 7被供至奇數列之副字元驅 動器F D R V 1〜7。雖未特別限制，副字元選擇線 FX0〜FX7，於陣列周邊部係由和主字元線MW0等 相同之第2層金屬配線層M2形成。副字元選擇線F X 〇 〜FX7，係於副字元驅動器對應之部分分岐，在與相同 地由第2層金屬配線層M2構成之主字元線MW0〜 MW i呈交叉處，係由第3層金屬配線層M3構成’向與 主字元線正交之方向延伸而導入副字元驅動器之輸入。 本紙張尺度適用中國國家揉準（CNS >八4规格（210X297公釐） ........... - - 1 -i I In . 士^一---------- rj U3 、? (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 A7 B7五、發明説明（27 ) 圖11爲階層化字元驅動器方式對應之副字元驅動器 SDRV之一實施例之電路圖。於此實施例中，爲確保高 信賴性，副字元選擇線及主字元線，係由一對信號線構成 。即，一對構成之副字元選擇線之信號FXi B及FXi ，當信號FX i B爲內部高電壓VCH之Η位準時信號 FX i η成爲負電壓VNN之L位準，當信號FX i Β爲 電路接地電位VS S之L位準時信號FX i η設定爲內部 降壓電壓VD L之Η位準之實質互補信號。 副字元選擇線之信號F X i及F X i Β，係於副字元 驅動器所設分岐部因驅動器DV 1及DV 2分別反轉，而 設定成對應之副字元驅動器所對應副字元選擇線之信號 FX i Bn及FX i η。該分岐之副字元選擇線之信號 F X i η，係利用爲以下說明之副字元驅動器S D R V之 動作電壓。即，被選擇者設定爲內部高電壓VCH，非被 選擇者設定爲電路接地電位vss (〇v)。分岐之副字 元選擇線之信號FX i Β η，當信號FX i η爲非選擇之 接地電位Ο V時，係用於將副字元線SWL設定爲負電壓 V Ν Ν。 一對構成之字元線MW i Β Ρ及MW i ΒΝ，當主字 元線MW i Β P爲內部高電壓V CH之Η位準時，主字元 線MWi ΒΝ成爲內部降壓電壓VDL之Η位準，當主字 元線MW i Β Ρ爲接地電位V S S之L位準時，主字元線 MW i BN成爲內部負電壓VNN之L位準般地供給實質 同相之選擇/非選擇信號。 —II i ^^1 ·11 n an m am » n -I I- - ----In U3 ,1' (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國11家梯準（CNS ) Α4规格（210X297公釐） -30- 經濟部中央橾準局貝工消費合作社印製 A7 B7___ 五、發明説明（28 ) 藉由上述2種信號MWi BP及MWi BN ’可驅動 和圖6相同之P通道型輸出MOSFET Ml 4及N通 道型輸出MOSFET Ml 7，使副字元線設定爲 VCH與VNN之選擇/非選擇位準。但是，與圖6之電 路之不同點爲，動作電壓係由副字元選擇線FX i η供給 。因此，在副字之選擇線FX i η爲0V之非選擇位準， 主字元線之信號MWi ΒΡ及MWi ΒΝ爲選擇位準時’ 爲使副字元線SWL設爲非選擇之負電壓VNN而設有 MOSFET M18 及M19，於該MOSFET Ml 9之閘極供給有副字元選擇線FX i Bn之內部降壓 電壓VDL。如此，則當副字元選擇線FXi η爲0V之 非選擇位準，主字元線之信號MW i ΒΡ及MW i ΒΝ爲 選擇位準時，MOSFET M19成爲ON狀態，而使 副字元線SWL設定成負電壓VNN之非選擇位準。 MOSFET M15、M16 及M18，如上述般 係用於分擔施加在輸出MOSFET M14' M17及 Ml 9之閘極絕緣膜之電壓使其降低者’使上述各信號之 信號振幅縮小爲VNN〜VD L及V S S〜V CH之現象 之相乘作用，而可確保元件之高信賴性。 圖12爲副字元選擇線及主字元線之驅動用之驅動器 之一實施例之電路圖。如圖1 3之波形圖所示，驅動器 FDRV，係接受X解碼器XDEC形成之〇〜VDL之 小振幅之副字元選擇線FSXi ，而形成供至副字元選擇 線之信號FXi及FXiB。即，小振幅信號FSXi ， 本紙張尺度適用中困國家標準（CNS > A4规格（210X297公釐）_ y _ I I I— I - - - I .1 - ! I 1 n m 丁 言 {請先閲讀背面之注意事項再填寫本頁) A7 B7_·_ 五、發明説明（29 ) 係介由和圖6相同之位準轉換電路L S N及L S P分別轉 換成VNN〜VDL及0〜VCH之信號振幅，並介由設 於輸出部之驅動器D V 3及D V 4而輸出至副字元選擇線 F X i 及 F X i B。 — 主字元驅動器MDRV，係如圖1 3之波形圖所示， 接受X解碼器形成之於0〜V D L變化之小振幅之主字元 線選擇信號，而形成供至主字元線MWi BN及MWiB P之選擇/非選擇信號。即，小振幅信號XDEC，係介 由和圖6相同之位準轉換電路L SN及L S P分別轉換爲 VNN〜VDL及0〜VCH之信號振幅，並介由設於輸 出部之驅動器DV5及DV6而驅動主字元線MWi BN 及M W i B P者。 於此種階層字元方式，如上述般，在構成各驅動器之 輸出MOSFET設有電壓分擔用MOSFET，而且， 其信號振幅分爲P通道型MO S F E T側及N通道型 MO S F E T側用，以2個較小之信號振幅傳送，因此可 確保元件之高信賴性。 經濟部中央樣準局貝工消费合作社印製 圖1 4爲本發明之動態型RAM中之電源電路之另一 實施例之槪略方塊圖。此實施例之動態型RAM，係具多 數（圖中爲4個）記憶陣列M C A。該記憶陣列M C A， 當採取階層字元驅動方式時，係分別由後述之多數記憶區 塊構成。於此實施例中’相對於高電壓用充電泵電路 VPPG及負電壓用充電泵電路VBBG，設有多數定電 壓電路RGN及RG P。雖未特別限制’該定電壓電路 -32- {請先聞讀背面之注意事項再填寫本頁} 本紙張尺度逍用中國國家梂準（CNS ) A4規格（210X297公釐） B7 五、發明説明（30 ) RGN及RGP，係與多數構成之記憶陣列MCA —對一 對應設置多數個。於各記憶陣列MCA ’因電壓V CHS VNN爲相同，使VC Η及VNN呈對應而形成基準電壓 VRH及VRN之基準電壓產生電路RG F Ρ及RGF Ν 可用共同電路。 此構成中，可將定電壓電路RGP及RGN配置成近 接於作爲負載之記憶陣列MC Α之字元線選擇電路 XD E C與WD，可縮短其間之配線，降低電源阻抗之同 時’充電泵電路V P P G及V B B G及基準電壓產生電路 RGFP與RGFN可共用，故可縮小電路規模。充電泵 電路VP PG及VBBG形成之電壓，可事先形成絕對値 較大俾即使字元線於選擇狀態或非選擇狀態變化時產生電 壓變動時亦不會有問題，又，基準電壓產生電路’僅作爲 差動電路之參照電壓使用，幾乎未流通電流’故於多數電 路共同設置，即使其間之配線長較長亦大致不會有問題。 經濟部中央樣隼局貝工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 圖15爲階層化字元驅動器方式對應之副字元選擇線 用驅動器及副字元驅動器之另一實施例之電路圖。此實施 例中，係藉由1條主字元線MWi B及1條副字元選擇線 F X i B來選擇副字元線者，藉由1條副字元選擇線之主 字元線之構成，可減少配線數之同時’減少電路元件數。 相對於副字元選擇線及主字元線以1條構成，選擇/ 非選擇之信號位準，如圖1 6之波形所示，係設爲VNN 〜V C Η之較大信號振幅。在副字元選擇線之上述分岐部 ，設形成反轉信號之驅動器。該驅動器，係以VCH及 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X297公釐） 經濟部中央標準局另工消费合作社印«. A7 B7五、發明説明（31 ) VNN電壓動作，如圖1 6之波形圖所示，形成與信號 FX i Β η反轉之副字元選擇線FX i η，作爲副字元驅 動器之動作電壓。 於分岐部之驅動器，副字元選擇線F X i Β之信號， 係介由閘極供給有VD L之N通道型MO S F E T M2 1而傳至輸出負電壓VNN之N通道型之輸出 MOSFET M25之閘極，並介由閘極供給有接地電 位VS S之P通道型MOSFET M2 0傳至輸出高電 壓VCH之P通道型之輸出MOS F ET M2 2之閘極 。在P通道型輸出MOSFET M2 2與輸出端之間， 串接***閘極施加有V S S之P通道型MO S F E T M24，N通道型輸出MOSFET M25與輸出端之 間，設閘極施加有VDL之N通道型MOSFET Μ 2 4。 如上述般，即使副字元選擇線FX i Β設爲VCH及 VNN之較大信號振幅，但在構成驅動器之輸出 MOSFET M22及M25 ，和圖7同樣僅施加較小 之電壓，故可確保元件之高信賴性。 副字元驅動器係和驅動器一樣。但是，當主字元線 MWi B爲VNN之選擇位準，副字元選擇線FX i η爲 VNN之非選擇位準時，爲使副字元線SWL i設爲負電 壓VNN之非選擇位準，而設置閘極接有副字元選擇線 FXiBn 之MOSFET27，其 Η 位準（VCH)係 和上述同樣介由閘極施加有VD L之電壓分割用 • -II ,^1 —^n -.....I - - I- Γ - I - m i I (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度遑用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央標準局貝工消费合作杜印装 A7 B7 五、發明説明（32 ) MO S F E T傳至閘極而成ON狀態，使副字元線 SWL i設爲負電壓。此時，在與副字元線SWL i連接 之輸出端之間，串接閘極施加有VD L之電壓分割用 MOSFET M26。 — 驅動副字元選擇線FX i B或主字元線MWi B之驅 動器，係用於形成VNN〜VCH之輸出信號者，故爲利 用圖6所示字元驅動器者。 ’ 圖1 7爲基準電壓產生電路之一實施例之電路圖。此 實施例中，產生VCH及VNN對應之基準電壓VRN及 VRP。基準電壓產生電路，基準電壓產生電路係由：利 用雙極性電晶體之矽禁帶寬度（silicon-band-gap)之基準 電壓電路B G G，及使基準電壓電路形成之電壓轉換爲電 流信號之電壓電流轉換電路I VCON，及將該電流信號 利用於電流鏡電路以形成各基準電壓VRN及VRP之電 路構成。 雙極性電晶體T1及T2，其射極面積AE形成爲1與 8之比，將集極及基極共用連接，設定爲二極體形態，同 時，於射極介由1ΜΩ之高電阻流通相同電流，產生矽禁 帶寬度對應之差電壓，施加於8 8 ΚΩ之電阻上以產生定 電流。亦即，以差動MOSFET Q21及Q22構成 之差動放大電路控制供至上述高電阻之電壓，俾使電晶體 T 1之射極電壓與介由8 8 ΚΩ之電晶體T 2之射極電壓 相等。據此，可於上述高電阻產生1.26V之基準電壓 ----------.裝------訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家揉準（CNS ) A4規格（210X297公釐） -35- 經濟部中央標準局貝工消费合作社印装 A7 B7 五、發明説明（33 ) 上述電晶體T1及T2，係以P通道型MOSFET 之源極、汲極擴散領域爲射極，以其形成之η型井領域 nWE L L爲基極，以Ρ _型基板爲集極。集極與基極爲 共接，設定爲供至P —型基板之接地電位。產生於8 8 ΚΩ電阻上之差電壓，係對應與流通相同電流之上述高電 阻間之電阻値比而設爲1 . 2 6 V之電壓。 閘極供給有接地電位而作爲電阻元件作用之P通道型 MOSFET Q23，係構成起動電路。當VREF爲 0V，亦即在電晶體ΤΙ、 T2爲OFF狀態，差動 MOSFET Q21及Q22爲OFF狀態時乃能穩定 起見，由電晶體ΤΙ、T2，及差像放大電路構成之 BGG係用於設置上述起動電路而形成1.26V之基準 電壓者。 電壓電流轉換電路I VCON，係由差動 MOSFET Q24與Q25構成之差動電路及輸出 MOSFET Q26而構成電壓耦合器電路，使基準電 壓V R E F流經電阻R F而形成定電流。該定電流流經輸 出MOSFET Q26，故與閘極及源極共用之P通道 型MOSFET Q27、 Q30構成電流鏡電路，取出 由MOSFET Q27及Q30之汲極經電流轉換成之 基準電流。雖未特別限制，電阻R F形成之基準電壓 V R E F 〇，係利用爲後述之位準感測。 MOSFET Q27之汲極輸出之基準電流，係供 至源極接於充電泵電路VBBG所形成之一1.0V之基 本紙張尺度適用中國囷家棣準（CNS ) A4规格（210X297公釐） -36 - il u^i m 1^1 nn n^— i n n n^i HI In I <請先閲讀背面之注意事項再填寫本頁) 經濟部中央檫準局貝工消费合作社印装 A7 B7 五、發明説明（34 ) 板電壓VBB的N通道型MOSFET Q28及Q27 所形成之電流鏡電路，該輸出電流流經設於接地電位之間 之電阻RL1 ，以產生—〇 . 75V之基準電壓VRN。 於電阻R L 1，並接電容器C 3"以達電壓之穩定。 MOSFET Q30之汲極輸出之基準電流，係供 至由源極接於電路接地電位之N通道型MO S F E T Q 3 1及Q 3 2形成之電流鏡電路，流經該電流鏡電路之 基準電流，係供至源極接於充電泵電路V p p G所產生高 電壓VPP之P通道型MOSFET Q33及Q34， 於該輸出與內部電壓VDD (VDL)之間設電阻RL2 ，以VDD爲基準而形成約2.25V之基準電壓VRP 。電容器C 4係爲使基準電壓VR P穩定而設。 構成電流鏡電路之P通道型M〇 S F E T及N通道型 M〇 S F E T分別設定成相同之元件尺寸，以形成與電阻 RF所形成基準電壓爲相等之電流，則基準電壓VRP及 VRN可以下式（1 )及（2)表示。 VRP = VREFxRL 2/RF+VDD(VDL) ......(1 ) VRN — — VREFxRL 1/RF ...... (2) 如此般於上述實施例電路中，係利用矽禁帶寬度形成 基準電壓VREF，藉由電阻比RL2/RF、R L 1 / RF形成基準電壓VRP及VRN者，故即使使用製程變 動大之半導體電路形成之電路元件’上述電阻比不受其影 響，故可以高精度形成基準電壓VRP及VRN。 本紙張尺度適用中國國家標準（CNS ) A4规格（210x297公釐） -37- —--------裝-- (請先聞讀背面之注意事項再填寫本頁) 訂 A7 B7 五、發明説明（35 ) 圖18爲定電壓產生電路RGP之一實施例之電路圖 。此實施例中’差動放大電路由2個電路構成，差動 MOSFET Q40及Q41及可變電阻元件之間作用 之MOSFET Q44所構成之電路，係於形成動作電 流之MOSFET Q48之閘極常時施加VDL之定電 壓而常時地動作。即，爲使記憶體電路於待機狀態時之定 電壓產生電路本身之電流消費減少，於MO S F E T Q 4 8僅流通小電流。 爲對應於記憶體存取之字元線之選擇/非選擇動作之 切換，使具較大電流供給能力，藉由控制信號ACTH使 N通道型MOSFET Q47設爲ON狀態，俾於記憶 體存取時使由差動MOSFET Q4 2及Q4 3及作爲 可變電阻元件使用之MOSFET Q4 5所構成之定電 壓電路動作。該電路，當信號A C TH爲L位準之非動作 狀態時，係令P通道型MOSFET Q46爲〇N狀態 ，令作爲可變電阻元件使用之MOSFET Q45爲 0 F F狀態。 經濟部中央標準局貝工消费合作社印製 -- 1^ - ·- II 8— n'*JZ i^i HI n —i n ^^1 (請先聞讀背面之注意事項再填寫本頁)* aT Printed by the Central Consumer Bureau of the Ministry of Economic Affairs, Consumer Affairs Cooperative Cooperative Association Α7 Β7 V. Description of Invention (21) Therefore, the output signal of the CMO S converter circuit of the other party is set to the high level corresponding to the high voltage VCH. As a result, the P-channel MOSFET Q 2 1 is in the 0 F F state, so that a direct current does not flow through the CMO S converter circuit forming one of the L-level output signals N 4. The level conversion operation of the level conversion circuit LS Ν is almost the same as the above, so only the output signal N 1 of the gate circuit G 1 constituting the X decoder XD EC will be described below as the L level timing corresponding to the ground potential VS S Action. The P-channel type MO S F E T of the CMO S converter circuit supplied with one of the output signals N 1 is set to the 0 N state. The CMOS converter circuit of the other party is supplied with the inverted level signal, so the N-channel MOS F ET becomes ON. Due to the ON state of the P-channel type MO SF Ε T of the CMOS converter circuit of one side, the output signal N 2 becomes the level of the internal step-down voltage VD L, which makes the N-channel type of the CMO S converter circuit of the other side MO SF Ε Τ becomes ON. As a result, the output signal of the CMO S converter circuit of the other side is turned on because two N-channel type MO S F E T are turned on, and a negative voltage VNN is output. As a result, an output signal N 2 corresponding to the internal step-down voltage VD L can be formed, so that the N-channel type M 0 SF Ε Τ corresponding to the negative voltage VNN side becomes 0 FF state, so that the direct current does not flow through CMO S converter circuit on one side. FIG. 8 is a circuit diagram of another embodiment of the word line driver WD. In this embodiment, the X decoder is divided into two circuits. A four-word selection signal N1 is formed at the first decoder XDEC. The selection signal is a selection signal X 〇 formed by a second decoder (not shown). This paper size is applicable to China National Standard (CNS) A4 specification (210 × 297 mm) -24- (Please read the note on the back first Please fill in this page for further information.) _, 1T printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Invention Description (22) X01, X10 and XII are used to control the switching MOSFETs Ml 0 ~ Ml 3 for the corresponding ones Character drive WD i. The word driver WD i 'is represented by a circuit, and has both the level conversion function and the character driving function. "-P-channel output MOSFETs M3 and M4, N-channel MOSFETs M6 and M5. Drivers. The N-channel type output MOSFET M6. Is latched with the N-channel type MOSFET M 7 and has a level switching function. The MOSFET M7 is connected in series with an N-channel MOSFET M8 for withstand voltage relaxation, and the MOSFET M5 is provided with an internal step-down voltage V D L at the gate. The P-channel output MOSFET M3 is a level-switched P-channel MOSFET M2 with a latching configuration. The gate of the output MOSFET M3 is pre-charged at a high voltage by the P-channel MOSFET M1 controlled by the precharge signal WPH. VCH. At its input point, a selection signal N 5 is supplied through a switching MOSFET M10. FIG. 9 is a timing chart illustrating the operation of the character driver. When the precharge signal WPH is at the L level of the circuit ground potential GND, the P-channel MOSFET M1 is turned on, and the input terminal is precharged to a high voltage VCH. The MOSFET M3 is turned off due to the precharge operation, and at the same time, the gate potential N 3 of the N-channel output MOSFET M 6 is set to the level of VD L-VT through the MOSFET M 9 ′ MOSFET M8 in the ON state. As a result, this paper size applies to the Chinese national standard (CNS M4 specification (2〗 0X297) 嫠 -25- n n. I ϊ I nn I l · —,--I-mn I an DING J3 (Please read first Note on the back, please fill out this search again) A7 B7 V. Description of the invention (23) M 0 SFET M6 becomes ON state, making the word line Wi become the non-selection level of negative voltage VNN. Because of the ON state of MOSFET M6, The gate of the MO SFET M7 that is set to the latched state is supplied with a negative voltage VNN and becomes an FF state. Therefore, the through current can be prevented from flowing through the precharged MOSFET M1 that becomes the 0 N state, and the ON state is always used for voltage relaxation. The MOSFETs M9 and M8 and MOSFET M7 are connected in series. In the Ministry of Economic Affairs, the quasi bureau, the shellfisher, consumer cooperation, Du printed, because the X decoder operation, the first decoder XD EC 1 output signal N 1 becomes L level. After that, the MOSFET M10 is turned on because the selection signal X00 is at the Η level among the 4 word lines. Therefore, the selection signal N 5 at the input terminal may be at the L level. As a result, the output MOSFET M3 is turned off. The state is changed to the ON state, so that the word line Wi rises from a negative voltage VNN to a high voltage V CH Because of this voltage rise, MOSFET M7 becomes ON state, and the gate voltage N3 of MOSFET M6 decreases from VDL-VT to negative voltage VNN. Therefore, MOSFET M6 is set to OFF state, and the potential of word line Wi is fast. Rise to high voltage v C Η. For other non-selected word lines, the precharge voltage is maintained in the corresponding word driver. Therefore, the P-channel output MOSFET is turned OFF and the N-channel output MO SF Ε Τ is turned ON. The non-selection level of the negative voltage VNN is maintained. At the end of the selection operation of the word line Wi, the decoder signal χ〇〇 is set to the L level, and the MOSFET M10 is set to the OFF state. -26- (Please listen first (Please read the notes on the back and fill in this page again) This paper size is applicable to China Standard S (CNS) A4 (210X297 mm) Printed by A7 B7, Shellfish Consumer Cooperative, Central Samples Bureau, Ministry of Economic Affairs In addition, the output signal N 1 of the first decoder XDE C 1 is restored to the 之后 level. After that, the precharge signal WP Η becomes the L level, so that MO SF Ε Τ Μ 1 is turned ON. Therefore, the input terminal The voltage N 5 is precharged to a high voltage VCH. Because of this precharge action, P Channel type output MOSFET M3 OFF state, while the gate voltage of the N-channel MOSFET M6 \ 3 by MOSFET M8 set to VDL - Η limited level of VT. Due to the ON state of the MOSFET M6, the selection level (VCH) of the word line Wi rises to the negative voltage VNN corresponding to the non-selection level. In this configuration, the voltage applied to the output MOSFET M3 or M6 is limited as described above, so that high reliability of the device can be ensured. In this embodiment, for the first X decoder circuit XDE C, the word driver corresponding to the four word lines is shared. In this way, the number of MO S F E T necessary for one line can be reduced. In other words, the pitches of the word lines arranged at high density and the pitches of the X decoders forming the selection signal can be made consistent ', making high integration possible. Fig. 10 is a structural diagram of an embodiment when the present invention is applied to a hierarchical (divided character line) character driver. Hierarchical character lines refer to those that divide character lines into main character lines and sub-character lines, and connect the sub-character lines to the billion-character grid. In such a hierarchical character method, a high-resistance character line is made of a low-resistance metal wiring layer as a bottom layer to alleviate the wiring restriction of the metal wiring layer in the so-called character shunt method. With this type of segmented character line, a large memory capacity and a high accumulation can be achieved. The figure shows the relationship between the main character line and the auxiliary character line of the memory block. = ^^ 1 111. In. -Ii n ^ i I- 1 * ml -II n I ---- (Please first Read the notes on the reverse side and fill in this page) The paper size is in accordance with the Chinese National Ladder Standard (CMS) A4 specification (210X297 mm) -27- B7 V. Description of the invention (25) The outline structure. In the figure, two main character lines MW0 and MWi are represented. The main character lines MW0, MWi, etc. are selected / non-selected by each of the drivers MDRVO, MDRVi, etc. provided in the main character driver MWD. On one main word line MWO, a multi-array sub-word line SWL is provided in the extension direction. In the figure, three groups of sub-word lines SWL are representatively shown. The sub-word lines SWL are alternately arranged in a memory block MATO and MAT 1 with a total of 8 sub-word lines of an even number of 0 to 6 and an odd number of 1 to 7. In this way, for one main character line, eight sub-character lines are allocated in the direction of arrangement, so that the pitch of the main character line can be buffered to 1/8. Printed by the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China. Please read the precautions on the back before filling out this page} Remove the even number of the main character driver MWD adjacent to 0 ~ 6, and the main character line not shown In addition to the odd numbers 1 to 7 arranged on the far side of the MW0 (the opposite side of the character driver), the sub-character driver SWD 1 and the like arranged between the memory blocks are used to form the left and right memory areas centered on it. One of the blocks MAT 0 and MAT 1 selects the auxiliary character line. In this way, by dividing the length of the auxiliary character line with respect to the extension direction of the main character line, one auxiliary character line can be reduced. The number of connected memory cells speeds up the selection of memory cells. As described above, the sub-character lines are divided into even numbers 0 to 6 and odd numbers 1 to 7, and sub-letter drivers SWD are arranged on both sides of the memory block. The structure of SWD 1 can be matched with the configuration of the memory cell, so that the substantial pitch of the sub-word line SWL with a high density can be doubled in the sub-word drivers SWD0 and SWD 1, which can be set to the sub-word driver. Driver SDRV of SWD 0 and SWD1, and the corresponding auxiliary character line paper Zhang scale is applicable to China National Standards (CNS) A4 specification (210X297 mm) -28- Printed by Aijia Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _ B7 V. Description of the invention (26) SWL etc. for effective wiring design. Driver S DRV is formed by the logical product (AND) of the main character line MWi and the sub character selection line FX1, and the sub character line SWL is selected / non-selected. It is formed by the gate circuits AN3 and AN4 constituting the X decoder XDEC. The selection signal is supplied to the main character driver MWD. The main character driver MWD is composed of the drivers MDRVO, MDRV i, etc. that receive the selection signal, and is used to connect each of the four sub-word lines in each of the memory blocks MATO and ΜΑΙ. The main character lines MW0, MWi, etc., which correspond to 0 to 6 (1 to 7) as selection signals, are driven by selection / non-selection. A sub-word line selection line FX i is provided to select from 4 sub-word lines 〇 ~ 6 or 1 ~ 7 select one sub-character line. The sub-character selection line FX i is composed of 8 such as FX0 ~ FX7, and is formed by the gate electrodes AN1 and AN2 included in the X decoder XDEC. Signal. The driver FD RV 〇 included in the main character driver MWD, etc., the even sub-character selection lines FX0 to FX 6 The sub-character drivers SDRV0 to 6 supplied to the even-numbered agent, and the odd-numbered sub-character selection lines FX 1 to FX 7 are supplied to the odd-numbered sub-character drivers FDRV 1 to 7 via the driver FDRV1. Although not particularly limited The auxiliary character selection lines FX0 to FX7 are formed at the periphery of the array by the same second metal wiring layer M2 as the main character line MW0. The auxiliary character selection lines FX 0 to FX7 are connected to the auxiliary character driver. The corresponding part is divided at the intersection with the main word line MW0 ~ MWi which is formed by the second metal wiring layer M2 in the same way, and it is formed by the third metal wiring layer M3. It is orthogonal to the main word line The direction extends and the input of the sub-character driver is introduced. This paper size is applicable to Chinese national standard (CNS > 8 4 size (210X297 mm) ...........--1 -i I In. 士 ^ 一 -------- -rj U3,? (Please read the precautions on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 B7 V. Description of the invention (27) Figure 11 shows the correspondence of the hierarchical character drive method. A circuit diagram of one embodiment of the sub-character driver SDRV. In this embodiment, to ensure high reliability, the sub-character selection line and the main character line are composed of a pair of signal lines. The signal FXi B and FXi of the character selection line. When the signal FX i B is the level of the internal high voltage VCH, the signal FX i η becomes the L level of the negative voltage VNN. When the signal FX i Β is the circuit ground potential VS S The L-bit on-time signal FX i η is set to be a substantially complementary signal of the Η level of the internal step-down voltage VD L. The signals FX i and FX i Β of the sub-character selection line are connected to the sub-character driver of the sub-character driver. DV 1 and DV 2 are respectively inverted, and are set to the signals FX i Bn and FX i η of the corresponding sub-character selection line corresponding to the corresponding sub-character driver. The signal FX i η of the divided sub-character selection line is the operating voltage of the sub-character driver SDRV described below. That is, the selected person is set to the internal high voltage VCH, and the non-selected person is set to the circuit ground potential vss. (〇v). The signal FX i Β η of the auxiliary character selection line of the divergence is used to set the auxiliary character line SWL to a negative voltage V Ν Ν when the signal FX i η is a non-selected ground potential OV. When the main character line MW i Β P and MW i ΒΝ are at a level of the internal high voltage V CH, the main character line MWi ΒΝ becomes the voltage of the internal step-down voltage VDL. When the main word line MW i PB is at the L level of the ground potential VSS, the main word line MW i BN becomes the L level of the internal negative voltage VNN and supplies substantially in-phase selection / non-selection signals. —II i ^^ 1 · 11 n an m am »n -I I------ In U3, 1 '(Please read the precautions on the back before filling this page) This paper uses 11 Chinese ladders Standard (CNS) Α4 Specification (210X297 mm) -30- Printed by Shellfish Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs A7 B7___ V. Description of Invention 28) The two signals MWi BP and MWi BN ′ can drive the same P-channel output MOSFET Ml 4 and N-channel output MOSFET Ml 7 as shown in FIG. 6, so that the sub-word line is set to the choice of VCH and VNN / Non-selection level. However, the difference from the circuit of FIG. 6 is that the operating voltage is supplied from the sub-character selection line FX i η. Therefore, when the selection line FX i η of the auxiliary word is at the non-selection level of 0V, when the signals MWi ΒΡ and MWi ΒΝ of the main word line are the selection level, the sub-word line SWL is set to the non-selected negative voltage VNN. MOSFETs M18 and M19 are provided, and an internal step-down voltage VDL of the sub-character selection line FX i Bn is supplied to the gate of the MOSFET M19. In this way, when the sub-character selection line FXi η is at a non-selection level of 0V, and the signals of the main character line MW i ΒΡ and MW i ΒΝ are at the selection level, the MOSFET M19 is turned on and the sub-word line SWL is made. Set to the non-selection level of negative voltage VNN. The MOSFETs M15, M16, and M18 are used to share the voltage applied to the gate insulating films of the output MOSFETs M14 'M17 and M19 to reduce them as described above. The signal amplitudes of the above signals are reduced to VNN ~ VD L and The multiplication of the phenomena of VSS to V CH can ensure the high reliability of the device. Fig. 12 is a circuit diagram of an embodiment of a driver for driving the sub-character selection line and the main character line. As shown in the waveform diagram of FIG. 13, the driver FDRV accepts the sub-character selection lines FSXi with a small amplitude of 0 to VDL formed by the X decoder XDEC to form signals Fxi and FXiB for the sub-character selection lines. That is, the small-amplitude signal FSXi, this paper size applies to the national standard of difficulty (CNS > A4 specification (210X297mm) _ y _ III— I---I .1-! I 1 nm Ding Yan {Please read the back first Please note this page and fill in this page again) A7 B7_ · _ V. Description of the invention (29) It is converted to the signal amplitudes of VNN ~ VDL and 0 ~ VCH by the same level conversion circuit LSN and LSP as shown in Fig. 6, respectively. The drivers DV 3 and DV 4 provided in the output section output the sub-character selection lines FX i and FX i B. — The main character driver MDRV, as shown in the waveform diagram of Figure 13, accepts the main character line selection signal formed by the X decoder with a small amplitude ranging from 0 to VDL, and forms the main character line MWi BN. And MWiB P selection / non-selection signals. That is, the small-amplitude signal XDEC is converted into the signal amplitudes of VNN ~ VDL and 0 ~ VCH respectively by the same level conversion circuits L SN and LSP as those in FIG. 6, and is passed through the drivers DV5 and DV6 provided in the output section. Drive the main character lines MWi BN and MW i BP. In this hierarchical character method, as described above, the output MOSFETs constituting each driver are provided with a voltage sharing MOSFET, and the signal amplitude is divided into a P-channel type MO SFET side and an N-channel type MO SFET side. A small signal amplitude is transmitted, thus ensuring high reliability of the component. Printed by the Central Samples Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperative, Figure 14 is a schematic block diagram of another embodiment of the power supply circuit in the dynamic RAM of the present invention. The dynamic RAM of this embodiment has a majority (4 in the figure) of the memory array MCA. When the memory array MC A adopts the hierarchical character driving method, it is composed of a plurality of memory blocks described later. In this embodiment, a plurality of constant voltage circuits RGN and RG P are provided for the high voltage charge pump circuit VPPG and the negative voltage charge pump circuit VBBG. Although there is no special restriction, the constant voltage circuit-32- {Please read the precautions on the back before filling out this page} This paper size is in accordance with China National Standards (CNS) A4 specifications (210X297 mm) B7 V. Description of the invention (30) RGN and RGP are a plurality of memory arrays MCA which are configured in a one-to-one correspondence. Because the voltages V CHS VNN are the same in each memory array MCA ′, the reference voltage generating circuits RG F P and RGF NR that form the reference voltages VRH and VRN corresponding to VC and VNN can use a common circuit. In this configuration, the constant voltage circuits RGP and RGN can be arranged close to the word line selection circuits XD EC and WD of the memory array MC A as a load, which can shorten the wiring between them and reduce the power supply impedance while charging the circuit VPPG. And VBBG and reference voltage generating circuit RGFP and RGFN can be shared, so the circuit scale can be reduced. The voltage formed by the charge pump circuits VP PG and VBBG can be formed in advance to be absolutely large. Even if the character line changes in voltage when the selected state or non-selected state changes, there will be no problem. In addition, the reference voltage generating circuit is only It is used as a reference voltage for a differential circuit, because almost no current flows, so it is commonly installed in most circuits, and there is almost no problem even if the wiring length between them is long. Printed by the Central Sample Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative (please read the precautions on the back before filling out this page). Figure 15 shows the sub-character selection line driver and sub-character driver corresponding to the hierarchical character drive method. Circuit diagram of an embodiment. In this embodiment, a person who selects a sub-character line by using one main character line MWi B and a sub-character selection line FX i B, uses one of the main character lines of a sub-character selection line. The structure can reduce the number of wirings while reducing the number of circuit elements. Relative to the sub-character selection line and the main character line, which are composed of one, the selected / non-selected signal level, as shown in the waveform of FIG. 16, is set to a larger signal amplitude of VNN to V C Η. A driver for forming a reverse signal is provided in the branching portion of the sub-character selection line. This driver is based on the VCH and this paper standard and applies the Chinese National Standard (CNS) A4 specification (210X297 mm). It is printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7 V. Description of the invention (31) VNN voltage action, As shown in the waveform diagram of FIG. 16, a sub-character selection line FX i η that is inverted from the signal FX i Β η is formed as the operating voltage of the sub-character driver. The signal from the driver of the branch and the sub-character selection line FX i Β is transmitted through the gate to the N-channel type MO SFET M2 1 with VD L supplied to the N-channel type output MOSFET M25 that outputs negative voltage VNN. The gate is passed to the gate of the P-channel type output MOS F ET M2 2 which outputs the high voltage VCH through the P-channel type MOSFET M2 0 supplied with the ground potential VS S through the gate. Between the P-channel type output MOSFET M2 2 and the output terminal, a P-channel type MO SFET M24 with VSS applied to the gate and a N-channel type output MOSFET M25 between the gate and VDL are connected in series. Channel MOSFET Μ 2 4. As described above, even if the sub-character selection line FX i Β is set to a large signal amplitude of VCH and VNN, only small voltages are applied to the output MOSFETs M22 and M25 constituting the driver, as shown in FIG. 7, so the component can be ensured. High reliability. The sub-character driver is the same as the driver. However, when the main character line MWi B is the selection level of the VNN and the sub character selection line FX i η is the non-selection level of the VNN, the sub character line SWL i is set to the non-selection level of the negative voltage VNN. , And the MOSFET 27 with the sub-character selection line FXiBn connected to the gate is provided, and its VCH level is the same as that described above for the voltage division of VD L applied through the gate • -II, ^ 1 — ^ n-. .... I--I- Γ-I-mi I (Please read the precautions on the back before filling out this page) This paper adopts Chinese National Standard (CNS) A4 (210X297 mm) Central Standard of the Ministry of Economic Affairs Local shellfisher consumer cooperation Du printed A7 B7 V. Description of the invention (32) The MO SFET is transferred to the gate and turned ON, so that the sub word line SWL i is set to a negative voltage. At this time, between the output terminals connected to the sub-word line SWL i, a voltage division MOSFET M26 to which VD L is applied in series is connected in series. — The driver that drives the sub-character selection line FX i B or the main character line MWi B is used to form the output signals of VNN to VCH. Therefore, the character driver shown in FIG. 6 is used. FIG. 17 is a circuit diagram of an embodiment of a reference voltage generating circuit. In this embodiment, the reference voltages VRN and VRP corresponding to VCH and VNN are generated. A reference voltage generating circuit is composed of: a reference voltage circuit BGG using a silicon-band-gap of a bipolar transistor, and a voltage current that converts a voltage formed by the reference voltage circuit into a current signal The conversion circuit I VCON is configured by using the current signal in a current mirror circuit to form each of the reference voltages VRN and VRP. For the bipolar transistors T1 and T2, the emitter area AE is formed as a ratio of 1 to 8. The collector and the base are connected in common, and the diode shape is set. At the same time, the emitter has the same high resistance through 1MΩ. The current generates a differential voltage corresponding to the silicon forbidden band width, and is applied to a 88 KΩ resistor to generate a constant current. That is, a differential amplifier circuit composed of differential MOSFETs Q21 and Q22 controls the voltage supplied to the above-mentioned high resistance, so that the emitter voltage of transistor T 1 and the emitter voltage of transistor T 2 through 8 8 κΩ equal. Based on this, a reference voltage of 1.26V can be generated at the above-mentioned high resistance ----------. Install -------- order (please read the precautions on the back before filling this page) This paper size 逋Printed in China National Standard (CNS) A4 (210X297 mm) -35- Printed by Aigong Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs A7 B7 V. Description of the invention (33) The above-mentioned transistors T1 and T2 are P-channel type The source and drain diffusion areas of the MOSFET are emitters, the nWE LL area formed by the n-type wells is used as the base, and the P_-type substrate is used as the collector. The collector and base are connected in common and set to the ground potential supplied to the P-type substrate. The difference voltage generated in the 88 KΩ resistor is a voltage of 1.26 V corresponding to the resistance ratio between the above-mentioned high resistances flowing the same current. The gate is supplied with a ground potential and acts as a resistive element. The P-channel MOSFET Q23 constitutes a start-up circuit. When VREF is 0V, that is, when the transistors T1 and T2 are in the OFF state and the differential MOSFETs Q21 and Q22 are in the OFF state, it can be stable. The BGG composed of the transistors T1, T2, and the differential amplifier circuit is used. Those who set the starting circuit to form a reference voltage of 1.26V. The voltage-current conversion circuit I VCON is a voltage coupler circuit composed of a differential circuit composed of differential MOSFETs Q24 and Q25 and an output MOSFET Q26. The reference voltage V R E F flows through a resistor R F to form a constant current. This constant current flows through the output MOSFET Q26, so the P-channel MOSFETs Q27 and Q30 shared with the gate and source constitute a current mirror circuit, and the reference current converted from the drains of the MOSFETs Q27 and Q30 through current is taken out. Although not particularly limited, the reference voltage V R E F 0 formed by the resistor R F is used for level sensing described later. The reference current of the drain output of MOSFET Q27 is a basic paper size of 1.0V formed by the source connected to the charge pump circuit VBBG. Applicable to China National Standard (CNS) A4 (210X297 mm) -36- il u ^ im 1 ^ 1 nn n ^ — innn ^ i HI In I < Please read the notes on the back before filling out this page) Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 34) A current mirror circuit formed by N-channel MOSFETs Q28 and Q27 with a plate voltage VBB, and the output current flows through a resistor RL1 set between ground potentials to generate a reference voltage VRN of -0.75V. Connect resistor R L 1 and capacitor C 3 in parallel to achieve voltage stability. The reference current output from the drain of MOSFET Q30 is supplied to a current mirror circuit formed by N-channel MO SFETs Q 3 1 and Q 3 2 whose source is connected to the circuit ground potential. The reference current flowing through the current mirror circuit is P-channel MOSFETs Q33 and Q34 supplied to the source connected to the high-voltage VPP generated by the charge pump circuit V pp G. A resistor RL2 is set between the output and the internal voltage VDD (VDL), and approximately 2.25 is formed based on VDD. The reference voltage VRP of V. The capacitor C 4 is provided to stabilize the reference voltage VR P. The P-channel MMOSFET and N-channel MMOSFET constituting the current mirror circuit are respectively set to the same element size to form a current equal to the reference voltage formed by the resistor RF, then the reference voltages VRP and VRN can be expressed as follows ( 1) and (2). VRP = VREFxRL 2 / RF + VDD (VDL) ...... (1) VRN — — VREFxRL 1 / RF ...... (2) As in the circuit of the above embodiment, a silicon band gap is used The width forms the reference voltage VREF and the resistance ratios RL2 / RF and RL 1 / RF form the reference voltages VRP and VRN. Therefore, even if a circuit element is formed using a semiconductor circuit with a large process variation, the above-mentioned resistance ratio is not affected by it, so it can be The reference voltages VRP and VRN are formed with high accuracy. This paper size is applicable to China National Standard (CNS) A4 specification (210x297 mm) -37- —-------- install-(Please read the precautions on the back before filling this page) Order A7 B7 5 Explanation of the invention (35) FIG. 18 is a circuit diagram of an embodiment of the constant voltage generating circuit RGP. In this embodiment, the 'differential amplifier circuit is composed of two circuits. The circuit composed of the differential MOSFETs Q40 and Q41 and the MOSFET Q44 acting between the variable resistance elements is applied to the gate of the MOSFET Q48 which forms the operating current. The constant voltage of VDL operates constantly. That is, in order to reduce the current consumption of the constant voltage generating circuit itself when the memory circuit is in the standby state, only a small current flows in the MO S F E T Q 4 8. In order to switch the selection / non-selection of the word line corresponding to the memory access, it has a large current supply capacity. The N-channel MOSFET Q47 is set to the ON state by the control signal ACTH. At the same time, a constant voltage circuit composed of differential MOSFETs Q4 2 and Q4 3 and a MOSFET Q4 5 used as a variable resistance element is operated. In this circuit, when the signal A C TH is at the L-level non-operation state, the P-channel MOSFET Q46 is set to the ON state, and the MOSFET Q45 used as the variable resistance element is set to the 0 F F state. Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs-1 ^-·-II 8— n '* JZ i ^ i HI n —i n ^^ 1 (Please read the precautions on the back before filling this page)

圖1 9爲定電壓產生電路RGN之一實施例，之電路圖 。此實施例中，同樣地差動放大電路係由2個電路構成。 由差動MOSFET Q50及Q51及作爲可變電阻元 件之MOSFET Q52構成之電路，係於形成動作電 流之MOSFET Q43之閘極常時施加VSS之接地 電位而使常時動作。即，爲縮小記憶體電路於待機狀態時 之定電壓產生電路本身之電流消費，而使MO S F E T 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公兼） 經濟部中央標準局負工消費合作社印装 A7 B7 五、發明説明（36 ) Q 5 3僅流通小電流》 爲對應於記憶體存取之字元線之選擇/非選擇動作之 切換+，使具較大電流供給能力，藉由控制信號A C TN之 L位準使P通道型MOSFET Q58設爲〇N狀態， 俾於記憶體存取時使由差動MOSFET Q54與 Q4 4及作爲可變電阻元件使用之MOS F ET Q 5 6 所構成之定電壓電路動作。該電路，當信號A C TN爲Η 位準之非動作狀態時，係令Ν通道型Μ 0 S F Ε Τ Q 5 7爲ON狀態，令作爲可變電阻元件使用之 MOSFET Q56爲OFF狀態。 圖2 0爲VB B用之充電泵電路7之一實施例之電路 圖。此實施例中，雖未特別限制，但可由P通道型 MOSFET Q59〜Q66構成。該P通道型 MO S F Ε T係形成於N型井領域。因此可與形成有記憶 格之P型井領域作電氣分離，於充電泵動作中，於N型井 領域會產生少數載子，故對形成於P型井領域之記憶格不 會有任何影響。 利用MOS容量形成之電容器C13及藉MOSFE T Q6 1及6 3產生負電壓VBB之泵激電路之基本電 路被形成。電容器C14及MOSFET Q62及 Q 6 4爲同樣之基本電路，其輸入之脈衝0 S C及 0 S C B互相具有主動位準不重合之逆相關係，對應於輸 入脈衝交互動作以進行效率良好之充電泵動作。 MOSFET Q6 1及Q6 3基本上爲二極體形態 m' n^i i I 11 n^i k —^n In ml 一eJ (讀先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -39- 經濟部中央標準局負工消费合作杜印製 A7 B7__— 一 五、發明説明（37 ) ，如此則僅產生臨界値電壓分之位準損失。當脈衝信號 OSC之Η位準爲3.3V之低電壓時，實質上不動作。 因此，著眼於當輸入脈衝OSC爲L位準時， MOSFET Q61設爲ON狀態即可之情況，設置可 形成與輸入脈衝爲同樣脈衝之換流器電路N1〇及電容器 C 1 1及開關MOSFET Q59，以形成負電壓之控 制電壓。如此，則在無位準損失狀態下，可將電容器 C 1 3之負電位傳至基板電壓VB B側。當藉另一方之輸 入脈衝OSCB形成負電壓時，MOSFET Q59爲 ON狀態，以進行電容器Cl 1之充電。電容器Cl 1爲 可形成MOSFET Q61之控制電壓之足夠之小尺寸 電容器。 MOSFET Q63，因接受在深度閘極（通道部 分）接受另一方之輸入脈衝〇 S C B之驅動用換流器電路 N 1 3之Η位準之輸入信號而於較早之時序被設爲0 F F 狀態，使基板電位之放電效率較佳。同樣地，於 MOSFET Q6 1之深度閘極，因供給有驅動用換流 器電路N 1 2之輸出信號，當電容器C 1 3充電時，使 MOSFET Q61於較早時序成爲OFF狀態，使基 板電位V B B之漏電最小，供至另一方輸入脈衝0 S C B 對應之MOSFET Q6 2之閘極之控制電壓， MOSFET Q6 4及Q6 2之深度閘極電壓亦使用， 根據進行同樣動作之換流器電路N 1 3及電容器C 1 4形 成之脈衝信號及輸入脈衝0 S C而形成之脈衝信號。 裝------訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -40- 經濟部中央樣準局員工消费合作社印裝 B7____五、發明説明（38 ) 設有MOSFET Q65 (Q66)以使 MOSFET Q59及Q63(Q60及Q64)之鬧 極電壓於較早之時序放電，該MOSFET Q 6 5 (Q 6 6 )，其閘極與汲極共同連接成二極體形態’同時 ，於深度閘極供給用於接受本身之輸入脈衝0 s c (OSCB)之驅動用換流器電器N12 (N13)之輸 出信號，如據以使MOSFET Q63 (Q64)作互 補之開關控制。如此則當響應於輸入脈衝0 s c (OSCB)，驅動用換流器電路N1 2 (N1 3)之輸 出信號變化爲L位準時，可使MOSFET Q 6 3 (Q 6 4 )更早由ON狀態切換爲OF F狀態’故可使基 板電位有效放電爲負電壓。 圖21爲形成供至VBB用之充電泵電路7之振盪脈 衝之振盪電路6之一實施例之電路圖。此實施例中’於構 成CMOS換流器電路之P通道型MOS FET Q6 3 及N通道型MO S FET Q70分別串接作爲電阻元件 之P通道型MOSFET Q68及N通道型 MOSFET Q69，以構成次段之CMOS換流器電 路之輸入容量及時間常數電路俾進行信號延遲。將該 CMOS換流器電路之奇數個（圖中爲5個）縱向連接構 成環形振盪器。 爲使環形振盪器間歇性地動作，換言之，當基板電壓 VBB到達所要之負電壓（_1.0V左右）時使振盪電 路之動作停止以圖基板電壓V B B之穩定化及低消費電力 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家梯準（CNS ) A4规格（210X297公釐） -41 - A7 B7 經濟部中央樣準局只工消费合作社印裂 五 、發明説明（39 ) 1 1 化 而 設 有 控制電 路。信號D E TA爲後述說明之位準 感 測 1 1 I 器 所 形 成 之信號 ，當判斷基板電壓VB B到達所要電 位 時 1 1 I 設 定 爲 L 位準。 因信號D E TA之L位準，使通過換 流 器 y—s. 請 1 1 N 1 5 及 N 1 6 之輸出信號成爲L位準，使設於構成 環 形 先 閲 讀 1 1 振 盪 器 最 終段之 CMO S換流器電路上之作爲電阻元 件 之 背 面 I 1 N 通 道 型 Μ 0 S FET設爲OFF狀態，同時，使設 於 輸 注 意 -dr 1 I 出 端 之 Ρ 通道型 MOS FE 丁設爲ON狀態，強制地 使 最 ψ 項 再 1 1 終 段 輸 出 固定爲 Η位準。即，使閘電路G 1及G2之 輸 出 填 寫 本 裝 爲 Η 位 準 ，使閘 電路G 3之輸出信號爲L位準，使振 盪 脈 頁 1 1 衝 0 S C 爲L位 準，使振盪脈衝0 S C Β固定爲Η位準 . 〇 1 信 號 V Β 0 S C SW，當記憶體於待機狀態時， 係 爲 1 I Η 位 準 之 信號， 因信號VBOS C SW之Η位準，閘 電 路 1 訂 | G 1 關 閉 聞極， 閘電路G 2導通，取代環形振盪器所 形 成 1 1 較 高 頻 y 而以內 藏之自激再生定時器用之振盪脈衝 1 1 S L 0 S C作爲 供至充電泵電路之振盪脈衝0 S C、 1 1 〇 S C B 使用。 即使於如此低頻之充電泵電路動作中 因 I 信 號 D E Τ Α之 L位準，閘電路G 2開關閘極使振盪 脈 衝 1 1 0 S C 爲 L位準 ，使振盪脈衝0 S C Β固定爲Η位準。 1 圖 2 2爲V Β Β用之位準感測器8之一實施例之 電 路 1 1 圖 0 藉 閘 、源極 間施加定電壓VRE F 0之Ν通道型 1 | Μ 〇 S F E T Q 7 2形成定電流，並據以由電流鏡 電 路 1 I 形成 基 準. 電流i 1。於電流路徑串接多數個Ν通道型 1 I Μ 0 S F E T以 供給基板電壓VB Β。多數個串接之 1 Μ 0 S F E T， 設有調整用端子，俾作於元件之製程 變 動 1 1 1 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -42- 經濟部中央標隼局貝工消費合作社印装 A7 B7 五、發明説明（40 ) 調整。亦即，當基板電壓VBB爲一1.〇時，使流經串 接MOSFET之電流i 2與電流i 1取得平衡。即，使 MOSFET Q76之源極電位與接地電位一致，以進 行流經MOSFET Q76之電流i 2與電流i 1之平 衡調整。爲使基準電流i 1之調整爲可能，於N通道型電 流鏡電路串接2個MOSFET Q73及Q74，藉選 擇性使源極與汲極短路來調整電流鏡之電流比。 當基板電壓V B B之絕對値小於設定電壓時， MOSFET Q 7 6之源極電位成爲較接地電位高，具 i 2 > 1 1之關係。如此則，與流通基準電流i 1之P通 道型MOSFET Q76並接之P通道型MOSFET Q 7 7未流通電流，與流通有電流i 1所對應電流之N 通道型MOSFET Q78間之電流差對應地使電壓 v s設爲L位準'該L位準之信號v s，經由 MOSFET Q68〜Q71構成之CMOS換流器電 路放大，再經換流器電路及閘電路G 4而作爲感測輸出 D E T A。 因感測輸出D E TA之Η位準使與MO S F E T Q 7 8呈並接形態形成電流路徑，並使信號ν s更朝L位 準側下降。當基板電位V Β Β之絕對値大於所要使用電壓 時，電流i 2> i 1，該電流差分流經Ρ通道型 MOSFET Q77，使電壓vs上昇至Η位準側。當 電位ν s大於CMO S換流器電路之邏輯臨界値時，感測 輸出D Ε ΤΑ變爲L位準，回復至使電壓ν s朝L位準側 ^1 ' n —I- ·1^— ^1» » - - In 1-: - - τ» -'s (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國囷家梯準（CNS ) A4規格（210X297公釐） -43- 經濟部中央標準局貝工消费合作杜印装 A7 B7__ 五、發明説明（41 ) 下降，N通道型MOSFET成OFF狀態使電壓v s急 速上昇至Η位準。藉由此種回授電路使CMO S換流器電 路之位準判斷具磁滯特性。因此種磁滞特性可控制使振盪 電路之間歇動作穩定之同時，使基板電壓VB Β穩定於設 定値之10%範圍內。 信號S ΕΤΒ爲電源投入後暫時爲Η位準之信號，因 信號S Ε Τ Β之Η位準強制使感測檢出D Ε ΤΑ爲Η位準 ，以起動振盪電路。電壓V S S或V S Ρ，係於判斷電壓 ν s之Η位準/L位準之CMOS換流器電路等在低消費 電流動作時作爲偏壓使用。 圖2 3爲VP P用之充電泵電路2之一實施例之電路 圖。此實施例中，爲使不受外部端子供給之電源電壓變動 之影響，而產生穩定之高電壓VP P，以內部降壓電壓 VD L作爲動作電壓。當振盪脈衝0 S CH爲Η位準時， 對電容器C8、 C9、及C10充電直至內部降壓電壓 VD L爲止。充電時，因電容器C 7所形成昇壓電壓充電 用之M〇 S F Ε T被設爲ON狀態，故可在沒有臨界値電 壓之位準損失狀態下進行VD L之充電電壓。 當振盪脈衝0 S CH變爲L位準時，對電容器C 7充 電之同時，電容器C10產生2VDL之昇壓電壓。因 MOSFET Q71及Q72構成之CMOS換流器電 路之動作電壓被設爲電容器C 9所形成之2 VD L之昇壓 電壓，於電容器C 8供給有該2VD L之電壓，故該 2VDL之昇壓電壓形成3VDL之昇壓電壓VPP/使 1^1- n 1^1 In HI an - HI n I an (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） -44- 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（42 ) 輸出用MO S F E T成爲〇 N狀態。如此則，電容器 C 1 0所形成2 VD L之昇壓電壓在沒有位準損失狀態下 作爲昇壓電壓V P P輸出。 因內部降壓電壓VDL爲約1 . 5V，上述實施例中 ，充電泵電路可形成最大約3 V之昇壓電壓V P P。此實 施例中’昇壓電壓VPP爲2.6V即可，故藉後述之振 盪電路之間歇動作來產生2 . 6 V之昇壓電壓VPP。 圖2 4爲VP P用振盪電路1之一實施例之電路圖。 此實施例之振盪電路1 ，係使用和上述VBB用振盪電路 6實質相同之電路。不同點爲，對應於充電泵電路使振盪 脈衝OSCH僅輸出1個脈衝。Figure 19 is a circuit diagram of an embodiment of the constant voltage generating circuit RGN. In this embodiment, similarly, the differential amplifier circuit is composed of two circuits. A circuit composed of differential MOSFETs Q50 and Q51 and a MOSFET Q52 as a variable resistance element is a circuit in which the gate of the MOSFET Q43 that forms an operating current is always applied with the ground potential of VSS to operate normally. That is, in order to reduce the current consumption of the constant voltage generating circuit itself when the memory circuit is in the standby state, the paper size of the MO SFET is applied to the Chinese National Standard (CNS) A4 specification (210X297). Cooperative printed A7 B7 V. Description of the invention (36) Q 5 3 Only small current flows "is the switching of the selection / non-selection action corresponding to the character line accessed by the memory +, so that it has a larger current supply capacity. The P level MOSFET Q58 is set to ON state by the L level of the control signal AC TN. When the memory is accessed, the differential MOSFETs Q54 and Q4 are used, and the MOS F ET Q 5 is used as a variable resistance element. 6 The constant voltage circuit constituted operates. In this circuit, when the signal A C TN is in a non-operation state of Η level, the N channel type M 0 S F E T Q 5 7 is turned on, and the MOSFET Q56 used as a variable resistance element is turned off. Fig. 20 is a circuit diagram of an embodiment of the charge pump circuit 7 for VB B. In this embodiment, although not particularly limited, it may be constituted by P-channel MOSFETs Q59 to Q66. The P-channel type MO S F ET system is formed in the field of N-type wells. Therefore, it can be electrically separated from the P-well area where the memory grid is formed. In the operation of the charge pump, a few carriers will be generated in the N-well area, so it will not have any impact on the memory cells formed in the P-well area. A basic circuit of a capacitor C13 formed by using a MOS capacity and a pumping circuit that generates a negative voltage VBB by using MOSFE T Q6 1 and 63 is formed. Capacitor C14 and MOSFET Q62 and Q 6 4 are the same basic circuit. The input pulses 0 SC and 0 SCB have an inverse relationship between the active levels and do not coincide with each other. They correspond to the input pulse interaction to perform a highly efficient charge pump operation. . MOSFETs Q6 1 and Q6 3 are basically in the form of diodes m 'n ^ ii I 11 n ^ ik — ^ n In ml one eJ (read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specification (210X297 mm) -39- Duty printing of A7 B7 by the Central Bureau of Standards, Ministry of Economic Affairs, A7 B7 __— 15. Description of the invention (37), so only the level loss of the critical voltage is generated. When the high level of the pulse signal OSC is a low voltage of 3.3V, it does not substantially operate. Therefore, focusing on the case where the input pulse OSC is at the L level, the MOSFET Q61 can be set to the ON state, and the inverter circuit N10, the capacitor C 1 1 and the switching MOSFET Q59, which can form the same pulse as the input pulse, are set. To form a negative control voltage. In this way, in the state of no level loss, the negative potential of the capacitor C 1 3 can be transmitted to the substrate voltage VB B side. When a negative voltage is formed by the input pulse OSCB of the other party, the MOSFET Q59 is turned on to charge the capacitor Cl1. The capacitor Cl 1 is a capacitor of a small enough size to form the control voltage of the MOSFET Q61. MOSFET Q63 is set to 0 FF state at an earlier timing because it accepts the input signal from the other side at the deep gate (channel part). SCB's drive inverter circuit N 1 3 So that the discharge efficiency of the substrate potential is better. Similarly, the deep gate of MOSFET Q6 1 is supplied with the output signal of the drive converter circuit N 1 2. When the capacitor C 1 3 is charged, the MOSFET Q61 is turned off at an earlier timing and the substrate potential is The leakage current of VBB is the smallest, and it is supplied to the other side. The control voltage of the gate of MOSFET Q6 2 corresponding to the input pulse 0 SCB, and the deep gate voltage of MOSFET Q6 4 and Q6 2 are also used. According to the inverter circuit N 1 that performs the same operation 3 and the capacitor C 1 4 and the pulse signal formed by the input pulse 0 SC. Packing ------ order (please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) Cooperative printed B7____V. Description of the invention (38) MOSFET Q65 (Q66) is provided to discharge the alarm voltage of MOSFETs Q59 and Q63 (Q60 and Q64) at an earlier timing. The MOSFET Q 6 5 (Q 6 6 ), The gate and the drain are connected together to form a diode, and at the same time, the deep gate is supplied with the output signal of the drive inverter device N12 (N13) for receiving its own input pulse 0 sc (OSCB), For example, the MOSFET Q63 (Q64) is used for complementary switching control. In this way, when the output signal of the drive inverter circuit N1 2 (N1 3) changes to the L level in response to the input pulse 0 sc (OSCB), the MOSFET Q 6 3 (Q 6 4) can be turned ON earlier. By switching to the OF F state, the substrate potential can be effectively discharged to a negative voltage. Fig. 21 is a circuit diagram of an embodiment of an oscillating circuit 6 forming an oscillating pulse of a charge pump circuit 7 for VBB. In this embodiment, the P-channel MOS FET Q6 3 and the N-channel MO S FET Q70 constituting the CMOS inverter circuit are connected in series with a P-channel MOSFET Q68 and an N-channel MOSFET Q69 as resistive elements, respectively, to form a secondary circuit. The input capacity and time constant circuit of the CMOS inverter circuit of the segment perform signal delay. An odd number (5 in the figure) of the CMOS inverter circuit is connected vertically to form a ring oscillator. In order to make the ring oscillator operate intermittently, in other words, when the substrate voltage VBB reaches the required negative voltage (about 1.0V), the operation of the oscillation circuit is stopped to stabilize the substrate voltage VBB and low power consumption (please listen first Read the notes on the back and fill in this page again.) This paper size is applicable to China National Standard for Ladder (CNS) A4 (210X297 mm) -41-A7 B7 The Central Procurement Bureau of the Ministry of Economic Affairs only works with consumer cooperatives. 39) The control circuit is provided. The signal D E TA is a signal formed by the level sensing 1 1 I device described later. When it is judged that the substrate voltage VB B reaches the desired level, the 1 1 I is set to the L level. Due to the L level of the signal DE TA, the output signals passing through the inverter y-s. Please make the 1 1 N 1 5 and N 1 6 output signals to the L level. The back side of the CMO S inverter circuit as a resistance element I 1 N channel type M 0 S FET is set to OFF state, and at the same time, the P channel type MOS FE set at the output end of -dr 1 I is set to ON. State, forcing the most ψ term to 1 1 and the final stage output to be fixed at the Η level. That is, make the output of the gate circuits G 1 and G2 fill in the Η level, make the output signal of the gate circuit G 3 be the L level, make the oscillation pulse page 1 1 punch 0 SC, and make the oscillation pulse 0. SC Β is fixed at the Η level. 〇1 signal V Β 0 SC SW, when the memory is in the standby state, it is a 1 I Η level signal. Because of the high level of the signal VBOS C SW, the gate circuit 1 is ordered | G 1 turns off the sense electrode, and the gate circuit G 2 turns on, instead of the ring oscillator 1 1 forming a higher frequency y and using the built-in self-excited regeneration timer oscillation pulse 1 1 SL 0 SC as the oscillation pulse for the charge pump circuit 0 SC, 1 1 〇 SCB is used. Even in such a low-frequency charge pump circuit operation, due to the L level of the I signal DE T Α, the gate of the gate circuit G 2 switches the oscillation pulse 1 1 0 SC to the L level, and the oscillation pulse 0 SC Β is fixed at the Η position. quasi. 1 Figure 2 2 is a circuit of an embodiment of the level sensor 8 for V Β Β 1 1 Figure 0 N-channel type 1 | 〇 SFETQ 7 2 formed by applying a constant voltage VRE F 0 between the gate and the source Constant current, and based on the current mirror circuit 1 I to form a reference. Current i 1. A plurality of N-channel type 1 I M 0 S F E T are connected in series to the current path to supply the substrate voltage VB Β. Most of the 1 M 0 SFETs connected in series are provided with adjustment terminals, which are used to change the process of the components. 1 1 1 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -42- Central standard of the Ministry of Economic Affairs Printed A7 B7 of Beihai Shellfish Consumer Cooperatives 5. Description of invention (40) Adjustment. That is, when the substrate voltage VBB is -1.0, the current i 2 and the current i 1 flowing through the series MOSFET are balanced. That is, the source potential of the MOSFET Q76 is made to be the same as the ground potential, so that the current i 2 and the current i 1 flowing through the MOSFET Q76 are adjusted in balance. In order to make the adjustment of the reference current i 1 possible, two MOSFETs Q73 and Q74 are connected in series to the N-channel current mirror circuit, and the current ratio of the current mirror is adjusted by selectively shorting the source and the drain. When the absolute voltage of the substrate voltage V B B is smaller than the set voltage, the source potential of the MOSFET Q 7 6 becomes higher than the ground potential, and has a relationship of i 2 > 1 1. In this way, the P-channel MOSFET Q76 connected in parallel with the P-channel MOSFET Q76 flowing the reference current i 1 has no current flowing, and corresponds to the current difference between the N-channel MOSFET Q78 flowing the current corresponding to the current i 1. The voltage vs is set to the L level. The signal V of the L level is amplified by a CMOS inverter circuit composed of MOSFETs Q68 to Q71, and then passed through the inverter circuit and the gate circuit G 4 as a sensing output DETA. Due to the high level of the sensing output D E TA, a current path is formed in parallel with MO S F E T Q 7 8, and the signal ν s is further decreased toward the L level side. When the absolute potential of the substrate potential V Β Β is greater than the voltage to be used, the current i 2 > i 1, the current differentially flows through the P-channel MOSFET Q77, so that the voltage vs rises to the Η level side. When the potential ν s is greater than the logic threshold C of the CMO S converter circuit, the sensing output D Ε ΤΑ becomes the L level and returns to the voltage ν s toward the L level side ^ 1 'n —I- · 1 ^ — ^ 1 »»--In 1-:--τ »-'s (Please read the precautions on the back before filling out this page) This paper size is applicable to China's Standards (CNS) A4 (210X297 mm) -43- The Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperation, Du printed equipment A7 B7__ V. Description of the invention (41) The N-channel MOSFET is turned off, causing the voltage vs. the voltage to rise rapidly to the high level. By using this feedback circuit, the level judgment of the CMO S inverter circuit has hysteresis characteristics. Therefore, the hysteresis characteristic can be controlled to stabilize the intermittent operation of the oscillating circuit and stabilize the substrate voltage VB Β within a range of 10% of the set value. The signal S ETB is a signal that is temporarily at a high level after the power is turned on. Because the level of the signal S Ε Τ Β forces the detection to detect that D Ε Α is at a high level to start the oscillation circuit. The voltage V S S or V S P is used as a bias voltage when a low-current consumption CMOS inverter circuit is used to determine the level of the voltage ν s / L level. Fig. 23 is a circuit diagram of an embodiment of the charge pump circuit 2 for VPP. In this embodiment, in order not to be affected by the fluctuation of the power supply voltage supplied from the external terminals, a stable high voltage VP P is generated, and the internal step-down voltage VD L is used as the operating voltage. When the oscillation pulse 0 S CH is at the high level, the capacitors C8, C9, and C10 are charged until the internal step-down voltage VD L is reached. During charging, the voltage MOS F E T for charging the boosted voltage formed by the capacitor C 7 is set to the ON state, so the VD L charging voltage can be performed in a state where there is no critical voltage drop. When the oscillating pulse 0 S CH becomes the L level, the capacitor C 7 generates a boosted voltage of 2 VDL while charging the capacitor C 7. Because the operating voltage of the CMOS inverter circuit composed of MOSFET Q71 and Q72 is set to the boost voltage of 2 VD L formed by capacitor C 9, the voltage of 2 VD L is supplied to capacitor C 8, so the boost of 2 VDL The voltage is 3VDL boost voltage VPP / make 1 ^ 1- n 1 ^ 1 In HI an-HI n I an (Please read the precautions on the back before filling this page) This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm) -44- Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A7 B7 V. Description of the invention (42) The MO SFET for output becomes ON state. In this way, the boosted voltage of 2 VD L formed by the capacitor C 10 is output as the boosted voltage V P P without a level loss. Because the internal step-down voltage VDL is about 1.5 V, in the above embodiment, the charge pump circuit can form a boost voltage V P P of up to about 3 V. In this embodiment, the step-up voltage VPP may be 2.6V, so the step-up voltage of the oscillating circuit described later is used to generate a step-up voltage VPP of 2.6V. FIG. 24 is a circuit diagram of an embodiment of the oscillating circuit 1 for VPP. The oscillating circuit 1 of this embodiment uses a circuit substantially the same as the above-mentioned oscillating circuit 6 for VBB. The difference is that the oscillation pump OSCH only outputs one pulse corresponding to the charge pump circuit.

圖2 5爲VP P用之位準感測器3之一實施例之電路 圖。此實施例中，於接受內部降壓電壓VDL之P通道型 MOSFET Q72之源極施加昇壓電壓VPP。於 Μ 0 S F E T Q7 2設有在電源投入時供給暫時設爲L 位準之起動信號NSENB之MOSFET Q73。正 常狀態下，MOSFET Q73爲ON狀態，藉由與Ν 通道型MOSFET Q74之電阻比使昇壓電壓VPP 分壓。並以N通道型MOSFET Q76、 Q77及N 通道型MOSFET Q78構成之換流器電路之邏輯臨 界値來判斷該分壓電壓。 即，當昇壓電壓VP P大於設定値時，分壓電壓成爲 大於邏輯臨界値電壓，形成L位準之輸出信號，使其經由 2段之CMO S換流器電路放大而將感測輸出D E TH設 HH n n - i ml ,*Rn HI m nn U3 *T (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度遑用中國國家標準（CNS ) A4規格（210X297公釐） -45- 經濟部中央揉準局貝工消费合作杜印製 A7 B7五、發明説明（43 ) 爲L位準。據此使振盪電路之動作停止。當昇壓電壓 V P P小於設定値時，分壓電壓變爲小於邏輯臨界値電壓 ，形成Η位準之輸出信號，並使之經由2段之CMO S換 流器電路放大使輸出D Ε ΤΗ成爲Η位準。據此使振盪電 路之動作再開始。電源投入時，使信號N S ΕΝΒ設爲η 位準，使V Ρ Ρ之感測路徑之Ρ通道型MO S F Ε Τ Q73爲OFF狀態之同時，使N通道型MOSFET Q75爲ON狀態，使放大MOSFET Q76成爲 0 F F狀態。據此使感測輸出D Ε Τ Η強制爲Η位準，使 振盪電路動作。 圖2 6爲本發明之動態型RAM之一實施例之槪略全 體構成圖。動態型R A Μ係由：將進行資訊記憶之記憶格 配置成矩陣狀之記憶格陣列MCA;及當其中之1位元單 位之存取時選擇1個記憶格，當多數位元單位之存取時選 擇多數個記億格的X解碼器D E C、字元驅動器WD及Y 解碼器YD E C ;及接受外部控制信號/RA S (行位址 促發）、/CAS (列位址促發）、/WE (寫入能動） 、及/0E(輸出能動）並進行控制之控制電路構成。 動態型R A Μ之記憶格，係由1電容器，1電晶體（ MOSFET)構成。圖中，WD爲字元驅動器’輸出字 元線Wi (i=l〜η) ^字元驅動器WD，係由其前段 之X解碼器XDEC選擇。SA爲感測放大器’ b i t、 /b i t爲位元線，AC爲陣列控制電路，由AC輸出位 元線之等化信號E Q及感測放大器起動信號。1 0 c係設 1^—· ml in m .HI · In ^n· in 當 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐）_ 46 _ 經濟部中夬樣準局貝工消费合作社印裝Fig. 25 is a circuit diagram of an embodiment of the level sensor 3 for VPP. In this embodiment, the boosted voltage VPP is applied to the source of the P-channel MOSFET Q72 that receives the internal step-down voltage VDL. A MOSFET Q73 is provided at the M 0 S F E T Q7 2 to supply a start signal NSENB temporarily set to the L level when the power is turned on. In the normal state, the MOSFET Q73 is ON, and the boost voltage VPP is divided by the resistance ratio with the N-channel MOSFET Q74. The logic threshold of the inverter circuit composed of N-channel MOSFET Q76, Q77 and N-channel MOSFET Q78 is used to determine the divided voltage. That is, when the boosted voltage VP P is greater than the set voltage, the divided voltage becomes greater than the logic critical voltage, forming an L-level output signal, which is amplified by the 2-stage CMO S converter circuit to increase the sensed output DE. TH is set to HH nn-i ml, * Rn HI m nn U3 * T (Please read the precautions on the back before filling this page) This paper uses the Chinese National Standard (CNS) A4 size (210X297 mm) -45- The Central Government Bureau of the Ministry of Economic Affairs and the Bureau of Shellfish Consumer Cooperation Du printed A7 B7 5. Invention Description (43) is L level. This stops the operation of the oscillation circuit. When the boost voltage VPP is less than the set voltage, the divided voltage becomes less than the logic threshold voltage, forming a high-level output signal, and amplifying it through the CMO S converter circuit of the two stages to make the output D Ε ΤΗ become Η Level. Accordingly, the operation of the oscillation circuit is restarted. When the power is turned on, the signal NS ΕΝΒ is set to the η level, and the P channel type MO SF Ε Τ Q73 of the sensing path of V PP is turned off, and the N channel MOSFET Q75 is turned on, so that the amplified MOSFET is turned on. Q76 becomes 0 FF. Accordingly, the sensing output D Ε Τ Η is forced to a level, and the oscillation circuit is operated. FIG. 26 is a schematic overall configuration diagram of an embodiment of a dynamic RAM according to the present invention. The dynamic RA Μ is composed of: the memory cells for information memory are arranged in a matrix-like memory cell array MCA; and when one of the bit units is accessed, one memory cell is selected. When selecting most of the X decoder DEC, character driver WD and Y decoder YD EC; and accept external control signals / RA S (row address promotion), / CAS (column address promotion), / WE (write active) and / 0E (output active) control circuits for controlling. The dynamic RAM memory is composed of 1 capacitor and 1 transistor (MOSFET). In the figure, WD is a character driver 'output character line Wi (i = 1 to η). The character driver WD is selected by the X decoder XDEC in the preceding stage. SA is a sense amplifier 'bit, / bit is a bit line, AC is an array control circuit, and AC outputs an equalized signal E Q of the bit line and a start signal of the sense amplifier. 1 0 c is set 1 ^ — · ml in m .HI · In ^ n · in When (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297) (Centi) _ 46 _ Printed by the Shellfish Consumer Cooperative of the China Prototype Bureau of the Ministry of Economic Affairs

A7 B7五、發明説明（44 ) 置有讀出放大器（主放大器）RA及寫入放大器（WA俾 於讀出/寫入時進行I/0線之選擇與資料之放大。 記憶體之讀出動作，係由信號E Q成爲Η位準（ V CH)，位元線設定爲等化時開始。信號E Q成爲L位 準（VNN)，等化被解除，字元線由負電壓VNN上昇 爲V C Η之選擇位準。據此則來自於字元線所接記憶格之 信號出現於位元線。之後，藉感測放大器起動信號S A Ρ 及S AN起動感測放大器。如此則位元線上之信號被設定 成外部電壓V e X t或未圖示之內部阪壓電壓VD L之Η 位準與接地電位V S S之L位準。以Υ解碼器YD E C之 輸出來選擇位元線上附加之行選擇開關，使位元線接'於輸 出入線I/O並經由讀出放大器RA，輸出入緩衝器所包 含輸出緩衝器將資料輸出於晶片外。 記憶體之寫入動作，係如上述般於選擇動作中，輸出 入緩衝器包含之輸入緩衝器設定爲動作狀態，使由晶片外 輸入之寫入資料由寫入放大器WA —輸出入線I / 0及行 選擇開關、位元線而寫入記憶格之電容器內。 此實施例中，作爲內部電源電路，藉由基板電壓產生 電路，在形成有記憶格之P型井領域形成負偏壓V B B之 充電泵電路VBBG，及利用該電壓VBB，藉由未圖示 之定電壓電路形成使字元線設定爲非選擇位準之負電壓 VNN。又，藉充電泵電路V P P G產生昇壓電壓VP P ，再藉定電壓來產生字元線之選擇位準V C Η對應之高電 壓。該高電壓VCH，在不受構成記憶格之M0SFET I---------裝------訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家揉準（CNS > Α4規格（210Χ297公釐） -47- 經濟部中央樣準局月工消费合作社印製 A7 ____B7_ 五、發明説明（45 ) 之臨界値電壓影響下，使位元線之Η位準完全寫入電容器 內者。基板電壓V Β Β係作用爲，減低位元線或感測放大 器之Ρ η接合容量，或提早記憶格之MO S F Ε Τ之臨界 値電壓以改善資料保持特性，吸收因α線感應之少數載子 以減低系統錯誤（soft Error)。 記憶格之選擇用之位址信號A i ，係介由位址緩衝器 供至解碼器XDEC、 YDEC等。於動態型RAM中， 藉由位址多工方式，X系位址信號同步於/RA S信號被 輸入，之後，Y系位址信號同步於信號/CA S被輸入。 於位址緩衝器設位址閂鎖電路，以分時方式保持輸入之位 址。又，圖中雖被省略，但於動態型記憶格中，保持於電 容器之資訊電荷將隨時間之經過而消失。因此，在電荷消 失前，有必要進行讀出以回復原來之電荷之再生動作。圖 中亦被省略，但於控制電路中設有自動再生控制電路，可 於一定時間間隔作再生動作。 圖2 7爲本發明之動態型RAM中之字元驅動器之另 一實施例之電路圖。此實施例之特徵在於’適用於對上述 之階層字元線方式之副字之驅動器未施予階層化方式之字 元驅動器者。即，使用解碼信號X 0作爲字元驅動器 WD i之動作電壓。依此構成，可省略上述開關 MOSFET，即使附加有闻耐壓用之MOSFET’其 字元驅動器WD i之全體元件數亦僅需6個’個數少’故 可適用字元線節矩更小之記憶陣列。 此實施例中，針對作爲X解碼器XD E C形成選擇信 本紙張尺度逍用中國國家揉準（CNS ) Α4规格（210X 297公釐）_ 48 _ - I - I ^^1 ϋ— Hi 士之 ·νβ {請先聞讀背面之注意事項再填寫本頁) A7 B7A7 B7 V. Description of the invention (44) A sense amplifier (main amplifier) RA and a write amplifier (WA 俾) are used to select I / 0 lines and magnify data during read / write. The action starts when the signal EQ becomes the V level and the bit line is set to equalize. The signal EQ becomes the L level (VNN) and the equalization is released. The word line rises from the negative voltage VNN to VC. The selection level of 。. According to this, the signal from the memory cell connected to the word line appears on the bit line. Then, the sense amplifier is activated by the sense amplifier activation signals SA P and SAN to activate the sense amplifier. The signal is set to the Η level of the external voltage V e X t or the internal voltage VD L (not shown) and the L level of the ground potential VSS. The output of the Y decoder YD EC is used to select the additional line on the bit line Select the switch so that the bit line is connected to the input / output line I / O and output the data out of the chip through the sense amplifier RA, the output buffer included in the input / output buffer. The writing operation of the memory is as described above. In the selection operation, the input buffer included in the input and output buffers is set to In the working state, the written data input from the outside of the chip is written into the capacitor of the memory cell by the write amplifier WA—input / output line I / 0, row selection switch, and bit line. In this embodiment, as the internal power supply circuit, A charge pump circuit VBBG that forms a negative bias VBB in the P-well area where the memory cell is formed by the substrate voltage generating circuit, and uses the voltage VBB to set the word line to a constant voltage circuit (not shown). The negative voltage VNN of the non-selection level. In addition, the boost pump voltage VP P is generated by the charge pump circuit VPPG, and then the fixed voltage is used to generate the high voltage corresponding to the selection level VC 字 of the word line. Subject to M0SFET I which constitutes the memory cell --------------------- (please read the precautions on the back before filling in this page) The paper size is in accordance with the Chinese national standard (CNS > Α4 Specifications (210 × 297 mm) -47- Printed by the Central Industry Standards Bureau of the Ministry of Economic Affairs, Moon Industry Consumer Cooperative, A7 ____B7_ V. Under the influence of the critical threshold voltage of the invention description (45), the threshold level of the bit line is completely written into the capacitor The function of the substrate voltage V Β Β is to reduce The p η junction capacity of the element line or the sense amplifier, or the critical threshold voltage of MO SF Ε Τ of the memory cell in advance to improve the data retention characteristics, and absorb a small number of carriers induced by the α line to reduce the soft error. The address signal A i used for the selection of the grid is supplied to the decoders XDEC, YDEC, etc. via the address buffer. In the dynamic RAM, by the address multiplexing method, the X-series address signal is synchronized to / RA The S signal is input, and then the Y address signal is input in synchronization with the signal / CA S. An address latch circuit is set in the address buffer to keep the input address in a time-sharing manner. In addition, although the figure is omitted, the information charge held in the capacitor in the dynamic memory cell will disappear with the passage of time. Therefore, before the charge disappears, it is necessary to perform a read operation to restore the original charge. The figure is also omitted, but an automatic regeneration control circuit is provided in the control circuit, which can perform regeneration operation at a certain time interval. Fig. 27 is a circuit diagram of another embodiment of a character driver in a dynamic RAM of the present invention. This embodiment is characterized in that it is' suitable for a character driver that does not apply the hierarchical character driver to the above-mentioned character driver of the hierarchical character line method. That is, the decoded signal X 0 is used as the operating voltage of the character driver WD i. According to this structure, the above-mentioned switching MOSFET can be omitted, and even if the MOSFET for the voltage withstand voltage is added, the total number of components of the character driver WD i needs only six. Memory array. In this embodiment, the paper size of the selected letter is selected as the X-decoder XD EC. The paper size of the Chinese National Standard (CNS) A4 (210X 297 mm) _ 48 _-I-I ^^ 1 ϋ — Hi Shizhi · Νβ (Please read the notes on the back before filling in this page) A7 B7

經濟部中央橾準局員工消費合作社印$L 五、發明説明（46 ) 號之邏輯電路，及將輸出信號作位準轉換之2個位準轉換 電路LSP及LSN，分配字元線4條分之字元驅動器。 相對於此，亦可將解碼器信號X i由4種類擴大爲8種類 ，而共用字元線8條分之字元驅動器。此情況下，X解碼 器之佈線節矩可緩和，因此藉由將位準轉換電路L S P及 L S N朝橫向擴張，即可減少佈線圖型之縱向尺寸（字元 線之延長方向）。 圖2 8爲本發明之動態型RAM中之外部電歷~及內部 電壓VCH、 VNN、 VDL之關係之說明之一實施例之 電壓特性圖。一般，於半導體記憶體中，出廠前爲篩選出 初期不良品而需施加較正常使用電壓爲高之電壓，以除掉 不良元件，即所謂老化試驗或預類試驗。此實施例中，爲 使該試驗容易，及提昇試驗之良品率，而將閘極絕緣膜如 上述設爲2種類，使V CH與VD L在一定之位準差之狀 態下與外部電源電壓呈比例上昇，於標準動作領域及預熱 試驗之間切換其位準差。 相對地，負電壓VNN ’與外部電壓無關，而保持於 一定値。故預熱時設定爲較大亦可。雖亦可藉由增大上述 電壓變化之斜率來增大V CH與VD L間之差。但是，採 用上述方式時，VCH僅將圖1 7之電阻RL 2之電阻値 切換爲2段而容易實現，此爲優點。藉由此種電壓切換， 不論是在標準動作領域或預熱領域均可精確設定電壓，可 防止施加應力過大所導致元件之破壞，結果，可提昇良品 率。上述VDL相等於外部電壓V e X t。 -------- I— (請先閲讀背面之注意事項再填寫 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -49 - 經濟部中央標隼局舅工消费合作社印製 A7 _____B7__ 五、發明説明（47 ) 圖2 9爲本發明之動態型RAM中之外部電壓與內部 電壓VCH、VNN、VDL間之關係說明之另一實施例 之電壓特性圖。此實施例中，外部電源電壓設爲2 . 5 V 時，使用電壓限制器降壓，將標準動作領域之內部電壓 乂01^設爲1.5乂，俾可使用與圖2 8之實施例相同種 類、相同厚度之閘極絕緣膜。上述2種類MOSFET之 中，較厚閘極絕緣膜之MO S F E T，除字元驅動器或記 憶格以外，亦可作爲輸入緩衝器或輸出緩衝器使用，較薄 閘極絕緣膜之MO S F E T作爲週邊電路或感測放大器使 用。 上述V CH及VD L，於標準動作領域附近係與外部 電源電壓無關而保持一定位準，而於預熱領域附近則對應 外部電源電壓而上昇。其切換，係與圖2 8之實施例相同 ，於標準動作領域與預熱領域之間進行。負電壓VNN， 係與外部電源電壓無關而保持一定。此實施例中，亦如上 述般，VCH係以VDL爲基準而產生基準電壓VRP， 將電阻RL 2之電阻値切換爲2段，於預熱領域增大與 V D L間之差電壓。如此則不論標準動作領域或預熱領域 均可精確設定施加於MO S F E T之電壓，減低因過大應 力所導致之不良元件，提昇製品良率。 上述VDL，當於標準動作領域時係使用基準電壓 VREFO，藉和上述同樣之定電壓電路來產生VDL， 於預熱領域，則切換爲依存於上述外部電源電壓變化之電 壓，以取代電壓VRE F 〇。此處，依存於外部電壓而變 本紙張及度適用中國國家揉準（CNS ) A4規格（210X297公釐） ' 1^1- ^^^1 In Bn^ ml in * n^— ^^^1 ^^^1 i ^ V 、T (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作杜印装 A7 B7 五、發明説明（48 ) 化之電壓可利用，將電阻之一端接VDL，另一端接於以 接地電位V S S之基準之N通道型MO S F E T之電流鏡 電路，利用其產生之電壓即可。 圖3 0爲搭載有本發明之電源電路之動態型RAM之 一實施例之槪略設計圖。此實施例中，未特別限制，但記 憶陣列，係於晶片之縱橫各設4個，晶片全體由1 6個記 億格陣列構成。晶片之長邊方向中央部分設爲間接電路領 域，縱向設以並列之"□'表示之接合焊墊及包含電源電 路之周邊電路。於間接電路領域，對應於接合焊墊適當地 形成位址緩衝器電路、資料輸出/入緩衝器。 如上述般相對半導體晶片之長邊方向，左右各2個計 4個，及上下各4個，合計1 6個構成之各記億陣列中， 相對於長邊方向於上下中央部分畫分爲2，於畫分之各2 個中央部分設主字元選擇電路MWL。在與主字元選擇電 路MWL之各記憶格陣列鄰接之上下，形成未圖示之主字 元驅動器，以分別驅動畫分爲上下之記億陣列之主字元線 。在晶片之橫方向並列配置之各2個之記憶格陣列之間， 設Y選擇電路YD。 上述記憶格陣列，係於長邊方向及與其呈直角方向（ 橫方向）配列多數記憶區塊。即，1個記憶格，係於長邊 方向設8個記億區塊，於直角方向作1 6分割而設1 6個 記憶區塊。換言之，字元線被8分割，位元線對1 6分割 。如此則，1個記憶區塊所設記憶格之數目爲8分割及 1 6分割，可實現記憶體存取之高速化》上述記憶區塊， m n^— ^^^1 ^fn ^^^1 ^n· n^— > ^—^1* -e (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） -51 - 經濟部中央樣準局貝工消费合作社印裝 A7 B7_ ·_五、發明説明（49 ) 如後述般，於圖中感測放大器領域以挾持其之狀態配置於 左右，副字元驅動器領域則配置於上下。設於感測放大器 領域之感測放大器’係由分時感測方式構成’除配置於記 憶格陣列兩端之感測放大器之外，以感測放大器爲中心而 於左右設互補位元線，並選擇地連接於左右任一之記憶區 塊之互補位元線。 如上述各2個成組配置之2個記憶陣列，係於其中央 部分配置主字元驅動選擇電路MWL及主字元驅動器。該 主字元選擇電路MWL，係對應以其爲中心分配於上下之 2個記憶陣列而共通設置。主字元驅動器，用於形成貫通 上述1個記憶陣列而延伸之主字元線之選擇信號。又，於 主字元驅動器亦設有副字元選擇用驅動器，如後述般與上 述主字元線平行延伸而形成副字元選擇線之選擇信號。 1個記億區塊，設定有2 5 6條副字元線（未圖示） ，與其呈正交之互補位元線（或資料線）有5 1 2對。於 1個記憶陣列中，於位元線方向設1 6個記億區塊，故全 體而言約設有8 K分之副字元線，晶片全體約設有1 6 K 分。又’於1個記憶陣列中，於字元線設有8個記憶區塊 ，故全體約設有4 K分之互補位元線。此種記憶陣列全體 設有4個，故全體設1 6 K分之互補資料線，全體之記憶 容量爲1 6KX 1 6K = 2 5 6M (百萬）位元之大記億 容量。 上述1個記億格陣列，係相對主字元線方向分割爲8 個。於該分割之每一記億格陣列設副字元驅動器（副字元 H- ^^^1 ·ϋι HI nn n ^^^1—*J U3 *T (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X 297公簇） •52- 經濟部中央樣準局員工消费合作社印装 A7 B7五、發明説明（50 ) 線驅動電路）。副字元驅動器，係相對於主字元線分割爲 1/8長度，以形成與其平行延伸之副字元線之選擇信號 。此實施例中’爲減少主字元線數，換言之，爲緩和主字 元線之配線節矩’雖未特別限制，設定爲相對1個主字元 線，於互補位元線方向配置4條構成之副字元線。如上述 般’於主字元線方向分割成8條，及相對於互補位元線方 向各分配4個之副字元線之中，爲選擇1條之副字元線， 而配置副字元選擇驅動器。該副字元選擇驅動器，係用以 形成選擇信號俾從朝副字元驅動器之配列方向延伸之4條 副字元選擇線之中選擇1條。 若著眼於1個記憶格陣列，則在1個主字元線所分配 8個記憶格陣列之中應選擇之記憶格所包含之1個記憶區 塊所對應之副字元驅動器中，1條副字元選擇線被選擇之 結果，1條主字元所屬8x4=32條副字元線之中之1 個副字元線被選擇。如上述般，於主字元線方向設有4 K (4 0 9 6 )個記憶格，故在1個副字元線接有4 0 9 6 / 8 = 5 1 2個記憶格。雖未特別限制，但於再生動作（ 例如自激再生模式）中，1條主字元線對應之8條副字元 線被設定爲選擇狀態。 如上述般，1個記憶陣列，係相對於互補位元線方向 具4 K位元之記憶容量。但是，相對1個互補位元線，連 接4 K之記憶格時，互補位元線之寄生容量變大，因與微 細之資訊記憶用電容器之容量比而無法獲得讀出之信號位 準，因此，相對於互補位元線方向分割成1 6分。即’藉 n^i I ^ian,T (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -53- A7 B7 經濟部中央標準局負工消费合作社印製 五 、發明説明（51 ) 1 1 由 記億 區 塊間配 置之感測放大器 ，使互 補位 元 線 作 1 6 分 1 | 割 。雖 未 特別限 制，但感測放大 器，如 上述 般 係 由 分 時 感 1 I 測 方式 構 成，故 除配置於記憶格 陣列兩 端之 感 測 放 大 器 以 請 1 1 外 ，係 以 感測放 大器1 6爲中心 於左右 設互 補位 元 線 而 先 閲 讀 1 1 選 擇性地 連接於左右之任一互補位元線 背 1 1 此 實 施例中 ，雖未特別限制 ，但設計成對應上述圖 注 意 重 1 I 1 4之 實 施例， 設有各2組合計 4組之 定電 壓 電 路 R G Ρ ψ 項 再 1 1 R G N 。亦即 ，挾持接合焊墊 列，於 縱向 各 分 配 2 組 ( 填 寫 本 裝 R G P 及 R G N )。結果，1組定電壓電路< G N 及 頁 1 1 R G P ) ，負責 4個記憶格陣列 。充電 泵電 路 V P P G 及 1 1 V B B G ，係設 於晶片中央部分 ，對上 述4 個 定 電 壓 電 路 1 I R G. P 、 R G N 供給充電泵電壓 V Ρ Ρ 及V Β Β 〇 設 於 中 1 訂 | 央 之基 準 電壓產 生電路R G F N 亦對上 述4 組 定 電 壓 產 生 1 電 路分 別 供給定 電壓。於此構成 中，充 電泵 電 路 V P Ρ G 1 1 與 V B B G及基 準電壓產生電路 R G F Ν與 各 定 電 壓 電 路 1 1 間 之距 離 爲均一 且形成較短。 \ . * I 圖 3 1爲本 發明適用之單晶 片微電 腦之 一 實 施 例 之 方 1 1 1 塊 構成 圖 。此實 施例之單晶片微 電腦Μ C U 係 組 裝 於 白 1 1 動 車或 產 業用機 械等，作爲控制裝置。 1 回 圖 中 之微電 腦M C U，係設 計成儲 程式 方 式 之 中 央 處 1 | 理 裝置 C P U。 於中央處理裝置 CPU ，介 由 內 部 匯 流 排 1 I I B U S 連接有 R 0 M ( Read Only Memory) 、 R A Μ ( 1 1 Random Access Memory)、類比 數位轉 換電 路 A / D 監 1 1 視 計時 器 W D T 、計時器電路T [Μ及序列通信介面 1 1 1 本紙張尺度適用中國國家標準（CNS M4规格（210X297公釐） -54- 經濟部中央樣準局員工消費合作杜印製 A7 B7 五、發明説明（52 ) SCI 。又，包含中央處理裝置CPU之微電腦MCU之 各部，供給有來自時脈產生電路C L KG之特定時脈信號 C L K。微電腦MC U另具有：控制時脈產生電路 C L KG之動作的時脈控制器C L K C，及電源投入時令 微電腦MC U之各部重置於初期狀態之電源重置電路 P 0 R。 於監視計時器上，供給來自C PU之內部信號PR， 並將輸出信號，即異常檢測信號T D供至時脈控制器 CLKC。時脈產生電路CLKG之一方端子，係介由外 部端子E XTA L接於水晶振盪器XTA L之一方電極， 另一方輸入端子則供給有時脈控制器C L K C之時脈輸出 信號CG。水晶振盪器XTAL之另一方電極，係介由外 部端子XTAL接於時脈控制器CLKC。 於電源重置電路POR，介由外部端子VC C及 V S S分別供給作爲單晶片微電腦M C U之動作電源的電 源電壓VCC及接地電位VSS，其輸出信號，即電源重 置信號POR則供至時脈控制器CLKC。於時脈控制器 C LKC另供給有來自C PU之完全停止控制暫存器 R S T P之輸出信號R S T P及模式控制暫存器R C MD 之輸出信號CMD，其輸出信號，即正常重置信號RS， 則供至包含C P U之微電腦M C U之各部。 CPU，係依儲存於ROM之使用者程式作動作，以 執行特定之運算處理，同時，控制微電腦之各部》此實施 例中，C P U具備可依指令寫入之完全停止控制暫存器及Printed by the Consumers' Cooperative of the Central Economic and Technical Bureau of the Ministry of Economic Affairs of the People's Republic of China Co., Ltd. $ 5. The logic circuit of invention description (46) and the two level conversion circuits LSP and LSN for level conversion of the output signal. Allocate 4 character lines. Zigzag drive. On the other hand, the decoder signal X i can also be expanded from 4 types to 8 types, and a character driver of 8 divided word lines can be used. In this case, the wiring pitch of the X decoder can be relaxed. Therefore, by expanding the level conversion circuits L S P and L S N in the horizontal direction, the vertical size of the wiring pattern (the extending direction of the character lines) can be reduced. Fig. 28 is a voltage characteristic diagram of an embodiment illustrating the relationship between the external calendar and the internal voltages VCH, VNN, and VDL in the dynamic RAM of the present invention. Generally, in the semiconductor memory, in order to screen out the initial defective products before shipment, a higher voltage than the normal use voltage must be applied to remove the defective components, which is the so-called aging test or pre-type test. In this embodiment, in order to make the test easy and improve the yield of the test, the gate insulation film is set to two types as described above, so that V CH and VD L are at a certain level with the external power supply voltage. Rise proportionally, switch the level difference between the standard action field and the warm-up test. On the other hand, the negative voltage VNN ′ is independent of the external voltage and remains at a certain level. Therefore, it can be set to a large value during preheating. The difference between V CH and V D L can be increased by increasing the slope of the voltage change. However, when the above method is adopted, VCH can be easily realized only by switching the resistance 値 of the resistance RL 2 in FIG. 17 to two stages, which is an advantage. With this kind of voltage switching, the voltage can be set accurately in both the standard operation field and the preheating field, which can prevent the damage of the component caused by excessive stress, and as a result, the yield can be improved. The above VDL is equal to the external voltage V e X t. -------- I— (Please read the notes on the back before filling in this paper. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -49-Masonry Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Printed A7 _____B7__ 5. Description of the invention (47) Figure 2 9 is a voltage characteristic diagram of another embodiment of the relationship between the external voltage and the internal voltage VCH, VNN, VDL in the dynamic RAM of the present invention. This embodiment When the external power supply voltage is set to 2.5 V, the voltage limiter is used to reduce the voltage, and the internal voltage in the standard operating field 乂 01 ^ is set to 1.5 乂. The same type and the same thickness as in the embodiment of FIG. 2 8 can be used. Gate insulation film. Among the above two types of MOSFETs, MO SFETs with thicker gate insulation films can be used as input buffers or output buffers in addition to character drivers or memory cells. Thinner gate insulation films The MO SFET is used as a peripheral circuit or a sense amplifier. The above-mentioned V CH and VD L are maintained near a standard operation area regardless of the external power supply voltage and remain in a fixed position, while near the preheating area, they correspond to the external power supply voltage. The switching is the same as in the embodiment of FIG. 28, and it is performed between the standard operation field and the preheating field. The negative voltage VNN is maintained regardless of the external power supply voltage. In this embodiment, as described above, VCH generates a reference voltage VRP based on VDL, switches the resistance 値 of resistor RL 2 to two stages, and increases the difference voltage between VDL and VDL in the preheating field. In this way, it can be accurate regardless of the standard operation field or preheating field Set the voltage applied to the MO SFET to reduce defective components caused by excessive stress and improve product yield. The above VDL uses the reference voltage VREFO when it is used in the standard operation field, and generates VDL by the same constant voltage circuit as above. In the field of preheating, it is switched to a voltage that depends on the above external power supply voltage to replace the voltage VRE F 0. Here, the paper and the degree of change depending on the external voltage are applicable to China National Standard (CNS) A4 (210X297) Mm) '1 ^ 1- ^^^ 1 In Bn ^ ml in * n ^ — ^^^ 1 ^^^ 1 i ^ V, T (Please read the notes on the back before filling this page) Central Ministry of Economy Standards Bureau Shellfish Consumer Cooperation Du printed A7 B7 V. Description of the invention (48) The voltage can be used. One of the resistors is terminated to VDL and the other is connected to the current mirror circuit of the N-channel MO SFET based on the ground potential VSS. The voltage is sufficient. FIG. 30 is a schematic design diagram of an embodiment of a dynamic RAM equipped with the power supply circuit of the present invention. In this embodiment, it is not particularly limited, but the memory array is arranged on the vertical and horizontal sides of the chip. The whole chip is composed of 16 billion grid arrays. The central part of the long-side direction of the chip is set as the indirect circuit area, and the bonding pads indicated by the " □ 'in the vertical direction and the peripheral circuits including the power supply circuit are set in the vertical direction. In the field of indirect circuits, address buffer circuits and data input / output buffers are appropriately formed corresponding to the bonding pads. As described above, in the long-side direction of the semiconductor wafer, there are 4 on the left and right, and 4 on the top and bottom. A main character selection circuit MWL is set in each of the two central parts of the drawing. Adjacent to the memory cell arrays of the main character selection circuit MWL, a main character driver (not shown) is formed to drive the main character lines divided into upper and lower billion arrays, respectively. A Y selection circuit YD is provided between the two memory cell arrays arranged side by side in the horizontal direction of the wafer. The above-mentioned memory cell array is arranged in the long-side direction and in a right-angle direction (horizontal direction) with a large number of memory blocks. That is, one memory cell is provided with 8 billion memory blocks in the long side direction, and 16 memory blocks are divided by 16 in the right direction. In other words, the word line is divided by 8 and the bit line pair is divided by 16. In this way, the number of memory cells set in a memory block is 8 divided and 16 divided, which can achieve high-speed memory access. "The above memory block, mn ^ — ^^^ 1 ^ fn ^^^ 1 ^ n · n ^ — > ^ — ^ 1 * -e (Please read the precautions on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 Washing (210X297 mm) -51-Economy Printed by the Central Bureau of Prototyping and Consumer Products Co., Ltd. A7 B7_ · _V. Description of the Invention (49) As will be described later, the sensor amplifier field is arranged on the left and right, and the sub-character driver field is placed on up and down. The sense amplifier provided in the field of the sense amplifier is constituted by a time-sharing sensing method. In addition to the sense amplifiers arranged at both ends of the memory cell array, the complementary bit lines are arranged around the sense amplifier as the center. It is selectively connected to the complementary bit lines of any one of the left and right memory blocks. As described above, each of the two memory arrays arranged in two groups is arranged in its central part with a main character drive selection circuit MWL and a main character driver. The main character selection circuit MWL is commonly provided corresponding to the two memory arrays centered on it. The main character driver is used to form a selection signal of a main character line extending through the one memory array. In addition, a driver for sub-character selection is also provided in the main character driver, which extends parallel to the main character line as described later to form a selection signal for the sub-character selection line. There are 2 256 sub-character lines (not shown) set in a block of 100 million, and there are 5 1 2 pairs of complementary bit lines (or data lines) orthogonal to it. In a memory array, 16 billion blocks are set in the direction of the bit line, so there are about 8 K sub-word lines in total, and the whole chip is about 16 K points. In a memory array, there are 8 memory blocks on the word line, so there are about 4 K complementary bit lines in the whole. There are four such memory arrays, so all 16 K points of complementary data lines are set, and the total memory capacity is 16KX 1 6K = 2 56M (million) bits. The above 1 billion grid is divided into 8 relative to the direction of the main character line. A sub-character driver is set on each of the billion grid arrays of this division (sub-characters H- ^^^ 1 · ϋ HI nn n ^^^ 1— * J U3 * T (Please read the precautions on the back before reading (Fill in this page) This paper uses the Chinese National Standard (CNS) A4 specification (210X 297 clusters). • 52- Printed A7 B7 by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs. 5. Description of the invention (50) Line drive circuit.) . The sub-character driver is divided into 1/8 lengths relative to the main character line to form a selection signal of the sub-character line extending parallel thereto. In this embodiment, 'to reduce the number of main character lines, in other words, to ease the wiring pitch of the main character lines', although not particularly limited, it is set to be relative to one main character line, and four are arranged in the direction of the complementary bit lines. Constitute the vice character line. As described above, among the sub-character lines divided in the direction of the main character line and 4 sub-character lines allocated to the direction of the complementary bit line, the sub-character is configured to select one sub-character line. Select the drive. The sub-character selection driver is used to form a selection signal, and select one of the four sub-character selection lines extending in the direction in which the sub-character drivers are arranged. If we focus on one memory cell array, one of the eight sub-array drivers corresponding to one memory block included in the eight memory cell arrays allocated by one main character line corresponds to one of the sub-character drivers. As a result of the sub-character selection line being selected, one of the 8 x 4 = 32 sub-character lines to which a main character belongs is selected. As mentioned above, there are 4 K (4 0 9 6) memory cells in the direction of the main character line, so 4 0 9 6/8 = 5 1 2 memory cells are connected to one auxiliary character line. Although not particularly limited, in a regeneration operation (for example, a self-excitation regeneration mode), eight sub-character lines corresponding to one main character line are set to a selected state. As mentioned above, a memory array has a memory capacity of 4 K bits with respect to the direction of the complementary bit line. However, when a 4 K memory cell is connected to one complementary bit line, the parasitic capacity of the complementary bit line becomes larger, and the readout signal level cannot be obtained due to the capacity ratio of the capacitor to the fine information memory capacitor. , Divided into 16 points relative to the direction of the complementary bit line. That is' borrow n ^ i I ^ ian, T (Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) -53- A7 B7 Central Standard of the Ministry of Economic Affairs Printed by the Bureau of Work and Consumer Cooperatives V. Description of the Invention (51) 1 1 By using a sense amplifier configured between 100 million blocks, the complementary bit line is divided into 16 points and 1 points. Although not particularly limited, the sense amplifier, as described above, is composed of a time-sharing sense 1 I measurement method, so in addition to the sense amplifiers arranged at both ends of the memory cell array, please use the sense amplifier 1 6 To set complementary bit lines on the left and right, read 1 1 first. Select any of the complementary bit lines on the left and right. Back 1 1 In this embodiment, although not particularly limited, it is designed to correspond to the above figure. Note that I 1 The embodiment of 14 is provided with a constant voltage circuit RG P ψ of 2 combinations and 4 groups, and then 1 1 RGN. That is, the bonding pad row is held, and two groups are allocated in the longitudinal direction (fill in R G P and R G N). As a result, one set of constant voltage circuits < G N and 1 1 R G P) are responsible for 4 memory cell arrays. The charge pump circuits VPPG and 1 1 VBBG are located in the central part of the chip. The above four constant voltage circuits 1 IR G. P and RGN supply the charge pump voltages V P P and V Β Β 〇 set in the middle of 1 | Central The reference voltage generating circuit RGFN also supplies constant voltages to the above-mentioned four sets of constant voltage generating circuits. In this configuration, the distances between the charge pump circuits V P PG G 1 1 and V B B G and the reference voltage generating circuit R G F Ν and each of the constant voltage circuits 1 1 are uniform and shorter. \ I * Fig. 3 1 is a block diagram of one embodiment of a single crystal microcomputer brain to which the present invention is applied. The single-chip microcomputer MICU of this embodiment is mounted on a white automobile or industrial machine as a control device. The microcomputer M C U in the figure is designed to be stored in the central part of the program. 1 | Device C P U. In the central processing unit CPU, the internal bus 1 IIBUS is connected with R 0 M (Read Only Memory), RA Μ (1 1 Random Access Memory), analog digital conversion circuit A / D monitoring 1 1 watch timer WDT, timing器 电路 T [M and serial communication interface 1 1 1 This paper size applies to Chinese national standards (CNS M4 specification (210X297 mm) -54- Staff consumption cooperation of the Central Prototype Bureau of the Ministry of Economic Affairs Du A7 B7 Printed 5. 52) SCI. In addition, each part of the microcomputer MCU including the central processing unit CPU is supplied with a specific clock signal CLK from the clock generation circuit CL KG. The microcomputer MC U also has: a time for controlling the operation of the clock generation circuit CL KG The pulse controller CLKC and the power reset circuit P 0 R that resets each part of the microcomputer MC U to the initial state when the power is turned on. On the watchdog timer, the internal signal PR from the CPU is supplied, and the output signal is output, that is, The abnormality detection signal TD is supplied to the clock controller CLKC. One terminal of the clock generating circuit CLKG is connected to one of the crystal oscillator XTA L via an external terminal E XTA L The other input terminal supplies the clock output signal CG of the clock controller CLKC. The other electrode of the crystal oscillator XTAL is connected to the clock controller CLKC via the external terminal XTAL. In the power reset circuit POR Through the external terminals VC C and VSS, the power supply voltage VCC and the ground potential VSS, which are the operating power supply of the single-chip microcomputer MCU, are supplied to the clock controller CLKC. The controller C LKC is additionally supplied with the output signal RSTP of the complete stop control register RSTP of the C PU and the output signal CMD of the mode control register RC MD. The output signal, namely, the normal reset signal RS, is provided to include Each part of the microcomputer MCU of the CPU. The CPU operates according to the user program stored in the ROM to perform specific arithmetic processing, and at the same time controls the parts of the microcomputer. In this embodiment, the CPU has a complete stop that can be written according to instructions. Control register and

In H li_ n HI » 1-- -.1 —II - - I Λ3-St (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家標準（CNS ) A4说格（210X297公釐） -55- 經濟部中央標準局員工消费合作杜印裝 A7 B7 五、發明説明（53 ) 模式控制暫存器，其輸出信號R s T P及R CMD則供至 時脈控制器CLKC。又，用於表示CPU之程式墊行狀 況之內部信號P R，則由監視計時器W D T常時監控，並 供至微電腦MCU之異常檢測-。R〇M係由例如具特定記 憶容量之掩罩ROM (MROM)等構成，以儲存C PU 控制之必要程式或固定資料。R A Μ則由例如具特定記憶 容量之靜態型RAM等構成，以暫時儲存C P U之運算結 果或控制資料等，快閃E P ROM爲電氣寫入可能之 ROM，當電源切斷時可記憶應保持之資料。 A / D (類比數位轉換電路），係將外部各種感測器 輸入之類比輸入信號轉換爲特定位元之數位信號，再介由 內部匯流排I BUS傳至CPU等。此實施例中，供給有 形成上述預充放電電壓用之基準電壓Vr e f。該基準電 壓V r e f亦可供至A/D轉換器，作爲A/D轉換動作 之基準電壓使用。A/D所包含之上述樣本保持裝置、預 充放電裝置使用之取樣時脈及預充放電時脈，係依時脈產 生電路C P G形成之時脈來產生。又，A/D轉換器 AD C本身使用之時脈信號亦同樣。 計時器電路T I Μ，係依時脈產生電路C P G供給之 時脈信號進行時間計時，序列通信介面S C I係於例如微 電腦外部所接序列輸出入裝置及R AM之間進行高速資料 傳送。 監視計時器WD T，係監控C P U輸出之內部信號 P R，當發現該內部信號P R超過特定時間乃未形成，換 —^1· ^^^1 H— 1^1 tn ^^^1 In f a— m ^^1 V / -\β (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度遑用中國國家揉準（CNS ) A4规格（210X297公釐） -56- 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（54 ) 言之，發現於長時間C PU未執行指令取入時，檢測出 CPU (即微電腦）之異常’並將該輸出信號（即異常檢 測信號）TD選擇性地設定爲Η位準。電腦重置電路 P〇R，則監控介由外部端子VCC及VSS供給之電源 電壓V C C及接地電位V S S之電位，在動作電源投入之 初，使其輸出信號，即電源重置信號P 0 R僅於特定期間 爲Η位準。監視計時器WDT之異常檢測信號TD及電源 重置電路Ρ 0 R之電源重置信號Ρ 0 R供至時脈控制器 C L K C。 組裝於汽車或產業用機械等之單晶片微電腦等，係設 有時脈控制器，俾於監視計時器之異常檢測或接受來自 c P U之指令執行特定暫存器寫入而選擇性地使時脈產生 電路之動作停止，該完全停止狀態之解除，僅藉由電源再 投入時之電源重置信號才可能，‘故異常產生時，動作電源 被切斷再投入之前，可使微電腦等之動作完全停止。 搭載有電源電路P 0W，俾產生微電腦之內部電壓 + v、+ V<及—V、一。該電源電路，係將充電泵 電路及定電壓電路組合以產生穩定之內部電壓+V、 +V /及—V、— 。電壓+V及—V，並未特別限制，但 可設爲12V及_12V之高電壓，以作爲EPROM之 寫入及消去電壓使用。 藉此則於搭載有E P R 0M之系統狀態下寫入爲可能 。一 V、— 設定爲上述A/D轉換器之動作電壓，因 A/D轉換器於正負二電壓動作，可使類比信號直接從外 (請先聞讀背面之注意事項再填寫本頁) 裝- 、-口 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -57- 經濟部中央標準局負工消费合作社印製 A7 B7 五、發明説明（55 ) 部端子輸入。即，不必如以一電源動作之A / D轉換器般 設置直流阻止用耦合容量，可輸入類比信號，故亦可接受 低頻之輸入信號，不需外加之大容量。 圖3 2爲本發明之基準電壓產生電路之另一實施例之 電路圖。此實施例中，使用P通道型MOSFET，即使 MO S F E T之臨界値電壓較高時亦有足夠電流流經差動 放大器，另設有雙端子構成之推挽式轉換電路，俾驅動P 通道型輸出緩衝器。 電晶體T 3、T 4之基、射極間電壓所形成節點（a )、（b)之電位爲0.6V〜0.7V，較低。因此， 於上述圖17之實施例電路中，於電源電壓爲3.3V〜 5V用之MO S F ET中，臨界値電壓與上述節點（a ) 、（b)之電位爲相同程度，無法流通足夠之電流，導致 電源投入特性或穩定性之惡化。特別是電源投入時，節點 (a)、 （b)之電位爲0V，差動放大器無法動作，亦 有可能產生基準電壓V r e f無法上昇之情況。 本實施例中，上述節點（a )、 （ b )之較低電壓係 由P通道型MOSFET MP1及MP2來承擔，故即 使該MOSFET MP1、MP2之臨界値電壓設定成 較高時亦可確保足夠之閘、汲極間電壓，可流通更多電流 ，如此即可改善電源投入之特性及穩定性。 又，因基準電壓V r e f以接地電位V S S爲基準作 成，故有必要將雙極性電晶體之基極或射極端接於接地電 位V S S。爲使其於低電源電壓動作，需P通道型 : - - - - - - - - .....I - - - . ^^1 - - n - --- I ------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國困家橾準（CNS ) A4规格（210X297公釐） -58- 經濟部中央揉準局貝工消费合作社印製 A7 ________B7_ 五、發明説明（56 ) M〇S F E T之驅動器。若以一般之P通道型 MO S F E T輸入之電流鏡負荷型放大器驅動，則無法輸 出足夠之Η位準，無法將P通道型之M〇 S切斷。因此， 本實施例中，爲解決此問題，設置雙端子構成之推換式轉 換電路以確保足夠之Η位準。 亦即，於構成差動放大器之一方之Ρ通道型 MOSFET ΜΡ 1之汲極與電路接地電位之間，連接 二極體形態之Ν通道型MOSFET Q80，及與之形 成電流鏡形態之Ν通道型M0SFETQ81。該 MOSFET Q81用於驅動設於電源電壓側之二極體 形態之P通道型MOSFET Q8 2。在構成差動放大 器之另一方P通道型MOS FET MP 2之汲極與電路 接地電位之間，亦連接二極體形態之N通道型 MOSFET Q83，及與之形成電流鏡形態之N通道 型MOSFET Q84。將該MOSFET Q84之 汲極，及與上述P通道型MOSFET Q8 2形成電流 鏡連接之P通道型MOS FET Q8 5之汲極予以連接 ，以構成雙端子構成之推挽式轉換電路。藉該推挽式電路 ，來驅動P通道型MOSFET MP3，驅動上述電晶 體T3、 T4。又，P通道型MOSFET Q87，其 閘極常時接於電路之接地電位，作爲電阻元件使用，具使 電源投入時之節點（a)、 （b)之電位上昇之功用，因 此，歐姆電阻値設爲極大。 本實施例中，即使MO S F E T之臨界値電壓較大， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐）In H li_ n HI »1-- -.1 —II--I Λ3-St (Please read the precautions on the back before filling out this page) The paper size is in accordance with the Chinese National Standard (CNS) A4 (210X297 mm) ) -55- Consumption cooperation between employees of the Central Bureau of Standards, Ministry of Economic Affairs, Du printed equipment A7 B7 V. Description of invention (53) The mode control register, the output signals R s TP and R CMD are supplied to the clock controller CLKC. In addition, the internal signal PR used to indicate the state of program execution of the CPU is constantly monitored by the watchdog timer W D T and supplied to the abnormality detection of the microcomputer MCU-. The ROM is composed of, for example, a mask ROM (MROM) with a specific memory capacity to store necessary programs or fixed data for CPU control. The RAM is composed of, for example, a static RAM with a specific memory capacity to temporarily store the calculation results or control data of the CPU. The flash EP ROM is a ROM that can be electrically written. When the power is turned off, the memory should be maintained. data. A / D (Analog Digital Conversion Circuit) converts analog input signals from various external sensor inputs into digital signals of specific bits, and then transmits them to the CPU via the internal bus I BUS. In this embodiment, a reference voltage Vr e f for forming the aforementioned precharge / discharge voltage is supplied. This reference voltage V r e f is also available to the A / D converter as a reference voltage for A / D conversion operation. The sampling clock and precharge / discharge clock used by the sample holding device and precharge / discharge device included in the A / D are generated according to the clock formed by the clock generation circuit CPG. The same applies to the clock signal used by the A / D converter AD C itself. The timer circuit T IM is used for timing based on the clock signal provided by the clock generating circuit CPG. The serial communication interface SCI is used for high-speed data transmission between the serial input / output device connected to the microcomputer and the RAM. The monitoring timer WD T is used to monitor the internal signal PR output by the CPU. When it is found that the internal signal PR has not been formed for a certain period of time, change — ^ 1 · ^^^ 1 H— 1 ^ 1 tn ^^^ 1 In fa— m ^^ 1 V /-\ β (Please read the notes on the back before filling in this page) This paper size is based on China National Standard (CNS) A4 (210X297 mm) -56- Employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative A7 B7 V. Description of the invention (54) In other words, it was found that the CPU (that is, the microcomputer) was abnormal when the CPU PU did not execute the instruction fetch for a long time, and output the signal (that is, the abnormal detection signal) TD is selectively set to the Η level. The computer reset circuit P0R monitors the potential of the power supply voltage VCC and the ground potential VSS supplied through the external terminals VCC and VSS, and outputs a signal when the operating power is turned on, that is, the power reset signal P 0 R is only During a certain period of time, it is the level. The abnormality detection signal TD of the watchdog timer WDT and the power reset signal P 0 R of the power reset circuit P 0 R are supplied to the clock controller C L K C. Single-chip microcomputers assembled in automobiles or industrial machinery, etc., are equipped with a clock controller, which is used to selectively detect the abnormality of the watchdog timer or receive instructions from the cPU to execute specific register writes. The operation of the pulse generating circuit is stopped, and the release of the completely stopped state is possible only by the power reset signal when the power is turned on again. 'Therefore, when an abnormality occurs, the microcomputer and other operations can be performed before the power is turned off Stop completely. It is equipped with a power circuit P 0W, which generates internal voltages of the microcomputer + v, + V < and -V, one. The power circuit is a combination of a charge pump circuit and a constant voltage circuit to generate stable internal voltages + V, + V / and -V,-. The voltages + V and -V are not particularly limited, but can be set to high voltages of 12V and _12V for use as the write and erase voltages of EPROM. This makes it possible to write in a system state equipped with EP 0M. One V, — set to the operating voltage of the above A / D converter, because the A / D converter operates at two positive and negative voltages, the analog signal can be directly from the outside (please read the precautions on the back before filling this page) -,-The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -57- Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 B7 V. Description of the invention (55) Terminal input. That is, it is not necessary to set the DC blocking coupling capacity like an A / D converter operated by a power supply, and an analog signal can be input, so a low-frequency input signal can also be accepted without the need for additional large capacity. Fig. 32 is a circuit diagram of another embodiment of the reference voltage generating circuit of the present invention. In this embodiment, a P-channel MOSFET is used, and even when the critical threshold voltage of the MO SFET is high, there is sufficient current to flow through the differential amplifier. There is also a push-pull conversion circuit composed of two terminals to drive the P-channel output buffer. The potentials of the bases of the transistors T 3 and T 4 and the voltage between the emitters (a) and (b) are 0.6V to 0.7V, which is relatively low. Therefore, in the circuit of the embodiment of FIG. 17 described above, in MO SF ET with a power supply voltage of 3.3V to 5V, the critical threshold voltage is the same level as the potential of the above nodes (a) and (b), which cannot circulate enough. The current causes deterioration of the power input characteristics or stability. Especially when the power is turned on, the potentials of nodes (a) and (b) are 0V, the differential amplifier cannot operate, and the reference voltage V r e f may not rise. In this embodiment, the lower voltages of the above nodes (a) and (b) are borne by the P-channel MOSFETs MP1 and MP2, so even when the critical threshold voltages of the MOSFETs MP1 and MP2 are set to be high, sufficient power can be ensured. The voltage between the gate and the drain can flow more current, so the characteristics and stability of the power input can be improved. Since the reference voltage V r e f is generated based on the ground potential V S S, it is necessary to connect the base or emitter terminal of the bipolar transistor to the ground potential V S S. In order to operate at low power voltage, P channel type is required:--------..... I---. ^^ 1--n---- I ------- (Please read the precautions on the back before filling in this page) This paper size is applicable to China Standards for Households (CNS) A4 (210X297 mm) -58- Printed by A7 ________B7_ 2. Description of the invention (56) Driver of MOSFET. If it is driven by a common P-channel type MO S F E T input current mirror load type amplifier, it will not be able to output a sufficient level and the P-channel type MOS cannot be cut off. Therefore, in this embodiment, in order to solve this problem, a two-terminal push-type conversion circuit is provided to ensure a sufficient level. That is, between the drain of the P-channel MOSFET MP 1 constituting one of the differential amplifiers and the circuit ground potential, an N-channel MOSFET Q80 in the form of a diode is connected to the N-channel type with which it forms a current mirror M0SFETQ81. This MOSFET Q81 is used to drive a P-channel type MOSFET Q82, which is a diode provided on the power supply voltage side. Between the drain of the other P-channel MOS FET MP 2 constituting the differential amplifier and the circuit ground potential, an N-channel MOSFET Q83 in the form of a diode and an N-channel MOSFET in the form of a current mirror are also connected. Q84. The drain of the MOSFET Q84 and the drain of the P-channel MOS FET Q8 5 connected to the P-channel MOSFET Q8 2 to form a current mirror are connected to form a two-terminal push-pull conversion circuit. The push-pull circuit is used to drive the P-channel MOSFET MP3 and the above-mentioned transistors T3 and T4. In addition, the P-channel MOSFET Q87 is often connected to the ground potential of the circuit as a resistance element, and has the function of increasing the potential of nodes (a) and (b) when the power is turned on. Therefore, the ohmic resistance is set For great. In this embodiment, even if the critical threshold voltage of MO S F E T is large, the paper size is applicable to China National Standard (CNS) A4 (210X29 * 7mm)

In I ! I ! - —1 I - - - - ,. 1 - I - __==I----- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印«. A7 _______B7_ 五、發明説明（57 ) 亦可由極低之電源電壓穩定地動作β又，電源投入時之上 昇快，穩定性高。 圖3 3爲本發明之電源電路之另一實施例之電路圖。 此實施例中，係令使充電泵電路動作之振盪脈衝之頻率對 應於負載電流而變化者。 充電泵電路，爲減低消費電流可考慮設定成振盪電路 之頻率動作時及待機時之2種類。但是，此種構成時，需 配合各個模式之最大電流來決定振盪頻率。如上述般，以 低電源電壓動作之電路中，爲求高速動作化需降低 M〇 S F Ε Τ之臨界値電壓。因此，待機狀態等電路未動 作時，亦即即使在〇 F F狀態之Μ 0 S F Ε Τ亦流通較大 之臨界漏電流。該電流，相對於溫度係呈指數函數變化， 故需配合將振盪頻率設爲較高，如此則消費電流變成大於 必要以上，此爲問題。 本實施例中，於形成昇壓電壓V C Η之Ρ通道型輸出 MOSFET Ml並接Ρ通道型電流檢測用之 MOSFET M2。於該MOSFET M2形成與輸 出MOSFET Ml之尺寸比K對應之檢測電流ΚΙL ，使該電流Κ I L流經二極體形態之Ν通道型 MOSFET M3將與之對應之電壓信號CFB供至振 盪電路，以使振盪頻率連續變化。即，控制振盪電路使對 應於檢測電流ΚIL之增加而使振盪頻率變高。 圖3 4爲上述圖3 3之實施例電路所用振盪電路之一 實施例之電路圖。振盪電路’係利用將換流器電路縱向連 本紙張尺度適用中國國家標準（CNS > A4规格（210X 297公釐）_ ρ〇 . ^^1· 1^1 I m ·*RHI n· ^n· \ J U3 ，T (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（58 ) 接成環狀之環狀振盪器’流通各換流器電路之動作電流的 N通道型MOSFET M5〜M9 ’係與檢測上述電流 之N通道型MOSFET M3設成成電流鏡形態。亦即 ，於各MOSFET M5〜M9之閘極供給有信號 C F B ° 藉由閘極供給有C F B之N通道型MO S F E T M4轉換成a I L之電流，並使其流經二極體形態之P通 道型MOSFET M10，其與流通動作電流於各換流 器電路之P通道型MOSFET Ml 1〜Ml 5設定成 電流鏡形態，對應於信號C F B來控制各換流器電路之延 遲時間，使與電流之增加成反比例來變化延遲時間’以控 制振盪頻率。 當上述電源電路之負載電流I L增加時，振盪頻率亦 變高，單位時間之充電泵次數增加，電源電路具對應於負 載電流增加之電流供給能力。此時，振盪輸出脈衝之任務 比大致保持一定，故充電泵電路之效率亦大致一定。 經濟部中央樣準局員工消费合作杜印製 依本實施例，則當MO S F E T之臨界値電壓變低’ 或因高溫負載電流增加時，輸入充電泵電路之振盪脈衝之 振盪頻率亦對應著自動變高，故不會有電流供給能力不足 之情況。又，低溫時振盪頻率自動變低以減低消費電流， 故極適用於要求消費電流之攜帶用電子機器搭載之電源電 路。 上述實施例中，係以昇壓電路爲例具體說明。但亦可 適用於形成負電壓之負充電泵電路。 -61 -In I! I!-—1 I----,. 1-I-__ == I ----- (Please read the notes on the back before filling out this page) Central Standard Bureau of the Ministry of Economic Affairs Seal «. A7 _______B7_ V. Description of the invention (57) It can also operate stably from extremely low power voltage β. It also rises quickly when power is turned on and has high stability. FIG. 33 is a circuit diagram of another embodiment of the power supply circuit of the present invention. In this embodiment, the frequency of the oscillation pulse that causes the charge pump circuit to operate is changed in accordance with the load current. To reduce the consumption current, the charge pump circuit can be set to two types: the frequency of the oscillation circuit and the standby mode. However, with this configuration, the maximum current of each mode needs to be used to determine the oscillation frequency. As described above, in a circuit operating with a low power supply voltage, in order to achieve high-speed operation, it is necessary to reduce the critical threshold voltage of MOS F E T. Therefore, when the circuit such as the standby state is not operating, that is, even if the M 0 S F ET in the 0 F F state, a large critical leakage current flows. This current changes exponentially with respect to temperature, so it is necessary to set the oscillation frequency to a higher value, so that the consumption current becomes larger than necessary, which is a problem. In this embodiment, the P-channel type output MOSFET M1 that forms the boosted voltage V CC is connected in parallel with the MOSFET M2 for the P-channel type current detection. A detection current KIL corresponding to the size ratio K of the output MOSFET M1 is formed on the MOSFET M2, and the current K IL flows through the N-channel MOSFET M3 in the form of a diode, and the corresponding voltage signal CFB is supplied to the oscillating circuit. Make the oscillation frequency continuously change. That is, the oscillation circuit is controlled to increase the oscillation frequency in response to an increase in the detection current KIL. Fig. 34 is a circuit diagram of an embodiment of an oscillation circuit used in the circuit of the embodiment of Fig. 33 described above. The oscillating circuit is based on the vertical connection of the inverter circuit to the paper size. The Chinese national standard (CNS > A4 specification (210X 297 mm)) _ ρ〇. ^^ 1 · 1 ^ 1 I m · * RHI n · ^ n · \ J U3, T (Please read the notes on the back before filling in this page) A7 B7 V. Description of the invention (58) Ring oscillator connected in a ring 'N of the operating current of each inverter circuit The channel-type MOSFETs M5 to M9 are formed in a current mirror form with the N-channel-type MOSFET M3 that detects the above-mentioned current. That is, a signal CFB is supplied to the gates of each of the MOSFETs M5 to M9. The N-channel type MO SFET M4 is converted into a IL current and made to flow through the diode-shaped P-channel type MOSFET M10, and the P-channel type MOSFET Ml 1 ~ Ml 5 which flows the operating current in each converter circuit Set to the current mirror shape, corresponding to the signal CFB to control the delay time of each converter circuit, so that the delay time is changed in inverse proportion to the increase in current to control the oscillation frequency. When the load current IL of the power supply circuit increases, the oscillation The frequency also becomes higher, and the charge pump times per unit time As the number increases, the power supply circuit has a current supply capability corresponding to an increase in load current. At this time, the duty ratio of the oscillating output pulse remains approximately constant, so the efficiency of the charge pump circuit is also approximately constant. Employees' cooperation cooperation of the Central Prototype Bureau of the Ministry of Economic Affairs According to this embodiment, when the critical threshold voltage of the MO SFET becomes lower or when the high-temperature load current increases, the oscillation frequency of the oscillation pulse input to the charge pump circuit also automatically increases, so there will be no insufficient current supply capacity. In addition, the oscillation frequency is automatically lowered at low temperature to reduce the consumption current, so it is very suitable for the power supply circuit mounted on the portable electronic device that requires the consumption current. In the above embodiment, the step-up circuit is taken as an example for specific explanation. However, it can also be applied to a negative charge pump circuit that forms a negative voltage.

In I 111. m 1^1 ^^1 1^1 U3 、T (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央揉準局貝工消费合作杜印製 A7 B7 五、發明説明（59 ) 圖3 5爲本發明之輸出電路之一實施例之電路圖。此 實施例，係適合於可減低漏電流、增強驅動能力之推挽式 輸出電路。此實施例電路，和圖1之感測放大器驅動電路 同樣，爲增強驅動能力而將N通道型驅動MO S F E T M01及P通道型驅動MOSFET M02設定成低臨 界値電壓者。因此，爲減低該MOSFET M01或 M0 2爲0 F F狀態時之臨界漏電流所導致流通於兩 MOSFET M01與M02之直流電流（貫通電流） ，而設有形成輸入信號之位準轉換電路L S N及L S P， 俾使供給於該MOSFET M01及M02之閘極之 〇 F F狀態時之源•閘極間成爲逆偏壓狀態。 一方之位準轉換電路L SN，係接受VS S — VDD 之輸入信號，轉換成VDD — VNN位準據此則於 VNN之輸出狀態下，於MOSFET M01之閘極與 源極間施加有VNN — V S S之逆偏壓。另一方之位準轉 換電路LSP，係接受VSS-VDD之輸入信號，並轉 換爲VCH-VS S之位準。據此則於VCH之輸出狀態 下，於MOSFET M02之閘極與源極間，施加有 VDD — VCH之逆偏壓。 上述V D D亦可爲半導體積體電路裝置之內部所形成 者，或直接使用外部端子供給之動作電壓。 此實施例中，於CMOS (推挽）電路係設計成，縮 小輸出M〇 S F E T之臨界値電壓以增強驅動能力，並使 用位準轉換電路作爲驅動電路，使設定成0 F F狀態之信 n - - ί :- I -I I I I— . In I— -is n (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度遑用中國國家橾準（CNS ) A4规格（210X297公釐） -62- 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（60 ) 號位準將MOSFET閘極、源極間設定爲逆偏壓狀態’ 據此來抑制臨界漏電流所引起之貫通電流。因此，極適用 於3 V以下低電壓動作之電路或系統。 圖3 6爲本發明之輸出電路適用於輸出緩衝器之一實 施例之電路圖。此實施例之輸出緩衝器，亦可增強驅動能 力之同時，抑制臨界漏電流導致之貫通電流。此實施例中 ，於位準轉換電路LSP與LSN，輸出MOSFET Μ〇2與Μ 0 1之間之間***電阻R g 1及R g 2 ，閘極 保護MOSFET ME2及ME1。 上述電阻Rgl、Rg2，係爲增長驅動 MO S F E T之閘極電壓之變化時間，使輸出之上昇及下 降波形鈍化以防止上沖（overshoot)或下沖（undershoot) 者》 閘極保護MOSFET ME 1及ME2，係作爲防 止當輸出端D 0由外部施加高電壓時輸出MO S F E T MO 1及M0 2之閘極絕緣膜之破壞。亦即，當輸出端 DO之電位大於電源電壓VDD時，P通道型 MOSFET ME1成爲ON狀態，使輸出 MOSFET M02之閘極與輸出端DO短路，當輸出 端D 0之電位成爲接地電位V S S以下時，N通道型 MOSFET ME2成爲ON狀態，使輸出 MOSFET M01之閘極與輸出端DO短路，俾使高 電壓不施加於閘極絕緣膜。 此實施例中，對上述位準轉換電路L SN與L S P， 本紙張尺度適用中國固家揉準（CNS ) A4規格（210X297公釐） -63- ----------裝-- (請先聞讀背面之注意事項再填寫本頁) 訂 A7 B7 五、發明説明（61 ) 介由以輸出控制信號Η I Z控制之閘電路或換流器電路等 分別輸入輸入信號。藉由該控制電路，來防止輸出緩衝器 之貫通電流之同時，使用輸出MOSFET Μ01及 Μ 0 2設爲0 F F狀態，設爲輸出高阻抗狀態。 上述本實施電路中，於推挽式輸出緩衝器，可增強驅 動能力之同時，抑制臨界漏電流引起之貫通電路。因此， 適合於3 V以下低電壓動作之電路或系統》 上述實施例所獲得作用效果如下。 (1)於具有以外部端子所供給電源電壓作動作之第 1電路方塊，及以電源電路形成之內部電壓作動作之第2 電路方塊的半導體積體電路裝置中，以充電泵電路形成絕 對値大於上述內部電壓之較大電壓，於該輸出電壓與內部 電壓之間設可變阻抗裝置，藉以充電泵電路所形成輸出電 壓爲動作電壓之差動放大電路來比較基準電壓與內部電壓 ，據以控制可變阻抗裝置俾使兩者一致並據以形成內部電 壓，如此即可產生穩定之任意之內部電壓。 經濟部中央揉準局負工消费合作社印裝 (請先閲讀背面之注意事項再填寫本頁) (2 )上述電源電路設2種類，以藉該電源電路可穩 定產生與外部端所供給電壓同極性之絕對値大之電壓，及 與外部端子所供給電壓爲不同極性之電壓。 (3)以上述電源電路形成動態型RAM之字元線選 擇位準及負電壓之非選擇位準，則可改善記億格之資料保 持特性，確保元件之高信賴性。 (4 )上述電源電路所設之差動放大電路，可藉由將 以可維持內部電壓程度之較小電流常時動作者，及以內部 本&張尺度適用中國國家橾準（CNS > A4規格（210X297公釐） 經濟部中央橾準局員工消费合作社印製 A7 B7 一 ___ 五、發明説明（62 ) 電路設爲動作狀態時爲維持內部電壓之必要之較大電流作 動者予以組合，則可以低消費電力形成必要之電壓。 (5) 將上述第1電源電路之充電泵電路所形成輸出 電壓，施加於形成有動態型記億格之P型井領域所形成深 度較深之N型井領域上，則可利用該處之寄生容量，同時 ’不需採取閂鎖昇壓（Latch-up )之特別對策。 (6) 上述第2電源電路之充電泵電路所形成輸出電 壓，可作爲基板之負偏壓供至形成有動態型記憶格之P型 井領域，因此，除利用接合容量之外，可改善α線所引起 之Software Error (系統錯誤），且電路之共用可簡化電路 規模。 (7) 上述內部電路係由：對上述外部端子所供給電 源電壓降壓以形成定電壓之第3電源電路，及以該第3電 源電路所形降壓電壓作動作之電路部分構成，如此即可在 不受外部電源影響下使內部電路穩定動作。 (8 )構成上述內部電路，輸出上述第1電源電路所 形成Η位準，及第2電源電路所形成L位準之輸出電路中 ，將用於輸出上述第1電源電路所形成內部電壓之第1導 電型輸出MO S F Ε Τ，及對用於輸出上述第2電源電路 所形成內部電壓之第2導電型輸出MO S F Ε Τ ’閘極分 別供給有接地電位之第1導電型Μ 0 S F Ε Τ ’及閘極供 給有內部電壓之第2導電型MO S F Ε Τ分別串接設置’ 則可將施加於各MO S F Ε Τ之電壓分割，可確保高信賴 性。 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） n- I I j m - - , n^i ^^1 I - —I i. K ^ ^ (請先閲讀背面之注意事項再填寫本頁) -65- 經濟部中央標準局貝工消费合作社印製 A7 __B7_____ 五、發明説明（63 ) (9)用以形成驅動信號俾供至構成上述輸出電路之 第1導電型輸出MOS F ET之閘極的第1驅動電路，係 使用將以上述電源電壓或內部降壓電壓及電路之接地電位 動作之內部電路所形成輸入信號轉換爲上述第1電源電路 之輸出電壓及電路之接地電位對應之第1信號位準的第1 位準轉換電路，用以形成驅動信號俾供至構成上述輸出電 路之第2導電型輸出MO S F E T之閘極的第2驅動電路 ，係使用將上述輸入信號轉換爲上述內部電壓及第2電源 電路之輸出電壓對應之第2信號位準的第2位準轉換電路 ，如此則可抑制施加於輸出MO S F E T之電壓，可確保 高信賴性。 (1 0 )構成動態型記憶格之位址選擇Μ ◦ S F E T 之閘極絕緣膜，及形成字元線之選擇信號的輸出 MO S F Ε Τ之閘極絕緣膜係設定爲相同之第1膜厚，感 測放大器及位址選擇電路之構成之MO S F Ε Τ之閘極絕 緣膜係設定爲較上述第1膜厚薄之第2膜厚，如此則可實 現高信賴性及動作之高速化》 (11)上述內部電路係由幾何學選出之多數電路所 構成，上述電源電路係由：與上述多數電路一對一對應， 用於產生與上述外部端子供給之電壓爲同極性且絕對値大 之電壓的多數形成之第1電源電路，及用於產生與上述外 部端子所供給電壓爲不同極性之多數形成之第2電源電路 所構成，使上述第1及第2充電泵電路共用，鄰接上述多 數電路分別設多數可變阻抗裝置及差動放大電路，如此則 —^1 ^^1» H— 1 - - m i In » In ^^^1 1^1 0¾ ，vs (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） -66- 經濟部中央標準局貝工消费合作杜印製 A7 B7 五、發明説明（64 ) 可實現電路之簡略化並使效率好之動作電壓之供給爲可能 〇 (1 2 )將動態型記憶格多數個以矩陣狀構成之記億 陣列分割成多數組，上述第1及第2電源電路，令第1及 第2充電泵電路共用，對應上述各組之記憶陣列設多數個 可變阻抗裝置及差動放大電路，如此即可實現電路簡略化 之同時，實現效率佳之動作電壓之供給，並增大記憶容量 〇 (1 3 )上述內部電路，適用於包含中央處理裝置， 快閃式E P R Ο Μ、類比/數位轉換電路之單晶片微電腦 ，藉由上述第1電源電路及第2電源電路來形成快閃式 E P R 0Μ及類比/數位轉換電路之動作用之正負電壓， 則於晶片上之記億資訊之抹除或在不使用耦合電容器之狀 態下，可直接輸入類比信號。 (1 4 )上述內部電路係具備：用於輸出上述電源電 壓或其以下之電壓的Ρ通道型MO S F Ε Τ ;及輸出電路 之接地電位的Ν通道型MOSFET;及藉由第1電源電 路之輸出電壓或充電泵輸出電壓使Ρ通道型MO S F Ε Τ 設爲OF F狀態時之信號位準所用，藉由上述第2電源電 路之輸出電壓或充電泵輸出電壓使N通道型MO S F Ε T 設爲0 F F狀態時之信號位準所用之電路；如此則使 MOSFET在源、閘極間施加逆偏壓狀態下設爲OFF 狀態，可大幅降低臨界漏電流。 (1 5 )上述基準電壓係以電壓電流轉換電路將射極 本紙張尺度逍用中國國家梯準（CNS ) A4規格（210X297公釐） -67- ----------裝-- (請先閲讀背面之注意事項再填寫本頁) 、tr 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（65 ) 電流密度差所對應形成之矽禁帶寬度予以利用所形成之定 電壓轉換爲定電流； 令上述定電流介由1至多數形成之電流鏡電路而轉換 成來自構成上述電源電路之施加有充電泵電壓之電流鏡電 路的定電流並流經電阻器之一端，令該電阻器之另一端連 接於特定之內部電壓端子，如此即可使高精度及高穩定之 電壓設定爲可能。 (1 6 )射極面積形成較小，共接之基極及集極係接 於電路接地電位的第1電晶體；令其射極接具較大電阻値 之第1電阻器之一端，射極面積形成較大，共接之基極及 集極係接於電路接地電位的第2電晶體；令其射極接與上 述第1電阻器之電阻値比較可忽視程度之第2電阻器之一 端，令另一端接與上述第1電阻器具大略相同電阻値之第 3電阻器之一端，藉由包含用以接受上述第1電晶體之射 極電位及第2電阻器與第3電阻器之連接點之電位之P通 道型差動MO S F E T的差動放大電路，以形成使上述兩 電壓相同之電壓，並供至與上述第1電阻器及第3電阻器 之共接之另一端以形成上述定電壓，如此則可形成穩定之 低電壓之定電壓。 (1 7 )於上述電源電路中，構成上述可變阻抗裝置 之MO S F E T之閘極與源極爲共接，設有藉由其尺寸比 所對應之較小Μ 0 S F E T來形成負載電流對應之感測電 流的電流感測MO S F Ε Τ，對應於上述感測電流使振盪 頻率變化之振盪電路所形成之振盪脈衝，來控制上述充電 ^ m nfBV 0¾ 、ve (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X2.97公釐） -68- 經濟部中央標準局貝工消费合作社印製 A7 ____B7___ 五、發明説明（66 ) 泵電路之泵激（pumping)週期，如此即可提昇充電泵電路 之效率。 產業上之利用可能性 _ 本發明可廣泛利用於，如上述般於動態型R A Μ或單 晶片微電腦等，相對於外部端子所供給電壓，以與之爲不 同之內部電壓爲必要之各種半導體積體電路裝置。 圖面之簡單說明 圖1 :本發明之動態型R A Μ之記憶陣列部之一實施 例之槪略電路圖。 圖2 :本發明之動態型RAM之電源電路部之一實施 例之槪略電路圖。 圖3 :本發明之動態型RAM之槪略動作說明用之波 形圖。 圖4:本發明之動態型RAM之一實施例之槪略元件 斷面圖》 圖5:本發明之動態型RAM之另一實施例之槪略元 件斷面圖。 圖6:本發明之動態型RAM之字元驅動器WD之一 實施例之電路圖。 圖7 :圖6之字元驅動器之動作說明用之波形圖。 圖8 :本發明之動態型RAM中之字元驅動器WD之 另一實施例之電路圖。 本紙張尺度適用中國固家樑準（CNS ) A4規格（210X297公釐） ^ m ^^1 -- - I I - --—^ V 士义 —11- - - - - - I - I n Τ» 0¾ 、τ (請先閱讀背面之注意事項再填寫本頁) B7 經濟部中央標準局貝工消費合作杜印製 五、發明説明（67 ) 圖9:圖8之字元驅動器之動作說明用之波形圖。 圖10:本發明適用於階層化字元驅動器時之一實施 例之構成圖。 圖11:圖10之階層化字元驅動方式對應之副字元 驅動器SDRV之一實施例之電路圖。 圖12:圖11之副字元選擇線及主字元線之驅動用 驅動器之一實施例之電路圖。 圖13:圖12之電路動作說明用之波形圖。 圖14:本發明之動態型RAM中之電源電路之另一 實施例之槪略方塊圖。 圖15:階層化字元驅動方式對應之副字元選擇線用 驅動器及副字元驅動器之另一實施例之電路圖。 圖16:圖15之電路動作說明之波形圖。 圖17:基準電壓產生電路之一實施例之電路圖。 圖18:圖2之定電壓產生電路RGP之一實施例之 電路圖。 圖19:圖2之定電壓產生電路RGN之一實施例之 電路圖。 圖20:圖2之VBB用充電泵電路7之一實施例之 電路圖.。 圖21:圖2之VBB用振盪電路6之一實施例之電 路圖。 圖2 2 :圖2之VBB用位準感測器8之一實施例之 電路圖。 ----------^-- (請先閲讀背面之注意事項再填寫本頁)In I 111. m 1 ^ 1 ^^ 1 1 ^ 1 U3, T (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Central Ministry of Economic Affairs A7 B7 printed by Zhuhai Bureau Consumer Cooperative Co., Ltd. 5. Description of the invention (59) Figure 35 is a circuit diagram of one embodiment of the output circuit of the present invention. This embodiment is suitable for a push-pull output circuit which can reduce the leakage current and enhance the driving ability. The circuit of this embodiment is the same as the driving circuit of the sense amplifier of FIG. 1. In order to enhance the driving ability, the N-channel type driving MOSFET M01 and P-channel type driving MOSFET M02 are set to a low threshold voltage. Therefore, in order to reduce the direct current (through current) flowing through the two MOSFETs M01 and M02 caused by the critical leakage current when the MOSFET M01 or M0 2 is in the 0 FF state, level conversion circuits LSN and LSP that form an input signal are provided. , The source and gate between the MOSFETs M01 and M02 supplied in the 0FF state are reverse biased. One level conversion circuit L SN accepts the input signal of V S — VDD and converts it to VDD — VNN level. Based on the VNN output state, VNN is applied between the gate and source of MOSFET M01 — VSS reverse bias. The other level conversion circuit LSP accepts the input signal of VSS-VDD and converts it to the VCH-VS S level. Accordingly, under the output state of VCH, a reverse bias voltage of VDD-VCH is applied between the gate and source of MOSFET M02. The above V D D may also be formed inside the semiconductor integrated circuit device, or an operating voltage supplied directly from an external terminal. In this embodiment, the CMOS (push-pull) circuit is designed to reduce the threshold voltage of the output MOSFET to enhance the driving ability, and use a level conversion circuit as the driving circuit to set the letter n to 0 FF state n- -ί:-I -IIII—. In I— -is n (Please read the precautions on the back before filling this page) This paper size is in accordance with China National Standard (CNS) A4 (210X297mm) -62- Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A7 B7 V. Description of invention (60) The MOSFET gate and source are set to a reverse bias state 'according to this to suppress the through current caused by the critical leakage current. Therefore, it is very suitable for circuits or systems with low voltage operation below 3 V. Fig. 36 is a circuit diagram of an embodiment in which the output circuit of the present invention is applicable to an output buffer. The output buffer of this embodiment can also enhance the driving capability and suppress the shoot-through current caused by the critical leakage current. In this embodiment, resistors Rg1 and Rg2 are inserted between the level conversion circuit LSP and LSN, and between the output MOSFETs Mo2 and M01, and the gates protect the MOSFETs ME2 and ME1. The above-mentioned resistors Rgl and Rg2 are to increase the change time of the gate voltage of the driving MO SFET, to passivate the rising and falling waveforms of the output to prevent overshoot or undershoot. Gate protection MOSFET ME 1 and ME2 is to prevent the destruction of the gate insulating film of the outputs MO SFETs MO 1 and M0 2 when the output terminal D 0 is applied with a high voltage from the outside. That is, when the potential of the output terminal DO is greater than the power supply voltage VDD, the P-channel MOSFET ME1 is turned on, and the gate of the output MOSFET M02 is short-circuited to the output terminal DO. When the potential of the output terminal D 0 becomes below the ground potential VSS The N-channel MOSFET ME2 is turned on, shorting the gate of the output MOSFET M01 and the output terminal DO, so that high voltage is not applied to the gate insulating film. In this embodiment, for the above-mentioned level conversion circuits L SN and LSP, the paper size is applicable to China Gujiazheng (CNS) A4 specification (210X297 mm) -63- ---------- install- -(Please read the precautions on the back before filling out this page) Order A7 B7 V. Description of the invention (61) Input the input signals respectively through the output control signal Η IZ controlled gate circuit or inverter circuit. This control circuit prevents the through current of the output buffer, and sets the output MOSFETs M01 and M 0 2 to the 0 F F state and the output high impedance state. In the above-mentioned implementation circuit, the push-pull type output buffer can enhance the driving capability while suppressing the penetrating circuit caused by the critical leakage current. Therefore, a circuit or system suitable for low-voltage operation below 3 V is described below. (1) In a semiconductor integrated circuit device having a first circuit block operated by a power supply voltage supplied from an external terminal and a second circuit block operated by an internal voltage formed by a power supply circuit, an absolute pump circuit is formed by a charge pump circuit. A larger voltage than the above-mentioned internal voltage. A variable impedance device is provided between the output voltage and the internal voltage. The reference voltage and the internal voltage are compared by using a differential amplifier circuit with the output voltage formed by the charge pump circuit as the operating voltage. Control the variable impedance device so that the two are consistent and form an internal voltage accordingly, so that a stable arbitrary internal voltage can be generated. Printed by the Central Government Bureau of the Ministry of Economic Affairs, Consumer Cooperatives (please read the precautions on the back before filling out this page) (2) The above power supply circuit is provided in 2 types, so that the power supply circuit can stably generate the same voltage as the external supply voltage Absolutely large voltage of polarity and voltage with a different polarity from the voltage supplied by the external terminal. (3) The word line selection level of the dynamic RAM and the non-selection level of the negative voltage are formed by the above-mentioned power supply circuit, which can improve the data retention characteristics of the billion grid and ensure the high reliability of the component. (4) The differential amplifier circuit set in the above power supply circuit can be operated by a small current that can maintain the internal voltage level, and the internal & Zhang standard is applicable to China National Standards (CNS > A4 Specifications (210X297 mm) A7 B7 printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs ___ V. Description of the Invention (62) When the circuit is set to the operating state, the large current actuators necessary to maintain the internal voltage are combined, (5) The output voltage formed by the charge pump circuit of the first power supply circuit described above is applied to the deeper N-type formed in the field of P-type wells with a dynamic pattern of 100 million grids. In the field of wells, you can use the parasitic capacity there, and at the same time, "special measures for latch-up are not required." (6) The output voltage formed by the charge pump circuit of the second power supply circuit can be used as The negative bias voltage of the substrate is supplied to the P-well area where a dynamic memory cell is formed. Therefore, in addition to using the joint capacity, the Software Error (system error) caused by the alpha line can be improved, and the common circuit can be used. (7) Simplify the circuit scale. (7) The above-mentioned internal circuit consists of a third power supply circuit that steps down the power supply voltage supplied from the external terminals to form a constant voltage, and a circuit part that operates with the step-down voltage formed by the third power supply circuit. It is structured so that the internal circuit can be operated stably without being affected by the external power supply. (8) The internal circuit is configured to output the level formed by the first power supply circuit and the L level output formed by the second power supply circuit. In the circuit, a first conductive type output MO SF Ε T for outputting the internal voltage formed by the first power supply circuit and a second conductive type output MO SF Ε for outputting the internal voltage formed by the second power supply circuit Τ 'the gates are supplied with the first conductive type M 0 SF Ε Τ ′ and the gates are supplied with the internal voltage MO SF Ε Τ respectively, which can be connected in series, and can be applied to each MO SF Ε The voltage division of Τ can ensure high reliability. The paper size is applicable to China National Standard (CNS) A4 (210X297 mm) n- II jm--, n ^ i ^^ 1 I-—I i. K ^ ^ (Please read the note on the back first Please fill in this page again) -65- Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative A7 __B7_____ V. Description of the invention (63) (9) Used to form a driving signal for the first conductivity type output constituting the above output circuit The first drive circuit of the gate of the MOS F ET uses an input signal formed by an internal circuit that operates with the above-mentioned power supply voltage or internal step-down voltage and the ground potential of the circuit to convert the output voltage and circuit of the first power supply circuit described above. The first level conversion circuit of the first signal level corresponding to the ground potential is used to form a driving signal to be supplied to the gate of the second conductive type output MO SFET constituting the output circuit. The input signal is converted into the second level conversion circuit of the second signal level corresponding to the internal voltage and the output voltage of the second power supply circuit. In this way, the voltage applied to the output MO SFET can be suppressed, and high reliability can be ensured. (1 0) The address selection M constituting the dynamic memory cell ◦ The gate insulating film of the SFET and the gate insulating film of the output signal MO SF Ε Τ forming the word line are set to the same first film thickness The gate insulation film of MO SF Ε Τ composed of the sense amplifier and the address selection circuit is set to a second film thickness that is thinner than the first film thickness described above, so that high reliability and high-speed operation can be achieved "( 11) The internal circuit is composed of a plurality of circuits selected geometrically, and the power supply circuit is one-to-one corresponding to the majority of the circuits, and is used to generate a voltage of the same polarity and absolute magnitude as the voltage supplied from the external terminal. A first power supply circuit formed by a plurality of electrodes and a second power supply circuit formed by a plurality of electrodes having a different polarity from the voltage supplied from the external terminal. The first and second charge pump circuits are shared and adjacent to the majority circuit. Most variable impedance devices and differential amplifier circuits are set separately, so — —1 ^^ 1 »H— 1--mi In» In ^^^ 1 1 ^ 1 0¾, vs (Please read the precautions on the back before (Fill in this page) Applicable to China National Standard (CNS) A4 specification (210X297mm) -66- Printed by Alabaster Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs, printed A7 B7 V. Description of Invention (64) The circuit can be simplified and efficient. The supply of the operating voltage is possible. (1 2) The dynamic memory cells are divided into a plurality of arrays of a multi-matrix array composed of a matrix. The above-mentioned first and second power supply circuits share the first and second charge pump circuits. A plurality of variable impedance devices and differential amplifier circuits are provided corresponding to the memory arrays of the above groups, so that the circuit can be simplified, the operation voltage can be supplied with high efficiency, and the memory capacity can be increased. (1 3) Internal circuit, suitable for single-chip microcomputer including central processing device, flash EPR 0 μM, analog / digital conversion circuit, using the above first power circuit and second power circuit to form flash EPR 0M and analog / digital The positive and negative voltages used in the operation of the conversion circuit can be directly inputted by analog signals when the billions of information on the chip is erased or when a coupling capacitor is not used. (1 4) The internal circuit is provided with a P-channel type MO SF Ε Τ for outputting the power supply voltage or lower; an N-channel type MOSFET of a ground potential of the output circuit; and The output voltage or charge pump output voltage is used for the signal level when the P-channel type MO SF Ε Τ is set to the OF F state. The output voltage of the second power circuit or the charge pump output voltage is used to make the N-channel type MO SF Ε T The circuit used for the signal level when it is set to 0 FF state; in this way, the MOSFET is set to the OFF state when a reverse bias is applied between the source and the gate, which can greatly reduce the critical leakage current. (1 5) The above reference voltage is a voltage-current conversion circuit that uses the paper size of the emitter to use the Chinese National Standard (CNS) A4 specification (210X297 mm) -67- ---------- install- -(Please read the precautions on the back before filling this page), tr Printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by Aigong Consumer Cooperative A7 B7 V. Description of the invention (65) The silicon forbidden band width corresponding to the current density difference shall be used. The formed constant voltage is converted into a constant current; the above-mentioned constant current is converted into a constant current from a current mirror circuit with a charge pump voltage applied to the power supply circuit through a current mirror circuit formed by 1 to a majority and flows through the resistor. At one end, the other end of the resistor is connected to a specific internal voltage terminal, so that a high-precision and highly stable voltage setting can be made possible. (1 6) The emitter area is small, and the base and collector connected in common are connected to the first transistor of the circuit ground potential; the emitter is connected to one end of the first resistor with a larger resistance, the emitter The electrode area is large, and the common base and collector are connected to the second transistor of the circuit ground potential; the emitter is connected to the second resistor of the second resistor which is negligible compared with the resistance of the first resistor. One end, so that the other end is connected to one end of a third resistor having approximately the same resistance as the first resistance device, and includes an emitter potential for receiving the first transistor and the second resistor and the third resistor. The P-channel type differential MO SFET differential amplifier circuit at the potential of the connection point is formed to make the above two voltages the same voltage, and is supplied to the other end connected in common with the first resistor and the third resistor to form The above constant voltage can form a stable low voltage constant voltage. (1 7) In the above power supply circuit, the gate and source of the MO SFET constituting the variable impedance device are connected in common, and a sense of load current correspondence is formed by its size being smaller than the corresponding M 0 SFET. The current sensing current sensing MO SF Ε Τ corresponds to the oscillating pulse formed by the oscillating circuit whose oscillating frequency is changed by the above-mentioned sensing current to control the above charging ^ m nfBV 0¾, ve (Please read the precautions on the back before filling (This page) This paper size is applicable to China National Standard (CNS) A4 specification (210X2.97mm) -68- Printed by A7 Consumer Products Cooperative of Central Standards Bureau of the Ministry of Economic Affairs A7 ____B7___ 5. Description of the invention (66) Pump circuit pump The pumping cycle can improve the efficiency of the charge pump circuit. Industrial Applicability _ The present invention can be widely used in various semiconductor devices, such as dynamic RAMs or single-chip microcomputers, which require an internal voltage different from the voltage supplied from external terminals, as described above. Body circuit device. Brief Description of the Drawings Figure 1: A schematic circuit diagram of an embodiment of the dynamic RAM memory array section of the present invention. FIG. 2 is a schematic circuit diagram of an embodiment of a power circuit section of a dynamic RAM of the present invention. Fig. 3 is a waveform diagram for explaining a rough operation of the dynamic RAM of the present invention. FIG. 4 is a schematic cross-sectional view of an embodiment of a dynamic RAM of the present invention. FIG. 5 is a schematic cross-sectional view of an embodiment of a dynamic RAM of the present invention. Fig. 6 is a circuit diagram of an embodiment of a word driver WD of a dynamic RAM of the present invention. Fig. 7: A waveform diagram for explaining the operation of the character driver of Fig. 6. Fig. 8 is a circuit diagram of another embodiment of the word driver WD in the dynamic RAM of the present invention. This paper size applies to China Gujialiang Standard (CNS) A4 specification (210X297 mm) ^ m ^^ 1--II---- ^ V Shiyi—11------I-I n Τ » 0¾, τ (please read the precautions on the back before filling this page) B7 Printed by Shelley Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (67) Figure 9: Used to explain the operation of the character driver in Figure 8 Wave chart. Fig. 10 is a structural diagram of an embodiment when the present invention is applied to a hierarchical character driver. Fig. 11 is a circuit diagram of an embodiment of the sub-character driver SDRV corresponding to the hierarchical character driving method of Fig. 10. Fig. 12 is a circuit diagram of an embodiment of a driver for driving the sub-character selection line and the main character line of Fig. 11; Fig. 13: A waveform diagram for explaining the operation of the circuit of Fig. 12. Fig. 14 is a schematic block diagram of another embodiment of a power supply circuit in a dynamic RAM according to the present invention. Fig. 15 is a circuit diagram of another embodiment of a sub-character selection line driver and a sub-character driver corresponding to the hierarchical character driving method. FIG. 16: A waveform diagram illustrating the operation of the circuit of FIG. FIG. 17 is a circuit diagram of an embodiment of a reference voltage generating circuit. Fig. 18 is a circuit diagram of an embodiment of the constant voltage generating circuit RGP of Fig. 2. Fig. 19 is a circuit diagram of an embodiment of the constant voltage generating circuit RGN of Fig. 2. Fig. 20: A circuit diagram of an embodiment of the charge pump circuit 7 for VBB of Fig. 2. Fig. 21 is a circuit diagram of an embodiment of the oscillation circuit 6 for VBB of Fig. 2. Fig. 22: A circuit diagram of an embodiment of the level sensor 8 for VBB of Fig. 2. ---------- ^-(Please read the notes on the back before filling this page)

'1T 本紙張尺度適用中國國家揉準（CNS )人4说格（210X297公釐） -70- 經濟部中央標準局貝工消费合作社印製 A7 B7_ 五、發明説明（68 ) 圖23:圖2之VPP用充電泵電路2之一實施例之 電路圖。 圖24:圖2之VPP用振盪電路1之一實施例之電 路圖。 圖25:圖2之VPP用位準感測器之一實施例之電 路圖。 圖26:本發明之動態型RAM之全體之一實施例之 槪略構成圖。 圖2 7 :本發明之動態型RAM中之字元驅動器之另 一實施例之電路圖。 圖2 8 :本發明之動態型RAM中之外部電壓及內部 電壓VCH與VNN、 VDL之關係說明之一實施例之電 壓特性圖。 圖29:本發明之動態型RAM中之外部電壓及內部 電壓VCH與VNN、 VDL之關係說明之另一實施例之 電壓特性'圖。 圖30:搭載有本發明之電源電路的動態型RAM之 一實施例之槪略設計圖。 圖31:本發明適用之單晶片微電腦之一實施例之方 塊構成圖。 圖3 2 :本發明之基準電壓產生電路之另一實施例之 電路圖。 圖3 3 :本發明之電源電路之另一實施例之電路圖。 圖3 4 :圖3 3之電源電路所用振盪電路之一實施例 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） I- — I I I - I I - I- I ·1 I nig 1- (請先閲讀背面之注意事項再填寫本頁) -71 - A7 B7 五、發明説明（69 ) 之電路圖。 圖3 5 :本發明之輸出電路之一實施例之電路圖。 圖3 6 :本發明之輸出電路適用於輸出緩衝器時之一 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁)'1T This paper size is applicable to China National Standards (CNS) person 4 (210X297 mm) -70- Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7_ 5. Description of the invention (68) Figure 23: Figure 2 A circuit diagram of one embodiment of the VPP charge pump circuit 2. Fig. 24 is a circuit diagram of an embodiment of the oscillation circuit 1 for VPP of Fig. 2. Fig. 25 is a circuit diagram of an embodiment of the level sensor for VPP of Fig. 2. Fig. 26 is a schematic configuration diagram of an embodiment of the entire dynamic RAM of the present invention. Fig. 27 is a circuit diagram of another embodiment of the character driver in the dynamic RAM of the present invention. Fig. 28 is a voltage characteristic diagram of an embodiment illustrating the relationship between the external voltage and the internal voltage VCH and VNN and VDL in the dynamic RAM of the present invention. Fig. 29 is a graph showing the voltage characteristics of another embodiment of the relationship between the external voltage and the internal voltage VCH, VNN, and VDL in the dynamic RAM of the present invention. Fig. 30 is a schematic design diagram of an embodiment of a dynamic RAM equipped with a power supply circuit of the present invention. Fig. 31 is a block diagram of an embodiment of a single-chip microcomputer to which the present invention is applied. Figure 32: A circuit diagram of another embodiment of the reference voltage generating circuit of the present invention. Figure 33: A circuit diagram of another embodiment of the power supply circuit of the present invention. Figure 34: An example of an oscillation circuit used in the power supply circuit of Figure 33 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) I- — III-II-I- I · 1 I nig 1- (Please read the precautions on the back before filling this page) -71-A7 B7 V. Circuit description of the invention description (69). Figure 35: A circuit diagram of an embodiment of the output circuit of the present invention. Figure 36: The output circuit of the present invention is applicable to one of the output buffers. It is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page)

實 施 例之電 路 圖 〇 主 要 元件對 照 表 Μ A C 記 憶 陣 列 W 1 字 元 線 W 2 字 元 線 W 3 字 元 線 b i t 位元 線 / b i 1 t 位 元 線 C s 記 憶 電 容 器 V C H 高 電 壓 V S S 電 路 接 地 電 位 V N N 負 電 壓 V D L 內 部 降 壓 電 壓 s A 感 測 放 大 器 Q 4 N 通 道 型 放 大 Μ 〇 S F E T Q 5 N 通 道 型 放 大 Μ 0 S F E T Q 6 P 通 道 型 放 大 Μ 0 S F E T Q 7 P 通 道 型 放 大 Μ 0 S F E T Q 8 N 通 道 型 電 源 開 關 Μ 0 S F E T Q 9 P 通 道 型 電 源 開 關 Μ 〇 S F E T 本紙張尺度適用中國囷家標準（CNS ) A4規格（210X297公釐） 一 72- 經濟部中央標準局貝工消费合作社印裝 A7 B7五、發明説明（7〇 ) E Q 等化信號 5 A P D 驅動器 XDEC X解碼器 W D 字元驅動器 — A C 陣列控制電路 VPPG 高電壓產生電路 1 振盪電路 2 充電泵電路 3 位準感測器 RGFP 基準電壓產生電路 RGP 定電壓產生電路 4 差動放大電路 V B B G 負電壓產生電路 6 振盪電路 7 負充電泵電路 8 位準感測器 LSP 位準轉換電路 L S N 位準轉換電路 IV1 換流器電路 M W 〇 主字元線 M W i 主字元線 MWD 主字元驅動器 M D R V 0 驅動器 M D R V i 驅動器 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家橾準（CNS ) A4規格（210X297公釐） -73- A7 B7 五、發明説明（71 ) S W L 副字元線 MATO 記憶區塊 ΜΑΤΙ 記憶區塊 S W D 〇 副字元驅動器 ' S W D 1 副字元驅動器 FX0〜FX6 副字元選擇線 A Ν 3 閘電路 A N 4 閘電路 T 1 雙極性電晶體 T 2 雙極性電晶體 I V C Ο N 電壓電流轉換電路 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 C 7 電容 器 C 8 電容 器 C 9 電容 器 C 1 0 電 容 器 Μ c u 單 晶 片 微 電 腦 C P u 中 央 處 理 裝 置 R 0 M 唯 讀 記 憶 體 R A M 隨 機 存取 轉 換 電 路 A / D 類 比 數 位 轉 換 電 路 W D T 監 視 計 時 器 T I M 計時 器 電 路 S c I 序 列 通 訊 介 面 C L K 時 脈 產 生 電 路 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -74- A7 B7 五、發明説明（72 ) P 0 R 電源重置電路 CLKC 時脈控制器 X T A L 水晶振盪器 CPG 時脈產生電路 — H· ϋ· >—.^1 «^ϋ In In I 一穴.ml 111— ^^^1 { m 、ve (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印策 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -75-Circuit diagram of the embodiment 〇 Main component comparison table AC memory array W 1 word line W 2 word line W 3 word line bit bit line / bi 1 t bit line C s memory capacitor VCH high voltage VSS circuit ground potential VNN Negative voltage VDL Internal step-down voltage s A Sense amplifier Q 4 N Channel type amplifier 〇 SFETQ 5 N Channel type amplifier M 0 SFETQ 6 P Channel type amplifier Μ 0 SFETQ 7 P Channel type amplifier Μ 0 SFETQ 8 N Channel type Power switch M 0 SFETQ 9 P Channel-type power switch M 〇SFET This paper size is applicable to the Chinese family standard (CNS) A4 specification (210X297 mm) -72- Printed by the Central Laboratories of the Ministry of Economic Affairs, Peigong Consumer Cooperatives Description of the invention (7〇) EQ equalization signal 5 APD driver XDEC X decoder WD character driver — AC array control circuit VPPG high voltage generation circuit 1 Oscillation circuit 2 Charge pump circuit 3 Level sensor RGFP Reference voltage generation circuit RGP Constant voltage generation circuit 4 Differential amplifier circuit VBBG Negative voltage generation circuit 6 Oscillation circuit 7 Negative charge pump circuit 8 level sensor LSP level Conversion circuit LSN Level conversion circuit IV1 Converter circuit MW 〇 Main character line MW i Main character line MWD Main character driver MDRV 0 Driver MDRV i driver (Please read the precautions on the back before filling this page) This Paper size General China National Standard (CNS) A4 specification (210X297 mm) -73- A7 B7 V. Description of invention (71) SWL sub-character line MATO memory block ΜΑΙ memory block SWD 〇 sub-character driver 'SWD 1 Sub-character driver FX0 ~ FX6 Sub-character selection line A Ν 3 Gate circuit AN 4 Gate circuit T 1 Bipolar transistor T 2 Bipolar transistor IVC 〇 N Voltage and current conversion circuit (please read the precautions on the back first) (Fill in this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy C 7 Capacitor C 8 Capacitor C 9 Capacitor C 1 0 Capacitor Μ cu single chip microcomputer CP u central processing unit R 0 M read-only memory RAM random access conversion circuit A / D analog digital conversion circuit WDT watchdog timer TIM timer circuit S c I serial communication interface CLK clock generation circuit Paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -74- A7 B7 V. Description of invention (72) P 0 R Power reset circuit CLKC Clock controller XTAL Crystal oscillator CPG Clock generation circuit — H · ϋ · > —. ^ 1 «^ ϋ In In I 一 Cavity.ml 111— ^^^ 1 {m ， ve (please read the precautions on the back before filling this page) Employees of the Central Bureau of Standards of the Ministry of Economic Affairs Cooperative printed policy This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -75-

Claims (1)

六、申請專利範圍 1 種半導體積體電路裝置，係具備有： 以外部端子所供給之電源電壓動作，並形成與上述外 部端子所供給電壓爲不同之內部電壓的電源電路；及 施加有上述電源電路所形成內部電壓的內部電路； 上述電源電路係包含有： 用於形成相對於上述內部電壓之絕對値爲較大之電壓 的充電泵電路：及 設於上述充電泵電路所形成輸出電壓與上述內部電壓 之間的可變阻抗裝置；及 以上述充電泵電路所形成輸出電壓爲動作電壓，將上 述必要之內部電壓所對應基準電壓與上述內部電壓作比較 ，並控制上述可變阻抗裝置俾使兩者一致的差動放大電路 〇 2 .如申請專利範圍第1項之半導體積體電路裝置， 其中 上述電源電路係由： 用於產生與上述外部端子所供給電壓爲相同極性且絕 對値大之電壓的第1電源電路；及 經濟部中央標隼局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 用於產生與上述外部端子所供給電壓爲不同極性之電 壓的第2電源電路所構成。 3 .如申請專利範圍第2項之半導體積體電路裝置， 其中 上述內部電路係包含以位址選擇MO S F E T及記憶 電容器構成之動態型記憶格爲記憶格之記憶體電路者； 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐）-76 - 經濟部中央標準局貝工消費合作社印製 B8 __a___________ 六、申請專利範圍 -上述第1電源電路係形成上述動態型記憶格之位址選 擇MO S F E T之閘極所連接字元線之選擇位準者； 上述第2電源電路係形成上述動態型記憶格之位址選 擇MO S F E T之閘極所連接字元線之負電壓之非選擇位 準者。 4 .如申請專利範圍第2項之半導體積體電路裝置， 其中 分別設於上述第1及第2電源電路之差動放大電路係 由： 以可維持上述內部電壓之程度之大小之電流常時作動 作的第1差動放大電路；及 以上述內部電路設定於動作狀態時維持上述內部電壓 必要之電流所對應之較大電流作動作的第2差動放大電路 所構成。 5 .如申請專利範圍第2項之半導體積體電路裝置， 其中 上述第1電源電路之充電泵電路所形成之輸出電壓， 係施加於形成有構成上述內部電路之元件所形成P井領域 的深度較深之N型井領域者》 6 .如申請專利範圍第2項之半導體積體電路裝置， 其中 上述第2電源電路之充電泵電路所形成輸出電壓，係 使用作爲供至形成有構成上述內部電路之元件之上述P型 井領域之基板負偏壓（Back Bias Voltage)。 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐）~~- T'i - 丨 — — II 1 裝— n ϋ I 11 咏 (請先閲讀背面之注意事項再填寫本頁) 六、申請專利範圍 7 .如申請專利範圍第1項之半導體積體電路裝置， 其中 上述內部電路係包含有： 對上述外部端子所供給電源電壓降壓以形成定電壓的 第3電源電路；及 以上述第3電源電路形成之降壓電壓作動作的電路部 分。 8 .如申請專利範圍第2項之半導體積體電路裝置， 其中 上述內部電路係包含用以輸出上述第1電源電路所形 成之Η (高）位準及第2電源電路所形成L (低位準）之 輸出電路； 上述輸出電路係由： 用於輸出上述第1電源電路所形成內部電壓之第1導 電型輸出MO S F Ε Τ，及輸出上述第2電源電路所形成 內部電壓之第2導電型輸出MOSFET;及 經濟部中央標隼局員工消費合作社印裝 (請先閱讀背面之注意事項再填寫本頁) 於上述第1導電型輸出MO S F Ε Τ與輸出端子之間 連接有源、汲極路徑，閘極供給有接地電位之電壓分割用 第1導電型MOSFET;及 、於上述第2導電型輸出MO S F Ε Τ與輸出端子之間 連接有源、汲極路徑，閘極供給有電源電壓之電壓分割用 第2導電型MO S F Ε Τ所形成。 9 .如申請專利範圍第8項之半導體積體電路裝置， 其中 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210X297公釐）~ 08 · 08 · 經濟部中央標準局貝工消費合作社印裝 Bb CS 六、申請專利範圍 於構成上述輸出電路之第1導電型輸出MO S F E Τ 之閘極，設有用於形成其驅動信號之第1驅動電路； 上述第1驅動電路係由，將以上述電源電壓或內部降 壓電壓及電路之接地電位作動作之內部電路所形成輸入信 號，轉換爲上述第1電源電路之輸出電壓及上述電路之接 地電位對應之第1信號位準的第1位準轉換電路構成； 於構成上述輸出電路之第2導電型輸出MO S F Ε Τ 之閘極，設有形成其驅動信號的第2驅動電路； 上述第2驅動電路係由將上述輸入信號轉換爲上述內 部電壓及上述第2電源電路之輸出電壓所對應第2信號位 準的第2位準轉換電路所構成。 1 0 .如申請專利範圍第2項之半導體積體電路裝置 ，其中 上述內部電路係包含記憶體電路，該記憶體電路係以 位址選擇MO S F Ε Τ及記憶電容器形成之動態型記憶格 爲記憶格，且具有：接於上述位址選擇MO S F Ε Τ之閘 極的字元線，接於上述位址選擇M〇 S F Ε Τ之汲極的位 元線，放大讀出於上述位元線之信號的感測放大器，形成 上述字元線之選擇信號的輸出MO S F Ε Τ，及形成該選 擇信號的位址選擇電路： 上述位址選擇MO S F Ε Τ之閘極絕緣膜，及用於形 成上述位址選擇MO S F Ε Τ之閘極所接字元線之選擇信 號的輸出MO S F Ε Τ之閘極絕緣膜係設定爲相同之第1 膜厚； 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）* 79 - (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 經濟部中央標準局貝工消费合作社印製 C8 D8 六、申請專利範圍 上述動態型記憶格之讀出信號之放大用感測放大器及 構成位址選擇電路之MO S F E T之閘極絕緣膜，係設定 爲相對於上述第1膜厚爲較薄之第2膜厚。 1 1 .如申請專利範圍第i項之半導體積體電路裝置 ，其中 上述內部電路係由以幾何學選出之多數電路構成； 上述電源電路係由：與上述多數電路爲一對一對應， 用於產生與上述外部端子供給之電壓爲同極性且絕對値大 之電壓之多數構成之第1電源電路，及用於產生與上述外 部端子所供給電壓爲不同極性之電壓之多數構成的第2電 源電路所構成； 上述第1及第2電源電路，其上述第1及第2充電栗 電路爲共用，鄰接於上述多數電路分別設有多數個上述可 變阻抗裝置及差動放大電路。 12.如申請專利範圍第11項之半導體積體電路裝 置，其中 上述多數電路之各個，係由動態型記憶格之多數個以 矩陣狀構成之記憶陣列、感測放大器及其對應之位址選擇 電路所構成。 1 3 .如申請專利範圍第1項之半導體積體電路裝置 ，其中 上述內部電路爲包含有： 中央處理裝置， 快閃式EPROM，及 ---------------ir------冰 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 六、申請專利範圍 類比/數位轉換電路； 上述第1電源電路與第2電源電路，係形成上述快閃 式E P R 0M及類比數位轉換電路之動作所用正、負電壓 者。 1 4 .如申請專利範圍第1項之半導體積體電路裝置 ，其中 上述內部電路係具有： 用於輸出上述電源電壓或其以下之電壓的P通道型 MO S F E T，及輸出電路之接地電位的N通道型的 Μ 0 S F E T ;及 經由上述第1電源電路之輸出電壓或充電泵輸出電壓 使上述Ρ通道型MO S F Ε Τ設爲0 F F狀態時之信號位 準所用，經由上述第2電源電路之輸出電壓或充電泵輸出 電壓使上述Ν通道型MO S F Ε Τ設爲0 F F狀態時之信 號位準所用之電路。 1 5 .如申請專利範圍第1項之半導體積體電路裝置 ，其中 上述基準電壓係 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 將射極電流密度差所對應形成之矽禁帶寬度（silicon-band-gap ) 予以利用所形成之定電壓轉換爲定電流的電壓電 流轉換電路； 令上述定電流介由1至多數形成之電流鏡電路而轉換 成來自構成上述電源電路之施加有充電泵電壓之電流鏡電 路的定電流並流經電阻器之一端，令該電阻器之另一端連 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠)_ 81 - B8 C8 D8 六、申請專利範圍 接於特定之內部電壓端子而形成。 1 6 .如申請專利範圍第1項之半導體積體電路裝置 ，其中 上述電源電路係具備有：- 射極面積形成較小，共接之基極及集極係接於電路接 地電位的第1電晶體； 射極面積形成較大，共接之基極及集極係接於電路接 地電位的第2電晶體； 一端接上述第1電晶體之射極，且具有較大電阻値的 第1電阻器； 一端接上述第2電晶體之射極，且與上述第1電阻器 之電阻値比較爲可忽視程度之小的第2電阻器； 一端接上述第2電阻器之另一端，具與上述第1電阻 器大略相同大小電阻値的第3電阻器：及 包含有，接受上述第1電晶體之射極電位及上述第2 電阻器與第3電阻器之連接點之電位，形成使兩電壓爲相 同之電壓以供至上述第1電阻器與第3電阻器之共接之另 —端之P通道型差動MO S F E T的差動放大電路； 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 、由上述第1電阻器與第3電阻器之共接點來形成上述 定電壓。 1 7 .如申請專利範圍第1項之半導體積體電路裝置 ，其中 上述電源電路， 構成上述可變阻抗裝置之MO S F E T之閘極與源極 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-82 - B8 C8 D8 六、申請專利範圍 爲共接，設有藉由其尺寸比所對應之較小M〇 s F E T來 形成負載電流對應之感測電流的電流感測Μ 0 S F Ε Τ， 接受對應於上述感測電流使振盪頻率變化之振盪電路 所形成之振盪脈衝，以控制上述充電泵電路之泵激 (pumping )週期者。 ---------裝-- (請先閲讀背面之注意事項再填寫本頁) *11 .—冰 經濟部中央標準局貝工消費合作社印製 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐）-83 ·6. Patent application scope A semiconductor integrated circuit device comprising: a power supply circuit that operates with a power supply voltage supplied from an external terminal and forms an internal voltage different from the voltage supplied from the external terminal; and the power supply is applied The internal circuit formed by the internal voltage of the circuit; the power supply circuit includes: a charge pump circuit for forming a relatively large absolute voltage relative to the internal voltage: and an output voltage formed by the charge pump circuit and the above A variable impedance device between internal voltages; and using the output voltage formed by the charge pump circuit as an operating voltage, comparing a reference voltage corresponding to the necessary internal voltage with the internal voltage, and controlling the variable impedance device to actuate The same differential amplifier circuit 02. For example, the semiconductor integrated circuit device of the first scope of the patent application, wherein the power supply circuit is used to generate the absolute polarity of the same polarity as the voltage supplied by the external terminal. Voltage first power circuit; and employees of the Central Bureau of Standards, Ministry of Economic Affairs Cooperative printing fee (Read Notes on the back and then fill the page) for generating a second power supply circuit composed of an electrical voltage of different polarities of the voltage supplied to the external terminal. 3. The semiconductor integrated circuit device according to item 2 of the scope of patent application, wherein the above-mentioned internal circuit includes a memory circuit including a dynamic memory cell composed of an address selection MO SFET and a memory capacitor; Printed with Chinese National Standard (CNS) A4 specification (210X297 mm) -76-Printed by BEIJING Consumer Cooperatives, Central Standards Bureau of the Ministry of Economic Affairs __a___________ VI. Scope of Patent Application-The above 1st power supply circuit forms the position of the dynamic memory The selection level of the word line connected to the gate of the MO SFET is selected; the second power circuit is the non-selection of the negative voltage of the word line connected to the gate of the MO SFET to form the address of the dynamic memory cell. Level person. 4. If the semiconductor integrated circuit device according to item 2 of the scope of the patent application, wherein the differential amplifier circuits respectively provided in the above first and second power supply circuits are: A first differential amplifier circuit that operates; and a second differential amplifier circuit that operates with a larger current corresponding to a current necessary to maintain the internal voltage when the internal circuit is set to the operating state. 5. The semiconductor integrated circuit device according to item 2 of the scope of patent application, wherein the output voltage formed by the charge pump circuit of the first power supply circuit is applied to the depth of the P-well field formed by the components forming the internal circuit. Those in the deeper N-type well field "6. For example, the semiconductor integrated circuit device of the second scope of the patent application, wherein the output voltage formed by the charge pump circuit of the second power supply circuit is used as a supply to the formation of the internal structure The components of the circuit are the substrate back bias voltage of the P-well field. This paper size applies to Chinese National Standard (CNS) A4 now (210X297 mm) ~~-T'i-丨 — — II 1 Pack — n ϋ I 11 Yong (Please read the precautions on the back before filling this page) 6. Patent application scope 7. The semiconductor integrated circuit device according to item 1 of the patent application scope, wherein the internal circuit includes: a third power supply circuit that steps down the power supply voltage supplied from the external terminal to form a constant voltage; and A circuit portion that operates with the step-down voltage formed by the third power supply circuit. 8. The semiconductor integrated circuit device according to item 2 of the scope of patent application, wherein the internal circuit includes a Η (high) level formed by the first power circuit and an L (low level) formed by the second power circuit ) Output circuit; the above output circuit is composed of: a first conductive type output MO SF E T for outputting the internal voltage formed by the first power supply circuit, and a second conductive type outputting the internal voltage formed by the second power supply circuit Output MOSFET; and printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) Connect the active and drain terminals between the first conductive output MO SF Ε Τ and the output terminal And the gate is supplied with the first conductive MOSFET for voltage division of the ground potential; and the source and drain paths are connected between the second conductive output MO SF Ε Τ and the output terminal, and the gate is supplied with a power supply voltage The voltage division is formed by the second conductive type MO SF ET. 9. If the semiconductor integrated circuit device of item 8 of the scope of patent application, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ 08 · 08 · Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Install Bb CS 6. The scope of the patent application is on the gate of the first conductive output MO SFE T which constitutes the above output circuit, and the first driving circuit for forming its driving signal is provided; the above first driving circuit is based on the above The input signal formed by the internal circuit that operates from the power supply voltage or internal step-down voltage and the ground potential of the circuit is converted to the first level of the first signal level corresponding to the output voltage of the first power circuit and the ground potential of the circuit Conversion circuit structure; a second driving circuit for forming a driving signal is provided on a gate of the second conductive type output MO SF Ε Τ constituting the output circuit; the second driving circuit converts the input signal into the internal circuit. The voltage and the second level conversion circuit corresponding to the second signal level of the output voltage of the second power supply circuit are configured. 10. The semiconductor integrated circuit device according to item 2 of the scope of patent application, wherein the internal circuit includes a memory circuit, and the memory circuit is a dynamic memory cell formed by address selection MO SF Ε Τ and a memory capacitor as: A memory cell having: a word line connected to the gate of the above address selection MO SF Ε Τ, a bit line connected to the drain of the above address selection MO SF Ε Τ, and amplifying and reading the above bit The sense amplifier of the signal of the line forms the output signal MO SF ET of the selection signal of the word line, and an address selection circuit forming the selection signal: the gate insulation film of the address selection MO SF ET, and In order to form the output signal of the selection signal of the word line connected to the gate of the address selection MO SF Ε Τ, the gate insulation film of MO SF Ε Τ is set to the same first film thickness; CNS) Α4 specification (210 × 297 mm) * 79-(Please read the precautions on the back before filling out this page)-Binding and ordering C8 D8 printed by the Bayer Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs The sense amplifier for amplifying the readout signal of the memory cell and the gate insulating film of the MO S F E T constituting the address selection circuit are set to a second film thickness which is thinner than the first film thickness. 1 1. The semiconductor integrated circuit device according to item i of the patent application range, wherein the internal circuit is composed of a plurality of circuits selected by geometry; the power supply circuit is: one-to-one correspondence with the majority circuit, and is used for A first power supply circuit configured to generate a majority of voltages of the same polarity and absolute magnitude as the voltage supplied from the external terminal, and a second power supply circuit configured to generate a majority of voltages of a different polarity from the voltage supplied by the external terminal. The first and second power supply circuits are common, and the first and second charging pump circuits are shared, and a plurality of the variable impedance devices and differential amplifier circuits are provided adjacent to the plurality of circuits, respectively. 12. The semiconductor integrated circuit device according to item 11 of the scope of patent application, wherein each of the majority of the circuits described above is a memory array, a sense amplifier, and a corresponding address selection composed of a plurality of dynamic memory cells in a matrix shape. Circuit. 1 3. According to the semiconductor integrated circuit device of the first scope of the patent application, the above internal circuit includes: a central processing device, a flash EPROM, and --------------- ir ------ ice (please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297mm) 6. Analogue / digital conversion circuit for patent application scope; above The first power supply circuit and the second power supply circuit are the positive and negative voltages used to form the operations of the above-mentioned flash-type EPR 0M and analog digital conversion circuit. 14. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the internal circuit has: a P-channel type MO SFET for outputting the power supply voltage or a lower voltage, and N of the ground potential of the output circuit Channel-type M 0 SFET; and the signal level when the P-channel MO SF Ε Τ is set to the 0 FF state through the output voltage of the first power circuit or the output voltage of the charge pump, through the second power circuit The circuit used when the output voltage or the output voltage of the charge pump makes the above N-channel type MO SF Ε Τ the signal level when it is set to 0 FF state. 1 5. If the semiconductor integrated circuit device of the first scope of the patent application, the above reference voltage is printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). The silicon-band-gap corresponding to the difference is a voltage-current conversion circuit that converts the formed constant voltage into a constant current; the constant current is converted into a current mirror circuit formed by 1 to a majority The constant current from the current mirror circuit with the charge pump voltage applied to the power supply circuit above flows through one end of the resistor, so that the other end of the resistor is connected to the paper size and applies the Chinese National Standard (CNS) A4 specification (210X297 cm) ) _ 81-B8 C8 D8 VI. The scope of patent application is formed by connecting to specific internal voltage terminals. 16. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the power supply circuit is provided with:-the emitter area is formed small, and the base and collector connected in common are connected to the first ground potential of the circuit Transistor; the emitter has a large area, and the common base and collector are connected to the second transistor of the ground potential of the circuit; one end is connected to the emitter of the first transistor and has a large resistance; A resistor; one end of which is connected to the emitter of the second transistor and a second resistor which is negligible compared to the resistance of the first resistor; and one end of which is connected to the other end of the second resistor, and The first resistor has a resistance of approximately the same size as the third resistor: and includes a resistor that receives the emitter potential of the first transistor and the potential of the connection point between the second resistor and the third resistor, forming two The voltage is the same voltage for the differential amplifier circuit of the P-channel type differential MO SFET at the other end of the first resistor and the third resistor in common; printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ( Please read the note on the back first Please fill in this page again for more information). The above-mentioned constant voltage is formed by the common connection point of the first resistor and the third resistor. 17. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the power supply circuit, the gate and source of the MO SFET constituting the variable impedance device described above are in accordance with Chinese National Standard (CNS) A4 specifications ( 210X297mm) -82-B8 C8 D8 6. The scope of patent application is common, and the current sensing M 0 is set to form the load current corresponding to the load current by its smaller Mos FET than the corresponding size. SF ET, who receives an oscillating pulse formed by an oscillating circuit that changes the oscillating frequency corresponding to the sensing current to control the pumping cycle of the charge pump circuit. --------- Installation-(Please read the precautions on the back before filling out this page) * 11 .—Printed by the Central Standards Bureau of the Ministry of Ice Economy, Shellfish Consumer Cooperatives, this paper is printed in accordance with Chinese standards ( CNS) A4 size (210X297 mm) -83 ·