TW378351B - Semiconductor integrated circuit device, semiconductor memory system, and clock synchronization circuit - Google Patents

Semiconductor integrated circuit device, semiconductor memory system, and clock synchronization circuit Download PDF

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Publication number
TW378351B
TW378351B TW087109413A TW87109413A TW378351B TW 378351 B TW378351 B TW 378351B TW 087109413 A TW087109413 A TW 087109413A TW 87109413 A TW87109413 A TW 87109413A TW 378351 B TW378351 B TW 378351B
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Taiwan
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circuit
signal
input
logic gate
transmission direction
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TW087109413A
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Chinese (zh)
Inventor
Hiromasa Noda
Masakazu Aoki
Hitoshi Tanaka
Hideyuki Aoki
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Hitachi Ltd
Hitachi Microcomputer Syst
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Pulse Circuits (AREA)

Abstract

The present invention comprises an impedance element for coupling input signals from the first and the second input signals; a logic gate circuit for inverting the first or the second input signal into an output signal; a grid-like delay circuit arranged like grids in the first signal transmission direction and the second signal transmission direction; in which the input clock signals of the respective logic gate circuits from the first one to the final one in the 1st signal transmission direction are successively delayed in the 1st signal transmission direction, and output signals are provided from the output terminals of plural logic gate circuits which are arranged in the 1st signal transmission direction and which belong to the plural section obtained from the second signal transmission direction.

Description

A 7 ___·__B7_ 五、發明説明（1 ) 發明所屬之技術領域 本發明係關於半導體積體電路裝置與半導體記憶體系 統’特別是關於利用於需要被以微小而且高精度控制的延 遲訊號的有效技術。此外·，本發明係關於利用於具備高應 .答性與高精度的時脈同步電路與搭載該電路的SD R AM (動態型隨機存取記憶體）之類的半導體積體電路裝置之 有效的技術。 爲了獲得數十微微秒（pico-second)的時間分解能之 電路範例，例如有被發表於下述I S S C C國際固體電路 會議的陣列震盪器（Array Oscillator)。此俥列震盪器， 於列方向並排多數柑同的環狀震盪器（Ring Oscillator)， 將各段作爲2個輸入使用1個輸入連接成爲環狀，同時將 各段的輸出供給至相鄰段的另一方的輸入，於行方向也使 其連接成爲環狀。關於如此的震盪器，被記載於ISSCC93/ ANALOG TECHNIQUES/PAPER TA7.5,1993^^ 118-119H 1¾ 及 ISSCC/SESSI0N18/MEM0RIES WITH SPECIAL ARCHITECTURES/PAPER FP 1 8.5,1995年第 308〜309頁，以 及曰本專利特開平8 — 7895 1號公報。 不包含如同步鏡像延遲（Synchronous Mirror Delay) 之類的回饋迴圈（feedback loop)的時脈同步i路，具有 同步所必要的時間（時脈時間）只要2〜3個週期的需時 較短的特長。這是藉由將輸入時脈的週期作爲延遲電路的 段數而進行測定使得上述時脈時間可以縮短。此測定電路 的時間分解能，係以每一段延遲電路的構成要素的延遲時 本紙張尺度適州中國風家標蜂（CNS ) Λ4規格（210X297公釐） 請 先 閲 讀 背 面 之 注 意 事 項 i 訂 經濟部中央標準局員工消費合作社印裝 • 4- 經濟部中央標皁局員工消贽合A社印策 A 7 _B7__五、發明説明（2 ) 間來決定的，一般而言，係爲CMO S轉換器（invertor) 電路的2段份量的延遲時間的程度》如此使用S M D的時 脈同步電路之例，已有日本專利特開平8 — 2 3 7 0 9 1 號公報。 發明槪要 爲了發展動態型RAM (DRAM)等半導體記億體 的高速化，而使在統括複數的DRAM進行控制的記億體 控制器之間的實裝基板上的訊號傳送傳送延遲一致，換句 話說，估計在上述實裝基板上的訊號傳播延遲，使相關的 小的訊號延遲在內部的延遲時間變大，使相關的大的訊號 延遲在內部的延遲時間變小而使記億體控制器所見到的記 憶體存取時間一致，藉此可以容易確保佔有於週期時間的 可取入資料的時間（空窗期，window)，可以謀求記憶體 週期時間週期時間的高速化。例如，於具有特性阻抗爲 5 0歐姆的訊號配線的基板，以1公分間隔實裝半導體記 憶體的話，各半導體記億體之間的訊號傳播延遲時間約爲 5 0微微秒。因此，爲了要如上所述使記憶體控制器與各 半>導體記憶體之間的訊號傳送延遲一致化，於各半導體記 億體內部必須要設有例如具有數10微微秒的高精度時間 分解能的延遲電路。 本案發明人等，爲了實現如上述般的具有高精度的時 間分解能的延遲電路，檢討了利用前述陣列震盪器的方法 。然而，於上述的陣列震盪器，於行方向的邏輯段數雖然 請 先 閱 讀 背 ^3 之 注 意 項 貪 訂 1.：： .線 本紙張尺度適用中國國家標卑（CNS ) Λ4規格（210X297公釐） -5 - B7 經濟部中央標隼局兵工消於合作社印1-1 五 、發明説明 丨（3 ) nte 應 該 被形 成 具有各 個段數都 具 有相 等 的延 遲 的 延 遲 訊 號 但 是 在被形 成於 實 際的 半 導 體 基 板 上 的 電 路 9 上 述 行 方 向 的 訊 號 延 遲 並無 法 確 認 良 好 的 直 線 性 ， 而 成 爲 某 段較快 某 段 較 慢 〇 亦即 9 可知即使 直 接 利 用 如 上 述 般 的 陣 列 震 盪 器 的 原 理 > 也無 法 獲 得 如 上 述 般 的 1 0 數 微 微 秒 的 微 小 而 且 均 等 的延 遲訊 號 0 假 設 獲 得了 微 小而 且 均 等 的 訊 號 延 遲 > 但 還 是 發 現會 產 生 在 半 導 體基 板 上 行 方 向 與 列 方 向 配 置 格 子 狀的 邏 輯 電 路 使 輸 出 來自 被 配 置 爲 格 子 狀 的 內 部 的 逝 邏 輯 電 路 的 延 遲 訊 號 的 場 合 ，與 使 輸 出 來 白 被 配 置 於格 子 狀的 外 側 的 邏 輯 電 路 的 延 遲 訊號 的 場 合 無 法 均 等 配 置 供 取 出 輸 出 訊 號 之 用 的 訊 號 路 徑的 問- 題 〇 此 外 前述 陣 列 震 ζίΜ. m 器 由 於 係 以 環 狀 震 ΛΜ, Μ 器 構 成 的 緣 故 從 停 止 狀態 直 到 動 作 安 定 爲 止 的 起 動 時 間 較 長 0 亦 即 根 據 本 案 發 明人 的 檢 討 可 以 明 白 要 局 速 形 成所 要 的 訊 號 是 困 難 的 〇 本 發 明 的第 1 巨 的 在 於 提 供 具 備 形 成 具有 微 小 而 且 高 精 度 的 時 間分 解 能 的 訊 號 的 電 路 的 半 導 體 積 體 電 路 裝 置 0 本 發 明 的 第2 百 的 在 於 提 供 於 半 導 體 基 板 上 有 效 率 地 配 置 同 時 具 備可 以 形 成 具 有 微 小 而 且 高 度 的 時 間 分 解 能 的 延 遲 訊 號 的延 遲 電 路 的 半 導 體 積 體 電 路 裝 置 e 本 發 明 的 第 3 § 的 ， 在於 提 供 實 現 以 高 速 輸 出 入 資 料 的 半 導 體 記 億 體 系 統 〇 本 發 明 的第 4 巨 的 在 於 提 供 具 備 高 速 形 成 具 有 微 小而 本紙張尺度適用中國國家標.华（rNS)A4規格（2丨0X297公釐） 五、發明説明（4 且高精度的時間分解能的訊號的電路的半導體積體電路。 請 先 閱 讀 背 ίϊ 之 注 意 % % 本 1 對應於上述本發明的第1〜第4目的而被揭示的發明 之中具代表性者之槪要，簡單說明如下。亦即 具備一種延遲電路的半導體積體電路裝置，該延遲電 路係具有： 接受從第1輸入訊號開始直到依序延遲的第Μ(M= 2、3、4、…）輸入訊號爲止的Μ條訊號線，及 從對應於上述第1輸入訊號的第1邏輯閘電路群開始 直到對應於上述第Μ輸入訊號的第Μ邏輯閘電路群爲止的 Μ個邏輯閘電路群的延遲電路； 各邏輯閘電路群具有從第1邏輯閘電路開始直到第Ν (Ν=3、4、5、…）邏輯閘電路爲止的Ν個邏輯閘電 路，上述邏輯閘電路分別具有第1輸入端子、第2輸入端 子以及輸出端子，. 於上述邏輯閘電路的第1輸入端子與第2輸入端子之 間分別設有耦合元件， 經濟部中决標準局S工消费合作社印1i 於各邏輯閘電路群，從上述第1邏輯閘電路開始直到 第Ν邏輯閘電路爲止透過上述輸出端子與上述第1輸入端 子被縱向連續連接， 上述Μ條訊號線分別被連接至對應的邏輯閘電路群的 第1邏輯閘電路的第1輸入端子， 從上述第1邏輯閘電路群開始於第Μ — 1邏輯閘電路 群之每一個，第L (L = l、2、3、…）邏輯閘電路的 第1輸入端子，被連接至下一個邏輯閘電路群的第L邏輯 本紙張尺度適用中國國家標埤（rNS ) Λ4規格（210 X 297公釐） Α7 Β7 經滴部中央標準局貝Η消费合#社印？木 五、發明説明（5 ) 閘電路的第2輸入端子， 上述第Μ邏輯蘭電路群的指定邏輯閘電路的第1輸入 端子係被連接於上述第1邏輯閘電路群的指定邏輯閘電路 的第2輸入端子， 從複數之上述第Ν邏輯閘電路的上述輸出端子獲得依 序延遲的輸出訊號的上述延遲電路的半導體積體電路裝置 〇 簡單說明對應於上述本發明之第1〜第4目的所揭示 的發明之中其他具有代表性者之槪要，則如下所述：亦即 具備：複數個使被輸入至第1與第2輸入端子的2個 輸入訊號耦合的阻抗手段被設於上述第1與第2輸入端子 間，因應被供給於上述第1與第2輸入端子的輸入訊號形 成輸出訊號的邏輯閘電路，上述複數個邏輯閘電路係可以 於第1訊號傳達方向與第2訊號傳達方向上被配置爲格子 .狀的延遲電路，於第1訊號傳達方向呈第1個以外的第Κ 個，於第2訊號傳達方向被配置於第L段的邏輯閘電路手 段K L的上述第1輸入端子上於第1訊辑傳達方向呈相同 的第Κ個，於第2訊號傳達方向呈第L- 1段的邏輯閘電 路的輸出訊號或是在第1段邏輯閘電路被供給輸入時脈訊 號，於上述邏輯閘電路手段KL的第2輸入端子在第1訊 號傳達方向呈前1個之第Κ- 1個，在第2傳達方向呈相 同的第L段的被供給至邏輯閛電路之第1輸入端子的輸入 訊號被供給，而且，於第1訊號傳達方向呈第1個，於第 2訊號傳達方向呈第L段的邏輯閜電路的第2輸入端子， (請先閱讀背面之注意事項A 7 ___ · __B7_ V. Description of the Invention (1) The technical field to which the invention belongs The present invention relates to semiconductor integrated circuit devices and semiconductor memory systems, and particularly to the effectiveness of delay signals that need to be controlled with small and high precision technology. In addition, the present invention is effective for use in a semiconductor integrated circuit device such as a clock synchronization circuit having high response time, high accuracy, and an SD RAM (Dynamic Random Access Memory) equipped with the circuit. Technology. In order to obtain a circuit example of time resolution of tens of pico-seconds, for example, there is an Array Oscillator which has been published at the ISSC International Solid-State Circuit Conference below. This oscillating oscillator is a ring oscillator (Ring Oscillator) with most of the same side by side in the row direction. Each segment is used as 2 inputs and 1 input is connected to form a ring. At the same time, the output of each segment is supplied to adjacent segments. The input of the other side of the input also makes the connection loop. Such oscillators are described in ISSCC93 / ANALOG TECHNIQUES / PAPER TA7.5, 1993 ^^ 118-119H 1¾ and ISSCC / SESSI0N18 / MEM0RIES WITH SPECIAL ARCHITECTURES / PAPER FP 1 8.5, pages 308-309 of 1995, and Japanese Patent Laid-Open No. 8-7895 No. 1. It does not include the clock synchronization i channel of the feedback loop such as Synchronous Mirror Delay. It has the time (clock time) necessary for synchronization as long as 2 to 3 cycles. Specialty. This is achieved by measuring the period of the input clock as the number of stages of the delay circuit, so that the above clock time can be shortened. The time resolution of this measurement circuit is based on the delay time of the constituent elements of each delay circuit. The paper size is suitable for the China Wind House Standard Bee (CNS) Λ4 specification (210X297 mm). Please read the precautions on the back. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards • 4- Employees of the Central Bureau of Standards of the Ministry of Economic Affairs, A Co., Ltd., Printing Policy A 7 _B7__ V. The description of the invention (2) is generally determined by the CMO S conversion Degree of Delay Time of Two-Segment Weighting of an Invertor Circuit "As an example of a clock synchronization circuit using an SMD, there has been Japanese Patent Laid-Open No. 8-2 37 0 91. In order to increase the speed of semiconductor memory devices such as dynamic RAM (DRAM), the invention has to make the signal transmission and transmission delays on the mounted substrates consistent between the memory controllers that control multiple DRAMs. In other words, it is estimated that the signal propagation delay on the above-mentioned mounting substrate makes the internal delay time of the small related signal delays larger, and the internal delay time of the related large signal delays becomes smaller, so that the billion control The memory access time seen by the controller is consistent, thereby making it possible to easily ensure the time (empty window period, window) of the fetchable data occupying the cycle time, and to speed up the memory cycle time cycle time. For example, if a semiconductor memory is mounted on a substrate having a signal wiring with a characteristic impedance of 50 ohms, the signal propagation delay time between each semiconductor memory is about 50 picoseconds. Therefore, in order to make the signal transmission delay between the memory controller and each semi-> conductor memory uniform as described above, it is necessary to provide a high-precision time of several ten picoseconds in each semiconductor memory. Decomposable delay circuit. In order to realize a delay circuit with high-precision time-resolving energy as described above, the inventors of the present case reviewed the method using the aforementioned array oscillator. However, in the above array oscillator, the number of logical segments in the row direction, please read the note of ^ 3 first. 1 .: The size of the paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297). (B)) -5-B7 The Ministry of Economic Affairs Central Bureau of Standards Bureau ’s ordnance disappeared at the cooperative cooperative seal 1-1 V. Description of the invention 丨 (3) nte should be formed with a delay signal with equal delay for each segment number but after being formed at Circuits on an actual semiconductor substrate 9 The above-mentioned signal delay in the row direction does not confirm good linearity, and it becomes faster in a certain section and slower in a certain section. That is, 9 It can be seen that even if the principle of an array oscillator as described above is directly used> ; It is also impossible to obtain a small and equal delay signal of 10 tens of picoseconds as described above. 0 Assuming that a small and equal signal delay is obtained > However, it is found that it will occur in the upward direction and the column direction of the semiconductor substrate. When a grid-like logic circuit is arranged to output a delayed signal from an internal elapsed logic circuit arranged in a grid, it cannot be equally arranged when a delayed signal is output from a logic circuit arranged outside the grid. The problem of taking out the signal path for the output signal-In addition, the aforementioned array vibration ζίΜ.m device is composed of a ring vibration ΛΜ, Μ device, so the start time from the stop state to the stable operation is longer. The review of the inventor of this case can understand that it is difficult to form a desired signal at a fast speed. The first major feature of the present invention is to provide a semiconductor integrated circuit device including a circuit that forms a signal with a minute and highly accurate time-resolving energy. 0 The present invention The 200th is to efficiently provide on the semiconductor substrate A semiconductor integrated circuit device equipped with a delay circuit capable of forming a delay signal having a minute and highly time-decomposable energy is provided. A third aspect of the present invention is to provide a semiconductor memory system that realizes high-speed input and output of data. The present invention The fourth largest is to provide a circuit with high speed to form a signal with a small and paper size that is applicable to the Chinese national standard. Hua (rNS) A4 specification (2 丨 0X297 mm) 5. Description of the invention (4 and high-precision time-resolving energy signal) Semiconductor integrated circuit. Please read the note from the back of% ϊ%% Ben 1 This is a summary of the representative of the inventions disclosed in correspondence with the first to fourth objects of the present invention, which are briefly described below. That is, a semiconductor integrated circuit device provided with a delay circuit, the delay circuit has: M pieces that accept from the first input signal to the sequentially delayed M (M = 2, 3, 4, ...) input signals Signal lines and delay circuits of M logic gate circuit groups from the first logic gate circuit group corresponding to the first input signal to the M logic gate circuit group corresponding to the M input signal; each logic gate The circuit group includes N logic gate circuits from the first logic gate circuit to the Nth (N = 3, 4, 5, ...) logic gate circuit. The logic gate circuits each have a first input terminal and a second input terminal. And output terminals. Coupling elements are provided between the first input terminal and the second input terminal of the logic gate circuit. The 1 logic gate circuit is continuously connected vertically through the output terminal and the first input terminal through the Nth logic gate circuit, and the M signal lines are respectively connected to corresponding logic gate circuits. The first input terminal of the first logic gate circuit of the group starts from the above-mentioned first logic gate circuit group and starts at each of the M-1 logic gate circuit groups, and the L (L = 1, 2, 3, ...) logic gate The first input terminal of the circuit is connected to the L logic book of the next logic gate circuit group. The paper size is applicable to the Chinese national standard (rNS) Λ4 specification (210 X 297 mm) Α7 Β7合 合 # 社 印? (5) Description of the invention (5) The second input terminal of the gate circuit, the first input terminal of the designated logic gate circuit of the Mth logic blue circuit group is connected to the designated logic gate circuit of the first logic gate circuit group. The second input terminal is a semiconductor integrated circuit device of the delay circuit that obtains sequentially delayed output signals from the output terminals of the plurality of the Nth logic gate circuits. A brief description corresponds to the first to fourth objects of the present invention. The essentials of other representative ones among the disclosed inventions are as follows: That is, a plurality of impedance means for coupling two input signals input to the first and second input terminals are provided in the above. Between the first and second input terminals, a logic gate circuit is formed according to the input signals supplied to the first and second input terminals, and the plurality of logic gate circuits can transmit signals in the first signal direction and the second signal. The delay circuit is arranged in a grid shape in the transmission direction, and is the Kth other than the first in the first signal transmission direction, and is disposed in the logic of the Lth stage in the second signal transmission direction. The above-mentioned first input terminal of the gate circuit means KL is the same K in the first signal transmission direction, and the output signal of the logic gate circuit in the L-1 stage in the second signal transmission direction or in the first signal The segment logic gate circuit is supplied with an input clock signal. The second input terminal of the above-mentioned logic gate circuit means KL is the first K-1 in the first signal transmission direction and the same L-th in the second transmission direction. The input signal of the segment is supplied to the first input terminal of the logic circuit. The input signal is first in the first signal transmission direction, and the second input of the logic L circuit in the L signal is transmitted in the second signal transmission direction. Terminals, (Please read the precautions on the back first

_本頁) 訂 本紙張尺度適用中國囤家標碑（CNS ) Λ4規格（210X297公釐） -8 - 部 中 央 標 準 局 貝 工 消 费 合 .作 社 印 % A 7 __B7 _；_ 五'發明説明（6 ) 於第1訊號傳達方向呈最終段，於上述第2訊號傳達方向 較其更呈前段的邏輯閘電路，被供給與被供給於該處之第 1輸入端子的輸入訊號成爲同相關係的被供給至第1輸入 端子的輸入訊號，於上述第2訊號傳達方向呈第1段，於 第1訊號傳達方向呈第1個的邏輯閘電路之第1與第2輸 入端子，通過構成緩衝器電路的輸入電路被供給時脈訊號 ，於第1訊號傳達方向被供給至從第2個直到最後一個爲 止的各邏輯閘電路的第1輸入端子的上述輸入時脈訊號， 係藉由構成上述緩衝器電路的輸入電路於上述第1訊號傳 達方向依序被延遲者，於上述第2訊號傳達方向係至少第 複數段，從在第1訊號傳達方向被配列的複數邏輯閘電路 的輸出端子獲得輸出訊號。 簡單說明對應於上述本發明之第1〜第4目的所揭示 的發明之中其他具有代表性者之槪要，則如下所述：亦即 一種半導體積體電路裝置，其特徵爲具有： 具備接受基準時脈訊號形成從第1輸入時脈訊號開始 直到依序延遲的第Μ (M=2、3、4、…）輸入時脈訊 號爲止的複數單位電路，對應於分別被包含於前述複數單 位電路的電路元件的特性依序不同的情形，於上述基準時 脈訊號的1個週期內形成從上述第1輸入時脈訊號開始直 \ 到第Μ輸入時脈訊號爲止的第1電路，及 接受從上述第1輸入時脈訊號開始直到上述第Μ時脈 訊號爲止，也從自上述第1輸入時脈訊號開始直到第Μ輸 入時脈訊號爲止的各延遲量獲得以均等的延遲量依序延遲 本紙張尺度適用中國國家標H*. ( CNS > Λ4規格（21 ΟΧ297公釐） ---------11 (請先閱讀背面之注意Ϋ-項本頁 訂 .多丨 -9- 經濟部中央標羋局貞工消费合作社印^ A7 __ B7 五、發明説明（7 ) 的複數輸出時脈訊號的第2電路； 上述第2電路，係具備對應於Μ行XN列（N=3、 4、…）的複數邏輯閘電路，以使訊號被傳達於前述複數 邏輯閘電路的行方向與列方向的方式被配線的延遲電路之 半導體積體電路裝置。 本發明的第5目的在於提供具高精度高應答性的時脈 同步電路及使用該電路的半導體積體電路裝置。本發明之 第6目的在於提供以高精度實現在待機時耗電量低而且可 高速恢復的時脈同.步電路及使用該電路的半導體積體電路 。本發明之第7目的在於提供不增大電路的規模，以高精 度實現高應答性的時脈同步電路以及使用該電路的半導體 積體電路。本發明之其他目的，本發明之前述以及其他的 目的與新的特徵，應可從本說明書的記載以及圖面資料來 了解。 簡單說明對應於上述本發明之第5〜第7目的所揭示 的發明之中其他具有代表性者之槪要，則如下所述：亦即 使用使具有較大的時間分解能之時脈訊號傳播的第1 延遲電路，及第1端緣檢測電路，及第1多路轉換器形成 對應於上述較大的時間分解能的延遲1個時脈的時脈訊號 ，使用第2延遲電路，及第2端緣檢測電路，及第2多路 轉換器，以補正上述第1延遲電路的誤差，同時作爲上述 第2延遲電路具有較小的時間分解能的第2延遲電路，設 有使被輸入第1與第2輸入端子間的2個輸入訊號耦合的 阻抗手段，使用複數個使對於輸入訊號反轉的輸出訊號之 本纸張尺度通用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閱讀背面之注意事項再Ϊ本頁) 訂 •10- 經濟部中央標準局员工消费合作社印ii A7 B7____五、發明説明（8 ) 邏輯閛手段構成於第1訊號傳達方向與第2訊號傳達方向 配置爲格子狀的格子狀延遲電路，於第1訊號傳達方向在 第1個直到最後一個爲止的各邏輯閘手段將輸入時脈訊號 於上述第1訊號傳達方向依序使其延遲輸入，於上述第2 訊號傳達方向至少最後一段或是一個之前，使用從被配列 於第1訊號傳達方向的複數邏輯閘電路手段的輸出端子獲 得輸出訊號者，將期搭載於同步dram等之半導體積體 電路裝置》 發明之實施形態 於第1圖，顯示相關於本發明的格子狀延遲電路之一 實施例之電路圖。該圖的各電路元件，係藉由習知的半導 體積體電路製造技術構成其所必要的動態型RAM等的電 路元件，同時被形成於如單結晶矽之類的1個半導體基板 上。 作爲被配列爲格子狀的延遲要素之邏輯閘手段，其代 表之一係如本例所顯示般的，係由被設於N A N D閘電路 ND與相關的NAND閘電路ND之2個輸入i η 1與 i η 2之間的耦合電容C Ρ所構成。此耦合電容C Ρ的電 容値’並未有特別的限制，其係作爲1 p F程度的半導體 積體電路，具有比較大的電容値的電容元件。 作爲上述延遲要素的邏輯閘手段，以在第1訊號傳達 方向之列方向（Row)上m段，在第2訊號傳達方向之行方 向（Column)上η段的方式被配置爲格子狀。第1訊號傳 本紙張尺度通州中國國家標率（（’NS ) Λ4規格（210X297公楚) ' '— (請先閲讀背面之注意事項本頁) —1Τ-----HI 0 五、發明説明（9 ) A7 B7 達方向之中，針對第1列加以說明之，於第2訊號傳達方 向之行方向被排列的η段所構成的邏輯閘電路手段之中， 第1段的邏輯閘電路的2個輸入端子i n 1與i η 2被共 通化，緩衝器電路的反相器電路I NV 1的輸出訊號被供 給，其輸出訊號被供給至第2段之同樣被共通化的第1與 第2.輸入端子in 1與i η2。第2段的輸出訊號，被供 給至第3段的第1輸入端子i n 1。以下也同樣地，於從 第4段直到第η段爲止的第1輸入端子i n 1，被供給前 段電路的輸出訊號。 第1訊號傳達方向之中，針對第2列加以說明之.，由 被排列在第2訊號傳達方向之行方向的η段所形成的邏輯 閘手段之中，緩衝電路的反相器電路I NV 2的輸出訊號 被供給至第1段邏輯閘手段的第1輸入端子i η 1，其輸 出訊號被供給至第2段之第1輸入端子i η 1。第2段的 輸出訊號被供給至第3段之第1輸入端子i η 1。以下也 同樣地，在第4段到第η段爲止前段的輸出訊號被供給至 第1輸入端子i nl。於上述第1段直到第η段，前段的 輸出訊號被供給至第1輸入端子i η 1。於上述第1段直 到第η段的各邏輯閘手段的第2輸入端子i η 2，分別被 供給前1個上述第1個之第1段直到第η段之各邏輯閘手 段的第1輸入端子i η 1的輸入訊號。 第1訊號傳達方向之中，於從第3段直到最後一段之 第m段的各列，也與上述第2個相同，被排列於第2訊號 傳達方向之行方向的η段所形成的邏輯閘手段之中，於第 請 先 閱 面 之 注 意 事 項_ This page) The paper size of the edition is applicable to the Chinese storehouse inscription (CNS) Λ4 specification (210X297 mm) -8-The Ministry of Standards and Technology Bureau of the United States Shellfish Consumption Cooperation. Printed by the Press Society% A 7 __B7 _; (6) The logic gate circuit which is in the final stage in the first signal transmission direction and which is in the previous stage in the second signal transmission direction is provided in the same phase relationship with the input signal of the first input terminal provided there. The input signal supplied to the first input terminal is the first segment in the above-mentioned second signal transmission direction, and the first and second input terminals of the logic gate circuit are the first in the first signal transmission direction, forming a buffer. The clock signal is supplied to the input circuit of the circuit, and the above-mentioned input clock signal is supplied to the first input terminal of each logic gate circuit from the second to the last in the first signal transmission direction by constituting the buffer described above. The input circuit of the encoder circuit is sequentially delayed in the first signal transmission direction, and the second signal transmission direction is at least a plurality of stages from the complex logic gate circuit arranged in the first signal transmission direction. Obtaining an output signal terminal. A brief description of key points corresponding to other representative inventions disclosed in the first to fourth objects of the present invention is as follows: That is, a semiconductor integrated circuit device having the following features: The reference clock signal forms a complex unit circuit from the first input clock signal to the sequentially delayed M (M = 2, 3, 4, ...) input clock signal, corresponding to each of the plural units included In the case where the characteristics of the circuit elements of the circuit are sequentially different, a first circuit from the first input clock signal to the Mth input clock signal is formed within one cycle of the reference clock signal, and the first circuit is received. From the first input clock signal to the M clock signal, each delay amount from the first input clock signal to the M input clock signal is sequentially delayed with an equal delay amount. The size of this paper is applicable to Chinese national standard H *. (CNS > Λ4 size (21 〇 × 297mm) --------- 11 (Please read the note on the back first-item order. Multi- 丨 -9 -Central Ministry of Economic Affairs Printed by Zhengong Consumer Cooperative ^ A7 __ B7 V. The second circuit of the complex output clock signal of the invention description (7); The above second circuit is provided with a row corresponding to M rows and XN columns (N = 3, 4, ...). A semiconductor integrated circuit device of a delay circuit that is wired so that a signal is transmitted to the row direction and the column direction of the complex logic gate circuit, and a complex logic gate circuit. A fifth object of the present invention is to provide a highly accurate and highly responsive circuit. A clock synchronization circuit and a semiconductor integrated circuit device using the same. A sixth object of the present invention is to provide a high-accuracy clock synchronization with low power consumption during standby and high-speed recovery. Step circuit and use of this circuit A semiconductor integrated circuit is provided. A seventh object of the present invention is to provide a clock synchronization circuit that achieves high responsiveness with high accuracy without increasing the scale of the circuit, and a semiconductor integrated circuit using the same. The foregoing and other objects and new features of the present invention can be understood from the description of this specification and the drawings. The brief description corresponds to the fifth to fifth aspects of the present invention. The key points of other representative inventions among the inventions disclosed in the seven objectives are as follows: that is, a first delay circuit that propagates a clock signal having a large time resolution energy, and a first edge detection circuit are used. And the first multiplexer forms a clock signal delayed by one clock corresponding to the above-mentioned large time resolution energy, using a second delay circuit, a second edge detection circuit, and a second multiplexer, In order to correct the error of the first delay circuit, and as a second delay circuit with a small time resolution capability, the second delay circuit is provided with an impedance that couples two input signals input between the first and second input terminals. Means, use a plurality of paper standards for reversing the input signal to the output paper. Common Chinese National Standard (CNS) Λ4 specification (210X297 mm) (please read the precautions on the back first, and then click this page) Order • 10- Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7____ V. Explanation of the invention (8) The logic means is composed of a grid-like delay signal arranged in the first signal transmission direction and the second signal transmission direction. Way, each logic gate means in the first signal transmission direction from the first to the last one will input the clock signal in the first signal transmission direction in order to delay the input, at least the last segment in the second signal transmission direction Or one who has obtained an output signal from an output terminal of a plurality of logic gate circuits arranged in the first signal transmission direction, and will be mounted on a semiconductor integrated circuit device such as a synchronous dram, etc. A diagram showing a circuit diagram of an embodiment of a grid-like delay circuit according to the present invention. Each of the circuit elements in the figure is a circuit element such as a dynamic RAM, which is required to be constructed by a conventional semiconductor volume circuit manufacturing technology, and is formed on a semiconductor substrate such as single crystal silicon. As a logic gate means arranged as a grid-like delay element, one of the representatives is as shown in this example, which is provided by two inputs i η 1 provided in the NAND gate circuit ND and the related NAND gate circuit ND. Coupling capacitance C P between i η 2. The capacitance 値 'of the coupling capacitor C P is not particularly limited, and it is a capacitor element having a relatively large capacitance 作为 as a semiconductor integrated circuit of about 1 p F. The logic gate means as the delay element is arranged in a grid pattern such that m segments are in the row direction (Row) of the first signal transmission direction and n segments are in the row direction (Column) of the second signal transmission direction. The first signal is the paper standard Tongzhou China National Standards (('NS) Λ4 specification (210X297))' '— (Please read the precautions on the back page first) —1Τ ----- HI 0 V. Invention Explanation (9) Among the directions of A7 and B7, the first column is explained. Among the logic gate circuit means composed of n segments arranged in the row direction of the second signal transmission direction, the logic gate circuit of the first segment The two input terminals in 1 and i η 2 are shared, and the output signal of the inverter circuit I NV 1 of the buffer circuit is supplied, and the output signal is supplied to the first and The second input terminal in 1 and i η2. The output signal of the second stage is supplied to the first input terminal in 1 of the third stage. The same applies to the first stage from the fourth stage to the nth stage. The input terminal in 1 is supplied to the output signal of the preceding circuit. Among the first signal transmission directions, the second column is explained. A logic gate formed by η segments arranged in the row direction of the second signal transmission direction. Among the methods, the output signal of the inverter circuit I NV 2 of the buffer circuit is supplied to the first stage The output signal of the first input terminal i η 1 of the logic gate means is supplied to the first input terminal i η 1 of the second stage. The output signal of the second stage is supplied to the first input terminal i η 1 of the third stage. The same applies hereinafter to the first input terminal i nl from the fourth paragraph to the nth paragraph. From the first paragraph to the nth paragraph, the output signal from the previous paragraph is supplied to the first input terminal. i η 1. The second input terminal i η 2 of each logic gate means from the first stage to the η stage is supplied to each logic gate means of the previous 1st stage from the first stage to the η stage. The input signal of the first input terminal i η 1 in the first signal. In the direction of the first signal transmission, the columns from the third paragraph to the m-th paragraph of the last paragraph are also the same as the second one and are arranged in the second signal. Among the logic gates formed by the η segment of the direction of the direction of travel, please read the precautions first.

訂Order

本紙張尺度遶用中國國家標準（CNS ) Λ4規格（210X297公釐） •12- 五、發明説明（10 ) A7 B7 β 經濟部中央標準而货工消贽合作社印·».')木 1段邏輯閘電 器電路的反相 於從第3段直 至第2段之第 給至第3段之 4段直到第η 端子i η 1。 手段的第2輸 之上述第2個 輯閘手段的第 於第1訊 被排列的η個 輯閘手段的第 方向最後一段 的第1輸入端 的輸入訊號。 第2訊號傳達 所被供給的輸 個，於第2訊 入端子i η 2 入訊號Β 2被 至輸入訊號Τ 於上述第 於第1訊號傳 路的第1輸 器電路I Ν 到最後一段 1輸入端子 第1輸入端 段爲止，前 於從上述第 入端子i η 直到第m -1輸入端子 號傳達方向 邏輯閘手段 2個輸入端 之第m個從 子所被供給 例如，於上 方向呈第1 入訊號Β 1 號傳達方向 所被供給的 供給至輸入 5。 2訊號傳達 達方向爲最 入端子ini，分別被供給緩衝 3直到INVm的各輸出訊號。 之第m列第1段輸出訊號被供給 i η 1，第2段之輸出訊號被供 子ini。以下也同樣地，從第 段的輸出訊號被供給至第1輸入 1段直到第η段爲止的各邏輯閘 2，於第1訊號傳達方向前1個 1個的第1段直到第η段的各邏 i η 1的輸入訊號分別被供給。 呈第.1個，於第2訊號傳達方向 之中，從第3段直到第η段的邏 子in2，於上述第1訊號傳達 第1段直到第η段的邏輯閘手段 的訊號之中，被供給被設爲同相 述第1訊號傳達方向呈第m個於 段的邏輯閘手段的第1輸入端子 ，係於第1訊號傳達方向呈第1 呈第3段的邏輯閘手段的第2輸 輸入訊號T3。以下，同樣地輸 訊號T4，輸入訊號B3被供給 方向第η段若爲最後一段的話， 後一段m於第2訊號傳達方向第 請 先 閲 讀 背 ιέ 之 注 意 事 項 頁 訂 、结 本紙張尺度適用中國國家標绛（CNS ) Λ4規格（210X297公釐） -13 - Α7 Β7 經濟部中夾標準局兵工消费合作社印Μ 五 '發明説明（11 ) η - 2個輸入訊號B n — 2 ,被作爲供給至於上述第1訊 號傳達方向爲第1個於第2訊號傳達方向爲最後一段之第 η段的邏輯閘手段的輸入手段i η 2的輸入訊號Τ η。 一般而言，被配置於在第1訊號傳達方向呈第1個以 外的第Κ個，於第2訊號傳達方向爲第L段的邏輯閘手段 (K，L )之上述第1輸入端子被供給於第1訊號傳達方 向爲同樣的第Κ個，於第2訊號傳達方向爲第L 一 1段的 邏輯閘電路的輸出訊號或者是在第1段邏輯閘手段被供給 輸入時脈訊號，於上述邏輯閘手段（Κ，L )的第2輸入 端子，被供給供給至於第1訊號傳達方向呈前1個之第Κ -1個，於第2訊號傳達方向呈同樣第L段的邏輯閘手段 的第1輸入端子的輸入訊號。 於在上述第1訊號傳達方向爲第1個，於第2訊號傳 達方向爲第L個的邏輯閘手段的第2輸入端子，於第1訊 號傳達方向呈最後一段，於上述第2訊號傳達方向爲較其 更爲前段的邏輯閘手段，被供給與被供給至其之第1輸入 端子的輸入訊號具有同相關係的第1輸入端子被供給的輸 入訊號。 而，於上述第2訊號傳達方向呈第1段，於第1訊號 傳達方向呈第1個的邏輯閘手段的第1與第2輸入端子， 被供給通過構成緩衝器電路的輸入電路之時脈訊號，而被 供給至於第1訊號傳達方向從第2個直到最後一個的各邏. 輯閘手段的第1輸入端子的上述輸入時脈訊號，係藉由構 成上述緩衝器電路的輸入電路而於上述第1訊號傳達方向 ί蜻先閲請背面之注意事項^^本頁) 訂 .ο 本纸張尺度適用中国國家標準（（'NS ) Λ4規格（210X297公釐） -14- ill 經濟部中央標準局Μ工消费合作社印^ A7 _ B7__五、發明説明（彳2 ) 依序被延遲。 上述緩衝器電路，係構成輸入時脈訊號的延遲補正部 ·. 者，反相器電路I NV 1〜I NVm各個輸出訊號依序 被延遲。例如，爲了從1個時脈輸入形成相互相位與時脈 週期相比微量偏移的m個時脈延遲訊號S 1〜Sm，使用 用了閘寬度爲等差數列的MO S F E T的反相器電路 I NV 1〜I NVm。總之，於上述緩衝器電路的反相器 電路INV1〜INVm的輸入端子，雖未有特別的限制 ，接受從外部端子被供給的時脈訊號的輸入電路IB的輸 出訊號被共通供給，對於從上述各反相器電路I NV 1所 輸出的訊號S 1，以使反相器電路I NV2的輸出訊號 S 2較其爲慢，而且使反相器電路I NV 3的輸出訊號 S 3更慢的方式，形成對應於上述第1訊號傳達方向依序 被延遲的訊號，相關的訊號被輸入至上述格子狀延遲電路 而作爲輸出時脈訊號。形成上述依序延遲的訊號S 1、 S 2 ..... S m的電路並不以上述實施例爲限。例如，爲 了變更MO S F E T的元件特性，可以變更上述閘寬度以 外的元件製造上之指定値。此外，也可以使用 MOSFET以外的電路元件。 藉由上述格子狀延遲電路而形成的輸出訊號，例如， 作爲於上述第2訊號傳達方向爲最後一段之第η段，於第 1訊號傳達方向爲第1個至第m個之邏輯閘手段的輸出訊 號。對於輸入時脈訊號如果得到被設爲同相與反相的輸出 訊號的話，則使其加上於上述第2訊號傳達方向是第 {請先聞讀背面之注意事項再填^本頁) 訂 本紙張尺度適用中國國家標準（（’NS ) Λ4規格（2) Ο X 297公釐） •15- 經濟部中央標隼局員工消费合作社印米 A7 B7五、發明説明（13 ) η 0 1段，於第1訊號傳達方向被設於第1個至第m個的 邏輯閘手段的輸出訊號》如果是選擇輸出複數種類的延遲 訊號的話，只要選擇如後所述的使微小延遲間隔一致者， 總之，於第2訊號傳達方向將最後一段作爲基準選擇複數 段即可。 於第2圖，顯示相關於本發明的格子狀延遲電路的另 一實施例的電路圖。在此實施例，於邏輯閛手段，設有供 取出輸出訊號之用的輸出緩衝器I NV L。其他的構成， 與前述第1圖之實施例相同。於格子狀延遲電路，只有在 上述第2訊號傳達方向之僅有特定段附加輸出用的緩衝器 電路，以及於該特定段輸出負荷條件相異，從次一段來看 輸入條件變得不同。 因此，於上述格子狀邏輯閘手段，僅有特定段成爲相 異的輸出入條件，則變得無法獲得精度較佳的微小延遲訊 號。在此，於第2圖之實施例，於被配置爲格子狀態的邏 輯閘手段，與是否取出輸出訊號無關，全都附加輸出緩衝 器電路IN VL。藉此，於第2訊號傳達方向，從在任意 段被排列於第1傳達方向的邏輯閘手段獲得輸出訊號的方 式，也可以使藉此所形成的微小訊號延遲時間不受到任何 影響。 上述第1圖或第2圖的格子狀延遲電路，係可以理解 爲所謂將前述的陣列震盪器的一部份取出來利用，於陣列 震盪器係在行方向與列方向的境界條件以自身最佳的震盪 頻率震盪者。對此，本發明相關的格子狀延遲電路，因爲 (請先閲讀背面之注意參項再填k本頁) 訂 /1 本紙張尺度適用中國國家標卑（C’NS ) Λ4規格（21〇Χ297公釐） -16- A7 B7 經濟部中央標準局貝工消費合作社印？木 五、發明説明（14 ) 在上述第2訊號傳達方向之行方向上不具有回饋迴圈的緣 故所以不會產生震盪動作，被輸出的時脈訊號的週期，與 從外部被輸入的時脈訊號的週期相等》此外，於被輸入各 延遲段的第1訊號傳達方向依序被延遲的時脈訊號，係由 構成上述延遲補正部的緩衝器電路相互相位與時脈週期相 比偏移微小量者，但並非以所希望的數十微微秒的等級線 形排列。 然而，延遲補正部與第1訊號傳達方向的境界條件， 亦即藉由B h與Τ η + 2之連接，時脈延遲訊號隨著通過 數段延遲要素，各延遲段的相位關係被補正，可獲得與前 述陣列震盪器同樣線形的相位關係。 而且，本實施例的電路，因爲不需要環狀震盪器，所 以從停止狀態到動作安定狀態爲止的起動時間較短。亦即 本實施例之電路適於高速動住。而且，由於起動時間短的 特徵，可以在不使用_@使此電^一止，謀求被搭載此 電路的半導體晶片的低耗電量化。 在第2圖的實施例，於各延遲要素之邏輯閘手段，僅 連接陣列內的其他延遲要素之邏輯閘手段的輸入，附加在 上述延遲段方向之第2訊號傳達方向上的境界條件下所被 實現的相位關係之不同而不使其關係崩壞而設有輸出電路 I NVL，通過相關的輸出電路I NVL獲得上述線形相 位關係（微小延遲量）之輸出訊號。 於第3圖A、B，顯示藉由供說明相關於本發明的格 子狀延遲電路的動作之用的電腦模擬所求出的特性圖。第 (讀先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國ϋ家標準（（:NS > Λ4規格（21 OX 297公釐） -17- 經濟部中央標羋局®；工消费合作社印製 A7 ___B7 五、發明説明（15 ) 3圖A係從外部被輸入升起的端緣的場合之傳播，第3圖 B係顯示從外部被輸入降下端緣的場合的傳播，於第3圖 A與B，分別以時間軸爲撗軸，列方向排列的各邏輯閘電 路段的升起端緣（或者是降下端緣）的傳播以白球（〇） 表示，降下端緣（或者是升起端緣）的傳播以黑球（·） 表示。時間軸的原點爲外部時脈輸入的升起端緣，或者是 降下端緣。輸入時脈，爲脈衝寬度負荷50 %，200 MHz。 於第3圖A及B，在第2傳達方向之第1段、第2段 ，上述延遲補正部的延遲訊號成爲支配的，相位差並非等 間隔（線形）排列。但是，在第4段之後的後側段微小延 遲量成爲一定，可判別上述〇或參排列於一直線上。於第 3圖A與B，各奇數段的端緣的位置相異，是因爲延遲要 素是NAND閘電路的緣故。升起係以並連接續的2個P 通道型MOSFET，降下是以串連接續的2個N通道型 M〇S F E T驅動的緣故，所以對於輸入的輸出計時相異 。對此，偶數段的輸出，係以其2個相異的輸出計時的和 來決定的緣故，第3圖A與B都在相同的位置。 於第4圖A、B、C、D及E，顯示被使用於上述格 子狀延遲電路的延遲要素的其他實施例的電路圖。在第4 圖A，作爲延遲要素使用NOR閘電路NR。總之， NOR閘電路NR的2個輸入i η 1與i η 2之間作爲耦 合手段設有電容CP。此NOR閘電路NR的輸出訊號 A 〇 u t，於一方被接續於陣列內的其他延遲要素之 本紙乐尺度適用中國园家標卑（（WS ) Λ4規格（210X297公釐） (錡先閔讀背面之注意事項再填寫本頁) 訂 -18- 五 、發明説明（16 ) N 0 R閘 電路的 輸 入端子，另一方被接續於爲獲得 輸 出 訊 號 而 作爲 輸出 緩 衝 器電路的反相器電路I V L的輸 入 端 子 在第 4圖 Β 作爲延遲要素使用共通接續2個 反 相 器 電 路 IV 1與 I V 2的輸出端子者。總之，反相器電路 I V 1與 IV 2 的 輸入端子ini與in 2隻間作 爲 耦 合 手 段 接續 電容 C Ρ ，共通接續其輸出端子獲得輸出訊號 A 0 u t ，同 時 將 其於一方供給至陣列內的其他延 遲 要 素 之 Ν OR 閘電 路 的 輸入端子，於另一方供給至爲獲 得 輸 出 訊 號 之作 爲輸 出 緩 衝器電路的反相器電路I V L的 輸 入 端 子 0 - 在第 4圖 C * 作爲延遲要素使用與前述同樣的 N A N D 閘電 路 Ν D，作爲耦合手段取代電容而使 用 電 阻 元 件 R G 。其 他 的 構成與前述第2圖之實施例相同 〇 如 此 9 作 爲奉禹 合手 段 之 電阻RG，也可以適用於上述第 4 ΓΗΪ 圖 A 與 第 4圖 Β 〇 藉 由 使用電阻元件，可以形成比較小 的 耦 合 元件 0 在第 4圖 D 9 - 作爲延遲要素使用與前述同樣的 N A N D 電路 Ν D ，作爲耦合手段取代電容使用二 極 體 接 續 的 Μ 0 S F Ε Τ Ml與M2。總之，二極體接續的 Μ 0 S F Ε Τ Μ 1係從輸入端子ini朝向in 2 傳 達 訊 號 電流 ，Μ 2 相 反地從輸入端子in2向ini 流 通 訊 號 電 流。 其他 的 構 成與前述第2圖的實施例相同。 如 此 作 爲 耦 合手 段之 二 極 體接續的MOSFET Ml與 Μ 2 本紙張尺度適_用中國國家標?f ( (、NS ) Λ4規格（210X 297公釐） -19- 五、發明説明（17 ) 也可以適用於上述第4圖A與第4圖B。藉由使用 MOSFET Ml'M2，可以藉與其他的 MOSFET相同的工程形成耦合元件。 在第4圖E，作爲延遲要素利用差動電路。總之，將 ___________ "- 被並連接續的N通道型MOSFET Q3、Q4的閘作 爲正相的第1輸入端子i η 1+與i η 2+設親合電容 C 1，於被共通化的汲極設作爲負荷的ρ通道型 MOSFET Q1與Q2同時得到反轉輸出ou t —。 將被接續爲並聯形態的N通道型MOSFET Q 7 ' Q8的閘作爲反相的第1輸入端子i nl —與i n2 —設 耦合電容C 2，於被共通化的汲極設有作爲負荷的ρ通道 型MOSFET Q5與Q5同時獲得正相輸出ou t + 。於差動動作的MOSFET Q3與Q4以及Q7與 Q 8的源極，設有使流動動作電流的N通道型 MOSFET Q9°P通道型MOSFET Q2與 Q6 ’與上述P通道型MOSFET Q9同樣藉由控制 電壓V c t r 1而被調整流動的電流進行1段附近之延遲 時間的控制》 被設於上述MOSFET Q3與Q4以及Q7與 Q8的之間的耦合電容C1與C2，可以如前述第4圖C 與第4圖D置換爲電阻或是MO S二極體。 於第5圖A、B，顯示供說明相關於本發明的格子狀 延遲電路之耦合手段的功能之用的特性圖。在此實施例， 如第4圖B所示，作爲延遲要素係使用使2個反相電路的 .(請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率（〇«)六4規格（210父297公釐） -20- 經濟部中央標準局爲工消費合作社印餐 A7 _B7五、發明説明（18 ) 輸出共通者，而藉由電腦模擬求出特性圖》第4圖A顯示 具有如前述第2圖的實施例所示作爲耦合手段約1 p F般 的比較大的電容値得電容之例。如此使2個輸入訊號的結 合度變大的話，於第2傳達方向在如第1段、第2段般的 前段於延遲補正部之延遲訊號成爲支配的訊號，相位差雖 未等間隔（線形）排列，但是可知較第4段更爲後段側之 微小延遲量成爲一定，上述〇或•排列於一直線上。 對此，於第5圖B，顯示以使上述2個輸入訊號的結 合度便小的方式使上述電容的電容量變小的場合之例。如 此使輸入耦合電容的電容値變小的話，即使上述第2訊號 傳達方向的後段側上述〇或•之直線性也變差。然而，與 前段側相比到底可以認可後段側之改善。 於第6圖，以與上述第5圖A、B的場合同樣的條件 ，使用將2個反相器電路的輸出共通化者，藉由削除上述 耦合電容的場合的電腦模擬所求得的特性圖。如此削除耦 合手段的話，雖然第2訊號傳達方向同樣地在後段側具有 一定的時間差，但是就作爲可以設定所要的微小量的延遲 之可變延遲電路來利用的第1訊號傳達方向上來看，第1 至第3個左右爲止排列具有微小量的延遲差*但是以後沒 有時間差，可知即使綜觀全體也無法作爲上述微小量延遲 電路來使用。 如上述般的使在第1訊號傳達方向依序被延遲的訊號 ，與於第2訊號傳達方向被依序延遲的訊號的結合度密合 ，對於上述第2訊號傳達方向之同相關係之2段份的延遲 (諳先閲讀背面之注意事項再填寫本頁) 訂 rj· 本紙張尺度適用中國S家標準（CNS ) Λ4規格（2丨0X 297公釐） -21 - Α7 Β7 Ά 部 中 央 標 準 局 貝 j- 消 合 社 印 % 五、發明説明（19 ) 時間被配置於第1傳達 而獲得的微小量延遲的 雖然並未針對此理由進 個輸入訊號相互干涉， 平均化而實現具有如上 延遲者。從另一個角度 反轉增幅器，使2個輸 器的輸入的場合，可以 線性良好的部份進行訊 素之訊號傳達被均等化 爲了使2個輸入訊號耦 於2個輸入端子間，但 2個輸入配線極端接近 件的場合之同樣的效果 又，上述第2訊號 時間以被配置於第1傳 割而可以獲得微小量延 2個輸入訊號結合的結 訊號路徑之信號延遲會 害的程度的結合，會使 子狀的做法失去意義。 於第7圖，顯示供 路的動作之用的波形圖 部的輸出訊號的升起端 方向的延遲要素的數目來均等分割 直線性變隹而言具有重要的功能。 行定量的解析，但是可以認爲是2 格子狀的各延遲要素之訊號變化被 述般的具有良好的直線性的微小量 看，上述延遲要素，可以視爲一種 入訊號耦合供給至相擺的反轉增幅 認爲在看其輸出入傳達特性時在直 號增幅的結果，格子狀的各延遲要 而獲得如上述般的良好的直線性。 合，在本實施例中，將耦合元件設 是方法並不以此爲限。例如藉由使 而配置，而可以獲得與設有耦合元 ，則無須特別增設耦合元件。 傳達方向之同相關係的2段份延遲 達方向的延遲要素的數目來均等分 遲，所以並不能夠導致完全使上述 論。總之，在2個訊號傳達方向的 相互對另一個訊號延遲要素引起損 將作爲延遲要素之閘電路等設成格 說明相關於本發明的格子狀延遲電 。例如，參見顯示於時間軸的中央 緣爲例，可知除了最初的數條以外 (請先閱讀背面之注意事項再填寫本頁) 、-0 Θ 本紙張尺度適用中國國家標準< CNS >Λ4規格（210X297公釐） -22- 經求-部中央標羋局员工消贽合.#社印製 A7 B7五、發明説明（20 ) ，時脈訊號的升起大約以5 0微微秒之等間隔升起。針對 輸出訊號的降下端緣，可知於上述時間軸的前側後段側的 時脈訊號的降下大約爲5 0微微秒的等間隔，可知在在時 間軸的後側，最初的時脈訊號的降下是雜亂的。 於第8圖，顯示使用了相關於本發明的上述格子狀延 遲電路的時脈產生電路之一實施例的方塊圖》此實施例的 時脈產生電路，例如搭載於動態型RAM之類的半導體記 憶裝置，相關的複數RAM及統括其而進行控制的記憶體 控制器之間在實裝機板上的訊號傳送延遲如果使其一致的 話，換句話說，估計在上述實裝基板上的訊號傳播延遲， 爲了使相關的訊號延遲較小的在內部使其延遲時間變大， 相關的訊號延遲較大的使其在內部的延遲變小而從記憶體 控制器所見的場合的記憶體存取時間變成一致的方式被使 用。 於格子狀延遲電路S QUAD，被供給時脈訊號 CCLK。此格子狀延遲電路SQUAD，對於上述被輸 入的時脈訊號C C LK，雖未有特別的限制，但是使其產 生6 4種微小延遲訊號。在上述格子狀延遲電路（ SQUAD)所被形成的6 4種微小延遲訊號，藉由多路 轉換器（MPX)選擇出一個，通過輸出電路作爲時脈訊 號D C L K而被輸出。控制計數器（Control Counter )，係 接受+1的遞增訊號INC與一1的遞減訊號而增加/減 少的計數器電路，形成9位元的計數輸出而供給至解碼器 電路（Decoder)。 (锖先閱讀背面之注意Ϋ-項再填寫本頁)This paper scale uses the Chinese National Standard (CNS) Λ4 specification (210X297 mm) • 12- V. Description of the invention (10) A7 B7 β Central standard of the Ministry of Economic Affairs and the seal of the goods and workers' cooperatives. The phase of the logic gate electrical circuit is reversed from the third paragraph to the second paragraph to the third paragraph to the fourth paragraph to the η terminal i η 1. The second input of the means is the input signal of the first input terminal of the n-th gate means of the n-th gate means arranged in the first direction. The second signal conveys the supplied input, and the input signal B 2 is input to the input signal T at the second signal input terminal i η 2. The first input circuit I Ν of the first signal transmission path to the last section 1 Up to the first input terminal segment of the input terminal, it precedes the input terminal i η to the m-1 input terminal number, and the m-th slave of the two input terminals is supplied. For example, it is presented in the upper direction. The first input signal B is supplied to input 5 in the direction of No. 1 transmission. 2 signal transmission The direction of arrival is the input terminal ini, which is supplied with buffers 3 to each output signal of INVm. The output signal of the first column in the m-th column is supplied to i η 1, and the output signal of the second column is supplied to the ini. In the same manner below, the output signal from the first stage is supplied to each logic gate 2 from the first input to the first stage to the nth stage, and the first stage from the first stage up to the nth stage in the first signal transmission direction. Input signals for each logic i η 1 are supplied. It is the first. In the direction of the second signal transmission, the logical in2 from the third paragraph to the nth paragraph, and the signal of the logic gate means from the first paragraph to the nth paragraph in the first signal, The first input terminal provided with the logic gate means having the first signal transmission direction in the same phase as the m-th segment is provided as the second input of the logic gate means in the first signal transmission direction with the first and third segments. Enter the signal T3. In the following, the signal T4 is inputted in the same way, and the input signal B3 is supplied in the direction of the nth paragraph. If the last paragraph is m, the latter paragraph is in the direction of the second signal transmission. National Standards (CNS) Λ4 specification (210X297 mm) -13-Α7 Β7 Printed by the Ministry of Economic Affairs Standards Bureau Ordnance Industry Consumer Cooperatives Co., Ltd. 5 'Invention Description (11) η-2 input signals B n — 2 are used as The input signal T η is provided to the input means i η 2 of the logic gate means of the first signal transmission direction which is the first η segment in the second signal transmission direction. Generally speaking, the above-mentioned first input terminal which is arranged at the logic gate means (K, L) which is in the first signal transmission direction other than the first K and which is the L-th stage in the second signal transmission direction is supplied. The output signal of the logic gate circuit in the first signal transmission direction is the same K, and the output signal of the second signal transmission direction is in the first L-1 stage, or the input clock signal is supplied by the first stage logic gate means. The second input terminal of the logic gate means (K, L) is supplied to the K-1 of the first one in the first signal transmission direction, and the logic gate means of the same L-th stage in the second signal transmission direction. Input signal of the first input terminal. The second input terminal of the logic gate means which is the first in the above-mentioned first signal transmission direction and the L-th in the second signal transmission direction is the last paragraph in the first signal transmission direction and in the above-mentioned second signal transmission direction In order to provide a logic gate method more advanced than that, an input signal is supplied to a first input terminal having an in-phase relationship with an input signal supplied to the first input terminal. The first and second input terminals of the logic gate means in the first signal transmission direction and the first logic gate means in the first signal transmission direction are supplied to the clock of the input circuit constituting the buffer circuit. The signal is supplied to each logic in the first signal transmission direction from the second to the last. The above-mentioned input clock signal of the first input terminal of the gate means is formed by the input circuit constituting the buffer circuit. The direction of the above first signal is conveyed. Please read the precautions on the back ^^ this page). Ο This paper size applies the Chinese national standard (('NS) Λ4 specification (210X297mm) -14-ill Central of the Ministry of Economic Affairs Printed by the Bureau of Standards, Industrial and Consumer Cooperatives ^ A7 _ B7__ V. Description of the invention (2) is sequentially delayed. The above buffer circuit is a delay correction unit constituting the input clock signal..., Inverter circuit I NV Each output signal of 1 ~ I NVm is sequentially delayed. For example, in order to form m clock delay signals S 1 ~ Sm whose phase is slightly shifted from the clock cycle from one clock input, a gate width is used. MO SFET Phaser circuit I NV 1 ~ I NVm. In short, although there are no particular restrictions on the input terminals of the inverter circuits INV1 to INVm of the buffer circuit described above, the input circuit IB receives a clock signal supplied from an external terminal. The output signal of the inverter circuit I NV1 is supplied in common, so that the output signal S 2 of the inverter circuit I NV2 is slower than the signal S 1 output from the inverter circuits I NV 1 and the inverter circuit I The output signal S 3 of NV 3 is slower and forms a signal that is sequentially delayed corresponding to the above-mentioned first signal transmission direction, and the related signals are input to the grid-like delay circuit as output clock signals. The above sequence is formed The circuits of the delayed signals S1, S2, ..... Sm are not limited to the above-mentioned embodiments. For example, in order to change the device characteristics of the MO SFET, the designation of the device beyond the gate width can be changed. In addition, circuit elements other than MOSFETs can also be used. The output signal formed by the above-mentioned grid-shaped delay circuit is, for example, the η-th segment that is the last segment in the second signal transmission direction, and the first signal The transmission direction is the output signal of the 1st to mth logic gate means. If the input clock signal is obtained as an in-phase and anti-phase output signal, it is added to the above-mentioned second signal transmission direction. Chapter {Please read the notes on the back before filling ^ this page) The size of the paper used in the edition is subject to Chinese national standards (('NS) Λ4 specifications (2) 〇 X 297 mm) • 15- Employees of the Central Bureau of Standards, Ministry of Economic Affairs Consumer Cooperative Indian Rice A7 B7 V. Description of the Invention (13) η 0 Paragraph 1, the output signal of the logic gate means set at the 1st to the mth in the direction of the first signal transmission "If it is a delay to select the output of multiple types In the case of a signal, it is only necessary to select a unit that has a small delay interval as described later. In short, a plurality of segments can be selected using the last segment as a reference in the second signal transmission direction. Fig. 2 is a circuit diagram showing another embodiment of a grid-shaped delay circuit according to the present invention. In this embodiment, an output buffer I NV L is provided for fetching an output signal in the logic unit. The other structures are the same as those of the first embodiment shown in FIG. 1. In the case of the grid-like delay circuit, only the buffer circuit for additional output in a specific section is provided in the second signal transmission direction, and the output load conditions in the specific section are different, and the input conditions are different from the next section. Therefore, in the above-mentioned grid-like logic gate method, only a specific segment becomes a different input / output condition, and it becomes impossible to obtain a fine delay signal with high accuracy. Here, in the embodiment shown in FIG. 2, the logic gate means arranged in a grid state are all added with an output buffer circuit IN VL regardless of whether or not an output signal is taken out. In this way, in the second signal transmission direction, the method of obtaining the output signal from the logic gate means arranged in an arbitrary section in the first transmission direction can also prevent the small signal delay time formed by this from being affected. The above-mentioned grid-like delay circuit of FIG. 1 or FIG. 2 can be understood as taking out a part of the aforementioned array oscillator and utilizing it. The boundary conditions of the array oscillator in the row direction and the column direction are the most in itself. Best Oscillator with Oscillation Frequency. In this regard, the grid-like delay circuit of the present invention, because (please read the note on the back and fill in this page) Order / 1 This paper size is applicable to the Chinese national standard (C'NS) Λ4 specification (21〇 × 297 (Mm) -16- A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs? Wooden Five. Description of the Invention (14) There is no feedback loop in the direction of the second signal transmission direction, so there is no oscillating action, the period of the clock signal being output, and the clock signal being input from the outside In addition, the clock signals that are sequentially delayed in the first signal transmission direction input to each delay segment are shifted by a small amount from the clock phase of the buffer circuits constituting the delay correction section relative to the clock period. However, it is not linearly arranged at a desired level of tens of picoseconds. However, the boundary condition between the delay correction part and the direction of the first signal transmission, that is, the connection between B h and τ η + 2, the clock delay signal passes through several delay elements, and the phase relationship of each delay section is corrected. The same linear phase relationship as the aforementioned array oscillator can be obtained. In addition, the circuit of this embodiment does not require a ring oscillator, so the startup time from the stopped state to the stable operation state is short. That is, the circuit of this embodiment is suitable for high-speed moving. In addition, due to the short start-up time, it is possible to reduce the power consumption of the semiconductor chip mounted with this circuit without using _ @. In the embodiment of FIG. 2, the logic gates of each delay element are connected only to the inputs of the logic gates of other delay elements in the array, and are added to the boundary conditions in the direction of the second signal transmission direction of the above delay segment direction. An output circuit I NVL is provided for the difference in the realized phase relationship without breaking the relationship, and the output signal of the linear phase relationship (small delay amount) is obtained through the related output circuit I NVL. Fig. 3A and B show characteristic diagrams obtained by computer simulation for explaining the operation of the lattice-shaped delay circuit according to the present invention. No. (Read the precautions on the back before you fill out this page) This paper size applies Chinese standards ((: NS > Λ4 size (21 OX 297 mm)) -17- Central Bureau of Standards, Ministry of Economic Affairs®; Industrial Consumption Cooperative prints A7 ___B7 V. Description of the invention (15) 3 Figure A shows the propagation of the occasion of the rising edge from the outside, and Figure 3 shows the propagation of the occasion of the falling edge from the outside. 3A and B, with the time axis as the y-axis, and the propagation of the rising edge (or falling edge) of each logic gate circuit segment arranged in the column direction is represented by a white ball (0), and the falling edge (or The rising edge) is represented by a black ball (·). The origin of the time axis is the rising edge or the falling edge of the external clock input. The input clock is a 50% pulse width load at 200 MHz. In FIGS. 3A and 3B, in the first and second paragraphs of the second transmission direction, the delay signals of the delay correction section are dominant, and the phase difference is not arranged at equal intervals (linear). However, in the fourth paragraph After that, the amount of slight delay in the rear side becomes constant, and it can be judged as above or in line. On the straight line. In Figure 3A and B, the positions of the edges of the odd-numbered segments are different because the delay element is a NAND gate circuit. The riser is connected to the 2 consecutive P-channel MOSFETs and lowered. It is driven by two N-channel MOSFETs connected in series, so the input and output timings are different. For this, the output of the even section is determined by the sum of the two different output timings. For this reason, Fig. 3 A and B are in the same position. Fig. 4 A, B, C, D, and E show circuit diagrams of other embodiments of delay elements used in the grid-shaped delay circuit. Fig. 4 In Figure A, a NOR gate circuit NR is used as a delay element. In short, a capacitor CP is provided as a coupling means between the two inputs i η 1 and i η 2 of the NOR gate circuit NR. The output signal A οut of this NOR gate circuit NR The Chinese paper scales ((WS) Λ4 specification (210X297 mm) are applied to the paper scales that are connected to other delay elements in the array on one side. (Please read the precautions on the back of this page before filling in this page). -V. Description of the invention (16) Input terminal of N 0 R gate circuit The other side is connected to the input terminal of the inverter circuit IVL which is an output buffer circuit to obtain an output signal. As shown in FIG. 4B, the two terminals of the inverter circuits IV 1 and IV 2 are connected in common as a delay element. In short, the input terminals ini and in 2 of the inverter circuits IV 1 and IV 2 are used as coupling means to connect the capacitor C P, and they are connected to the output terminals in common to obtain the output signal A 0 ut, and at the same time, they are supplied to the array at one side. The input terminal of the N OR gate circuit of other delay elements is supplied to the input terminal 0 of the inverter circuit IVL as an output buffer circuit to obtain an output signal.-In Fig. 4 C * Used as a delay element and The same NAND gate circuit ND described above uses a resistive element RG instead of a capacitor as a coupling means. The other structure is the same as that of the embodiment shown in FIG. 2 above. Therefore, the resistor RG, which is a Fengyu combination, can also be applied to the above-mentioned fourth ΓΗΪ Figure A and Figure B. 〇 By using a resistance element, it can be formed relatively small. The coupling element 0 in FIG. 4 D9-uses the same NAND circuit ND as the delay element, and uses a diode connected M 0 SF Ε Τ M1 and M2 as a coupling means instead of a capacitor. In short, the M0 S F Ε Τ Μ1 connected by the diodes transmits a signal current from the input terminal ini toward in2, and M2 reversely transmits a signal current from the input terminal in2 to ini. The other configurations are the same as those of the embodiment shown in FIG. 2 described above. The MOSFETs M1 and M 2 connected in this way as diodes are suitable for this paper. _F ((, NS) Λ4 specification (210X 297 mm) -19- V. Description of the invention (17) It can be applied to the above-mentioned Figures 4A and 4B. By using the MOSFET M1'M2, a coupling element can be formed by the same process as other MOSFETs. In Figure 4E, a differential circuit is used as a delay element. In short , ___________ "-The gates of the N-channel MOSFETs Q3 and Q4 connected in parallel are used as the normal first input terminals i η 1+ and i η 2+ and an affinity capacitor C 1 is provided. The drain is set as the load of the p-channel MOSFETs Q1 and Q2 to obtain an inverted output ou t —. The gate of the N-channel MOSFET Q 7 ′ Q8 connected in parallel is used as the first input terminal i nl — And i n2-a coupling capacitor C 2 is provided at the common drain electrode as a load, and ρ channel MOSFETs Q5 and Q5 simultaneously obtain a positive-phase output ou t +. MOSFETs Q3 and Q4 and Q7 and Q7 for differential operation The source of Q 8 is equipped with an N-channel MOSFET that allows an operating current to flow. Q 9 ° P-channel MOSFET Q 2 and Q6 'Same as the above-mentioned P-channel MOSFET Q9, the current flowing through the control voltage V ctr 1 is adjusted to control the delay time in the vicinity of the first stage. "It is set between the above-mentioned MOSFETs Q3 and Q4 and Q7 and Q8. The coupling capacitors C1 and C2 can be replaced with resistors or MO S diodes as shown in Figures 4C and 4D above. Figures 5A and 5B show grid-shaped delay circuits related to the present invention. The characteristic diagram of the function of the coupling means. In this embodiment, as shown in FIG. 4B, two inverting circuits are used as the delay element. (Please read the precautions on the back before filling this page) This paper scale applies to China ’s national standard (〇 «) 6 4 specifications (210 father 297 mm) -20- Central Standards Bureau of the Ministry of Economic Affairs prints meals for industrial and consumer cooperatives A7 _B7 V. Invention description (18) Common output, and Figure 4 shows the characteristic diagram by computer simulation. Figure 4A shows an example of obtaining a capacitor with a relatively large capacitor of about 1 p F as a coupling means as shown in the embodiment of Figure 2 above. In this way, two input signals are used. If the combination of The delay signal in the delay correction section of the two-stage first stage becomes the dominant signal. Although the phase difference is not arranged at equal intervals (linear), it can be seen that the slight delay amount on the rear side is constant compared to the fourth stage. In this regard, FIG. 5B shows an example of a case where the capacitance of the capacitor is reduced so that the combination of the two input signals is small. If the capacitance 値 of the input coupling capacitor is reduced as described above, the linearity of the above 0 or • is deteriorated even at the rear side of the second signal transmission direction. However, the improvement in the rear side can be recognized in comparison with the front side. In Fig. 6, the characteristics obtained by computer simulation in the case where the output of the two inverter circuits are common are used under the same conditions as in the case of Figs. Illustration. When the coupling means is removed in this way, although the second signal transmission direction also has a certain time difference on the rear side, but in terms of the first signal transmission direction, which is used as a variable delay circuit that can set a desired small amount of delay, the first The arrangement from 1 to the third has a slight delay difference *, but there is no time difference in the future. It can be seen that even if you look at the whole, it cannot be used as the above-mentioned small delay circuit. As described above, the combination of the signals that are sequentially delayed in the first signal transmission direction and the signals that are sequentially delayed in the second signal transmission direction are closely combined, and the two phases of the same phase relationship of the second signal transmission direction Delay (Please read the notes on the back before filling in this page) Ordering rj · This paper size is applicable to China Standards (CNS) Λ4 specifications (2 丨 0X 297 mm) -21-Α7 Β7 中央 Central Standards Bureau Bej-Published by the Society of Japan%. 5. Description of the invention (19) Although the time delay is allocated to the first transmission, the delay is small. Although the input signals do not interfere with each other for this reason, the averaging achieves the delay as described above. . When the amplifier is reversed from another angle, and the input of the two inputs is performed, the signal transmission of the signal can be equalized in the part with good linearity. The signal is equalized so that the two input signals are coupled between the two input terminals. The same effect is obtained when the input wiring is extremely close to the component. The second signal time is arranged at the first pass to obtain a degree of signal delay that will delay the combined signal path of the two input signals. The combination will make the childlike approach meaningless. In Fig. 7, a waveform chart showing the operation of the supply path is shown. The number of delay elements in the direction of the rising end of the output signal is evenly divided. The linearity has an important function. It can be analyzed quantitatively, but it can be considered that the signal change of each delay element in a two-lattice pattern is described as a small amount with good linearity. The above delay element can be regarded as a kind of input signal coupled to the phase pendulum. The inverse increase is considered to be the result of the increase in the straight number when looking at the input / output transmission characteristics, and each of the grid-like delays needs to obtain a good linearity as described above. In this embodiment, the method for setting the coupling element is not limited to this. For example, by using the configuration, the coupling element can be obtained and provided, and there is no need to add a special coupling element. The two-phase delay of the in-phase relationship of the direction of transmission is equally delayed by the number of delay elements in the direction of arrival, so it cannot lead to the above-mentioned theory completely. In short, the two signal transmission directions cause mutual loss to another signal delay element. The gate circuit and the like which are delay elements are set in grids. The grid-shaped delay circuit related to the present invention will be described below. For example, see the central edge shown on the time axis as an example, you can see that in addition to the first few (please read the precautions on the back before filling this page), -0 Θ This paper size applies the Chinese national standard < CNS > Λ4 Specifications (210X297 mm) -22- Jingqiu-Ministry Central Bureau of Standards Bureau staff elimination. # 社 印 A7 B7 V. Invention description (20), the rise of the clock signal is about 50 picoseconds, etc. The interval rises. Regarding the falling edge of the output signal, it can be seen that the drop of the clock signal on the front side and the rear side of the time axis is about 50 picoseconds at an equal interval. It can be seen that on the back side of the time axis, the initial drop of the clock signal is messy. FIG. 8 shows a block diagram of an embodiment of a clock generation circuit using the above-mentioned grid-shaped delay circuit according to the present invention. The clock generation circuit of this embodiment is, for example, mounted on a semiconductor such as a dynamic RAM. If the signal transmission delay between the memory device, the related plural RAMs and the memory controller that controls it is on the mounting board is consistent, in other words, the signal propagation delay on the mounting substrate is estimated. In order to make the delay of the related signal smaller internally, the delay time becomes larger, and the delay of the related signal larger makes the internal delay smaller, and the memory access time of the occasion seen from the memory controller becomes A consistent approach is used. A clock signal CCLK is supplied to the grid-like delay circuit S QUAD. Although this grid-shaped delay circuit SQUAD has no particular limitation on the clock signal C C LK inputted above, it generates 6 or 4 types of minute delay signals. Six or four types of micro-delay signals formed by the above-mentioned grid-like delay circuit (SQUAD) are selected by a multiplexer (MPX), and are output as clock signals D C L K through an output circuit. The control counter is a counter circuit that receives +1 increment signal INC and -1 decrement signal to increase / decrease, forms a 9-bit count output and supplies it to the decoder circuit (Decoder). (锖 Please read the note on the backΫ-item before filling this page)

本紙張尺度通用中國1家標CNS ) Λ4規格（210X 297公釐） -23 - 經濟部中央標隼局Μ工消费合作社印製 A7 ___B7 _五、發明説明（21 ) 在解碼器電路（Decoder)，形成由1 2位元所構成的 選擇訊號控制上述多路轉換器（MPX)，形成5位元的 前設訊號輸入至時脈計數器電路（CLK counter)。此時脈 計數器電路（CLK counter)，藉由訊號READ而被活性 化，進行時脈訊號C C L K的計數動作，在被指定的時脈 來到時，使產生授權（Enable)訊號，將上述輸出電路活性 化，作爲該時的被微小量延遲控制的資料選通脈衝（Strobe )而使時脈訊號DCLK輸出》 未圖示的記憶體控制器，輸出爲了對於上述時脈產生 電路進行資料選通脈衝訊號D C L K的調整之控制訊號。 上述控制計數器電路_( Control ..Counter)藉_由來自記憶體控 制器的指示，進行計上或者下之計數動作，該計數値被對 應於上述D C LK的輸出計時，將作爲上述資料選通脈衝 的時脈訊號DCLK的產生計時以約5 0微微秒的單位增 快或是延遲。總之，於電源打開之後，設有訓練期間指示 來自記憶體控制器的RAM讀出，以使該讀出訊號配合所 要的計時的方式進行上述的計上或者下，而進行時脈計時 調整。 於第9圖，顯示上述控制計數器電路之一實施例的電 路圖。將T型正反器接續爲縱列形態，通過將其非反轉輸 出Q或是反轉輸出/Q與指示計下動作的遞減訊號D E C ，及指示計上動作的遞增訊號I N C所控制的N 0 R閘電 路組合而被構成的選擇電路而被供給至下一段電路的輸入 端子T，藉此使進行計上或者計下動作者。 (請先閱讀背面之注意事項再填寫本頁) -訂 本紙張尺度適用中國國家標牟（CNS ) Λ4規格（210X297公釐） -24- 經清‘部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（22 ) 於第1 0圖，顯示上述解碼器電路之一實施例的電路 圖。解碼器電路，在上述控制計數器電路被形成的計數輸 出CNTO〜CNT9之中，下位6位元的計數輸出 CNT〇〜CNT5被使用作爲供形成多路轉換器MPX 用的選擇訊號之用。也就是說，上述6位元的計數輸出 CNT〇〜CNT5隻中，下位位元CNTO與CNT1 解碼形成DECOO〜03，將中位2位元CNT2、 CNT3解碼形成DEC20〜23，將上位2位元 CNT4、CNT5解碼形成DEC4 0〜43。這些 4X3=12種的解碼訊號DECOO〜DEC43，作 爲多路轉換器Μ P X的選擇訊號而被使用》 在上述控制計數器電路所被形成的計數輸出C Ν Τ 〇 〜C NT 9之中的上位3位元的計數輸出C Ν Τ 6〜 CNT8，CNT6係直接被輸出，上位2位元的計數輸 出01^1'7與01^丁8被解碼形成0£€70〜7 3。這 些解碼訊號DEC6與DEC70〜73，被供給至時脈 計數器電路（CLK Counter)。 於第1 1圖，顯示上述多路轉換器MPX之一實施例 的電路圖。在如前述般的格子狀延遲電路SQUAD所被 形成的64種延遲時脈訊號CLK0〜CKL6 3，如 CLK0〜CLK3的方式以4個爲1組，分爲16組被 輸入至4輸入的多路轉換器。此四輸入的多路轉換器，如 該圖所例示般的，由CMO S開關電路與輸出CMO S反 相器電路所構成。於合計由1 6個所構成的4輸入之多路 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁)The paper size is common to China's 1 standard CNS) Λ4 specification (210X 297 mm) -23-Printed by the Ministry of Economic Affairs Central Standards Bureau M Industrial Consumer Cooperative A7 ___B7 _V. Description of the invention (21) In the decoder circuit , Forming a selection signal composed of 12 bits to control the multiplexer (MPX), and forming a 5-bit pre-set signal to be input to a clock counter circuit (CLK counter). The clock counter circuit (CLK counter) is activated by the signal READ to perform the counting operation of the clock signal CCLK. When the designated clock arrives, it generates an Enable signal and outputs the output circuit. Activated to output the clock signal DCLK as a data strobe controlled by a small amount of delay at this time. A memory controller (not shown) outputs a data strobe for the clock generation circuit. Control signal for signal DCLK adjustment. The above-mentioned control counter circuit ((Control..Counter)) counts up or down by instructions from the memory controller. The count is counted by the output of the DC LK and will be used as the data strobe pulse. The timing of the clock signal DCLK is increased or delayed in units of about 50 picoseconds. In short, after the power is turned on, a RAM readout instruction from the memory controller is provided during the training period, and the readout signal is used to perform the above counting up or down to adjust the clock timing. Fig. 9 shows a circuit diagram of an embodiment of the control counter circuit described above. The T-type flip-flop is connected to a tandem form, and its non-inverting output Q or inverting output / Q and the decrement signal DEC indicating the operation under the indicator and the incremental signal INC controlled by the operation on the indicator N 0 The selection circuit formed by combining the R gate circuits is supplied to the input terminal T of the next-stage circuit, thereby allowing the operator to perform counting or counting. (Please read the notes on the back before filling in this page)-The size of the paper is applicable to China National Standards (CNS) Λ4 specification (210X297 mm) -24- Printed by the Central Bureau of Standardization of the Ministry of Economic Affairs, printed by A7 B7 V. Description of the Invention (22) Fig. 10 shows a circuit diagram of one embodiment of the decoder circuit described above. In the decoder circuit, among the count outputs CNTO to CNT9 formed by the control counter circuit, the lower 6-bit count outputs CNT0 to CNT5 are used as selection signals for forming the multiplexer MPX. In other words, among the above 6-bit count outputs CNT0 to CNT5, the lower bits CNTO and CNT1 are decoded to form DECOO ~ 03, the median 2 bits CNT2 and CNT3 are decoded to form DEC20 ~ 23, and the upper 2 bits are decoded. CNT4 and CNT5 are decoded to form DEC4 0 ~ 43. These 4X3 = 12 kinds of decoding signals DECOO ~ DEC43 are used as selection signals of the multiplexer MPX. The upper 3 of the count outputs C Ν Τ 〇 ~ C NT 9 formed by the above control counter circuit The bit count outputs C Ν Τ 6 to CNT8, CNT6 are directly output, and the upper 2-bit count outputs 01 ^ 1'7 and 01 ^ 丁 8 are decoded to form 0 £ € 70 ~ 73. These decoded signals DEC6 and DEC70 to 73 are supplied to a clock counter circuit (CLK Counter). Fig. 11 shows a circuit diagram of an embodiment of the above-mentioned multiplexer MPX. The 64 types of delayed clock signals CLK0 to CKL6 3 formed by the grid-like delay circuit SQUAD as described above, such as CLK0 to CLK3, are divided into four groups of four and divided into 16 groups. converter. The four-input multiplexer, as illustrated in the figure, is composed of a CMO S switching circuit and an output CMO S inverter circuit. In total, there are 4 inputs with 16 inputs. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)

,tT %_ -25- A7 _B7____ 五、發明说明（23 ) 轉換器，共通被供給上述下位位元的解碼輸出D E C 〇 〇 〜DE C 0 3 ,從各多路轉換器選擇1個時脈訊號。 由上述1 6個多路轉換器所選擇的1 6個時脈訊號， 與上述同樣被以4個1組分爲4組被輸入4輸入的多路轉 換器。於這些4組之多路轉換器，被共通供給中間位元之 解碼輸出D E C 2 0〜D E C 2 3而從各多路轉換器選擇 1個時脈訊號》接著，藉由上述多路轉換器所選擇的4個 時脈訊號被同樣地輸入至4輸入的多路轉換器，藉由上位 位元的解碼輸出D E C 4 0〜D E C 4 3選擇其中之一作 爲輸出時脈訊號CLKOUT。 於第1 2圖，顯示上述時脈計數器電路（CLK Counter )之一實施例的電路圖。於此時脈計數器電路，被供給上 述解碼器電路的輸出訊號D E C 6以及D E C 7 0〜7 3 作爲計數開始値，換句話說，就是初期値。上述5位元之 中的最下位位元所對應的解碼輸出DEC6，被使用於控 制設於計數輸出的最後一段的多路轉換器。 經濟部中央標隼局β Η消费合作社印？衣 (請先閲讀背面之注意事項再填寫本頁) 此時脈計數器電嗥，係僅使輝漫增定的時脈週期使前 述輸出電路活性化，使輸出時脈訊號D C LK者。總之， 對應於以上述控制計數器電路所被形成的計數値而將開始 値作爲初期値進行移位動作，僅延遲該移位動作所需要的 時脈份量形成授權訊號ENABLE。藉此RAM，同步於與來 自成爲基準的時脈的僅有被指定的時脈數延遲產生的時脈 訊號D C L K而進行資料輸出動作。 在此實施例，以使可以僅延遲上述時脈C C L K之 本紙張尺度通/1]中國國家標啤（CNS ) Λ4規格（210X297公釐） -26- A7 B7 經滴部中央標芈局負工消费合作社印^ 五、發明説明（24 ) 〇 · 5個週期（半個週期）的份量形成活性化訊號（ ENABLE)的方式被設有多路轉換器。解碼器電路的輸出訊 號（DEC7 0〜7 3)之中僅有1個成爲高準位H， DCLK產生訊號（READ)被輸入至利用主從正反器 電路（master slave flipflop circuit)的移位暫存器，於指 定的時脈週期後使產生上述活性化訊號D C L K。藉由根 據將此多路轉換器對應於輸出訊號（DE C 7 0〜7 3 ) 的4段之上述正反器而在延遲段的最後一段之將延遲訊號 以上述計數輸出CNT6進行控制，使輸出半個週期前的 主側輸出OUTH，這是由於將來自1個週期的延遲動作 的從側的輸出0 U T使其輸出而實現者》 例如，如前述般的使用2 0 ΟΜΗ z的外部時脈的場 合，在時脈計數器電路進行2 . 5 n s e c單位的延遲調 整，將其間藉由上述格子狀延遲電路S QUAD進行約 4 0微微秒單位的調整。因此在上述格子狀延遲電路 SQUAD，以4 0微微秒的刻度產生64種類的延遲訊 號。這是因爲40微微秒x64=2.5nsec的緣故 。此實施例之解碼器或是多路轉換器，係基於如此的數値 而被設計者。延遲調整的變動域爲22 . 5n s e c。 於第1 3圖，顯示使用相關於本發明之上述格子狀延 遲電路的時脈產生電路的另一實施例的方塊圖。在此實施 例的時脈產生電路，於在前述第8圖已經說明的時脈產生 電路之格子狀延遲電路S QUAD之前段處設有其他的延 〇!·~— —— — · - · · - - . . . . 1 遲要素（COARSE DELAY )。藉由如此般的延遲要素的插 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適扣中國國家標埤（CNS ) Λ4規格（210X297公釐） 27- 五、發明説明（25)入可以謀求延遲調整範圍1¾變多。 於第1 4圖，顯示上述延遲要素（COARSE DELAY ) 之一實施例的電路圖。此延遲要素，係使被直列接續的2 輸入之N A N D閘電路與反相器電路的延遲時間成爲輸出 (0 U T )的延遲時間的調整單位者》藉由解碼器電路而 被輸出的8條控制訊號之中，僅有1條成爲高準位，對應 於該控制訊號的1個N A N D閘電路打開閘，將輸入訊號 I N供給至被上述直列接續的N A N D閘電路列的1個輸 入。總之，上述直列接續的NAND閘電路與反相器電路 之段數，係藉由上述控制訊號而決定傳達輸入訊號I N的 上述調整單位的數目。 - 於第1 3圖的實施例，藉由在上述格子狀延遲電路 SQUAD的前段設上述之延遲要素（COARSE DELAY) ，例如使用2 0 ΟΜΗ z的外部時脈訊號的場合，上述格 子狀延遲電路SQUAD，只需大約以4 0微微秒的刻度 產生8種類的延遲訊號即可，可以大幅削減格子狀延遲電 路S Q UA D以及多路轉換器MP X的電路規模》 於第1 5圖，顯示被適用本發明之半導體記憶體系統 的一實施例之方塊圖。此實施例之半導體記憶體系統，係 由記憶體控制器MC與複數動態型RAM (DRAM)或 \ 者計記億體模組所構成，分別具有供特定其自身之I D。 訊號S 0係上述I D設定用的訊號。 記億體控制器M C，在電源打開之後進行訓練動作。 總之，與時脈訊號C CLK同步接受指令（CA0 — 9 ) (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（（’NS ) Λ4規格（210X297公釐） -28- 五、發明説明（26 ) (請先閱諫背面之注意事項再填寫本頁) ，首先選擇第1個DRAM，使輸出資料（DOO — 1 5 )以及D C LK。也將此動作對第2個〜第8個DRAM 進行。接受這些D C L K，以使這些成爲一定的延遲量的. 方式控制被搭載於各D RAM上的上述時脈產生電路。藉 此，從記億體控制器MC來看的場合，在與DRAM之間 的實裝基板上的訊號延遲藉由上述計時調整而被吸收，對 於任一D RAM都可以相等的計時取入資料，因此f保週 期時間內之可以取入資料的時間變得$荽易，週期時間的 高速化成爲可能，例如可以將時脈訊號C C L K的頻率設 定爲如200MHz般的高頻率。 於第1 6圖，顯示供說明上述半導體記億體系統之被 設於D R AM側的時脈產生電路的動作之用的計時圖。同 步於外部時脈訊號CCLK，從格子狀延遲電路 SQUAD，產生將其微小量延遲的複數時脈訊號。多路 轉換器MPX，形成以上述計數器控制器電路所指定的1 個延遲訊號而輸出。. 藉由計數器控制器電路接受讀取訊號R E A D，僅延 遲被指定的時脈訊號C C L K的數目使產生授權訊號 ENABLE ,上述多路轉換器MP X的輸出訊號被作爲內部時 脈訊號D C L K而被輸出。於上述讀取訊號R E A D在高 準位的有效期間，上述時脈訊號D C L K被輸出複數個者 。在此實施例，在與上述記憶體控制器間的訊_號傳達延_ 時間所應補償的上述內部時脈訊號D C L K被產生的緣故 t _ . —— 一... . ， ............. ，所以使得使用例如2 0 0M Η z般的高頻率的時脈訊號 本紙張尺度適用中國國家標埤（CNS > Λ4規格（210X297公釐） -29- A7 B7 經濟部中央標準局兵工消费合作社印掣 五、發明説明（27 ) C C L K之記億體存取成爲可能。 於第1 7圖，顯示使用了相關於本發明的格子狀延遲 電路的D ‘‘L L電路的一實施例的方塊圖。將外部時脈訊號 供給至上述格子狀延遲電路S QUAD，如前述般的形成 複數種延遲訊號。多路轉換器Μ P X選擇上述複數個延遲 訊號之一形成內部時脈訊號。此內部時脈訊號與被從上述 外部端子所供給的時脈訊號在柑位比較器（PHASE COMPARATOR)進行比較，將其比較結果供給至控制器（ CONTROLER)，形成控制訊號。在解碼器電路（DECODER )將上述控制訊號解碼形成多路轉換器MPX的選擇訊號 ，藉此可以謀求外部時脈訊號與內部時脈訊號的同步化。 控制器雖未有特別的限制，係由計數器電路所構成， 如第1 8圖所示的計時圖，從上述相位比較器的輸出向上 計數或是向下計數。爲了使外部時脈訊號與內部時脈訊號 同步化的時間縮短，構成上述控制器的計數器，將最上位 位元設爲1作爲初期値，藉由多路轉換器MP X使輸出來 自上述格子狀延遲電路S QUAD的調整範圍中點的延遲 訊號，如果內部時脈的相位超前的話則向上計數使增加延 遲量，如果內部時脈的相位已有延遲的話則向下計數使延 遲量減少。藉由如此的控制，可以形成與外部時脈訊號相 位同步的內部時脈訊號。在此實施例之D L L電路，因爲 如上述般的格子狀延遲電路的延遲數位數10微微秒的緣 故，所以可以實現高精度的相位時脈動作》 於上述格子狀延遲電路S QUAD的輸入側，如前述 (諳先聞讀背面之注意事項再填寫本頁), tT% _ -25- A7 _B7____ 5. Description of the Invention (23) The converter is commonly supplied with the above-mentioned decoding output of the lower bits DEC 〇〇 ～ DE C 0 3, and selects a clock signal from each multiplexer . The 16 clock signals selected by the above 16 multiplexers are inputted into the 4 input multiplexers in the same way as 4 groups with 4 groups. In these four groups of multiplexers, the decoded output DEC 2 0 to DEC 2 3 which are commonly supplied to the middle bit are selected from each multiplexer. Then, a clock signal is selected from the multiplexers. The selected four clock signals are similarly input to a four-input multiplexer, and one of them is selected as the output clock signal CLKOUT by the decoding output of the upper bits DEC 4 0 to DEC 4 3. FIG. 12 shows a circuit diagram of an embodiment of the above-mentioned clock counter circuit (CLK Counter). At the clock counter circuit, the output signals DE C 6 and DE C 7 0 to 7 3 of the above-mentioned decoder circuit are supplied as the counting start 値, in other words, the initial 値. The decoded output DEC6 corresponding to the lowest bit of the above-mentioned five bits is used to control the multiplexer provided at the last stage of the count output. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, β, Consumer Cooperatives? (Please read the precautions on the back before filling out this page) The pulse counter voltage is only used to activate the aforementioned output circuit and increase the clock signal D C LK. In short, the shift operation is performed with the start 値 as an initial phase corresponding to the count 形成 formed by the control counter circuit described above, and only the clock amount necessary for the shift operation is delayed to form the authorization signal ENABLE. With this RAM, data is output in synchronization with the clock signal D C L K which is generated by delaying only the specified clock number from the reference clock. In this embodiment, the paper size of the clock CCLK can be delayed only / 1] China National Standard Beer (CNS) Λ4 specification (210X297 mm) -26- A7 B7 Consumption cooperative seal ^ V. Description of the invention (24) 〇 5 cycles (half cycle) of the way to form the activation signal (ENABLE) is provided with a multiplexer. Only one of the output signals of the decoder circuit (DEC7 0 ~ 7 3) becomes the high level H, and the DCLK generation signal (READ) is input to the shift using the master slave flipflop circuit The register is used to generate the activation signal DCLK after a specified clock period. According to the above-mentioned flip-flops corresponding to 4 segments of the output signal (DE C 7 0 ~ 7 3), the multiplexer controls the delayed signal with the above-mentioned count output CNT6 in the last segment of the delay segment, so that The output of the master-side output OUTH half a cycle ago is achieved by outputting 0 UT of the slave-side output from the one-cycle delay operation. For example, when using an external of 2 0 ΜΜ z as described above In the case of pulses, the clock counter circuit performs a delay adjustment in units of 2.5 nsec, and in the meantime, it is adjusted in units of about 40 picoseconds by the grid-like delay circuit S QUAD. Therefore, in the above-mentioned grid-like delay circuit SQUAD, 64 types of delay signals are generated at a scale of 40 picoseconds. This is because 40 picoseconds x64 = 2.5nsec. The decoder or multiplexer of this embodiment is designed based on such data. The range of delay adjustment is 22.5 n s e c. Fig. 13 is a block diagram showing another embodiment of a clock generating circuit using the above-mentioned grid-like delay circuit according to the present invention. In the clock generation circuit of this embodiment, other delays are provided in front of the grid-shaped delay circuit S QUAD of the clock generation circuit already described in FIG. 8 above! --.... 1 COARSE DELAY. With the insertion of such delay elements (please read the notes on the back before filling this page) The size of the paper is suitable for the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 27- V. Description of the invention (25 ) Into the delay adjustment range 1¾ can be increased. FIG. 14 shows a circuit diagram of an embodiment of the above-mentioned delay element (COARSE DELAY). This delay element is a unit that adjusts the delay time of the two-input NAND gate circuit and inverter circuit in series to be the output (0 UT) delay time adjustment unit. Eight controls are output by the decoder circuit. Among the signals, only one of them becomes a high level, and one NAND gate circuit corresponding to the control signal opens the gate, and the input signal IN is supplied to one input of the NAND gate circuit column connected in series. In short, the number of segments of the in-line NAND gate circuit and the inverter circuit is determined by the above-mentioned control signal, and the number of the above-mentioned adjustment units for transmitting the input signal I N is determined. -In the embodiment of FIG. 13, the above-mentioned delay element (COARSE DELAY) is set in the front section of the above-mentioned grid-shaped delay circuit SQUAD. For example, when an external clock signal of 200 MHz is used, the above-mentioned grid-shaped delay circuit is used. SQUAD only needs to generate 8 types of delay signals with a scale of about 40 picoseconds, which can greatly reduce the circuit scale of the grid-like delay circuit SQ UA D and the multiplexer MP X. A block diagram of an embodiment of a semiconductor memory system to which the present invention is applied. The semiconductor memory system of this embodiment is composed of a memory controller MC and a complex dynamic RAM (DRAM) or a memory module, each of which has an ID for specifying itself. The signal S 0 is a signal for the aforementioned ID setting. The billion body controller MC performs training exercises after the power is turned on. In short, accept the instruction synchronously with the clock signal C CLK (CA0 — 9) (Please read the precautions on the back before filling this page) This paper size applies to the Chinese national standard (('NS) Λ4 specification (210X297 mm) -28 -V. Description of the invention (26) (Please read the notes on the back of the page before filling out this page), first select the first DRAM to output data (DOO — 1 5) and DC LK. This action is also performed on the second To 8th DRAMs. These DCLKs are received so that these become a certain amount of delay. The above-mentioned clock generation circuit mounted on each D RAM is controlled. From this, from the memory controller MC In the case of, the signal delay on the mounting substrate between the DRAM and the DRAM is absorbed by the above timing adjustment. For any D RAM, the data can be accessed at the same timing, so the data can be accessed during the f warranty period. Time becomes easy, and high-speed cycle time becomes possible. For example, the frequency of the clock signal CCLK can be set to a high frequency such as 200MHz. Figure 16 shows the description of the semiconductor memory system. Set in DR AM The timing chart for the operation of the clock generating circuit. Synchronous to the external clock signal CCLK, from the grid-like delay circuit SQUAD, a complex clock signal is generated which delays it by a small amount. The multiplexer MPX forms the above counter The controller circuit outputs a delay signal specified by the controller circuit. The counter controller circuit accepts the read signal READ and only delays the specified number of clock signals CCLK to generate the authorized signal ENABLE. The above-mentioned multiplexer MP X The output signal is output as the internal clock signal DCLK. During the valid period of the read signal READ in the high level, the clock signal DCLK is output in multiples. In this embodiment, it is controlled with the above memory. The signal _ signal transmission delay _ time should be compensated for the above internal clock signal DCLK is generated because t _. —— a ..... ....... The use of high-frequency clock signals such as 2000M Η z makes this paper standard applicable to China's national standard (CNS > Λ4 specification (210X297 mm) -29- A7 B7 Ordnance Industry Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs Imprint 5. Description of the invention (27) CCLK memory access is possible. Figure 17 shows a block diagram of an embodiment of the D "LL circuit using the grid-like delay circuit in accordance with the present invention. The external clock signal is supplied to the above-mentioned grid-shaped delay circuit S QUAD to form a plurality of delay signals as described above. The multiplexer MPX selects one of the plurality of delay signals to form an internal clock signal. This internal clock signal is compared with the clock signal supplied from the external terminal in a PHASE COMPARATOR, and the comparison result is supplied to a controller to form a control signal. The decoder circuit (DECODER) decodes the above control signal to form a selection signal of the multiplexer MPX, thereby synchronizing the external clock signal with the internal clock signal. Although the controller is not particularly limited, it is constituted by a counter circuit. As shown in FIG. 18, the timing chart counts up or down from the output of the phase comparator. In order to shorten the synchronization time between the external clock signal and the internal clock signal, the counter of the controller is configured, and the uppermost bit is set to 1 as an initial stage. The output from the above-mentioned grid is made by the multiplexer MP X The delay signal at the midpoint of the adjustment range of the delay circuit S QUAD. If the phase of the internal clock is advanced, it counts up to increase the amount of delay. If the phase of the internal clock is delayed, it counts down to decrease the amount of delay. With this control, an internal clock signal can be formed that is phase-synchronized with the external clock signal. In the DLL circuit of this embodiment, the delay digits of the grid-like delay circuit as described above are 10 picoseconds, so that a high-accuracy phase clock operation can be realized. As mentioned above (谙 first read the notes on the back and then fill out this page)

-、1T 本紙張尺度適用中國S家標埤（CNS ) Λ4規格（210X297公釐） •30· 經濟部中央梂準局貝工消费合作社印製 A7 ___B7五、發明説明（28 ) .第1 4圖所示般的***延遲要素，即使外部時脈的頻率較 低的場合’也可以謀求藉由上述格子狀延遲電路而進行高 精S的相位同步化。或者是，也可以使格子狀延遲電路與 多路轉換器的電路規模縮小》 於第1 9圖，顯示相關於本發明的格子狀延遲電路的 一實施例的配置圖。在此實施例，顯示著電路圖的形態， 但是作爲延遲電路之邏輯閘手段，係配合半導體幾何學的 配置而描繪的。在此實施例，以使由被排列在前述第1訊 號傳達方向的m個所構成的第η段的邏輯閘手段列，與較 其2段之後η + 2的邏輯閘手段列並排在一直線上的方式 配置。鄰接橫跨這2個邏輯閘手段列的後半與前半1段之 後的η + 1段的邏輯閘手段列被配置。如此，藉由將邏輯 閘列以每個半列相互錯開而配置，可以將上述格子狀延遲 電路構成2列的邏輯閘手段。 於如此的空間配置，將各邏輯閘手段進行在第1訊號 傳達方向與第2訊號傳達方向的格子狀的訊號傳達，可以 使這些訊號傳達之用的配線長度於各邏輯閘手段皆爲相等 長度，可以實現以高精度達成上述微小量延遲。而且，即 使獲得多數輸出訊號的場合，在被配置於上側的邏輯閘手 段可獲得來自上側的輸出訊號，在被配置於下側的邏輯閘 手段可獲得來自下側的輸出訊號的緣故，在輸出訊號路徑 上的訊號延遲也可以相互相等，所以可以實現更高精度的 微小量訊號延遲》 於第2 0圖，顯示被適用本發明的同步DRAM (以 (請先閲讀背面之注意事項再填寫本頁) -訂 ♦ 本紙張尺度適用中國國家標率（rNS ) Λ4規格（2丨0X297公釐） -31 - A7 _______B7_^_______五、發明説明（29 ) 下，簡稱爲S DRAM)之一實施例的全體方塊圖。被顯 示於該圖的SDRAM，雖未有特別的限制，但是係藉由 習知的半導體積體電路製造技術而被形成於例如單結晶矽 之類的1個半導體基板上。 此實施例之SDRAM，具備構成記億體區庫0的記 憶體陣列2 Ο 0A，與構成記憶體區庫1的記憶體陣列 200B。記億體20 0A與200B分別具備被矩陣配 置的動態型記憶體細胞，根據圖示被配置於同一列的記憶 體細胞的選擇端子，被結合於每一列的字（Word )線（未 圖示），被配置於每一行的記憶體細胞的資料輸出入端子 於每一行被結合於互補資料線（.未圖示）》 上述記憶體陣列2 0 0 A的未圖示之字線係依照根據 列解碼器2 0 1 A之列位址訊號的解碼結果而有1條被驅 動爲選擇準位。記憶體陣列2 0 0 A的未圖示的互補資料 線被結合於包含感覺擴大器以及行選擇電路的I/0線 2 0 2 A。包含感覺擴大器以及行選擇電路的I /0線 2 0 2 A之感覺擴大器，係藉由來自記憶體細胞的資料讀 出而檢測初出限於各個互補資料線的微小電位差使其擴大 之擴大電路。其之行開關電路，係將互補資料線個別選擇 使導通於互補I /0線之用的開關電路。行開關電路依照 跟據行解碼器2 0 3 A之行位址訊號的解碼結果而被選擇 動作。 於記憶體陣列2 0 0 B側也同樣地列解碼器2 0 0 B ，包含感覺擴大器以及行選擇電路的I /〇線2 0 2 B， (請先閲讀背面之注意事項再填寫本頁)-、 1T This paper size is applicable to China S standard (CNS) Λ4 specification (210X297 mm) • 30 · Printed by A7 _B7 printed by the Shellfish Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of invention (28). 1 4 The insertion delay element shown in the figure can achieve phase synchronization of high-precision S by the above-mentioned grid-shaped delay circuit even when the frequency of the external clock is low. Alternatively, the scale of the grid-like delay circuit and the multiplexer circuit can be reduced. Fig. 19 shows a layout diagram of an embodiment of the grid-like delay circuit according to the present invention. In this embodiment, a circuit diagram is shown, but as a logic gate means of the delay circuit, it is drawn in accordance with the configuration of the semiconductor geometry. In this embodiment, the logic gate means of the nth segment, which is composed of m pieces arranged in the aforementioned first signal transmission direction, is aligned side by side with the logic gate means of η + 2 after the two segments. Way configuration. The logic gates adjacent to the n + 1 segment after the second half of the two logic gates and the first half of the first half are arranged. As described above, by arranging the logic gates in a half-column arrangement with each other, the above-mentioned grid-shaped delay circuit can be configured as a logic gate in two rows. In such a spatial arrangement, each logic gate means is transmitted in a grid-like signal direction in the first signal transmission direction and the second signal transmission direction, so that the wiring length used for these signal transmissions is equal to each logic gate method. , Can achieve the aforementioned small amount of delay with high accuracy. Furthermore, even when most output signals are obtained, the output signal from the upper side can be obtained by the logic gate means arranged on the upper side, and the output signal from the lower side can be obtained by the logic gate means arranged on the lower side. The signal delays on the signal paths can also be equal to each other, so that a higher-precision minute signal delay can be achieved. "Figure 20 shows the synchronous DRAM to which the present invention is applied (to (please read the precautions on the back before filling in this Page)-Revision ♦ This paper size is applicable to China's national standard rate (rNS) Λ4 specification (2 丨 0X297 mm) -31-A7 _______ B7 _ ^ _______ 5. Implementation of the invention (29), referred to as S DRAM for short The overall block diagram of the example. Although the SDRAM shown in the figure is not particularly limited, it is formed on a single semiconductor substrate such as single crystal silicon by a conventional semiconductor integrated circuit manufacturing technology. The SDRAM of this embodiment is provided with a memory array 200A constituting the memory bank 0 and a memory array 200B constituting the memory bank 1. Billion body 200A and 200B are equipped with dynamic memory cells arranged in a matrix, and the selection terminals of the memory cells arranged in the same row according to the illustration are combined with the word line (not shown) of each column ), The data input and output terminals of the memory cells arranged in each row are combined with complementary data lines in each row (. Not shown). The unillustrated zigzag line of the memory array 2 0 0 A is in accordance with One of the decoding results of the column address signal of the column decoder 2 0 A is driven to the selection level. A complementary data line (not shown) of the memory array 2 0 A is combined with an I / 0 line 2 2 A including a sensor amplifier and a row selection circuit. I / 0 line 2 0 2 A sensor amplifier including sensor amplifier and row selection circuit is an amplifier circuit that detects the small potential difference of each complementary data line to make it expand by reading data from memory cells . The switching circuit in this row is a switching circuit for individually selecting complementary data lines to conduct conduction to complementary I / 0 lines. The row switching circuit is selected to operate in accordance with the decoding result of the row address signal of the row decoder 2 0 3 A. On the memory array 2 0 B side, the column decoder 2 0 B is the same, including the I / 〇 line 2 0 2 B of the sensor amplifier and the row selection circuit. (Please read the precautions on the back before filling in this page )

、1T 本紙浪尺度適用中國Ε家標埤（CNS )厶衫見格（2丨〇'〆297公釐） -32- 經滴部中央標準局負工消費合作社印？木 - A7 B7 五、發明説明（30 ) 被設有行解碼器2 0 3 B »上述互補I /〇線被接續於權 限（right)緩衝器2 1 4A、B的輸出端子以及主擴大器 2 1 2A‘、B的輸入端子。上述主擴大器2 1 2A、B的 輸出訊號，被傳到閂鎖/暫存器2 1 3的輸入端子，此閂 鎖/暫存器213的輸出訊號，透過輸出緩衝器211從 外部端子被輸出。此外，被從外部端子輸入的寫入訊號， 透過輸入緩衝器2 1 0被傳達到上述權限緩衝器2 1 4. A 、B的輸入端子。上述外部端子，被作爲將由1 6位元所 構成的資料D 0〜D 1 5輸出的資料輸出入端子。 位址輸入端子所供給的位址訊號A 0〜A 9係於行位 址緩衝器2 0 5與列位址緩衝器2 0 6以位址多路轉換器 的形式被取入。被供給的位址訊號分別保持其緩衝器。列 位址緩衝器2 0 6於刷新動作模式將被從刷新計數器 2 0 8所輸出的刷新位址訊號作爲列位址訊號而取入。行 位址緩衝器2 0 5的輸出作爲行位址計數器2 0 7的預設 資料而被供給，列（行）位址計數器2 0 7因應以後述的 指令等而被指定的動作模式，將作爲上述預設資料之行位 址訊號或者是該行位址訊號依序遞增的値，朝向行解碼器 203A、203B輸出。 於該圖虛線所示的控制器2 0 9，被供給時脈訊號 CLK，時脈授權訊號CKE，晶片選擇訊號/CS，行 位址選通脈衝訊號/C AS (記號/意味著被付與此記號 的訊號是低準位授權（low enable )，列位址選通脈衝訊號 /RA S以及權限授權訊號/WE等的外部控制訊號，及 本紙張尺度適用中國國家標哗（CNS)A4規格（ 210X297公釐） {諳先閱讀背面之注意事項再填寫本頁) 訂 ο 33 A7 B7 經濟部中央標丰局貝工消费合作社印製 五、發明説明（31 ) 從位址輸入端子A 〇〜A 9之控制資料，形成基於這些訊 號的準位變化或是計時等而控制S D RAM的動作模式以 及上述電路區塊的動作之用的內部計時訊號，具備模式暫 存器10、指令解碼器20、計時產生電路30、時脈緩 衝器40以及同步時脈產生電路50。 時脈訊號C L K，透過時脈緩衝器4 0被輸入至同步 時脈產生電路，在此內部時脈被產生。使用了前述格子狀 延遲電路的時脈產生電路被利用於此同步時脈產生電路。 此內部時脈，被作爲使輸出緩衝器2 11活性化之計時訊 號i n t . CLK來使用。於其他的電路，通過上述時脈 緩衝器的時脈訊號直接被傳遞。與上述外部時脈之延遲如 果成爲問題的話形成被上述同步化的時脈訊號，也對計時 產生電路3 0供給即可。 其他的外部輸入訊號與該當時脈訊號的升起端緣同步 而有定義》晶片選擇訊號/ C S係藉由該低準位而指示指 令輸入週期的開始。晶片選擇訊號/C S爲高準位時（晶 片非選擇狀態）或是其他的輸入並不具有定義。但是，後 述的記憶體區庫的選擇狀態或是短促脈衝（burst)動作等 的內部動作對於非選擇的變化並不會導致影響。/R A S ，/CAS，/WE等各訊號對於通常的DRAM之對應 訊號而言功能不同，在定義後述的指令週期時被作爲有定 義的訊號。 時脈授權訊號C K E係指是下一個時脈訊號的有效性 的訊號，該當C K E如果是高準位的話下一個時脈訊號 (誚先閩讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標埤（C，NS ) Λ4規格（210X29*7公釐）_ 34 η 經 濟 部 中 央 標 隼 局 Ά X. 消 費 合 -作 社 印 A7 ___ B7 ____五、發明説明（32 ) C L K的升起端緣被視爲有效，在低準位時被視爲無效。 又，雖未被圖示，於讀取模式，設有對於輸出緩衝器 211之輸出授權的進行控制的外部控制訊號/0E的場 合，相關的訊號/0E也被供給至控制器2 0 9，該訊號 例如於高準位時，輸出緩衝器2 1 1呈高輸出阻抗狀態。 上述列位址訊號，藉由同步於時脈訊號CLK(內部 時脈訊號）的升起端緣的後述之列位址選通脈衝區庫主動 指令週期之A 0〜A 8的位準而被定義的。 位址訊號A 9，係於上述列位址選通脈衝區庫主動指 令週期被視爲區庫選擇訊號。亦即，A 9的輸入爲低準位 時，被選擇記憶體區庫0，爲高準位時，記憶體區庫1被 選擇。記憶體區庫的選擇控制，雖未有特別的限制，僅有 選擇記憶體區庫側的列解碼器之活性化，非選擇記憶體Μ 庫側之行開關電路的全非選擇，可以藉由選擇記憶體區庫 側的輸入緩衝器2 1 0及對輸出緩衝器21 1的接續等的 肖理而進行。 後述之預充電指令週期之位址訊號A 8，對於互補資 料線等指示預充電動作的樣態，其高準位指示預充電的對 象係雙方的記憶體區庫，其低準位指示以位址訊號A 9所 指示的一方的記憶體區庫係預充電的對象》 上述行位址訊號，係藉由同步於時脈訊號CLK(內 部時脈）的升起端緣的讀取或是寫入指令（後述的行位址 讀出指令、行位址寫入指令）週期之A 〇〜A 7之準位而 被定義的。而如此被定義的行位址，被作爲短促脈衝存取 本紙張尺度適川中國囤家標埤（C、NS ) Λ4規格（210X 297公釐） -35- {請先閱讀背面之注意事項再填寫本頁) 訂 〇 A7 B7 滴 部 中 央 標 準 局 貝 工 消 費 合 .作 社 印 製 五、發明説明（33 ) 的開始位址。 其次，說明藉由指令而被指示的S D RAM的主要動 作模式。< (1 )模式暫存器設定指令（Mo ) 係供設定上述模式暫存器3 0的指令，/C S， /RAS，/CAS，/WE=低準位而被指定當該指令 ，應設定的資料（暫存器設定資料）係透過A0〜A9而 被給予。暫存器設定資料，雖未有特別的限制，爲短促脈 衝長度、CAS等待時間（latency)、權限模式等》雖未 有特別被限制，但是設定可能的短促脈衝長度爲1、2、 4、8、全頁，設定可能的C AS等待時間爲1、2、3 ，設定可能的權限模式，爲短促脈衝權限與單脈衝權限。 上述C A S等待時間，於後述藉由行位址讀取指令而 被指示的讀取動作時從/CA S的降下直到輸出緩衝器 2 1 1的輸出動作爲止指示要費內部時脈訊號的多少週期 份者。直到讀出資料確定爲止必須要有供讀出資料之用的 內部動作時間，將其因應內部時脈訊號的使用頻率而設定 之用者。換句話說，使用頻率高的內部時脈訊號的場合， C AS等待時間設定於相對的大値，使用頻率低的內部時 脈訊號的場合設定CA S等待時間於相對的小値》如此被 設有CA S等待時間功能的場合，被省略前述第8圖或第 13圖的時脈產生電路之時脈計數器的功能。 (2 )列位址選通脈衝區庫主動指令（A c ) 這是使根據列位址選通脈衝的指示與A 9之記憶體區 (餚先閱锖背面之注意事項其填寫本筲)、 1T The standard of this paper wave is applicable to China E-house standard (CNS) shirts (2 丨 〇'〆297mm) -32- Printed by the Labor Standards Cooperative of the Central Standards Bureau of the Ministry of Didi? Wood-A7 B7 V. Description of the invention (30) Line decoder 2 0 3 B »The complementary I / 〇 line is connected to the right buffer 2 1 4A, B output terminal and main amplifier 2 1 2A ', B input terminals. The output signals of the above-mentioned main amplifiers 2 1 2A and B are transmitted to the input terminals of the latch / register 2 1 3, and the output signals of the latch / register 213 are transmitted from the external terminals through the output buffer 211. Output. In addition, the write signal input from the external terminal is transmitted to the above-mentioned authority buffer 2 1 4. A and B input terminals through the input buffer 2 10. The external terminal is used as a data input / output terminal for outputting data D 0 to D 1 5 composed of 16 bits. The address signals A 0 ~ A 9 provided by the address input terminals are taken in by the row address buffer 2 05 and the column address buffer 2 06 in the form of an address multiplexer. The supplied address signals hold their respective buffers. In the refresh operation mode, the column address buffer 206 will receive the refresh address signal output from the refresh counter 208 as the column address signal. The output of the row address buffer 2 0 5 is supplied as preset data of the row address counter 2 0 7, and the column (row) address counter 2 0 7 is specified in response to an instruction to be described later and the like. The row address signal which is the above-mentioned preset data or the row address signal in which the row address signal is sequentially increased is output toward the row decoders 203A and 203B. The controller 209 shown by the dotted line in the figure is supplied with a clock signal CLK, a clock authorization signal CKE, a chip selection signal / CS, and a row address strobe signal / C AS (mark / means being paid The signals of this mark are low enable, external address control signals such as strobe pulse signal / RA S and authority authorization signal / WE, etc., and this paper standard is applicable to China National Standard (CNS) A4 specification (210X297mm) {谙 Please read the notes on the back before filling in this page) Order ο 33 A7 B7 Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (31) Input terminal A from the address 〇 ～ The control data of A 9 forms an internal timing signal for controlling the operation mode of SD RAM and the operation of the above-mentioned circuit blocks based on the level change or timing of these signals, and has a mode register 10 and an instruction decoder 20 A timing generating circuit 30, a clock buffer 40, and a synchronous clock generating circuit 50. The clock signal C L K is input to the synchronous clock generating circuit through the clock buffer 40, and the internal clock is generated. A clock generation circuit using the aforementioned grid-shaped delay circuit is used for this synchronous clock generation circuit. This internal clock is used as a timing signal i n. CLK to activate the output buffer 2 11. In other circuits, the clock signal through the clock buffer is directly transmitted. If the delay with the external clock is a problem, a clock signal synchronized with the above is formed, and it may be supplied to the timing generating circuit 30. Other external input signals are synchronized with the rising edge of the current pulse signal. There is a definition "Chip Select Signal / CS" indicates the start of the instruction input cycle by the low level. When the chip select signal / CS is at a high level (chip is not selected) or other inputs are not defined. However, internal selections such as the selected state of the memory bank or the burst operation will not affect the non-selected changes. Signals such as / R A S, / CAS, / WE have different functions for the corresponding signals of ordinary DRAM, and are used as defined signals when defining the instruction cycle described later. The clock authorization signal CKE refers to the validity of the next clock signal. If the CKE is at a high level, the next clock signal (read the precautions on the back first and then fill out this page). Applicable to China National Standard (C, NS) Λ4 specification (210X29 * 7mm) _ 34 η Central Standards Bureau of the Ministry of Economic Affairs X. Consumption Cooperation-Printed by A7 ___ B7 ____ V. Description of Invention (32) CLK The rising edge of is considered valid, and is considered invalid at low levels. Also, although not shown, in the read mode, when an external control signal / 0E for controlling the output authorization of the output buffer 211 is provided, the related signal / 0E is also supplied to the controller 209, When the signal is at a high level, for example, the output buffer 2 1 1 is in a high output impedance state. The above-mentioned column address signal is synchronized with the level of A 0 ~ A 8 of the active instruction cycle of the column address strobe area bank described later, which is synchronized with the rising edge of the clock signal CLK (internal clock signal). Defined. The address signal A 9 is based on the above-mentioned address strobe pulse zone bank active instruction cycle and is regarded as the zone bank selection signal. That is, when the input of A 9 is a low level, the memory bank 0 is selected, and when the input of A 9 is a high level, the memory bank 1 is selected. Although there is no particular restriction on the selection and control of the memory bank, only the activation of the column decoder on the bank side of the memory bank is selected. The input buffer 2 1 0 on the bank side of the memory area and the connection to the output buffer 21 1 are selected. The address signal A 8 of the precharge instruction cycle described later, for the complementary data line and other instructions indicating the precharge action, its high level indicates that the precharge object is the memory bank of both sides, and its low level indicates the position The memory bank of the party indicated by the address signal A 9 is the object to be precharged. "The above-mentioned line address signal is read or written by synchronizing with the rising edge of the clock signal CLK (internal clock). The level of A 0 ~ A 7 of the cycle of the input instruction (the row address read instruction and the row address write instruction described later) is defined. The row address thus defined is used as a short-pulse access to this paper. Standards of Sichuan Paper Store (C, NS) Λ4 specification (210X 297 mm) -35- {Please read the precautions on the back first (Fill in this page) Order 〇A7 B7 Printed by the Central Bureau of Standards, Shellfish Consumption Co., Ltd. 5. The start address of the description of invention (33). Next, the main operation modes of the SD RAM instructed by instructions will be described. < (1) The mode register setting command (Mo) is a command for setting the above-mentioned mode register 30, / CS, / RAS, / CAS, / WE = low level and is designated as the command. The setting data (register register setting data) is given through A0 to A9. Although there are no special restrictions on the register setting data, such as short pulse length, CAS latency, and permission mode, etc. Although there are no special restrictions, the possible short pulse length is set to 1, 2, 4, 8. For all pages, set the possible CA AS waiting time to 1, 2, and 3. Set the possible permission modes, short pulse permission and single pulse permission. The above CAS wait time indicates the number of cycles of the internal clock signal from the lowering of / CA S to the output operation of the output buffer 2 1 1 when the read operation is instructed by the row address read instruction described later. Share Until the read data is determined, there must be an internal operation time for reading data, and it must be set according to the frequency of use of the internal clock signal. In other words, when using a high-frequency internal clock signal, the C AS wait time is set to a relatively large value, and when using a low-frequency internal clock signal, the CA S wait time is set to a relatively small value. When the CA S waiting time function is provided, the function of the clock counter of the clock generating circuit of FIG. 8 or FIG. 13 is omitted. (2) Active address instruction of column address strobe area library (A c) This is to make the memory address of A 9 according to the instruction of column address strobe and the memory area (please read the precautions on the back of this page and fill in this note)

本紙張尺度適用中國國家標埤（CNS ) Λ4規格（.210X297公釐） -36- A7 B7 經 濟 部 中 央 標 準 局 工 消 合 -作 社 印 製 五、發明説明（34 ) 庫的選擇成爲有效的指令，藉由使/ 準位，/CAS，/WE=高準位而 至A 〇〜A 8的位址作爲列位址訊號 號被作爲記憶體區庫的選擇訊號而被 述般的同步於內部時脈訊號的升起端 指定當該指令的話，被選擇藉其被指 線，分別被導通於被接續於該當字線 對應的互補資料線。 (3 )行位址讀取指令（R e ) 此指令，係供開始短促脈衝讀取 同時也是給予行位址選通脈衝的指示 、/CAS =低準位，/RAS、/ 示，此時被供給至A0〜A 7的行位 而被取入。藉此而被取入的行位址訊 始位址而被供給至行位址計數器2 0 的短促脈衝讀取動作，於其之前被以 主動指令週期進行記憶體區庫與其之 擇字線的記憶體細胞，同步於內部時 計數器2 0 7所被輸出的位址訊號依 出。連續被讀出的資料數作爲藉由上 定的個數。此外從輸出緩衝器2 1 1 等待上述C A S等待時間所規定的內 而進行。 (4)行位址權限指令（Wr) CS，/RA.S =低 被指示，此時被供給 ，被供給至A 9的訊 取入。取入動作如上 緣而被進行。例如被 定的記億體區庫之字 的記億體細胞所分別 動作所必 之指令， W E =高 址被作爲 號係作爲 7。於藉 列位址選 字線的選 脈訊號依 序被選擇 述短促脈 讀出資料 部時脈訊 要的指令， 藉由/ C S 準位而被指 行位址訊號 短促脈衝開 此而被指示 通脈衝區庫 擇，該當選 照從行位址 而連續地讀 衝長度所堉 的開始，係 號的週期數 {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度迠用中國國家標埤（CNS ) Λ4規格（210 X 2们公釐） -37- 五、發明説明（35 ) 權限動作的樣態在模式暫存器10被設定於短促脈衝 權限時，爲了開始該當短促脈衝權限動作之用的必要的指 令’作爲權限動作的樣態之單脈衝權限被設定於模式暫存 器1 0時作爲開始該當單獨權限動作之用的必要指令。進 而’該當指令，給與單次寫入以及短促脈衝寫入之行位址 選通脈衝之指示》該當指令藉由/CS、/CAS、 /WE=低準位，/RAS=高準位而被指示，此時被供 給至A 〇〜A 7的位址作爲行位址訊號而被取入》藉此而 被取入的行位址訊號於短促脈衝線作爲短促脈衝開始位址 而被供給至行位址計數器2 0 7。藉此而被指示的短促脈 衝線動作的手續也與短促脈衝讀取動作同樣地進行。但是 寫入動作沒有C A S等待時間，寫入資料的取入是由該當 行位址權限指+週期開始的。 (5)預充電指令（Pr) 這是被作爲對藉由A8、A9而被選擇的記億體區庫 的動作開始指令，藉由/CS、/RAS、/WE=低準 位，/CAS=高準位而被指示。 (6 )自動刷新指令 此指令係供開始自動刷新之用的必要指令，藉由 /CS、/RAS、/CAS=低準位，/WE、CKE =高準位而被指示》 (7)短促脈衝停止在全頁之指令 係對於全頁之短促脈衝動作使其對於所有的記憶體區 庫停止之用的必要指令，在全頁以外的短促脈衝動作則被 {诗先閱讀背面之注意事項再填寫本頁) 訂 ·- 本紙張尺度適用中國囤家標缚（CNS ) Λ4規格（2丨0X297公釐） -38 - A7 B7 __ 五、發明说明（36 ) 忽視。此指令，係藉由/C S、/WE=低準位’ /RAS、/CAS=高準位而被指示。 (8)無操作指令（Nop) 此爲指示不進行實質的動作的指令，藉由/C s =低 準位，/RAS、/CAS、/WE的高準位而被指示。 於S DRAM，在一方的記億體區庫進行短促脈衝動 作時，在其途中指定其他的記億體區庫，被供給列位址選 通脈衝區庫主動指令的話，在該實行中的一方的記億體區 庫不會對動作產生任何影響，該其他的記億體區庫可以進 行列位址系的動作。例如，SDRAM具有從外部供給的 資料、位址以及保持控制訊號於內部的手段，其保持內容 ，特別是位址以及控制訊號雖未有特別的限制，但是每個 記憶體區庫都被保持著。或者是，藉由列位址選通脈衝區 庫主動指令而被選擇的記億體區塊之1條份的字線的資料 在行系動作之前預先讀出的動作之用而使被保持於閂鎖/ 暫存器2 1 3。 經滴部中央標準局貝工消費合作社印^ (請先閲讀背面之注意事項再填寫本頁) 也就是說，例如由1 6位元鎖構成的資料輸出入端子 只要資料DO〜D15不衝突，在處理未結束的指令實行 中，對於與該實行中的指令所處理的對象相異的記億體區 庫產生預充電指令、列位址選通脈衝區庫主動指令而可以 使預先開始內部動作。 SDRAM爲使同步於時脈訊號CLK (內部時脈訊 號）將資料、位址、控制訊號輸出入，而可以使與 DRAM同樣的大容量記億體以匹敵於S RAM的高速動 本紙浪尺度適州中國國家標率（CNS)M規格（210X297公釐） -39 - A7 B7 經漪部中央標準局员工消费合作社印製 五、發明説明（37 ) 作，此外藉由對被選擇的1條字線將幾個資料是否存取藉 由短促脈衝長度而指定，以使以內藏行位址計數器2 0 7 依序切換行系的選擇狀態之所謂將、複數個資料連續讀取或 是寫入的方式處理9 如此實施例所示的搭載時脈產生電路的場合’從記憶 體控制器發出讀取指令開始直到資料傳回爲止的時間於所 有的SDRAM都可以使其成爲相同，藉此可以使上述時 脈訊號C L K的頻率可以設爲例如2 0 Ο ΜΗ z般的高頻 。SDRAM也可以採用使時脈訊號int CLK的升 起與降下同步而將資料輸出的方式亦可。 第2 1圖顯示適用相關於本發明的格子狀震盪電路的 場合的一實施例的電路圖。除了被排列爲格子狀的延遲電 路，電路構成係與前述文獻所發表的電路有部份類似。但 是，爲了獲得具有相互相等的微小量延遲而使相位相異的 震盪訊號，作爲被排列爲上述格子狀的延遲電路之邏輯閘 手段，係如前述第1圖、第2圖及第4圖所示般的在2個 輸入間設有耦合手段者。 將作爲如上述般的各延遲電路的2個CMO S反相器 電路的輸出共通化，於2個輸入附加與前述同樣的嘔核電 容的場合的動作波形圖顯示於第2 2圖。此動作波形圖， 與前述相同係藉由電腦模凝而描繪的，可知具有相等的微 小量延遲量進行震盪動作的樣子。於此實施例的格子狀震 盪電路，藉由使其電路的至少一部份也採用如前述第1 9 圖的實施例般的配置，可以使震盪訊號f互的微小量延遲 (請先閱讀背面之注意事項再填寫本頁) 訂This paper size applies to China National Standards (CNS) Λ4 specifications (.210X297 mm) -36- A7 B7 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs-Printed by the Publishing Company 5. Inventory (34) The selection of the library becomes effective The command, by setting / level, / CAS, / WE = high level, to the address of A 0 ~ A 8 as the column address signal is used as the selection signal of the memory bank and described as synchronized with The rising end of the internal clock signal specifies that when this instruction is selected, it is selected to use its finger line to be respectively connected to the complementary data line connected to the corresponding word line. (3) Row address read instruction (R e) This instruction is used to start the short pulse read and also gives the row address strobe pulse, / CAS = low level, / RAS, / indicates, at this time It is supplied to the rows of A0 to A7 and taken in. In this way, the short pulse read operation of the fetched row address signal starting address and supplied to the row address counter 20 is performed by the memory bank and its selected word line in an active instruction cycle before it. The memory cells are synchronized to the internal address signal output by the counter 2 07. The number of consecutively read data is taken as the number specified above. In addition, it waits from the output buffer 2 1 1 within the time specified by the above C A S waiting time. (4) Row address authority command (Wr) CS, /RA.S = Low is indicated, it is supplied at this time, and it is supplied to the A 9 signal. The fetching operation is performed as above. For example, the number of billions of somatic cells in the set of the number of billions of somatic regions is determined to be necessary for each action. W E = high address is used as the number system and 7. The pulse selection signal of the word line selected by the row address is sequentially selected. The short pulse reads out the data required by the clock. The / CS level indicates that the short address pulse is turned on and instructed. Pass through the pulse area library selection, the selected photos should be read from the row address and continuously read the punch length, the cycle number of the serial number (please read the precautions on the back before filling this page) This paper standard uses Chinese national standard埤 (CNS) Λ4 specification (210 X 2 mm) -37- V. Description of the invention (35) When the mode register 10 is set to short pulse authority, in order to start the short pulse authority action The necessary command for the use of the single-pulse authority as the mode of the authority action is set in the mode register 10 as a necessary instruction for starting the individual authority action. Furthermore, 'Dang Dang instruction gives instructions for row address strobes for single writing and short pulse writing. "Dang Dang instruction uses / CS, / CAS, / WE = low level and / RAS = high level. It is instructed that the address supplied to A 0 ~ A 7 at this time is taken as the row address signal. "The row address signal thus taken in is supplied as the short pulse start address on the short pulse line. To the row address counter 2 0 7. The procedure of the short pulse line operation thus instructed is performed in the same manner as the short pulse read operation. However, there is no C A S waiting time for the writing operation. The fetching of the written data is started by the corresponding address authority indicator + cycle. (5) Pre-charge command (Pr) This is an action start command for the billion-body bank selected by A8 and A9. / CS, / RAS, / WE = low level, / CAS = High level is indicated. (6) Automatic refresh instruction This instruction is a necessary instruction for starting the automatic refresh. It is instructed by / CS, / RAS, / CAS = low level, / WE, CKE = high level. (7) Short The instruction to stop the pulse on the full page is a necessary instruction for the short pulse action of the full page to stop all the memory banks. The short pulse action outside the full page is subject to {Notes on the back of the poem before reading (Fill in this page) Order ·-This paper size is applicable to the Chinese storehouse standard (CNS) Λ4 specification (2 丨 0X297mm) -38-A7 B7 __ 5. Description of the invention (36) Ignored. This instruction is indicated by / C S, / WE = low level '/ RAS, / CAS = high level. (8) No operation instruction (Nop) This is an instruction that indicates that no substantial action is performed. It is indicated by / C s = low level and / RAS, / CAS, / WE high levels. In S DRAM, when a short pulse operation is performed on one bank of the bank, the other bank of the bank is designated on the way, and the column address strobe pulse bank is given an active instruction. The bank of the billion-body region will not have any effect on the movement. The other bank of the hundred-million region can perform the actions of the column address system. For example, SDRAM has externally supplied data, addresses, and means for maintaining control signals internally. Its contents, especially addresses and control signals, are not particularly limited, but each memory bank is maintained. . Or, the word line data of one copy of the memory block selected by the active instruction of the column address strobe area library is retained in the row read operation before the row operation. Latch / register 2 1 3. Printed by the Central Bureau of Standards, Shellfish Consumer Cooperatives ^ (Please read the precautions on the back before filling out this page) In other words, for example, the data input and output terminals composed of 16-bit locks as long as the data DO ~ D15 do not conflict, During the execution of the unfinished instruction execution, a precharge instruction and a column address strobe pulse area library active instruction are generated for a billion bank body library that is different from the object processed by the instruction being executed, so that internal operations can be started in advance. . SDRAM is used to output data, address, and control signals in synchronization with the clock signal CLK (internal clock signal), so that the same large-capacity memory as DRAM can be used to match the speed of S RAM. State China National Standards (CNS) M Specification (210X297 mm) -39-A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The Invention Description (37) is made, and by selecting a word Whether or not several data are accessed is specified by the short pulse length, so that the so-called read or multiple data is continuously read or written with the built-in row address counter 2 0 7 in order to switch the selection state of the row system. Method 9 In the case where the clock generation circuit is mounted as shown in this embodiment, the time from when the memory controller issues a read command to when the data is returned can be made the same for all SDRAMs. The frequency of the clock signal CLK can be set to a high frequency such as 200 MHz. SDRAM can also output data by synchronizing the rise and fall of the clock signal int CLK. Fig. 21 is a circuit diagram showing an embodiment in a case where the grid-shaped oscillator circuit according to the present invention is applied. Except for the delay circuits arranged in a grid, the circuit configuration is similar to that of the circuits published in the aforementioned literature. However, in order to obtain oscillating signals having mutually different minute amounts of delay and different phases, as a logic gate means of the delay circuits arranged in the above-mentioned grid shape, it is as described in Figs. A coupling means is provided between the two inputs as shown. The output waveforms of the two CMO S inverter circuits, which are the delay circuits as described above, are commoned, and the operation waveform diagram when the same nuclear vomiting capacitor is added to the two inputs is shown in FIG. 22. This operation waveform diagram is the same as that described above by computer modeling, and it can be seen that the oscillatory operation is performed with an equivalent small amount of delay. In the grid-shaped oscillator circuit of this embodiment, at least a part of the circuit also adopts the configuration as in the embodiment of FIG. 19 described above, so that the mutual oscillation signals f can be delayed by a small amount (please read the back first) (Please fill in this page again)

IV 本紙張尺度適用中國國家標4M CNS ) Λ4規格（210X297公釐） -40- A7 B7 五、發明説明（38 ) 相等，而且其輸出的取出變得更容易。 <-- 經濟部中央標隼局兵工消贫合作社印製 (請先閲讀背面之注意事項再填寫本頁) 上述實施例所可以得到的效.果歸納如下述。也就是說 (10設置使被輸入於第1與第2輸入端子間的2個 輸入訊號耦合的阻抗手段，使用複數個形成使對於輸入訊 號反轉的輸出訊號的邏輯閘手段，可以獲得：於第1訊號 傳達方向與第2訊號傳達方向配置爲格子狀，於第1訊號 傳達方向呈第1個以外的第K個，於第2訊號傳達方向被 配置於第L段的邏輯閘電路手段K L的上述第1輸入端子 上於第1訊號傳達方向呈相同的第K個，於第2訊號傳達 方向呈第L一1段的邏輯閘電路的輸出訊號或是在第1段 邏輯閘電路被供給輸入時脈訊號，於上述邏輯閘電路手段 K L的第2輸入端子在第1訊號傳達方向呈前1個之第K - 1個，在第2傳達方向呈相同的第L段的被供給至i輯 閘電路之第1輸入端子的輸入訊號被供給，而且，於第1 訊號傳達方向呈第1個，於第2訊號傳達方向呈第L段的 邏輯閘電路的第2輸入端子，於第1訊號傳達方向呈最終 段，於上述第2訊號傳達方向較其更呈前段的邏輯閘電路 ，被供給與被供給於該處之第1輸入端子的輸入訊號成爲 同相關係的被供給至第1輸入端子的輸入訊號，於上述第 2訊號傳達方向呈第1段，於第1訊號傳達方向呈第1個 的邏輯閘電路之第1與第2輸入端子，通過構成緩衝器電 路的輸入電路被供給時脈訊號，於第1訊號傳達方向被供 給至從第2個直到最後一個爲止的各邏輯閘電路的第1輸 入端子的上述輸入時脈訊號，係藉由構成上述緩衝器電路 本紙張尺度適用中國S家標缚（C’NS ) Λ4規格（210X297公釐） -41 經消部中央標準局吳工消合作社印^ A7 B7 五、發明説明（39 ) 的輸入電路於上述第1訊號傳達方向依序被延遲，藉此於 上述第2訊號傳達方向至少最後一段或是其最後一段的前 一段，可以獲得來自被配列於第1訊號傳達方向的複數邏 輯閘手段的輸出端子的具有微小量延遲的輸出訊號之效果 〇 (2 )藉由使用電容元件作爲上述阻抗手段，可以獲 得可以比較容易地進行良好的訊號結合的效果。 (3 )藉由使用電阻元件作爲上述阻抗手段，可以獲 得可以比較容易地進行良好的訊號結合的效果》 (4 )藉由使用NAND閘電路作爲上述邏輯閘手段 ，可以獲得可以構成比較簡單的格子狀延遲電路的效果。 (5 )藉由使用NOR閘電路作爲上述邏輯閘手段， 可以獲得可以構成比較簡單的格子狀延遲電路的效果。 (6 )藉由作爲上述邏輯閘手段將2個反相器電路的 輸出端子共通接續者，可以獲得可以構成簡單的格子狀延 遲電路的效果。 (7 )於上述第1訊號傳達方向呈最終段，於第2訊 號傳達方項第1段邏輯閘電路的第1輸入端子的輸入訊號 ，係被供給至於第1訊號傳達方向係第1個，於第2訊號 傳達方向係第3段之邏輯閘電路的第2輸入端子者，在於 第1訊號傳達方向係第1個而於第2訊號傳達方向的第2 段邏輯閘電路的第1與第2輸入端子，被共通供給於第1 及第2訊號傳達方向爲第1個邏輯閘電路的輸出訊號，藉 此可以獲得可於第2訊號傳達方向將最短的時間僅延遲上 (請先閲讀背面之注意事項再填寫本真) 訂 本紙張尺度適用中國围家標準（CNS > Λ4規格（2]〇X297公釐） •42· 經濟部中央標準局貝工消费合作社印製 A7 _____ B7 五、發明説明（40 ) 述第1傳達方向的等分段數份而實現效率佳的微小量延遲 的效果。 (80將上述格子狀延遲電路載於半導體基板上，被 設於上述第1訊號傳達方向的第N個邏輯閘手段，與第N + 2段之邏輯閘手段，係沿著相同的方向配置，第N+ 1 個邏輯閘手段，係橫跨第N個與後半部與第N + 2個的前 半部以使鄰接的方式配置之，藉此可使邏輯閘手段相互接 續的配線長度成爲相等的長度，可以高精度實現微小量訊 號延遲，同時其輸出訊號也變得容易取出的效果。 (9 )藉由構成被設有將被輸入第1與第2輸入端子 之間的2個輸入訊號耦合的阻抗手段，設有複數個具備形 成對於被供給至上述輸入端子的輸入訊號反轉的輸出訊號 之邏輯閘手段的格子狀震盪電路，可以獲得可得相互相等 的微小量延遲偏移的震盪訊號的效果。 (1 0 )將上述格子狀震盪電路於半導體基板上，被 設於上述第1訊號傳達方向的第N個邏輯閘手段，與第N + 2段之邏輯閘手段，係沿著相同的方向配置，第N+ 1 個邏輯閘手段，係橫跨第N個與後半部與第N + 2個的前 半部以使鄰接的方式配置之，藉此可使邏輯閘手段相互接 續的配線長度成爲相等的長度，可以高精度實現微小量訊 號延遲，同時其輸出訊號也變得容易取出的效果。 (1 1 )上述格子狀延遲電路的輸出訊號的1個以多 路轉換器選擇，可以獲得被輸入上述格子狀延遲電路的時 脈訊號與通過上述多路轉換器而被輸出的時脈訊號之相位 (姊先閱讀背面之注意事項再填寫本頁) 訂IV This paper size applies to Chinese national standard 4M CNS) Λ4 specification (210X297 mm) -40- A7 B7 5. The invention description (38) is equal, and its output becomes easier to take out. <-Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Poverty Alleviation Cooperative (please read the precautions on the back before filling out this page). The effects obtained by the above examples can be summarized as follows. That is, (10 sets impedance means for coupling two input signals input between the first and second input terminals, and using a plurality of logic gate means for forming an output signal for inverting the input signal, it is possible to obtain: The first signal transmission direction and the second signal transmission direction are arranged in a grid pattern. The first signal transmission direction is the Kth other than the first, and the second signal transmission direction is disposed in the L-th gate logic circuit means KL. The above-mentioned first input terminal is the same K-th in the first signal transmission direction, and the output signal of the logic gate circuit of the L-1 stage in the second signal transmission direction is supplied or the logic gate circuit of the first stage is supplied. The clock signal is input, and the second input terminal of the above-mentioned logic gate circuit means KL is the first K-1 in the first signal transmission direction, and the same L-th stage in the second transmission direction is supplied to i. The input signal of the first input terminal of the gate circuit is supplied, and the second input terminal of the logic gate circuit which is the first signal transmission direction in the first signal transmission direction and the L stage in the second signal transmission direction is provided in the first signal transmission direction. The direction of signal transmission is final. In the above-mentioned second signal transmission direction, the logic gate circuit, which is in the front stage, is supplied with the input signal supplied to the first input terminal in the same phase relationship with the input signal supplied to the first input terminal there. The first signal transmission direction is the first paragraph, and the first and second input terminals of the logic gate circuit which is the first in the first signal transmission direction are supplied with the clock signal through the input circuit constituting the snubber circuit. The signal transmission direction is supplied to the above-mentioned input clock signal of the first input terminal of each logic gate circuit from the second to the last, which is constituted by the above-mentioned buffer circuit. 'NS) Λ4 specification (210X297 mm) -41 Printed by Wu Gongxiao Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ A7 B7 V. The input circuit of the invention description (39) was delayed in order to transmit the first signal in the above order, thereby At least the last paragraph of the second signal transmission direction or the previous paragraph of the last paragraph, the micro-gates from the output terminals of the plurality of logic gate means arranged in the first signal transmission direction can be obtained. The effect of the output signal with a small amount of delay. (2) By using a capacitive element as the above-mentioned impedance means, it is possible to obtain a good signal combining effect relatively easily. (3) By using a resistive element as the above-mentioned impedance means, it is possible to Obtaining the effect that a good signal can be easily combined "(4) By using a NAND gate circuit as the above-mentioned logic gate means, the effect that a relatively simple grid-like delay circuit can be obtained. (5) By using a NOR gate As the logic gate means described above, the circuit can obtain the effect that a relatively simple grid-like delay circuit can be constructed. (6) By connecting the output terminals of the two inverter circuits in common as the logic gate means described above, a simple configuration can be obtained Effect of a grid-like delay circuit. (7) The input signal of the first input terminal of the first signal terminal of the first signal transmission direction in the above-mentioned first signal transmission direction is supplied to the first signal transmission direction, which is the first, The second input terminal of the logic gate circuit of the third stage in the second signal transmission direction is the first and the second stages of the logic gate circuit of the second stage in the first signal transmission direction and the second stage of the second signal transmission direction. 2 input terminals are commonly supplied to the output signal of the first logic gate circuit in the first and second signal transmission directions, so that the shortest time can be delayed only in the second signal transmission direction (please read the back first) Please fill in the truth for the matters needing attention.) The paper size of the book is applicable to the Chinese standard (CNS > Λ4 size (2) × 297mm). • 42 · Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Description of the invention (40) The effect of a small amount of delay with high efficiency is achieved by dividing the first transmission direction into several equal portions. (80) The lattice delay circuit is mounted on a semiconductor substrate and is provided in the first signal transmission direction. Nth logic gate Segment, the logic gate means of the N + 2 segment, are arranged in the same direction, the N + 1 logic gate means, span the N and the second half and the first half of the N + 2 so as to be adjacent It is configured in such a way that the wiring lengths of the logic gate means connected to each other can be equal to each other, and a small amount of signal delay can be achieved with high accuracy, and the output signal can also be easily taken out. (9) The composition is Impedance means for coupling two input signals input between the first and second input terminals are provided, and a plurality of logic gate means are provided with a logic gate means for forming an output signal inverting the input signal supplied to the input terminal. The grid-shaped oscillating circuit can obtain the effect of obtaining oscillating signals with a slight delay offset equal to each other. (1 0) The grid-shaped oscillating circuit is arranged on a semiconductor substrate and is provided at the Nth position in the first signal transmission direction. The logic gate means is arranged in the same direction as the logic gate means of the N + 2 stage. The N + 1 logic gate means is across the Nth and the second half and the first half of the N + 2. To make neighbors It is configured in such a way that the wiring lengths of the logic gate means connected to each other can be the same length, and a small amount of signal delay can be achieved with high accuracy, and the output signal can also be easily taken out. (1 1) The above grid shape One of the output signals of the delay circuit is selected by a multiplexer, and the phase of the clock signal input to the grid-shaped delay circuit and the clock signal output through the multiplexer can be obtained (see the (Please fill in this page again)

本紙張尺度適用中國國家標埤（CNS ) Λ4規格（210X297公釐） -43- 經濟部中央標皐局貝工消费合作社印？衣 A7 —____B7 ____ 五、發明説明（41 ) 比較器來比較，藉由接受其相位比較輸出訊號的控制電路 ，形成上述多路轉換器的控制訊號通過上述多路轉換器而 被輸出的時脈訊號被與上述時脈訊號以高精度同步化的效 果。 (1 2 )作爲上述控制電路使用上下計數器電路，可 以獲得對應於上述相位比較器的輸出而進行+1或是-1 的計數動作，將該計數結果解碼形成控制訊號而藉由控制 多路轉換器可以簡單地實現上述高精度的D L L電路的效 果。 ' (1 3 )具備於複數字線與複數位元線的交點記憶體 細胞被矩陣配置而成的記憶體陣列，及選擇相關的記憶體 陣列的記億體細胞的位址選擇電路*及使發出對應於被從 外部端子供給的時脈訊號的內部時脈訊號的時脈產生電路 ，及與上述內部時脈訊號同步將從上述記憶體細胞讀出的 訊號輸出之輸出入電路等而成的半導體記憶裝置，藉由使 用上述格子狀延遲電路作爲上述同步時脈產生電路，可以 獲得可以高精度進行資料輸出動作的效果》 (1 4 )藉由利用計數器電路於上述控制電路，可以 獲得對於被輸入的時脈訊號於被指定的時脈數之計數後選 擇上述格子狀延遲電路的複數之輸出訊號之中的一個的效 果。 (1 5 )具備複數個使用上述格子狀延遲電路形成內 部時脈訊號，使輸出上述記憶體細胞的讀出訊號的半導體 記億裝置，對於相關的複數半導體記憶裝置設有1個記憶 (讀先閱讀背面之注意事項再填寫本貫)This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) -43- Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs?衣 A7 —____ B7 ____ V. Description of the invention (41) The comparator compares, and the control circuit that accepts its phase comparison output signal forms the clock of the control signal of the multiplexer output through the multiplexer. The effect that the signal is synchronized with the above-mentioned clock signal with high accuracy. (1 2) As the control circuit, an up / down counter circuit is used, which can obtain a counting operation of +1 or -1 corresponding to the output of the phase comparator, decode the counting result to form a control signal, and control multiplexing. The device can simply achieve the effect of the above-mentioned high-precision DLL circuit. '(1 3) A memory array comprising memory cells arranged at the intersection of a complex digital line and a complex bit line, and an address selection circuit of a memory cell that selects the relevant memory array * and makes A clock generation circuit that emits an internal clock signal corresponding to a clock signal supplied from an external terminal, and an input / output circuit that outputs a signal output from the memory cell in synchronization with the internal clock signal In a semiconductor memory device, by using the above-mentioned grid-like delay circuit as the above-mentioned synchronous clock generating circuit, the effect of high-precision data output operation can be obtained. (1 4) By using a counter circuit in the above control circuit, it is possible to obtain The input clock signal has the effect of selecting one of the complex output signals of the grid-shaped delay circuit after the designated number of clocks is counted. (15) A plurality of semiconductor memory devices including an internal clock signal formed by using the above-mentioned grid-shaped delay circuit and outputting a readout signal of the memory cell, and one memory (reading first) (Read the notes on the back and fill out this book)

本紙浪尺度適川中國囤家標嗥（CNS ) Λ4規格（210X 297公釐〉 -44 - 經 濟 部 中 央 標 4*- 扁 貝 工 消 合 .作 社 印 製 A7 B7 _ 五、發明説明（42 ) 體控制電路，從上述記憶體控制電路對於上述各半導體記 憶裝置供給讀/寫的控制訊號與上述時脈訊號，同時產生 使與各半導體記憶裝置的訊號傳達延遲時間相互變成相等 的控制訊號，藉由形成被設於上述各半導體記憶裝置的格 子狀延遲電路的控制訊號，可以獲得可高速地讀出資料的 半導體記億體系統。 (1 6 )具備複數個使用上述格子狀延遲電路形成內 部時脈訊號，使輸出上述記憶體細胞的讀出訊號的記憶體 模組，對於相關的複數記憶體模組設有1個記憶體控制電 路，從上述記憶體控制電路對於上述各半導體記憶裝置供 給讀/寫的控制訊號與上述時脈訊號，同時產生使與各半 導體記憶裝置的訊號傳達延遲時間相互變成相等的控制訊 號，藉由形成被設於上述各半導體記憶裝置的格子狀延遲 電路的控制訊號，可以獲得可高速地讀出資料的半導體記 憶體系統。 本發明並非以前述實施例爲限，在不逸脫其要旨的範 圍內當然可以進行種種的變更〃例如，R A Μ的具體構成 ，除了如前述的同步DRAM之外，還可以適用泛用 DRAM，或是依據隨機存取記憶體匯流排規格的具有輸 出入功能的動態型RAM，靜態型RAM等，可以廣泛適 用於依照從如上述般的外部端子被供給的時脈訊號使其進 行資料·的輸出入動作的方式之半導體記憶體及使用該記憶 體的記憶體系統。此外，可以廣泛適用於形成同步於被從 外部供給的時脈訊號的內部時脈訊號，將其相位僅使對於 本紙張尺度適/fl中國國家標率（（，NS ) Λ4規格（210 X 297公釐） (请先閲讀背面之注意Ϋ-項再填??本頁)The scale of this paper is suitable for the Chinese storehouse standard (CNS) in Sichuan. Λ4 size (210X 297 mm) -44-Central standard of the Ministry of Economic Affairs. ) A body control circuit that supplies read / write control signals and the clock signals to the semiconductor memory devices from the memory control circuit, and simultaneously generates control signals that make the delay times of signal transmission with the semiconductor memory devices equal to each other, By forming a control signal of a grid-like delay circuit provided in each of the semiconductor memory devices, a semiconductor memory system capable of reading data at a high speed can be obtained. (1 6) A plurality of the above-mentioned grid-like delay circuits are used to form an internal structure. The clock signal is a memory module that outputs the read signal of the memory cell. A memory control circuit is provided for the relevant plural memory modules, and the semiconductor control device is supplied from the memory control circuit. The read / write control signal and the above-mentioned clock signal simultaneously generate a delay time for signal transmission to each semiconductor memory device The control signals which become equal to each other can be obtained by forming the control signals of the grid-like delay circuits provided in the above-mentioned semiconductor memory devices, thereby obtaining a semiconductor memory system capable of reading data at high speed. The present invention is not limited to the foregoing embodiments. Of course, various changes can be made within the scope that does not escape its gist. For example, the specific structure of the RA M, in addition to the aforementioned synchronous DRAM, can also be used for general-purpose DRAM, or based on the random access memory confluence. Row-type dynamic RAM and static RAM with input and output functions can be widely applied to semiconductor memory in accordance with the clock signal supplied from external terminals as described above to perform data input / output operations. And a memory system using the memory. In addition, it can be widely used to form an internal clock signal synchronized with a clock signal supplied from the outside, and its phase is only adapted to the paper standard / fl Chinese national standard ( (, NS) Λ4 specification (210 X 297 mm) (Please read the note on the back Ϋ-item before filling this page ??)

-45- 經 部 中 央 標 準 局 負 工 消 合 •作 社 印 % Α7 _ Β7 五、發明説明（43 ) 上述外部時脈訊號延遲微小量而已的有必要的各種半導體 積體電路裝置。 格子狀延遲電路或是格子狀震盪電路的配置，於半導 體基板上將電路構成爲格子狀態亦可。格子狀延遲電路， 在內部產生的計時訊號使其每次延遲微小量而已而輸出的 場合也可以同樣地利用。格子狀震盪電路，可以廣泛地利 用於形成複數種類地相位相異的震盪訊號的半導體積體電 路裝置。 於第2 3圖顯示相關於本發明的時脈同步電路的一實 施例的方塊圖。該圖得各電路方塊，與未圖示的其他電路 同樣藉由習知的半導體製造技術，被形成於如單結晶矽之 類的1個半導體基板上》 在此實施例，爲了確保可以同步的頻率帶域與電路規 模的縮小以及縮小同步誤差，使用2種類的_延遲電路。1 種延遲電路，爲了確保可以同步的頻率帶域，係以使各段 的時間成爲3 0 0微微秒以上的大的延遲電路（Coarse Delay ) CD 1〜CD3也就是時間分解能的精度較低的延 遲電路而被構成。這些延遲電路CD 1〜CD 3，係以相 互相同的電路構成的CMO S反相器電路的縱列接續而被 構成。 另一個延遲電路，係相關於本發明的發明人的開發知 各段的時間成爲2 0〜1 0 0微微秒的較小的格子狀延遲 電路SQUAD1與SQUAD2，也就是說，使用的是 時間分解能的精度較高的延遲電路。藉由組合上述時間分 (請先閱讀背面之注意事項再填寫本頁) -訂 Θ 本紙張尺度迠州中國國家標丰（CNS ) Λ4規格（210 X 297公釐） -46- 經漪部中央標隼局負工消費合作社印^ A7 B7 五、發明说明（44 ) 解能較大者與較小者之2種類，可以謀求確保上述可同步 的頻率帶域及電路規模的縮小以及同步誤差的縮小》總之 ，採用藉由上述時間分解.能較低的延遲電路CD 1〜 CD 3，形成大略的同步訊號，將被包含於其內的同步誤 差份藉由上述時間分解能較小的格子狀延遲電路 SQUAD1、SQUAD2來補正的構成》 在此實施例，爲了形成以高精度被上述同步化的時脈 訊號，作爲上述時間分解能低的延遲電路使用C D 1〜 CD3三個。一個延遲電路CD1，係使被輸入的時脈脈 衝C D M i η延遲供給至端緣檢測電路（Edge Detector) E D 1。此端緣檢測電路E D 1.，係比較上述延遲電路 CD 1的各段的延遲訊號，與延遲1個時脈而被輸入的時 脈脈衝的端緣，如果兩個端緣在時間上一致的話，在當時 檢測出延遲電路CD 1之端緣位置（亦即通過的延遲要素 電路的段數N )。 藉由在上述端緣檢測電路E D 1所被形成的檢測訊號 CNTLA控制多路轉換器MPX1與MPX2，從與上 述延遲電路CD 1相同構成的延遲電路CD 2與CD 3分 別輸出輸出脈衝CDMo u t與CD 〇 u t。裣從上述多 路轉換器MPX1輸出的輸出脈衝CDMout ，係被供 給至格子狀延遲電路S QUAD 1將其延遲訊號供給至端 緣檢測電路E D 2。此端緣檢測電路E D 2，比較上述格 子狀延遲電路S QUAD 1的各段的延遲訊號，與再延遲 1個時脈而被輸入的時脈脈衝的端緣，兩個端緣在時間上 本紙張尺度適用中國國家標啤< CNS ) Λ4規格（2丨0X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 -47- 經 濟 部 中 央 標 準 局 Ά 工 消 合 社 印 A 7 B7 五、發明说明（45 ) —致的話，在該時點檢測出格子狀延遲電路S QUAD 1 之端緣的位置（亦即通過了的延遲要素電路的段數）。 藉由在上述端緣檢測電路ED2被形成的檢測訊號 CNTLB控制多路轉換器MPX3，從與上述格子狀延 遲電路S QUAD 1相同構成的延遲電路S QUAD 2輸 出輸出脈衝FDout。此FDout ，作爲通過輸出驅 動器DRV2而被同步化的內部時脈訊號CLKo u t被 供給至未圖示的其他電路。 上述內部時脈訊號CLKout ，係與從外部端子供 給的輸入時脈訊號C LK i η被同步化者，相關的輸入時 脈訊號CLK i η，通過作爲輸入緩衝器的接收器 RCV1，以及驅動器DRV 1被供給至上述同步化電路 的共同節點COMMON呈上述輸入的時脈脈衝。總之，上述 驅動器D R V 1的輸出被接續的共通節點COMMON所取入 的輸入脈衝，不是直接被供給至上述延遲電路C D 1的輸 入，而是通過僞延遲電路DMD L 1與DMD L 2使其延 遲再被作爲上述延遲電路CD 1的輸入訊號CDMi η » 上述僞延遲電路DMD L 2，係以可以發揮時間分解能較 高的格子狀延遲電路SQUAD 1、SQUAD 2的所要 的性能的方式而進行時間調整的》僞延遲電路DMD L 1 ，係形成對應於上述接受器RCV 1與驅動器DRV 1與 多路轉換器MPX3的延遲時間者。 於第2 4圖，顯示供說明上述時脈同步電路的動作之 用的計時圖。從外部端子被輸入的時脈訊號C L K i η， 本紙張尺度適川中國國家標隼（CNS ) Λ4規格（210X297公釐） (錆先閱婧背面之注意事項再填艿本页) -訂 -48- 經满部中决標準局負工消费合-#社印？本 A7 B7 五、發明説明（46 ) 通過上述接受器RCV1與驅動器DRV 1僅使其延遲延 遲時間d 1變化共同節點COMMON的時脈脈衝。此共同節 點COMMON的輸入脈衝，藉由上述僞延遲電路DMD L 1 僅延遲延遲時間dDMl，藉由僞延遲電路DMDL 2僅 延遲延遲時間d MD 2呈上述延遲電路C D1的輸入脈衝 C D M i η。 此輸入脈衝CDM i η傳播延遲電路CD 1，其升起 端緣與被輸入至上述共同節點CO MM ON的延遲1週期而被 輸入的時脈的升起端緣進行比較，被檢測出對應於在上述 延遲電路CD 1的僅延遲延遲時間t DA者的端緣位置之 第N段，形成其檢測訊號CNT-LA。 藉由上述檢測訊號CNTLA多路轉換器MPX 1與 MP X 2被控制，通過延遲電路CD 2及CD 3輸出與上 述相同第N段的延遲訊號CDMo u t與CDo u t ，分 別被供給不同的格子狀延遲電路SQUAD 1與 SQUAD2 »與上述同樣地比較傳播格子狀延遲電路 SQUAD 1的時脈的升起端緣與於上述共同節點 COMMON延遲2週期被輸入的時脈的升起端緣，檢測出對 應於上述格子狀延遲電路S QUAD 1僅被延遲延遲時間 t D B而已者的端圓的第Μ段，形成其檢測訊號 CNTLB。總之，於上述格子狀延遲電路SQUAD1 的輸入，因爲上述僞延遲電路DMD L 1的輸出脈衝 CD i η僅被延遲在延遲電路CD2的延遲時間tDA與 在多路轉換器MP X I的延遲時間dMP X而被輸入的緣 (请先閱讀背面之注意事項再填K本頁) 訂 11丨 Θ 本紙張尺度適州中國國家標净（CNS > Λ4規格（210X297公釐） -49 經濟部中央標羋局貝工消贽合通社印製 A7 _________ B7_______ 五、發明说明（47 ) 故，所以僅有與其之差分的延遲時間t D B使其延遲者的 端緣被選擇。 藉由土述檢測訊號CNTLB控制多路轉換器 MP X 3 ,使輸出對應於與上述格子狀延遲電路 S Q U A D 1同樣電路構成的格子狀延遲電路 S Q UAD 2的上述延遲時間t D B的第Μ段延遲訊號 FD 〇 u t ，通過輸出驅動器DRV 2僅被延遲延遲時間 d 2的輸出時脈脈衝C LK 〇 u t ，在上述被輸入的時脈 脈衝C L K i_ η與在第3週期對應於具有上述延遲電路 S Q U A D 1的高時間分解能的爲小的誤差範圍內同步化 〇 若要定量說明上述動作的話，則如下所述。上述時間 分解能較低的延遲電路CD 1之端緣比較，由於相關的延 遲電路C D 1中所傳播的端緣，與共同節點COMMON的時 間差成爲1個時脈週期的緣故所以下式（1)成立。 dMD l + dMD2 + tDA = t CK-5A …（1) 此處t DA係上述延遲電路CD 1〜CD 3中的時脈 端緣的傳播時間，t CK係時脈週期，<5A係上述延遲電 路C D 1〜CD 3的時間分解能所導致的誤差。 針對時間分解能高的格子狀延遲電路SQUAD 1之 端緣比較，也同樣地成立下式（2)。 dDMl + tDA + dMPXA+tDB = t C K - (5 B ......... ( 2 ) 此處，dMDl係在僞延遲電路DMDL1的延遲時 (請先閱讀背面之注意事項再填寫本頁)-45- Central Ministry of Economic Affairs, Central Bureau of Standards and Technology, Office of the Ministry of Work •% Α7 _ Β7 V. Description of Invention (43) The above-mentioned external clock signal is delayed by a small amount, and various semiconductor integrated circuit devices are necessary. The arrangement of the grid-like delay circuit or the grid-like oscillator circuit may be configured in a grid state on the semiconductor substrate. The grid-like delay circuit can also be used in the case where an internally generated timing signal delays the output by a small amount each time. The lattice-shaped oscillating circuit can be widely used for forming semiconductor integrated circuit devices having a plurality of types of oscillating signals having different phases. Fig. 23 shows a block diagram of an embodiment of a clock synchronization circuit according to the present invention. Each circuit block in the figure is formed on a semiconductor substrate such as single crystal silicon by a conventional semiconductor manufacturing technology, like other circuits not shown. In this embodiment, in order to ensure synchronization, Two types of _delay circuits are used to reduce the frequency band and circuit scale and reduce synchronization errors. 1 type of delay circuit. In order to ensure the frequency band that can be synchronized, a large delay circuit (Coarse Delay) CD 1 ~ CD3 is used to make the time of each segment more than 300 picoseconds. The delay circuit is configured. These delay circuits CD1 to CD3 are formed by connecting a series of CMO S inverter circuits arranged in mutually identical circuits. Another delay circuit is related to the development of the inventor of the present invention. It is known that the small grid-like delay circuits SQUAD1 and SQUAD2 in which the time of each segment becomes 20 to 100 picoseconds, that is, the time resolution energy is used. Delay circuit with higher accuracy. By combining the above time minutes (please read the precautions on the back before filling this page)-Order Θ This paper size Luzhou China National Standard Feng (CNS) Λ4 size (210 X 297 mm) -46- Central of the Ministry of Economics Printed by the Bureau of Standards and Consumers ’Cooperatives ^ A7 B7 V. Description of the invention (44) The two types of solution, the larger and the smaller, can ensure the reduction of the above-mentioned synchronizable frequency band and circuit scale, and the synchronization error. "Zoom Out" In short, using the above-mentioned time decomposition. The lower delay circuits CD 1 to CD 3 can be used to form a rough synchronization signal, and the synchronization error component included in it can reduce the grid-like delay by the above time decomposition. Configuration of circuits SQUAD1 and SQUAD2 to correct "In this embodiment, in order to form a clock signal synchronized with the above precision with high accuracy, three CDs 1 to CD3 are used as the delay circuits with low time resolution. A delay circuit CD1 delays the input clock pulse C D M i η to the edge detection circuit E D 1. This edge detection circuit ED 1. compares the delay signal of each segment of the above-mentioned delay circuit CD 1 with the edge of the clock pulse which is delayed by one clock and input, if the two edges are consistent in time At that time, the edge position of the delay circuit CD 1 was detected (that is, the number of segments N of the delay element circuit that passed). The multiplexers MPX1 and MPX2 are controlled by the detection signal CNTLA formed by the edge detection circuit ED1, and the output pulses CDMo ut and CD3 are output from the delay circuits CD 2 and CD 3 having the same configuration as the delay circuit CD 1. CD 〇ut.输出 The output pulse CDMout output from the above-mentioned multiplexer MPX1 is supplied to the grid-like delay circuit SQUAD 1 and its delay signal is supplied to the edge detection circuit E D2. This edge detection circuit ED 2 compares the delay signal of each segment of the above-mentioned grid-like delay circuit S QUAD 1 with the edge of a clock pulse which is delayed by another clock and is input. Paper size applies to China National Standard Beer < CNS) Λ4 specification (2 丨 0X297 mm) (Please read the precautions on the back before filling out this page) Sub-47- Central Bureau of Standards, Ministry of Economic Affairs B7 V. Description of the invention (45) If it is the same, the position of the edge of the grid-shaped delay circuit S QUAD 1 (that is, the number of segments of the passed delay element circuit) is detected at this time. The multiplexer MPX3 is controlled by the detection signal CNTLB formed in the edge detection circuit ED2, and an output pulse FDout is output from a delay circuit S QUAD 2 having the same configuration as the lattice delay circuit S QUAD 1. This FDout is supplied to another circuit (not shown) as an internal clock signal CLCout that is synchronized by the output driver DRV2. The above-mentioned internal clock signal CLKout is synchronized with the input clock signal C LK i η supplied from an external terminal, and the related input clock signal CLK i η passes through the receiver RCV1 as an input buffer and the driver DRV 1 The common node COMMON supplied to the synchronization circuit has the above-mentioned input clock pulse. In short, the input pulse that the output of the driver DRV 1 is taken by the connected common node COMMON is not directly supplied to the input of the delay circuit CD 1 but is delayed by the dummy delay circuits DMD L 1 and DMD L 2 It is again used as the input signal CDMi of the delay circuit CD1. »The dummy delay circuit DMD L2 adjusts the time in such a way that the required performance of the grid-shaped delay circuits SQUAD 1 and SQUAD 2 with high time resolution can be exhibited. The pseudo delay circuit DMD L 1 forms delay times corresponding to the receiver RCV 1 and the driver DRV 1 and the multiplexer MPX3. Fig. 24 shows timing charts for explaining the operation of the above-mentioned clock synchronization circuit. The clock signal CLK i η input from the external terminal is in accordance with the Chinese National Standard (CNS) Λ4 specification (210X297 mm) of this paper (锖 Please read the precautions on the back of Jing before filling this page) -Order- 48- Work and Consumption Cooperation of the Bureau of Standards and Decisions of the Ministry of Economic Affairs- # 社 印? This A7 B7 V. Explanation of the invention (46) The receiver RCV1 and the driver DRV 1 only delay the delay time d 1 by changing the clock pulse of the common node COMMON. The input pulse of the common node COMMON is delayed only by the delay time dDM1 by the dummy delay circuit DMD L1, and only the delay time dMD2 by the dummy delay circuit DMDL 2 is the input pulse C D M i η of the delay circuit C D1. The rising edge of the input pulse CDM i η propagation delay circuit CD 1 is compared with the rising edge of the clock input to the common node CO MM ON with a delay of one cycle, and is detected to correspond to The detection signal CNT-LA is formed at the Nth stage of the edge position of the delay circuit CD 1 that is delayed only by the delay time t DA. The above-mentioned detection signals CNTLA multiplexers MPX 1 and MP X 2 are controlled, and the delay signals CDMo ut and CDo ut of the same N-th stage as described above are output through the delay circuits CD 2 and CD 3, and are respectively supplied to different grid shapes. Delay circuits SQUAD 1 and SQUAD 2 »Compared with the above, the rising edge of the clock of the propagation-lattice delay circuit SQUAD 1 is compared with the rising edge of the clock input to the common node COMMON with a delay of 2 cycles, and a correspondence is detected. The detection signal CNTLB is formed on the M-th segment of the end circle of the grid-like delay circuit S QUAD 1 which is delayed only by the delay time t DB. In short, at the input of the grid-like delay circuit SQUAD1, the output pulse CD i η of the dummy delay circuit DMD L 1 is delayed only by the delay time tDA of the delay circuit CD2 and the delay time dMP X of the multiplexer MP XI. And the entered margin (please read the notes on the back before filling the K page) Order 11 丨 Θ This paper size is suitable for China National Standard Net (CNS > Λ4 size (210X297 mm) -49 Central Ministry of Economic Standards) Printed by the Bureau of Industry and Technology Co., Ltd. A7 _________ B7_______ 5. Description of the Invention (47) Therefore, only the delay time t DB which is different from it makes the end of the delayer be selected. By the earth test signal CNTLB The multiplexer MP X 3 is controlled so that an output corresponding to the M-th stage delay signal FD 0ut of the delay time t DB of the grid-like delay circuit SQ UAD 2 having the same circuit as the grid-like delay circuit SQUAD 1 described above is output. The driver DRV 2 is delayed only by the output clock pulse C LK ut of the delay time d 2, and the input clock pulse CLK i_ η and the third cycle correspond to the above-mentioned delay circuit SQUAD 1 The high time resolution energy is synchronized within a small error range. If the above actions are to be quantitatively explained, it is as follows. The edge comparison of the delay circuit CD 1 with the above time resolution energy is relatively low. The propagated end edge has the following equation (1) because the time difference between the common node COMMON becomes one clock cycle. DMD l + dMD2 + tDA = t CK-5A… (1) where t DA is the above delay The propagation time of the clock edges in the circuits CD 1 to CD 3, t CK is the clock period, and < 5A is an error caused by the time resolution energy of the above-mentioned delay circuits CD 1 to CD 3. A grid pattern with a high time resolution energy The comparison of the edge of the delay circuit SQUAD 1 also holds the following formula (2): dDMl + tDA + dMPXA + tDB = t CK-(5 B ......... (2) Here, dMDl is When the delay of the pseudo-delay circuit DMDL1 (please read the precautions on the back before filling this page)

本紙張尺度適用中囷囷家標準（（，NS > Λ4規格（210X297公釐） -50- DA + dMPXA+tDB + τ A7 __B7 五、發明説明（48 ) 間，dMPXA係在多路轉換器MPX 1的延遲時間， 5 B係上述格子狀延遲電路S QUAD 1及S QUAD 2 的時間分解能所導致的誤差，較上述5 A爲小係爲1 〇微 微秒等級。 從上述輸入時脈訊號CLK i η直到輸出時脈訊號 CLKo u t爲止的傳播時間r，依照上述傳播路徑取延 遲時間的和，可以用下式（3)表示。 ' τ = d 1 + t dMPXB + d2 將上述（3 )式以上述（2)是加以整理的話可以式 (4 )來表示。 - d 1 + t CK-(5B-dDMl + dMPXB + d 2 ....... ( 4 ) 由上述式（4)，以使僞延遲電路dMd LI的延遲 時間dDMl等於作爲上述輸入緩衝器的接受器RVC 1 、驅動器DRV1的延遲時間dl，與輸出驅動器 DRV 2的延遲時間d 2以及多路轉換器MP X 3的延遲 時間dMPXB的和（d l + d2 + dMPXB)而設定 的話，則成立式（5) ，CLKi η與CLKou t成爲 與誤差5 B同步》 (5 ) 僞延遲電路DMD L 2，係上述格子狀延遲電路 SQUAD 1與SQUAD2的誤差調整用延遲電路。由 上述式（1) (2)，針對tDB整理的話，可得下式（ 本紙張尺度適用中國囤家標隼（CNS ) Λ4規格（210X 297公釐） {请先閲讀背面之注意事項再填寫本頁) Θ 經 濟 部 中 標 局 負 工 消 合 -作 社 印 % -訂 Isim -51 - 經濟部中央標準局負工消资合作社印掣 A7 B7 五、發明説明（49 ) 6 )。 t DB = dDM2-dMPXA+5A_5B …（6) 由此式（6)，如果使僞延遲電路DMDL 2的延遲 時間d D Μ 2變長，則可以使格子狀延遲電路 SQUAD1、SQUAD2的延遲時間tDB變長。格 子狀延遲電路SQUAD1、SQUAD2，如後述般的 在初段側的延遲段不安定，衰減震動的延遲時間具有不一 致性的緣故，所以避免使用如此般的初段側的延遲輸出， 而於可獲得更爲安定的高精度微小延遲時間的動作區域之 用的時間調整使用上述僞延遲電路DMD L 2的延遲時間 d D Μ 2。 在此實施例的時脈同步電路可以同步的時脈訊號的最 大週期t CKmax，係由延遲電路CD1〜CD3的最 大延遲時間，換句話說，係以C Μ 0 S反相器電路列的長 度而決定。以上述延遲電路CD 1〜CD 3的最大値，亦 即以全體的傳播延遲時間爲t DAma X，由式（1 )， 成立下式（7 )。 t CK<dDMl+dDM2 + tDAma x = t C K m a x ......... ( 7 ). 另一方面，可同步的時脈的最小週期可以沒有限制。 時脈週期變短的話，成爲dDMl + dDM2> t CK， 滿足式（1 )的正延遲時間t DA並不存在。但是如果下 式（8)成立的話，如下列式子（9)〜（1 2)所示可 以同步化》 {請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度漣圯中國國家標埤（（?NS ) Λ4現格（21〇X 297公釐） -52- 經濟部中央標準局β工消费合.#社印裝 A7 B7 五、發明説明（50 ) ciDMl + dDM2+tDA = nt;CK — <5A…（8) 由上述式（8) ’因爲 所以1 (dDMl + dDM2) / t CK<n< (tDAxnaxd + dDMl+.dDM2)/t CK ...... …（9 ) 如果 t DAma x>dDMl + dDM2 ......... (10) 則成立' (dDMl + dDM2) / t CK<n< 2 ( d D .M 1 + d D M 2 ) / t- C K ......... (11) 因而針對t CK而言dDMl + dDM2滿足下式 2 (dDMl + dDM2)/tCK-(dDMl + d D M 2 ) / t C K = (dDMl + dDM2)/tCK > 1 ......... ( 1 2.) 所以滿足式（1 1 )的自然數n必定存在》 亦即，以使t DAma X滿足式（10)的方式設定 的話，可以除去可同步的時脈的最小週期限制。但是’ η 增加的同時所需要的同步時脈的產生的時脈週期數也增加 。總之，爲了進行在延遲電路CD 1爲1次，在格子狀延 遲電路SQUAD 1爲1次合計2時脈週期的測定’對於 同步至少要有3時脈週期，但是較其更爲增加。相反的爲 了抑制此時脈週期數，有必要以使僞延遲電路DMD L 1 與DMDL 2的延遲時間dDMl或dDM2變小的方式 {請先閱讀背面之注意事項再填寫本頁) -訂 線I '0 本紙張尺度適用中國國家標绛（CNS ) Λ4規格（2丨0X297公釐） -53- A7 B7 經 濟 部 中 央 標 準 局 X 消 f： 合 作 社 印 製 五、發明説明（51 ) 使內部時脈驅動器dRVl的延遲11或是時脈接受器 RCV1的延遲dl〇變小。 於第5圖，顯示上述延遲電路CD 1的一實施例的 電路圖。延遲電路CD 1，係將4個CMOS反相器電路 作爲1個延遲要素CDun i t被縱列接續爲16段》以 使從各段獲得延遲訊號CD 0 0〜CD 1 5的方式構成者 。總之，延遲電路CD 1，係藉由4x16 = 64個 CMO S反相器電路而構成。其他的延遲電路C D 2與 C D 3也藉由同樣的電路構成。如上所述將延遲要素 CDun i t藉由4個CMOS反相器電路構成以藉此形 成約爲3 0 0微微秒程度的比較低的時間分解能的延遲訊 號。 於第2 6圖，顯示對應於上述延遲電路CD 1的端緣 檢測電路ED 1的一實施例的電路圖，於第2 7圖顯示對 應於格子狀延遲電路S QUAD 1的端緣檢測電路E D 2 的一實施例的電路圖。如第2 7圖所顯示的單位電路的具 體電路，係由被縱列接續的2個貫通閂鎖電路所構成。總 之，輸入側的貫通閂鎖電路，係由CMO S反相器電路 Nl、N通道型MOSFET Q1與P通道型 MOSFET Q2所構成的CMOS開關，構成閂鎖電 路的CMOS反相器電路N 3、復歸用的時脈反相器電路 C N 1所構成，輸出側的貫通閂鎖電路，係由N通道型 MOSFET Q3與P通道型MOSFET Q4鎖構 成的CMO S開關、構成閂鎖電路的CMO S反相器電路 (請先閱讀背面之注意事項再填寫本頁) 訂This paper size applies to the Chinese standard ((, NS > Λ4 specification (210X297mm) -50- DA + dMPXA + tDB + τ A7 __B7 V. Description of the invention (48), dMPXA is in the multiplexer The delay time of MPX 1, 5 B is the error caused by the time decomposition energy of the above-mentioned grid-like delay circuits S QUAD 1 and S QUAD 2, which is smaller than the above 5 A, which is on the order of 10 picoseconds. The clock signal CLK is input from the above. i η The propagation time r until the clock signal CLKo ut is output. The sum of the delay times according to the above propagation path can be expressed by the following formula (3). 'τ = d 1 + t dMPXB + d2 The above formula (3) If (2) above is sorted, it can be expressed by formula (4).-D 1 + t CK- (5B-dDMl + dMPXB + d 2... (4) From the above formula (4), So that the delay time dDM1 of the dummy delay circuit dMd LI is equal to the delay time dl of the receiver RVC 1 and the driver DRV1 as the input buffer, the delay time d 2 of the output driver DRV 2 and the delay of the multiplexer MP X 3 If the sum of time dMPXB (dl + d2 + dMPXB) is set, then equation (5) is established, and CLKi η and CLKou t are Synchronization with error 5 B "(5) The pseudo-delay circuit DMD L 2 is the delay adjustment circuit for error adjustment of the above-mentioned grid-shaped delay circuits SQUAD 1 and SQUAD 2. According to the above equations (1) and (2), tDB can be obtained. The following formula (This paper size applies to the Chinese storehouse standard (CNS) Λ4 specification (210X 297 mm) {Please read the precautions on the back before filling this page) -Order Isim -51-A7 B7 printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumers and Consumers Cooperative V. Description of the invention (49) 6) t DB = dDM2-dMPXA + 5A_5B… (6) From this formula (6), if Increasing the delay time d D M 2 of the dummy delay circuit DMDL 2 makes it possible to increase the delay time tDB of the grid-like delay circuits SQUAD1 and SQUAD2. The grid-like delay circuits SQUAD1 and SQUAD2 have a delay at the early stage side as described later. The stage is unstable, and the delay time of the damping vibration is inconsistent. Therefore, avoid using such a delay output on the initial stage side, and use the above time adjustment for the action area that can obtain a more stable high-precision minute delay time. Fake The delay time d D M 2 of the delay circuit DMD L 2. The maximum period t CKmax of the clock signal that the clock synchronization circuit can synchronize in this embodiment is the maximum delay time of the delay circuits CD1 to CD3, in other words, It is determined by the length of the C M 0 S inverter circuit column. Taking the maximum delay of the above-mentioned delay circuits CD 1 to CD 3, that is, the total propagation delay time is t DAma X, the following formula (7) is established from the formula (1). t CK < dDMl + dDM2 + tDAma x = t C K m a x ......... (7). On the other hand, the minimum period of the synchronizable clock may be unlimited. When the clock cycle becomes shorter, it becomes dDM1 + dDM2> t CK, and the positive delay time t DA satisfying the expression (1) does not exist. However, if the following formula (8) is established, it can be synchronized as shown in the following formulas (9) to (12): {Please read the precautions on the back before filling this page.)埤 ((? NS) Λ4 is present (21〇X 297 mm) -52- Central Standards Bureau of the Ministry of Economic Affairs β industry consumption. # 社 印 装 A7 B7 V. Description of the invention (50) ciDMl + dDM2 + tDA = nt ; CK — < 5A… (8) From the above formula (8) 'because 1 (dDMl + dDM2) / t CK < n < (tDAxnaxd + dDMl + .dDM2) / t CK ...... (9 ) If t DAma x > dDMl + dDM2 ......... (10) then it holds' (dDMl + dDM2) / t CK < n < 2 (d D .M 1 + d DM 2) / t- CK ......... (11) Therefore for t CK dDMl + dDM2 satisfies the following formula 2 (dDMl + dDM2) / tCK- (dDMl + d DM 2) / t CK = (dDMl + dDM2) / tCK > 1 ......... (1 2.) So the natural number n that satisfies the formula (1 1) must exist ", that is, if t DAma X is set to satisfy the formula (10) , You can remove the minimum cycle limit of the synchronizable clock. However, the number of clock cycles required to generate the synchronous clock also increases as' η increases. In short, in order to measure 1 clock cycle in the delay circuit CD 1 and 2 clock cycles in the grid-shaped delay circuit SQUAD 1 once, it is necessary to have at least 3 clock cycles for synchronization, but it is more than that. On the contrary, in order to suppress the number of pulse cycles at this time, it is necessary to make the delay time dDMl or dDM2 of the pseudo delay circuits DMD L 1 and DMDL 2 smaller (please read the precautions on the back before filling this page)-Order I '0 This paper size applies to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297 mm) -53- A7 B7 Central Bureau of Standards, Ministry of Economic Affairs X Consumer f: Printed by the cooperative V. Description of the invention (51) Make the internal clock The delay 11 of the driver dRV1 or the delay dl0 of the clock receiver RCV1 becomes smaller. Fig. 5 is a circuit diagram showing an embodiment of the above-mentioned delay circuit CD1. The delay circuit CD 1 is composed of four CMOS inverter circuits as one delay element, CDun it is successively connected to 16 segments, so that delay signals CD 0 0 to CD 15 are obtained from each segment. In short, the delay circuit CD 1 is constituted by 4 × 16 = 64 CMO S inverter circuits. The other delay circuits C D 2 and C D 3 are also configured by the same circuit. As described above, the delay element CDunit is composed of four CMOS inverter circuits to form a delay signal with a relatively low time resolution of about 300 picoseconds. Fig. 26 shows a circuit diagram of an embodiment of the edge detection circuit ED1 corresponding to the above-mentioned delay circuit CD 1, and Fig. 27 shows an edge detection circuit ED 2 of the grid-shaped delay circuit S QUAD 1. Circuit diagram of an embodiment. The specific circuit of the unit circuit as shown in Fig. 27 is composed of two through latch circuits connected in series. In short, the input latch-through circuit is a CMOS switch composed of CMO S inverter circuit N1, N-channel MOSFET Q1, and P-channel MOSFET Q2, and a CMOS inverter circuit N3 that constitutes a latch circuit. The clocked inverter circuit CN 1 for reset, the through latch circuit on the output side, is a CMO S switch composed of N-channel MOSFET Q3 and P-channel MOSFET Q4 lock, and a CMO S Phaser circuit (Please read the precautions on the back before filling this page)

本紙張尺度通用中國國家標绛（CNS )八4規格（210X297公釐） -54- 經濟部中央標準局H3C Η消费合作社印^ A7 B7 五、發明説明（52 ) . N4、復歸用的時脈反相器電路CN2所構成，爲了互補 地控制上述CMO S開關而設有反相器電路N 2，通過 NAND閘電路G1供給時脈訊號CLK。 於上述端緣檢測電路E D 2的一方的輸入，被供給上 述格子狀延遲電路SQUAD 1的各段延遲訊號CD i j 。於另一方的輸入，通過上述NAND閘電路G 1被輸入 至共同節點COMMON的時脈脈衝被供給。在共通節點 COMMON的時脈脈衝的升起端緣之各段的傳播延遲訊號被 取入，該被取入的輸出QB1與對應於延遲1個延遲段的 輸出Q以N 0 R閘電路比較之。兩訊號相異者總之上述共 通節點COMMON的時脈脈衝的升起時，成爲高準位者的輸 出變成低準位，檢測出仍未成爲高準位者的輸出Q的低準 位使其輸出。 在對應於上述第2 6圖的延遲電路CD 1的端緣檢測 電路EDI，如前所述般的爲了拓展可同步的時脈頻率帶 域，而追加2輸入的NOR閘電路A與反相器電路B以及 2輸入的NAND閘電路C。這是隨著時脈訊號 CLK i η的週期變短，爲了使延遲電路CD 1中同時存 在複數的升起端緣，而供取出最接近於延遲電路C D 1的 輸入C DM i η的端緣檢測訊號之用的電路。端緣被檢測 的話，對應的NOR電路A，形成低準位的輸出訊號通過 反相器電路B以使之後的2輸入N◦R閘電路A與 NAND閘電路C的閘關閉的方式健其非動作。此非動作 訊號的傳播使用到上述NOR閘電路與反相器電路，在此 (請先閱讀背面之注意t項再填寫本頁)The size of this paper is in accordance with China National Standards (CNS) 8 4 specifications (210X297 mm) -54- Central Standards Bureau of the Ministry of Economic Affairs H3C 印 Printed by Consumer Cooperatives ^ A7 B7 V. Description of the invention (52). N4. Clock of return The inverter circuit CN2 is configured to provide an inverter circuit N 2 for complementary control of the CMO S switch, and a clock signal CLK is supplied through a NAND gate circuit G1. One of the inputs to the edge detection circuit E D 2 is supplied to the delay signals CD i j of the respective stages of the grid-like delay circuit SQUAD 1. At the other input, a clock pulse input to the common node COMMON through the NAND gate circuit G1 is supplied. The propagation delay signal of each segment at the rising edge of the clock pulse of the common node COMMON is taken in, and the taken-in output QB1 is compared with the output Q corresponding to one delay segment with a N 0 R gate circuit. . The two signals are different. In short, when the clock pulse of the common node COMMON rises, the output of the person who has become the high level becomes the low level, and the output of the person who has not yet become the high level is detected as the low level of the output Q. . At the edge detection circuit EDI corresponding to the delay circuit CD 1 of FIG. 26 described above, a 2-input NOR gate circuit A and an inverter are added in order to expand the synchronizable clock frequency band as described above. Circuit B and 2-input NAND gate circuit C. This is because as the period of the clock signal CLK i η becomes shorter, in order to have a complex rising edge in the delay circuit CD 1 at the same time, the edge of the input C DM i η that is closest to the delay circuit CD 1 is taken out. Circuit for detecting signals. If the edge is detected, the corresponding NOR circuit A forms a low-level output signal. It passes through the inverter circuit B to close the gates of the next 2 inputs. action. The propagation of this non-operation signal uses the above-mentioned NOR gate circuit and inverter circuit, here (please read the note t on the back before filling this page)

本紙張尺度適/fl中國囤家標埤（CNS ) Λ4規格（210 X 297公釐） -55- A7 B7 五、發明説明（53 ) 之延遲時間有必要較延遲電路C D 1的各段的延遲要素的 延遲時間更小。在此，爲了同時簡化電路而將延遲電路 CD 1的延遲要素以4個COMS反相器電路構成，係如 上述般的被設定爲比較低的時間分解能者。 上述端緣檢測電路，係以使時脈C L K通過NAND 閘電路G 1而被輸入的方式構成，藉由使共通節點 COMMON成爲固定準位，或者是授權訊號ENABLE設爲低準 位，可以使上述共通節點COMMON的輸入脈衝停止供給。 藉此，端緣檢測電路如上述般的停止端緣檢測動作，停止 前的檢測訊號通過輸出側的閂鎖電路而被輸出。如此般的 時脈控制與輸出閂鎖功能，被利用於如後述般的低耗電動 作。 於第2 8圖，顯示多路轉換器MPX3的一實施例的 ........- 經濟部中央標準局貝工消費合-#社印裝 (請先閲讀背面之注意事項再填寫本頁) Θ 電路圖。在此實施例，格子狀延遲電路S QUAD 2形成 如CD0 0〜CD49之5 0個延遲訊號，以不選擇其中 不安定的前段電路的方式選擇3 6個延遲訊號。將多段轉 換器接續爲3段樹狀態使其從3 6個延遲訊號選擇1個的 方式構成。總之，初段與輸出段的多路轉換器MPX — R 爲3輸入的電路，第2段的多路轉換器MPX-D爲4輸 入的電路》亦即，設12個上述3輸入的多路轉換器 MPX-R，CD00/E00 〜CD35/E35 (未 圖示）鎖構成的延遲訊號CD i j與端緣檢測訊號E i j 每3個分成1 2組輸入，將1 2個的輸出訊號以及授權訊 號使用3個4輸入的多路轉換器MPX — D分別輸入，使 本紙張尺度適用中國國家標埤（CNS ) Λ4規格（210Χ297公釐） -56- 經濟部中央標準局貝工消费合祚社印製 A7 _B7_______ 五、發明説明（54 ) 輸出來自多路轉換器MPX—D的3個輸出與授權訊號， 以使從上述輸出段的多路轉換器Μ P X — R輸出其中之1 的方式構成者。 於該圖，作爲多路轉換器Μ Ρ X 3的輸入端子，如 CD 〇 0/Ε 0 0〜所示，請注意與第2 7圖所示的上述 格子狀延遲電路S QUAD 1的延遲段C D O 〇〜 CD49以及端緣檢測輸出E00〜E49不一致。 於第2 9圖，顯示供說明被使用於本發明的格子狀延 遲電路的動作之用的波形圖。例如，以被顯示於時間軸中 央部的輸出訊號的升起端緣爲例，可知除了最初的數條以 外，時脈訊號的升起大約以5 0微微秒的等間隔升起。至 於輸出訊號的降下端緣，可知是大約爲5 0微微秒之等間 隔，在時間軸的後側最初的時脈訊號的降下係凌亂的。 如上述般的爲了不使用在時間軸的前側對應於最初數 條的延遲訊號，設有前述僞延遲電路DM D L 2，以使用 如上述般的大約5 0微微秒的等間隔變化的區域藉此可以 縮小同步誤差<5 B。 上.述格子狀延遲電路SQUAD1與SQUAD2， 藉由如上述般的使N A N D閘電路作爲所謂線性電路來動 作而獲得高時間分解能者，與通常的CMO S電路相異流 動著比較大的消耗電流。但是，時脈同步電路，將被輸入 時脈週期的測定的時脈脈衝CLK i η的複數週期作爲1 回，可以大幅降低動作電流。 前述第2 7圖所示的端緣檢測電路’係保持之目的端 (谛先閲讀背面之注意事項再填寫本頁) ---------------1 )------ΐτί線 ^ . 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2丨0X297公釐） -57- A7 B7___ 五、發明説明（55 ) 緣檢測訊號者。亦即，如第3 0圖的計時圖所示將授權訊 號ENABLE設爲低準位，而由僞延遲電路DMDL1、 D M D L 2，延遲電路C D 1、C D 2，端緣檢測電路 EDI與ED2、多路轉換器ΜΡΧ1與格子狀延遲電路 S Q U A D 1所構成的時脈週期測定區塊停止動作；延遲 電路CD 1的輸入訊號CD i η、延遲電路CD2的輸入 訊號CDMi η以及多路轉換器ΜΡΧ1的輸出訊號 CDMo u t成爲低準位的狀態，也基於停止之前的時脈 週期測定結果，藉由延遲電路C D 3與多路轉換器 MPX2形成CDout，藉由格子狀延遲電路 SQUAD2以及多路轉換器MPX3形成FDo u t通 過輸出段驅動器DRV 2可以形成內部時脈訊號 C L K 〇 u t 。 經濟部中史標隼局员工消费合作社印ί本 {請先閲讀背面之注意事項再填寫本頁) 於第2 3圖，上述授權訊號ENABLE係藉由如習知的動 態型RAM的以自我刷新方式被設於晶片內的計時器Timer 而被形成。藉由此計時器Timer以複數個時脈訊號 CLK i η 1次的比率使上述授權訊號EN ABLE成爲高準位 ，使由上述僞延遲電路DMDL1、DMDL2，延遲電 路CD1、CD2、端緣檢測電路EDI與ED2、多路 轉換器MPX1與格子狀延遲電路SQUAD 1所構成的 時脈週期測定區塊動作，其時將端緣檢測訊號更新。於上 述時脈週期測定，由於必須要上述3個時脈，所以時脈訊 號CLK i η的3個週期份有必要使授權訊號ENABLE成爲 高準位。. 本紙張尺度適用中國國家標?('NS ) Λ4規格（210X297公釐） •58- A7 B7 五、發明説明（Μ ) 以使由於上述計時器Timer的週期隨著晶片溫度變化等 所產生的同步誤差<5 B在容許範圍（1 0 0微微秒以下） 的方式設定之。可以設爲大約1 00 ms e c以上的週 期，藉由上述時脈週期測定區塊的間歇動作，可以使使用 如上述般的耗電量大的格子狀延遲電路S Q U A D維持同 步誤差δ B維持於高精度，而且肪止耗電量的增加。 如上述般的，在此實施例的時脈同步電路時脈的同步 化最少需要3時脈週期。但是，這是在電源投入以前沒有 任何同步資訊的場合，在時脈週期測定區塊存在著停止前 的同步資訊而且有效的場合，可以獲得以1個時脈週期被 同步的內部時脈訊號CLKou. t。 經"-部中央標丰局貝Η消贽合4社印製 (请先閲讀背面之注意事項再填"·本頁) Θ 於第3 1圖，顯示供說明相關於本發明的時脈同步電 路的其他動作之一例之用的計時圖。於該圖，顯示著藉由 計時器Timer之時脈週期測定區塊的再起動動作之例。藉由 計時器Timer輸出計時訊號TMo u t的話，並不立刻使產 生授權訊號Enable，而使對應於共通節點COMMON的降下端 緣而使授權訊號Enable從低準位變化爲高準位。藉此，可以 使共通節點COMMON從低準位直到高準位爲止確保一定的 時間範圍。 藉由上述授權訊號Enable的高準位，上述僞延遲電路 DMDL1、DMDL2，延遲電路 CD1、CD2，端 緣檢測電路EDI與ED2，多路轉換器MPX1與格子 狀延遲電路S Q U A D所構成的時脈週期測定區塊被活化 ，分別使共通節點COMMON的高準位的升起端緣延遲，訊 本紙張尺度適用中國1家標埤（CNS ) Λ4規格（210X297公釐） •59- 經濟部中央標芈局只工消費合作社印¾ Α7 Β7 五、發明説明（57 ) 號CD i n、CDMi η以及CDMou t成爲高準位， 藉由端緣檢測電路E D 1與E D 2進行同步化動作。 於第2圖，顯示供說明相關於本發明的時脈同步電 路的其他動作之一例之用的計時圖。於該圖’顯示朝向降 低功率模式的模式轉換動作之例。在此降低功率模式，藉 由時脈授權訊號CKE的低準位，驅動器DRV 1停止動 作將輸出之共通節點COMM ON固定於低準位。藉此’+由上 述僞延遲電路DMDL1、DMDL2，延遲電路CD1 、CD2，端緣檢測電路ED1_ED2 *多路轉換器 MP X 1與格子狀延遲電路S QUAD 1所構成的時脈週 期測定區塊以及形成內部時脈訊號CLKou t的延遲電 路C D 3的輸出以及格子狀延遲電路S QUAD 2的輸出 也對應於上述共通節點COMMON被固訂於低準位，不進行 實質的動作。總之，上述延遲電路C D 3與格子狀延遲電 路SQUAD2，因爲同以CMOS電路構成的緣故，所 以對應於上述輸入之共通節點COMMON之低準位固定可以 使動作電流不流動。 於第.3 3圖，顯示供說明相關於本發明的時脈同步電 路的其他動作之一例之用的計時圖。於該圖，顯示從上述 降低功率模式復歸之動作之例。由此降低功率模式之復歸 \ ，係藉由上述時脈授權訊號C K E的高準位而被指示的。 藉由此訊號CKE的高準位，內部訊號I CKE被設爲高 準位，使開始驅動器DRV 1的動作。被由外部端子供給 的輸入時脈訊號CLK i η，通過接受器RCV1被輸入 (祷先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國囤家標卑（rNS ) Λ4規格（210X297公釐） -60- 經濟部中央標準局貝Μ消费合作社印？表 A7 B7 五、發明説明（58 ) ，藉由上述驅動器DRV 1的動作開始，上述接受器 RCV1的輸出CLKO被傳達至共通節點COMMON。 此共通節點COMMON的訊號，因爲藉由被保持於上述 端緣檢測電路E D 1的閂鎖電路的停止前的檢測訊號而使 多路轉換器MP X 2選擇延遲電路C D 3的延遲段之一的 緣故，所以其輸出訊號CD 〇 u t傳達至格子狀延遲電路 SQUAD 2的輸入，此格子狀延遲電路S QUAtD 2的 輸出，藉由被保持於上述端緣檢測電路E D 2的閂鎖電路 的停止前的檢測訊號而通過多路轉換器MPX 3而被輸出 。藉此，可以形成延遲1個週期的內部時脈訊號 C L K o u t ° 於第3 4圖，顯示供說明相關於本發明的時脈同步電 路的其他動作之一例之用的計時圖》於該圖，顯示上述降 低功率模式時的時脈同步動作之例。於上述時脈授權訊號 C K E被設爲低準位的降低功率模式，計時器Timer形成輸 出訊號TMo U t的話，與其對應將上述內部訊號 I CKE升起至高準位。藉此，驅動器DRV1.開始動作 ’與上述同樣地將共通節點COMM ON對應於從外部端子供 給的時脈訊號CLK i η而使其變化· 與此同時，在計時器Timer接受上述共通節點COMMON 的往低準位的變化，使授權訊號Enable變化爲高準位。亦即 ，與上述同樣地產生延遲1個週期的內部時脈訊號 C L K 〇 u t，同時將上述授權訊號Enable對應於高準位， 使由僞延遲電路DMDL1、DMDL2，延遲電路 本紙張尺度適用中國ϋ家標埤（CNS ) Λ4規格（210Χ297公釐） (諳先閱讀背面之注意事項再填寫本頁) 訂 -61 - 經濟部中央標準局貝工消费合作社印？木 A7 ___B7五、發明説明（59 ) CD1、CD2，端緣檢測電路EDI與ED2，多路轉 換器MP X 1與格子狀延遲電路S QUAD 1所構成的時 脈週期測定區塊開始動作，耗費3個週期將被保持於上述 端緣檢測電路ED I與ED 2的端緣檢測訊號置換爲新的 訊號。 如此即使時脈授權訊號C K E被設爲低準位的降低功 率模式持續比較長的時間，也可以由計時器週期地實施從 外部端子被供給地時脈訊號C L K i η與內部時脈訊號 CLKo u t的同步化動作，因此如前述第3 3圖所示般 的從降低功率模式之復歸，可以獲得1個週期後同步於由 外部端子所被供給的時脈訊號C L K i η的內部時脈訊號 C L Κ 〇 u t。 於第3 5圖，顯示供說明SDRAM的DDR名里的 波形圖。於該圖，顯示著對應於雙重資料比率（DDR: --- 一 ------·· Double Data Rate)規格的波形圖。在DDR規格，形成同 步化於被從外部端子供給的時脈訊號Ext·CLK的內 部時脈訊號i n t . C om-CLK，使此延遲以對於下 一個時脈先行指定時間的方式預先形成內部計時訊號 i n t . Da t a - CLK，以其升起降下的計時輸出資 料DO〜D3。總之，依照上述時脈訊號i n t · D a t a — C LK的升起降下使輸出輸出訊號D 〇〜D 3 。在此構成，於時脈訊號的1個週期中可以進行2次資料 輸出的緣故，所以.可以實現高速輸出動作。接著’係依照 對於外部時脈Ext . CLK使其先行的內部計時訊號 (誚先閱讀背面之注意事項再填寫本頁)The size of this paper is suitable / fl Chinese storehouse standard (CNS) Λ4 size (210 X 297 mm) -55- A7 B7 5. The delay time of the description of the invention (53) must be longer than the delay of each section of the delay circuit CD 1 The delay time of features is smaller. Here, in order to simplify the circuit at the same time, the delay element of the delay circuit CD 1 is constituted by four COMS inverter circuits, which are set to a relatively low time resolution capability as described above. The above-mentioned edge detection circuit is configured such that the clock CLK is input through the NAND gate circuit G1, and the common node COMMON is set to a fixed level or the authorization signal ENABLE is set to a low level. The input pulse of the common node COMMON is stopped. Thereby, the edge detection circuit stops the edge detection operation as described above, and the detection signal before the stop is output through the latch circuit on the output side. Such clock control and output latch functions are used for low-power electric operation as described below. In Fig. 28, an embodiment of the multiplexer MPX3 is shown .....--Central Standards Bureau, Ministry of Economic Affairs, Shellfish Consumption Co., Ltd.-# 社 印 装 (Please read the notes on the back before filling (This page) Θ circuit diagram. In this embodiment, the grid-like delay circuit S QUAD 2 is formed as 50 delay signals such as CD0 0 to CD49, and 36 delay signals are selected in such a manner that the unstable front-end circuit is not selected. The multi-segment converter is connected to a three-segment tree state, and it is constituted by selecting one from 36 delayed signals. In short, the multiplexer MPX-R of the first stage and the output stage is a 3-input circuit, and the multiplexer MPX-D of the second stage is a 4-input circuit. That is, 12 multiplexers with 3 inputs as described above are set. MPX-R, CD00 / E00 to CD35 / E35 (not shown), the delay signal CD ij and the edge detection signal E ij are divided into 12 input groups every 3, and the 12 output signals and authorized signals Use three 4-input multiplexers MPX-D to input separately, so that this paper size applies to China National Standard (CNS) Λ4 specification (210 × 297 mm) -56- Printed by the Sheller Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs System A7 _B7_______ V. Description of the invention (54) The output of the three outputs from the multiplexer MPX-D and the authorization signal, so that one of the multiplexers MPX-R from the above output section outputs one . In this figure, as the input terminal of the multiplexer MP X 3, as shown in CD 〇0 / Ε 0 0 ～, please pay attention to the delay section of the grid-like delay circuit S QUAD 1 shown in FIG. 27. CDO 0 to CD49 and edge detection outputs E00 to E49 do not match. Figures 29 and 9 show waveforms for explaining the operation of the grid-like delay circuit used in the present invention. For example, taking the rising edge of the output signal displayed at the center of the time axis as an example, it can be seen that, apart from the first few, the clock signal rises at approximately 50 picosecond intervals. As for the falling edge of the output signal, it can be seen that the interval is about 50 picoseconds, and the falling of the first clock signal on the rear side of the time axis is messy. As described above, in order not to use the delay signals corresponding to the first few delay signals on the front side of the time axis, the aforementioned dummy delay circuit DM DL 2 is provided so as to use an area that varies at regular intervals of about 50 picoseconds as described above. The synchronization error < 5 B can be reduced. As mentioned above, the grid-shaped delay circuits SQUAD1 and SQUAD2 obtain high-time resolution energy by operating the N A N D gate circuit as a so-called linear circuit as described above, which flows a relatively large current consumption differently from a normal CMO S circuit. However, the clock synchronization circuit uses the complex cycle of the clock pulse CLK i η which is input to the measurement of the clock cycle as one cycle, and can significantly reduce the operating current. The edge detection circuit shown in the aforementioned Figures 2 to 7 is for the purpose of retention (保持 Please read the precautions on the back before filling this page) --------------- 1)- ---- ΐτί 线 ^. This paper size applies to the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297 mm) -57- A7 B7___ V. Description of the invention (55) Edge detection signal. That is, as shown in the timing chart in FIG. 30, the authorization signal ENABLE is set to a low level, and the dummy delay circuits DMDL1, DMDL 2, the delay circuits CD 1, CD 2, the edge detection circuits EDI and ED2, and more The clock cycle measurement block composed of the MPX1 and the grid-shaped delay circuit SQUAD 1 stops operating; the input signal CD i η of the delay circuit CD 1, the input signal CDMi η of the delay circuit CD2, and the output of the multiplexer MPX1. The signal CDMo ut is at a low level, and based on the measurement result of the clock period before the stop, CDout is formed by the delay circuit CD 3 and the multiplexer MPX2, and is formed by the grid-shaped delay circuit SQUAD2 and the multiplexer MPX3. FDo ut can form the internal clock signal CLK 0ut through the output segment driver DRV 2. Printed by the Employees ’Cooperatives of the Shibuya Bureau of the Ministry of Economic Affairs {Please read the notes on the back before filling out this page) In Figure 2-3, the above-mentioned authorization signal ENABLE is self-refreshed by the dynamic RAM as is known. The method is formed by a timer in the chip. The timer Timer makes the above-mentioned authorization signal EN ABLE a high level at a ratio of a plurality of clock signals CLK i η once, so that the dummy delay circuits DMDL1, DMDL2, delay circuits CD1, CD2, and edge detection circuits EDI and ED2, multiplexer MPX1, and grid-shaped delay circuit SQUAD 1 constitute a clock cycle measurement block operation, and the edge detection signal is updated at this time. In the above-mentioned clock cycle measurement, since the above three clocks are required, it is necessary to make the authorization signal ENABLE a high level for the three cycles of the clock signal CLK i η. . This paper size applies Chinese national standard ('NS) Λ4 specification (210X297 mm) • 58- A7 B7 V. Description of the invention (M) so that the period due to the above-mentioned timer Timer changes with the temperature of the wafer, etc. The synchronization error < 5 B is set in a manner that is within an allowable range (less than 100 picoseconds). It can be set to a period of about 100 ms ec or more. By using the above-mentioned clock cycle measurement block intermittent operation, the grid-like delay circuit SQUAD with a large power consumption as described above can be used to maintain the synchronization error δ B at a high level. Accuracy and increase power consumption. As mentioned above, the clock synchronization of the clock synchronization circuit in this embodiment requires a minimum of 3 clock cycles. However, this is the case where there is no synchronization information before the power is turned on. When the synchronization information before the stop is valid in the clock period measurement block, the internal clock signal CLKou which is synchronized in one clock period can be obtained. . t. Printed by " -Ministry of Standards and Standards Bureau of the People's Republic of China Bureau of Printing and Printing Co., Ltd. (Please read the precautions on the back before filling in this page) Θ Figure 31 shows the time when the description is relevant to the present invention. Timing chart for other example of pulse synchronization circuit. This figure shows an example of the restart operation of the block measured by the clock cycle of the timer. When the timer signal TMout is output by the timer, the authorization signal Enable is not generated immediately, and the authorization signal Enable is changed from a low level to a high level corresponding to the falling edge of the common node COMMON. In this way, the common node COMMON can ensure a certain time range from the low level to the high level. With the high level of the above-mentioned authorization signal Enable, the clock cycle constituted by the dummy delay circuits DMDL1, DMDL2, delay circuits CD1, CD2, edge detection circuits EDI and ED2, multiplexer MPX1, and lattice delay circuit SQUAD The measurement block is activated, which delays the rising edge of the high level of the common node COMMON. The paper size of the paper is applicable to a Chinese standard (CNS) Λ4 specification (210X297 mm) • 59- Central Ministry of Economic Affairs Printed by the local consumer cooperative ¾ Α7 Β7 V. Invention Description (57) CD in, CDMi η, and CDMout are set to high levels, and the edge detection circuits ED 1 and ED 2 are synchronized. Fig. 2 shows a timing chart for explaining an example of another operation of the clock synchronization circuit according to the present invention. An example of the mode switching operation toward the reduced power mode is shown in the figure. In the reduced power mode, by the low level of the clock authorization signal CKE, the driver DRV 1 stops operating and the output common node COMM ON is fixed at the low level. With this, '+ a clock period measurement block composed of the above-mentioned pseudo delay circuits DMDL1, DMDL2, delay circuits CD1, CD2, and edge detection circuits ED1_ED2 * a multiplexer MP X 1 and a grid-like delay circuit S QUAD 1 and The output of the delay circuit CD 3 forming the internal clock signal CLKout and the output of the grid-like delay circuit S QUAD 2 are also fixed to a low level corresponding to the common node COMMON described above, and no substantial operation is performed. In short, because the delay circuit CD 3 and the grid-shaped delay circuit SQUAD2 are both constructed with a CMOS circuit, the low level of the common node COMMON corresponding to the above input is fixed to prevent the operating current from flowing. Fig. 3.3 shows a timing chart for explaining another example of the operation of the clock synchronization circuit according to the present invention. This figure shows an example of the operation of returning from the power reduction mode described above. The return of the reduced power mode \ is thus indicated by the high level of the clock authorization signal C K E described above. By this high level of the signal CKE, the internal signal I CKE is set to a high level, so that the operation of the driver DRV 1 is started. The input clock signal CLK i η supplied from the external terminal is input through the receiver RCV1 (please read the precautions on the back before filling this page) The size of the paper is applicable to the Chinese storehouse standard (rNS) Λ4 specification (210X297 Mm) -60- Printed by the Central Bureau of Standards of the Ministry of Economy Table A7 B7 V. Description of the invention (58) The output CLKO of the receiver RCV1 is transmitted to the common node COMMON by the operation of the driver DRV 1 described above. The signal of this common node COMMON is selected by the multiplexer MP X 2 as one of the delay sections of the delay circuit CD 3 by the detection signal before the stop of the latch circuit of the edge detection circuit ED 1. For this reason, the output signal CD 〇ut is transmitted to the input of the grid-like delay circuit SQUAD 2, and the output of the grid-like delay circuit S QUAtD 2 is held before the latch circuit of the edge detection circuit ED 2 is stopped. The detection signal is output through the multiplexer MPX 3. In this way, the internal clock signal CLK out ° which is delayed by one cycle can be formed in FIG. 34, showing a timing chart for explaining an example of other actions related to the clock synchronization circuit of the present invention. An example of the clock synchronization operation in the reduced power mode is shown. When the clock authorization signal C K E is set to a low-level power reduction mode, if the timer Timer forms an output signal TMo U t, the internal signal I CKE is raised to a high level correspondingly. As a result, the driver DRV1. Starts to operate, and changes the common node COMM ON in accordance with the clock signal CLK i η supplied from the external terminal in the same manner as described above. At the same time, the timer Timer receives the common node COMMON. The change to a low level causes the authorization signal Enable to change to a high level. That is to say, the internal clock signal CLKout which is delayed by one cycle is generated in the same way as above, and the above-mentioned authorization signal Enable is corresponding to a high level, so that the pseudo-delay circuits DMDL1 and DMDL2 and the delay circuit are applicable to China. House mark (CNS) Λ4 specification (210 × 297 mm) (谙 Please read the precautions on the back before filling out this page) Order -61-Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs? Wooden A7 ___B7 V. Description of the invention (59) CD1, CD2, edge detection circuits EDI and ED2, multiplexer MP X 1 and grid-shaped delay circuit S QUAD 1 constitute a clock cycle measurement block which starts to operate and consumes time. In three cycles, the edge detection signals held in the edge detection circuits EDI and ED 2 are replaced with new signals. In this way, even if the clock authorization signal CKE is set to a low level in the reduced power mode for a relatively long time, the timer can be periodically implemented by the timer to supply the ground clock signal CLK i η and the internal clock signal CLCo ut from the external terminal. Synchronization operation, as shown in the above-mentioned Figures 3 and 3, from the return to power reduction mode, the internal clock signal CL synchronized with the clock signal CLK i η supplied from the external terminal after one cycle can be obtained. Κ〇ut. Figures 3 and 5 show the waveforms in the DDR name of SDRAM. This figure shows a waveform chart corresponding to the double data rate (DDR: ------Double Data Rate) specification. In the DDR specification, an internal clock signal int. Com-CLK synchronized with the clock signal Ext · CLK supplied from an external terminal is formed so that this delay is pre-formed to internal timing in advance for the next clock Signal int. Da ta-CLK, output data DO ~ D3 with its rising and falling timing. In short, in accordance with the above-mentioned clock signal i n t · D a t a — C LK rises and falls to output the output signals D 0 to D 3. With this configuration, data can be output twice in one cycle of the clock signal, so high-speed output operation can be realized. Next ’is based on the external clock Ext. CLK to make its internal timing signal first (诮 Read the precautions on the back before filling this page)

、1T 本纸張尺度適用中國囤家標绛（C’NS ) Λ4規格（210X297公釐） -62- 五、發明説明（60 ) i n t . Da t a— CLK使輸出讀出資料者，所以在未 圖示的微處理器等，使用上述外.部時脈Ext . CLK與 該反轉的外部時脈Ext . CLKB之升起端緣，可以將 從S D R AM讀出的上述資料D 〇〜D 3取入。 在上述DDR規格，每半個時脈訊號CLK的週期進 行資料輸出的緣故，所以隨著時脈訊號C L K的頻率變高 時間範圍也變小。也就是說，藉由使用此實施例的時脈同 步電路可以高精度同步化，使用高頻率的時脈訊號C L K ，而且於DDR規格的SDRAM，使用如上述般的時間 分解能小的時脈同步電路是必需的條件。 上述動態形RAM，除了同步規格者以外同步於相同 的時脈訊號進行資料的輸出入的隨機從取記億體匯流排或 是同步連結（Sync Link)之類的進行通訊協議基礎的資料 傳送的記億體，使用相關於本發明的時脈同步電路是有利 於高精度以及高應答性等。而，設有使用了使移至前述計 時器Timer的間歇的時脈週期測定的指令，於電源打開時直 到被輸入上述'指令爲止藉由時脈週期測定區塊預先被活化 的方式使得耗電量更低化成爲可能。 於第3 6圖，顯示相關於本發明的時脈同步電路的另 一實施例的方塊圖。在此實施例，於格子狀延遲電路 S Q U A D的輸入側設開關，係以使切換通過僞延遲電路 -------- DMDL的訊號與通過輸入緩衝器（接受器）Re 的訊 號而輸入的方式進行者。被設於格子狀延遲電路 S Q U A D的各段延遲輸出的開關S，係對應於前述端緣 本紙張尺度適州中國國家標準（CNS ) Λ4規格（210X297公釐） ----------------1T-----Ίύ. (评先閱讀背面之注意事項再填寫本頁) -63- 經 滴 部 中 央 標 準 消 合 .作 社 印 掣 A7 B7 五、發明説明（61 ) 檢測電路e D。此外被設於其下部的電路，係對應於前述 多路轉換器Μ P X者》 僞延遲電路DMD L的延遲時間，係被設定爲對應在 輸入緩衝器Re c的延遲時間d 1，與在輸出驅動器 CLKDRV的延遲時間d2之延遲時間dl + d2。也就是說 ，於時脈週期測定時將開關設於上述僞延遲電路DMD L ，於上述格子狀延遲電路SQUAD進行如t CK 一（ d 1 + d 2 )般的延遲時間的設定，在被設定相關的延遲 時間之後切換開關使輸入緩衝器R e c的輸出訊號通過格 子狀延遲電路S QUAD而被輸出。結果，於格子狀延遲 電路上述延遲時間t CK — (dl + d2)係被設定者， 於輸入緩衝器R e c與輸出驅動器CLKDRV產生d 1 + d 2的延遲時間的緣故，對於從外部端子所供給的時脈 訊號ext . CLK可以形成每次僅延遲1個時脈週期 t CK的內部時脈訊號i n t . CLK。 在此實施例，可以簡單的完成電路，相反的在上述時 脈週期測定時，內部時脈訊號i n t . CLK成爲僅延遲 上述僞延遲電路DMD L的延遲時間而已的訊號，有必要 附加使該輸出無效的功能》此外，如果謀求可同步的時脈 頻率的擴張，只要如前述第2 3圖的實施例所示追加延遲 電路CD 1與端緣檢測電路ED 1與多路轉換器MPX 1 即可。 於第3 7圖，顯示相關於本發明的時脈同步電路的又 —實施例的方塊圖。在此實施例，使用測定用與輸出用2 (锖先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國1家標绛（（，NS ) Λ4規格（210X 297公釐） -64- 經滴部中央標準局貝工消费合作社印^ A7 B7 五、發明説明（62 ) 個格子狀延遲電路S QUAD。總之，與省略了前述第 2 3圖的實施例的延遲電路CD1〜CD 3等是等價的◊ 於此構成％如果謀求在測定用的格子狀延遲電路 S Q UA D之低耗電量的話，則只要將上述僞延遲電路 DMD L如前述實施例所示的使其間歇動作即可。 從上述第2 3圖等的實施例所可以得到的效果，綜合 整理如下。也就是 (1)使用複數個使傳播具有分解能比較低的時脈脈 衝的第1延遲電路與第1端緣檢測電路及第1多路轉換器 形成對應於上述較低的時間分解能延遲1個時脈的時脈訊 號，將其成爲使用具有比較高的時間分解能的第2延遲電 路與第2端緣檢測電路以及第2多路轉換器補正上述第1 延遲電路的誤差份的方式，同時作爲上述第2延遲電路作 爲具有高時間分解能的第2延遲電路，設有使彆輸入於第 1與第2輸入端子間的2個輸入訊號耦合的阻抗手段，對 於輸入訊號使其反轉形成輸出訊號的邏輯閘手段，配置於 第1訊號傳達方向與第2訊號傳達方向爲格子狀而構成的 格子狀延遲電路，於第1訊號傳達方向從第1個直到最後 一個爲止的各邏輯閘手段都將輸入時脈訊號於上述第1訊 號傳達方向依序使延遲輸入，於上述第2訊號傳達方向至 少最後一段或是前一段藉由使用從第1訊號傳達方向所被 排列的複數邏輯閘手段的輸出端子獲得輸出訊號者*可以 獲得可以高精度獲得高應答性的時脈同步電路的效果。 (2 )上述第1延遲電路，係以被構成爲同樣功能的 (請先閲讀背面之注意事項再填寫本頁) 0. Ί------------------(. J------訂-----線------------ 本紙張尺度適用中國國家標绛（C’NS ) Λ4規格（210X 297公釐） -65- 經满，部中央標準局貝工消费合作社印裝 A7 B7 五、發明説明（63 ) 第1之1、第1之2以及第1之3共3個延遲電路而構成 ，上述第1多路轉換器，係以第1之1、第1之2共2個 多路轉換器所構成，上述第2多路轉換器，係以被構成爲 同樣電路構成的第1之1與第1之2的2個延遲電路所構 成，藉由將其分別使用於時脈測定用與輸出時脈形成用， 可以持續形成輸出時脈訊號，可以獲得可使進行供同步化 之用的時脈週期測定動作的效果》 (3) 作爲構成上述第2延遲電路的格子狀延遲電路 ，藉由於上述第1訊號傳達方向呈最終段，於第2訊號傳 達方項第1段邏輯閘電路的第1輸入端子的輸入訊號，係 被供給至於第1訊號傳達方向係第1個，於第2訊號傳達 方向係第3段之邏輯閘電路的第2輸入端子者，在於第1 訊號傳達方向係第1個而於第2訊號傳達方向的第2段邏 輯閘電路的第1與第2輸入端子，被共通供給於第1及第 2訊號傳達方向爲第1個邏輯閘電路的輸出訊號，於第2 訊號傳達方向可以將最短時間延遲上述第1傳達方向的段 述份之等分的緣故，所以可獲得可以有效率地實現微小量 延遲的效果。 (4) 上述第1的1至3延遲電路，可以藉由將 CM〇 S反相器電路縱列接續而構成，可以藉簡單的構成 而得到所要的延遲時間，而且藉由使輸入訊號成爲固定準 位而獲得可以成爲低耗電量模式的效果》 (5 )於上述第1之2個延遲電路的輸入，通過第1 僞延遲電路供給輸入訊號，使上述第1僞延遲電路的輸出 本纸張尺度適用中國國家標率（CNS ) Λ4規格（210X297公釐） {诗先閲讀背面之注意事項再填寫本頁) -訂、 1T This paper size is applicable to Chinese storehouse standard (C'NS) Λ4 specification (210X297mm) -62- V. Description of the invention (60) int. Da ta— CLK makes the output read data, so The microprocessor and the like shown in the figure use the rising edge of the external clock Ext. CLK and the inverted external clock Ext. CLKB to read the data D 〇 ~ D 3 from SDR AM. Get in. In the above-mentioned DDR specification, data is output every half cycle of the clock signal CLK, so as the frequency of the clock signal C L K becomes higher, the time range becomes smaller. That is, by using the clock synchronization circuit of this embodiment, synchronization can be performed with high precision, and a high-frequency clock signal CLK is used. In addition, in a DDR-standard SDRAM, a clock synchronization circuit with a small time resolution as described above is used. Is a required condition. The above-mentioned dynamic-shaped RAM synchronizes data from the same clock signal to random input and output of data from the billion-byte bus or synchronization link (Sync Link) for data transmission based on the same clock signal except for the synchronization specifications. Remember that using a clock synchronization circuit according to the present invention is advantageous for high accuracy and high responsiveness. In addition, a command is used to measure the intermittent clock cycle, which is moved to the timer. When the power is turned on until the above-mentioned command is input, the clock cycle measurement block is activated in advance to consume power. It becomes possible to reduce the amount. Fig. 36 is a block diagram showing another embodiment of a clock synchronization circuit according to the present invention. In this embodiment, a switch is provided on the input side of the grid-shaped delay circuit SQUAD to switch between the signal passing through the pseudo delay circuit -------- DMDL and the signal passing through the input buffer (receiver) Re Way performer. The switches S provided in the delay outputs of each segment of the grid-shaped delay circuit SQUAD correspond to the aforementioned paper size of the end of the paper, the State Standard of China (CNS) Λ4 specification (210X297 mm) --------- ------- 1T ----- Ίύ. (Please read the notes on the back before filling out this page) -63- The central standard of the Ministry of Economic Affairs. Zuoshe Seal A7 B7 V. Description of the invention ( 61) Detection circuit e D. In addition, the circuit provided in the lower part thereof corresponds to the delay time of the aforementioned pseudo-delay circuit DMD L of the multiplexer MPX. The delay time is set to correspond to the delay time d 1 in the input buffer Rec and the delay time in the output buffer Rec. The delay time dl + d2 of the delay time d2 of the driver CLKDRV. In other words, the switch is set to the dummy delay circuit DMD L during the measurement of the clock period, and the delay time like t CK one (d 1 + d 2) is set in the grid-shaped delay circuit SQUAD. After the relevant delay time, the switch is switched so that the output signal of the input buffer Rec is output through the grid-like delay circuit SQUAD. As a result, the above-mentioned delay time t CK — (dl + d2) is set by the grid-shaped delay circuit, and because the input buffer R ec and the output driver CLKDRV generate a delay time of d 1 + d 2, The supplied clock signal ext. CLK can form an internal clock signal int. CLK that is delayed by only one clock cycle t CK at a time. In this embodiment, the circuit can be simply completed. On the contrary, when the above-mentioned clock cycle is measured, the internal clock signal int. Invalid function "In addition, if it is possible to expand the clock frequency that can be synchronized, it is only necessary to add the delay circuit CD 1 and the edge detection circuit ED 1 and the multiplexer MPX 1 as shown in the embodiment of FIG. 23. . Fig. 37 shows a block diagram of another embodiment of a clock synchronization circuit according to the present invention. In this example, use measurement and output 2 (锖 Please read the precautions on the back before filling this page) The size of the paper is applicable to one Chinese standard 绛 ((, NS) Λ4 specification (210X 297 mm) -64 -Printed by the Central Bureau of Standardization of the Ministry of Industry and Engineering Cooperative ^ A7 B7 V. Description of the invention (62) grid-like delay circuits S QUAD. In short, the delay circuits CD1 to CD 3 of the embodiment in which the foregoing FIG. 2 to 3 are omitted Equivalent is equivalent to this configuration%. If low power consumption of the grid-like delay circuit SQ UA D for measurement is required, the dummy delay circuit DMD L may be intermittently operated as shown in the foregoing embodiment. The effects that can be obtained from the embodiments of Figs. 2 to 3 are summarized as follows. That is, (1) the first delay circuit and the first terminal that use a plurality of clock pulses that have a relatively low resolution can be propagated. The edge detection circuit and the first multiplexer form a clock signal that can delay one clock corresponding to the above-mentioned lower time resolution, and make it a second delay circuit and a second edge detection using a relatively high time resolution Circuit and second A method for correcting the error component of the first delay circuit by the circuit converter, and as the second delay circuit as the second delay circuit with high time resolution, provided with two inputs between the first and second input terminals. The impedance means coupled to the input signal, and the logic gate means for inverting the input signal to form the output signal, are arranged in a grid-shaped delay circuit formed in a grid pattern in the first signal transmission direction and the second signal transmission direction, and in the first signal Each logic gate means from the first to the last transmits the input clock signal in the above-mentioned first signal transmission direction in order to delay the input in order, at least the last or the previous segment in the second signal transmission direction by Those who obtain the output signal by using the output terminals of the plural logic gates arranged from the first signal transmission direction * can obtain the effect of a clock synchronization circuit that can obtain a high response with high accuracy. (2) The above-mentioned first delay circuit is a system It is configured to have the same function (please read the precautions on the back before filling out this page) 0. Ί ------------------ (. J ------ Order ----- line ----- ------- This paper size applies to China's national standard (C'NS) Λ4 specification (210X 297 mm) -65- Jingman, printed by A7 B7, Shellfish Consumer Cooperative of the Central Bureau of Standards (63) Three delay circuits including 1-1, 1-2, and 1-3 are configured. The above-mentioned first multiplexer is based on two multiplexes of 1-1, 1-2 The second multiplexer is composed of two delay circuits of the first 1 and the first 2 configured as the same circuit, and is used for clock measurement and For output clock formation, the output clock signal can be continuously formed, and the effect of clock cycle measurement operation for synchronization can be obtained. (3) As a grid-like delay circuit constituting the second delay circuit, Since the above-mentioned first signal transmission direction is in the final stage, the input signal of the first input terminal of the logic gate circuit in the first signal transmission stage of the second signal transmission party is supplied to the first signal transmission direction which is the first and the second signal transmission direction. The signal transmission direction is the second input terminal of the logic gate circuit in the third paragraph, which is the first signal The reach direction is the first and the second input terminal of the second stage logic gate circuit in the second signal transmission direction, and is commonly supplied to the output of the first logic gate circuit in the first and second signal transmission directions. Since the shortest time can be delayed in the second signal transmission direction by the equal division of the paragraphs in the first transmission direction, a small delay can be efficiently achieved. (4) The first 1 to 3 delay circuits described above can be formed by connecting the CMOS inverter circuits in series, and the desired delay time can be obtained by a simple configuration, and the input signal can be fixed. (5) In the input of the first two delay circuits mentioned above, the input signal is supplied through the first pseudo delay circuit, so that the output of the first pseudo delay circuit is output. Zhang scale is applicable to China National Standard Rate (CNS) Λ4 specification (210X297 mm) {Read the notes on the back of the poem before filling this page)-Order

-66- 經濟部中央標準局兵-T-消费合-.-it社印製 A7 _ B7_____ 五、發明説明（64 ) 訊號從上述第2延遲電路被輸出的延遲訊號成爲在指定段 數以後的方式進行調整，通過上述第2僞延遲電路對於上 述第1之Ί個延遲電路輸入供給，藉此可以獲得可使格子 狀延遲電路在安定的動作區域動作的效果。 (6) 上述第1與第2端緣檢測電路分別於輸出部設 有閂鎖電路，藉由使定的控制訊號使其間歇地處於動作狀 態與非動作狀態，在非動作狀態藉由使輸出被保持於上述 閂鎖電路的檢測訊號可得所謂可以使時脈週期測定部的耗 電量大幅降低的效果。 (7) 使從外部端子被供給的時脈訊號通過輸入緩衝 器電路，及具有對應於輸出段驅動器的延遲電路的延遲電 路而輸入，通過了上述第2多路轉換器的輸出訊號通過輸 出段驅動器而使其輸出，藉此可以獲得所謂可使這些的輸 入電路以及驅動器的延遲份也都包括形成同步化的內部時 脈訊號的效果。 (8) 藉由將上述指定的控制訊號藉由計時器電路而 以一定的週期產生，可獲得所謂可以具有必要的時間間隔 自動持續進行時脈週期測定，大幅降低耗電量的效果》 (9) 使被從外部端子供給的時脈訊號供給至輸入緩 衝器電路，及使通過上述輸入緩衝器的時脈訊號延遲對應 於上述輸入緩衝器與輸出段驅動器的延遲時間的延遲時間 的僞延遲電路而被形成的延遲訊號供給至格子狀延遲電路 ，比較上述格子狀延遲電路的各段的延遲訊號，與通過輸 入緩衝器被輸入的時脈脈衝的延遲1個時脈的時脈端緣， 本紙張尺度適用中國國家標华（CNS M4規格（210X297公釐） (请先閲讀背面之注意事項再填寫本頁) • - - - i II - - - -I - - I I- - - »^1* -----"ST--^11|_線---- 〇 -67- 經 濟 部 中 央 標 羋 局 貝 X. 消 合 -作 社 印 % A7 _____._B7_ 五、發明説明（65 ) 檢測出兩端緣的時間一致將該檢測結果保持於閂鎖，將上 述輸入緩衝器電路的輸出供給至上述格子狀延遲電路的輸 入通過上述輸出段驅動器使輸出時脈訊號，可獲得所謂可 以簡單的構成進行對應於上述格子狀延遲'電路的時間分解 能的高精度同步化動作的效果。 (1 0 )使被從外部端子供給的時脈訊號供給至輸入 緩衝器電路，及使通過上述輸入緩衝器的時脈訊號延遲對 應於上述輸入緩衝器與輸出段驅動器的延遲時間的延遲時 間的僞延遲電路而被形成的延遲訊號供給至格子狀延遲電 路，比較上述格子狀延遲電路的各段的延遲訊號，與通過 輸入緩衝器被輸入的時脈脈衝的延遲1個時脈的時脈端緣 ，檢測出兩端緣的時間一致'於與上述同樣構成的其他格 子狀延遲電路的輸入供給上述輸入緩衝器電路的輸出，藉 由上述檢測結果控制多路轉換器，從上述其他的格子狀延 遲電路取出延遲訊號，通過上述輸出段驅動器使輸出時脈 訊號，藉此可獲得所謂可以持續同時進行時脈週期測定與 輸出動作獲得對應於上述格子狀延遲電路的時間分解能的 高精度輸出時脈訊號的效果。 (11)具備於複數字線與複數位元線的交點被以矩 陣狀配置有記憶體細胞而成的記億體陣列以及其選擇電路 ，及接受被由外部端子供給的控制訊號與時脈訊號，設有 依照上述控制訊號而使產生對應逾時脈訊號的內部時脈訊 號的時脈同步電路，依照該被同步化的內部時脈訊號使輸 出上述記憶體細胞的讀出訊號的輸出入電路的半導體積體 --------i)---------ΐτ------「線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210 X 297公釐） -68 - 經濟部中央標萆局員工消费合咻社印製 A7 B7 五、發明説明（66 ) 電路裝置，藉由使用上述（1 )至（8 )的格子狀延遲電 路的時脈同步電路’而可以獲得.所謂可以高頻率進行記憶 體動作，實現待機時的低耗電與高速復歸的效果。 以上基於由本發明的發明人所完成的實施例而具體說 明，但本發明並不以前述實施例爲限，在不逸脫其要旨的 範圍內當然可以進行種種的變更。例如，於大規模積體電 路，在各電路區快設有時脈同步電路者，係進行各電路區 快的內部時脈訊號的相互同步化者，可以省略接受來自外 部端子的時脈訊號的輸入緩衝器。於第1圖的實施例，也 可以構成爲如第1 8圖的實施例所示的同樣的延遲電路， 時間上分開爲時脈週期測定與時脈訊號的輸出動作來使用 而構成亦可。本發明相關的時脈同步電路，除了如 S D RAM等之類的記憶體以外，可以使用於微處理器， 或是構成周邊電路的各種半導體積體電路裝置。 若要簡單說明被揭示於本發明的發明中具.代表性者所 可獲得的效果，則如下述，亦即， 使用複數個使傳播具有分解能比較低的時脈脈衝的第 1延遲電路與第1端緣檢測電路及第1多路轉換器形成對 應於上述較低的時間分解能延遲1個時脈的時脈訊號，將 其成爲使用具有比較高的時間分解能的第2延遲電路與第 2端緣檢測電路以及第2多路轉換器補正上述第1延遲電 路的誤差份的方式，同時作爲上述第2延遲電路作爲1有 高時間分解能的第2延遲fL路，設有使彆輸入於第1與第 ............— -....------ 2輸入端子間的2個輸入訊號耦合的砠抗手段，對於輸入 (請先閲讀背面之注意事項再填寫本頁) 訂 \線| β 本紙張尺度適用中國囤家標华（CNS ) Λ4規格（2】0Χ297公釐） -69 - 經濟部中决標準局兵工消費合作社印？木 A7 B7 五、發明説明（67) 訊號使其反轉形成輸出訊號的邏輯閘手段，配置於第1訊 號傳達方向與第2訊號傳達方向爲格子狀而構成的格子狀 延遲電路：，於第1訊號傳達方向從第1個直到最後一個爲 止的各邏輯閘手段都將輸入時脈訊號於上述第1訊號傳達 方向依序使延遲輸入，於上述第2訊號傳達方向至少最後 一段或是前一段藉由使用從第1訊號傳達方向所被排列的 複數邏輯閘手段的輸出端子獲得輸出訊號者，可以獲得可 以高精度獲得高應答性的時脈同步電路的效果。 圖面之簡單說明 第1圖係本發明相關之格子狀延遲電路之一實施例之 電路圖。 第2圖係本發明相關之格子狀延遲電路之另一實施例 之電路圖。 第3圖A及B係供說明本發明相關之格子狀延遲電路 的動作之用的藉由電腦模擬所求出的特性圖。 第4圖A、B、C、D及E係顯示本發明相關的格子 狀延遲電路所使用的延遲要素的另一實施例之電路圖。 第5圖A及B，係供說明本發明相關之格子狀延遲電 路之耦合手段的功能之用的特性圖。 第6圖，係供說明本發明相關之格子狀延遲電路之耦 合手段的功能之用的特性圖。 第7圖，係供說明本發明相關之格子狀延遲電路的動 作之用的波形圖。 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適K!中國國家標啤（HMS ) Λ4現格（210X297公釐） •70- A7 B7 五、發明説明（68 ) 第.8圖係顯市本發明相關之使用上述格子狀延遲電路 之時脈產生電路之一實施例之方塊圖》 第9圈係顯不第8圖所不之解碼器電路的一實施例之 電路圖。 第1.0圖係顯兩第8圖的解碼器電路之一實施例之電 路圖。 . 第11圖係顯示第8圖的多路轉換器之一實施例之電 路圖。 第12圖係顯示第8圖的時脈計數電路之一實施例之 電路圖。 第13圖係顯示使用本發明相關之上述格子狀延遲電 路的時脈產生電路之另一實施例之方塊圖。 第1 4圖係顯不第1 3圖之延遲要素之一實施例支店 路途。 第15圖係顯示被適用本發明的半導體記憶體系統之 一實施例之方塊圖。 經滴部中决標準局兵工消费合#社印製 (請先閲讀背面之注意事項再填寫本頁) 第16圖係供說明第15圖的半導體記億體系統之被 設於DRAM側的時脈產生電路的動作之用的計時圖v 第17圖係顯示使甩相關於本發明的延遲電路的DL L電路之一實施例的方塊圖。 第18圖係供說明第17塗得DLL電路的動作之用 的計時圖。 第1 9圖係顯示相關於本發明之格子狀延遲電路之一 實施例的配置圖。 本紙張尺度適用中國囷家標啤（（，阳）厶4#見格（2〗0'/297公釐） -71 - 經 濟 部 中 央 標 準 貝 X 消 费 合 社 印 製 A7 B7 五、發明説明（69 ) 第2 0圖係顯示被適用本發明之同步DRAM之一實 施例之全體方塊圖。 第2 Ί圖係顯示相關於本發明的格子狀震盪電路的一 實施例之方塊圖。 第2 2圖係供說明相關於本發明之格子狀震盪電路的 動作之用的波形圖。 第2 3圖係顯示相關於本發明的時脈同步電路的一實 施例的方塊圖。 第2 4圖係供說明第2 3圖的時脈同步電路的動作之 用的計時圖。 第2 5圖係顯示第2 3圖的延遲電路CD 1的一實施 例之電路圖》 第2 6圖係顯示對應於第2 3圖的延遲電路C D 1的 端緣檢測電路E D 1的一實施例的電路圖。 第2 7圖係顯示對應於第2 3圖的格子狀延遲電路 S QUAD 1的端緣檢測電路ED 2的一實施例之電路圖 第2 8圖係顯示第2 3圖之多路轉換器MPX 2的一 實施例之電路圖。 第2 9圖係供說明被使用於本發明的格子狀延遲電路 的動作之用的波形圖。 第3 0掘係供說明相關於本發明的時脈同步電路的動 作之一例之用的計時圖。 第3 1圖係供說明相關於本發明的時脈同步電路的其 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2]0X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 ® •72- 經逆-部中央標準局只工消费合光社印？木 A7 B7 五、發明説明（70 ) 他動作之一例之用的計時圖。 第3 2圖係供說明相關於本發明的時脈同步電路的其 他動作之^例之用的計時圖。 第3 3圖係供說明相關於本發明的時脈同步電路的其 他動作之一例之用的計時圖。 第3 4圖係供說明相關於本發明的時脈同步電路的其 他動作之一例之用的計時圖。 第3 5圖係供說明第2 0圖的SDRAM的動作之一 例之用的計時圖。 第36圖係顯示相關於本發明的時脈同步電路的另一 實施例的方塊圖。 - 第3 7圖係顯示相關於本發明的時脈同步電路的又一 實施例的方塊圖》 (请先閲讀背面之注意事項再填寫本頁)-66- Printed by the Central Standards Bureau of the Ministry of Economic Affairs-T-Consumption -.- it A7 _ B7_____ V. Description of Invention (64) The delay signal output from the second delay circuit described above becomes after the specified number of segments The method is adjusted, and the second dummy delay circuit is input and supplied to the first delay circuit, thereby obtaining the effect that the grid-shaped delay circuit can be operated in a stable operation region. (6) The above-mentioned first and second edge detection circuits are provided with a latch circuit at the output section, respectively, so that a predetermined control signal makes it intermittently in an operating state and a non-acting state. The detection signal held in the latch circuit has the effect of significantly reducing the power consumption of the clock cycle measurement unit. (7) The clock signal supplied from the external terminal is input through the input buffer circuit and the delay circuit having a delay circuit corresponding to the output stage driver, and the output signal passing through the second multiplexer passes through the output stage. By driving the driver to output it, it is possible to obtain the effect that the input circuits and the delay of the driver can also include a synchronized internal clock signal. (8) By generating the specified control signal at a certain period by a timer circuit, the so-called clock cycle measurement can be automatically and continuously performed with the necessary time interval to significantly reduce the power consumption effect "(9 A pseudo-delay circuit that delays the clock signal supplied from the external terminal to the input buffer circuit and delays the clock signal that passes through the input buffer corresponding to the delay time of the input buffer and the output segment driver. The formed delay signal is supplied to a grid-like delay circuit, and the delay signal of each segment of the grid-like delay circuit is compared with the clock edge of a clock delayed by a clock pulse input through an input buffer. Paper size applies to China National Standard (CNS M4 specification (210X297 mm) (Please read the notes on the back before filling out this page) •---i II----I--I I---»^ 1 * ----- " ST-^ 11 | _line ---- 〇-67- Central Bureau of Standards, Ministry of Economic Affairs, X. Digestion-Printed by the Society% A7 _____._ B7_ V. Description of Invention (65 ) Detecting that the time at both edges is consistent The detection result is held in a latch, and the output of the input buffer circuit is supplied to the input of the grid-like delay circuit. The output segment driver is used to output the clock signal, so that a so-called simple structure can be obtained to respond to the grid-like delay. 'The effect of the high-precision synchronization operation of the time resolution of the circuit. (10) The clock signal supplied from the external terminal is supplied to the input buffer circuit, and the clock signal passing through the input buffer is delayed corresponding to the above. The delay signal formed by the dummy delay circuit of the delay time of the delay time of the input buffer and the output segment driver is supplied to the lattice delay circuit, and the delay signal of each segment of the lattice delay circuit is compared with the delay signal input through the input buffer. The clock pulse is delayed by the clock edge of one clock, and it is detected that the timing of the two edges is consistent. The input to the input buffer circuit is input to the input of the other grid-like delay circuit having the same structure as above. The detection result controls the multiplexer and takes out the delay from the other grid-like delay circuits described above. The clock signal is output by the output segment driver, thereby obtaining the effect that the so-called clock cycle measurement and output operation can be continuously performed simultaneously to obtain a high-accuracy output clock signal corresponding to the time-resolved energy of the grid-shaped delay circuit. (11) A memory array and a selection circuit including memory cells in which matrix cells are arranged at the intersections of complex digital lines and complex bit lines, and receive control signals and clock signals supplied from external terminals A clock synchronization circuit for generating an internal clock signal corresponding to a clock signal in accordance with the control signal is provided, and an input / output circuit for outputting the readout signal of the memory cell according to the synchronized internal clock signal Semiconductor assembly -------- i) --------- ΐτ ------ "Wire (please read the precautions on the back before filling this page) This paper is applicable to China National Standard (CNS) Λ4 specification (210 X 297 mm) -68-Printed by A7 B7, Consumers' Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (66) Circuit device, by using the above (1) to Case of (8) The clock synchronization circuit of the sub-delay circuit can be obtained. The so-called memory operation can be performed at a high frequency, and the effects of low power consumption and high-speed return during standby can be achieved. The above is specifically described based on the embodiment completed by the inventor of the present invention, but the present invention is not limited to the foregoing embodiment, and various changes can be made without departing from the scope of the invention. For example, in a large-scale integrated circuit, those who have clock synchronization circuits in each circuit area are those who synchronize the internal clock signals in each circuit area, and can omit receiving clock signals from external terminals. Input buffer. The embodiment shown in Fig. 1 may be configured as the same delay circuit as shown in the embodiment shown in Fig. 18, and may be divided into a clock period measurement and a clock signal output operation in time. The clock synchronization circuit related to the present invention can be used in a microprocessor or various semiconductor integrated circuit devices constituting peripheral circuits, in addition to a memory such as an SD memory. To briefly explain the effects obtained by the representative of the invention disclosed in the present invention, as follows, that is, the first delay circuit and the first delay circuit using a plurality of clock pulses which have a relatively low resolution can be used for propagation. The one-edge detection circuit and the first multiplexer form a clock signal that can delay one clock corresponding to the above-mentioned lower time resolution, and use it as a second delay circuit and a second terminal with a relatively high time resolution. The edge detection circuit and the second multiplexer correct the error portion of the first delay circuit, and at the same time, the second delay circuit is provided as a second delay fL circuit having a high time resolution capability, and a separate input is provided at the first Reactance means coupled with the 2 input signals between the 2nd ............- -....------ 2 input terminals, for input (please read the note on the back first) Please fill in this page again for the items) Order \ line | β This paper size is applicable to Chinese storehouse standard Chinese (CNS) Λ4 specification (2) 0 × 297 mm) -69-Printed by the Military Industry Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs? Wooden A7 B7 V. Description of the invention (67) The logic gate means for reversing the signal to form an output signal is arranged in a grid-like delay circuit composed of a grid in the first signal transmission direction and a second signal transmission direction: Each logic gate means from the first to the last signal transmission direction will input the clock signal in the first signal transmission direction in order to make the delay input, at least the last or the previous section in the second signal transmission direction. By using an output terminal of a plurality of logic gates arranged from the first signal transmission direction to obtain an output signal, it is possible to obtain an effect of a clock synchronization circuit that can obtain a high response with high accuracy. Brief Description of the Drawings Fig. 1 is a circuit diagram of an embodiment of a grid-like delay circuit according to the present invention. Fig. 2 is a circuit diagram of another embodiment of a grid-like delay circuit according to the present invention. 3 and 3 are characteristic diagrams obtained by computer simulation for explaining the operation of the grid-like delay circuit according to the present invention. Fig. 4A, B, C, D, and E are circuit diagrams showing another embodiment of delay elements used in the grid-like delay circuit according to the present invention. Figures 5 and 5 are characteristic diagrams for explaining the function of the coupling means of the grid-like delay circuit according to the present invention. Fig. 6 is a characteristic diagram for explaining the function of the coupling means of the lattice delay circuit according to the present invention. Fig. 7 is a waveform diagram for explaining the operation of the grid-like delay circuit according to the present invention. (Please read the notes on the back before filling this page) The size of the paper is suitable for K! China National Standard Beer (HMS) Λ4 now (210X297 mm) • 70- A7 B7 V. Description of the invention (68) No. 8 The diagram is a block diagram of an embodiment of the clock generating circuit using the above-mentioned grid-like delay circuit according to the present invention. The 9th circle is a circuit diagram of an embodiment of the decoder circuit shown in FIG. Fig. 1.0 is a circuit diagram showing one embodiment of the decoder circuit of Fig. 8 and Fig. 8 respectively. Fig. 11 is a circuit diagram showing an embodiment of the multiplexer of Fig. 8. Fig. 12 is a circuit diagram showing an embodiment of the clock counting circuit of Fig. 8. Fig. 13 is a block diagram showing another embodiment of a clock generating circuit using the above-mentioned grid-like delay circuit according to the present invention. FIG. 14 shows an example of a branch road of one of the delay elements of FIG. 13. Fig. 15 is a block diagram showing an embodiment of a semiconductor memory system to which the present invention is applied. Printed by the Ministry of Standards and Industry ’s Consumption Co., Ltd. (Please read the precautions on the back before filling out this page) Figure 16 is for explaining the semiconductor memory system of Figure 15 which is set on the DRAM side. Timing chart for the operation of the clock generating circuit v. FIG. 17 is a block diagram showing an embodiment of a DLL circuit related to the delay circuit of the present invention. Fig. 18 is a timing chart for explaining the operation of the 17th DLL circuit. Fig. 19 is a layout diagram showing an embodiment of a grid-like delay circuit according to the present invention. This paper size is applicable to China's standard beer ((, 阳) 厶 4 # see grid (2〗 0 '/ 297 mm) -71-Central Standard Shell of the Ministry of Economic Affairs X Consumer Co., Ltd. Printing A7 B7 V. Description of the invention ( 69) Figure 20 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied. Figure 2 is a block diagram showing an embodiment of a grid-shaped oscillator circuit related to the present invention. Figure 2 2 The figure is a waveform diagram for explaining the operation of the grid-shaped oscillator circuit related to the present invention. Figures 23 and 3 are block diagrams showing an embodiment of the clock synchronization circuit related to the present invention. Figures 2 to 4 are provided for Timing diagrams for explaining the operation of the clock synchronization circuit of Figs. 2 to 3. Figs. 2 to 5 are circuit diagrams showing an embodiment of the delay circuit CD 1 of Figs. 2 to 3; 3 is a circuit diagram of an embodiment of the edge detection circuit ED1 of the delay circuit CD 1 of FIG. 3. FIGS. 2 to 7 show one of the edge detection circuits ED 2 of the grid-shaped delay circuit S QUAD 1 corresponding to FIG. The circuit diagram of the embodiment No. 28 shows the multiplexer MPX 2 of No. 23 The circuit diagram of the embodiment. Figs. 2 to 9 are waveform diagrams for explaining the operation of the grid-shaped delay circuit used in the present invention. Fig. 30 is a diagram for explaining an example of the operation of the clock synchronization circuit according to the present invention. Timing chart for use. Figure 31 is for explaining the paper size of the clock synchronization circuit related to the present invention is applicable to the Chinese National Standard (CNS) Λ4 specification (2) 0X297 mm) (Please read the note on the back first Please fill in this page again) Order ® • 72- Economic and Reverse-Ministry of Standards and Technology only consumes the printing of Heguangsha? Wood A7 B7 V. Description of Invention (70) Timing chart for an example of other actions. Figure 3 2 It is a timing chart for explaining one example of other operations related to the clock synchronization circuit of the present invention. Fig. 33 is a timing chart for explaining one example of other operations related to the clock synchronization circuit of the present invention. Fig. 34 is a timing chart for explaining an example of another operation of the clock synchronization circuit according to the present invention. Fig. 35 is a timing chart for explaining an example of the operation of the SDRAM of Fig. 20 Fig. 36 is a diagram showing Pulse synchronization circuit block diagram of another embodiment - based on a block diagram of FIG. 37 is a further embodiment of the clock synchronization circuit of the present invention displays "(Read Notes on the back and then fill the page)

符 號 說明 1 0 模式暫存器 2 0 指令解碼器 3 0 計時產生器 4 0 時脈緩衝器 5 0 同步時脈產 生 器 2 0 5 行位址緩 衝 器 2 0 6 列位址緩 衝 器 2 0 7 行位址計數 器 2 0 8 刷新計數 器 本紙张尺度適用中國囤家'標準（CNS ) Λ4規格（210X297公釐） -73- A7 B7 2 13 經¾-部中央標準局貝工消费合作社印？木 五、發明説明（71 ) 閂鎖暫存器 (請先閱讀背面之注意事項再填寫本頁) 訂 ::線· 本紙張尺度適用中國國家標华（（’NS ) Λ4規格（210X297公釐） -74-Explanation of symbols 1 0 Mode register 2 0 Instruction decoder 3 0 Timing generator 4 0 Clock buffer 5 0 Synchronous clock generator 2 0 5 Row address buffer 2 0 6 Column address buffer 2 0 7 Row address counter 2 0 8 Refresh counter This paper size is applicable to the Chinese storehouse's standard (CNS) Λ4 specification (210X297 mm) -73- A7 B7 2 13 Printed by the Beige Consumer Cooperative of the Central Bureau of Standards? Wooden V. Description of the invention (71) Latch register (please read the precautions on the back before filling this page) Order :: line · This paper size applies to China National Standard (('NS) Λ4 specification (210X297 mm) ) -74-

Claims (1)

經濟部中央標準局員工消費合.作社印製 A8 B8 C8 _ D8__ 六、申請專利範圍 1 種半導體積體電路裝置，其特徵爲： 係具備一種兔遲電」路的半導體積體電路裝置，該延遲 電路係具有： 接受從第1輸入訊號開始直到依序延遲的第Μ (M = 2、3、4、…）輸入訊號爲止的Μ條訊號線，及 從對應於上述第1輸入訊號的第1邏輯閘電路群開始 直到對應於上述第Μ輸入訊號的第Μ邏輯閘電路群爲止的 Μ個邏輯_閘電路群的延遲電路； 、各邏輯閘電路群具有從第1邏輯蘭電路開始直到第Ν (Ν = 3、4、5、…）邏輯閘電路爲止的Ν個邏輯閘電 劈’上述邏輯閘電路分別具有第1輸入端子、第2輸入端 子以及輸出端子， 於上述邏輯閘電路的第1輸入端子與第2輸入端子之 間分別設有耦含元件， 於各邏輯閘電路群，從上述第1邏輯閘電路開始直到 第Ν邏輯閘電路爲止透過上述輸出端子與上述第1輸入端 子被縱向建， 上述μ條訊號線分別被連接至對應的邏.輯閘電路群的 第1邏輯閘電路的第1輸入端子， 從上述第1邏輯閘電路群開始於第Μ-1邏輯閘電路 群之每一個，第L (L=l、2、3、…）邏輯閘電路的 第1輸入端子，被連接至下一個邏輯閘電路群的第L邏輯 閘電路的第2輸入端子，， 上述第Μ邏輯閘電路群的指定邏輯閘電路的第1輸入 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公嫠）-75 - (请先閲讀背面之注意事項再填寫本頁) .订-----線丨 經濟部中央標準局員工消費合作社印裝 A8 B8 C8 D8 __ 六、申請專利範圍 端子係被連接於上述第1邏輯閘電路群的指定邏輯閘電路 的第2輸入端子， '-從複數之上述第N邏輯閘電路的上述輸出端子獲得依 序延遲的輸出訊號的上述延遲電路的半導體積體電路裝置 〇 2. 如申請專利範圍第1項之半導體積體電路裝置， 其中，上述耦合元件係含有電容元件者。 3. 如申請專利範圍第1項之半導體積體電路裝置， 其中，上述親合元件係含有電阻元件者。 4. 如申請專利範圍第1項之半導體積體電路裝置， 其中，上述邏輯閛電路係NA ND閘電路。 5·如申請專利範圍第4項之半導體積體電路裝置， 其中，上述耦合元件係含有電容元件者。 6.如申請專利範圍第1項之半導體積體電路裝置， 其中，上述邏輯閘電路係NOR閘電路。 7··如申請專利範圍第1項之半導體積體電路裝置， 其中’上述邏輯閘電路係由第1反相器_( inverter )電路與 第2反相器電路所構成，上述第1反相器電路的輸出端子 與上述第2反相器電路的輸出端子係被共通連接的· 8. 如申請專利範圍第1項之半導體積體電路裝置， 其中’上述第Μ邏輯閘電路群的第L (L = l、2、3、 …）邏輯閘電路的第1輸入端子係被連接於上述第1邏輯 閘電路群的第L + 2邏輯閘電路的第2輸入端子。 9. 如申請專利範圍第8項之半導體積體電路裝置， 本紙張尺度適用中國固家梯準（CNS ) A4規格（210X297公釐）-76 - (請先閲讀背面之注意事項再填寫本頁) 訂 B8 C8 D8 六、申請專利範圍 其中，以各邏輯閘電路群的第L邏輯閘電路所構成的第1 電路列與以第L + 2邏輯閘電路所構成的第2電路列，係 沿著半導體基板上的一條直線，而且，是以第Μ邏輯閘電 路群的第L邏輯閘電路與第1邏輯閘電路群的第L + 2邏 輯閘電路鄰接的方式被配置， 以各邏輯閘電路群的第L + 1邏輯閘電路群所構成的 第3電路列，其前半部與後半部係分別沿著上述第1電路 列的後半部與上述第2電路列的前半部而被配置的。 1 〇 .—種半導體積體電路裝置，其特徵爲： 係具備一種延遲電路的半導體積體電路裝置，該延遲 電路係具有： — . 經濟部中央標準局負工消費合作社印製 (請先《讀背面之注意事項再填寫本頁) 形成從第1輸入時脈訊號開始直到依序延遲的第Μ ( Μ=2、3、4、…）輸入時脈訊號爲止的輸入電路，及 從對應於上述第1輸入時脈訊號的第1邏輯閘電路群 開始直到對應於上述第Μ輸入時脈訊號的第Μ邏輯閘電路 群爲止的Μ個邏輯閘電路群，也從自第1輸入時脈訊號開 始直到第Μ輸入時脈訊號爲止的各延遲量，獲得以均等的 延遲量依序延遲的複數輸出時脈訊號的延遲電路； 各邏輯閫電路群具有從第1邏輯閘電路開始直到第Ν (Ν = 3、4、5、…）邏輯閘電路爲止的Ν個邏輯閘電 路，上述邏輯閘電路分別具有第1輸入端子、第2輸入端 子以及輸出端子， 、於各邏輯閘電路群，從上述第1邏輯閘電路開始直到 第Ν邏輯閘電路爲止透過上述輸出端子與上述第1輸入端 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -77- A8 B8 C8 D8 六、申請專利範圍 子被縱向連續連接， 從上述第1輸入時脈訊號開始第Μ輸入時脈訊號分別 被連接於對應的邏輯閘電路群的第1邏輯閘電路的第1輸 入端子， 從上述第1邏輯閘電路群開始於第Μ—1邏輯閘電路 群之每一個，第L (L=l、2、3、…）邏輯閘電路的 第1輸入端子，被連接至下一個邏輯閘電路群的第L邏輯 閘電路的第2輸入端子， 上述第Μ邏輯閘電路群的指定邏輯閘電路的第1輸入 端子係被連接於上述第1邏輯閘電路群的指定邏輯閘電路 的第2輸入端子， - 從複數之上述第Ν邏輯閘電路的上述輸出端子獲得上 述複數輸出時脈訊號的上述延遲電路的半導體積體電路裝 置。 經濟部中央標準局貝工消費合作社印裂 {請先Η讀背面之注意事項再填寫本頁) 11 .如申請專利範圍第10項之半導體積體電路裝 置，其中，上述輸入電路，具備接受基準時脈訊號形成從 上述第1輸入畤脈訊號開始直到依序延遲的第Μ (Μ〒2 、3、4、…）輸入時脈訊號爲止的複數單位電路，分別 被包含於前述複數單位電路的電路元件的特性依序不同》 12.如申請專利範圍第11項之半導體積體電路裝 置，其中，從上述第1輸入時脈訊號開始依序延遲的第Μ 輸入時脈訊號，係被形成於上述基準時脈訊號的1個週期 內。 1 3 . —種半導體積體電路裝置，其特徵爲具有： 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X297公釐） -78- 六、申請專利範圍 具備接受基準時脈訊號形成從第1輸入時脈訊號開始 直到依序延遲的第Μ (M=2、3、4、…）輸入時脈訊 號爲止的複數單位電路，對應於分別被包含於前述複數單 位電路的電路元件的特性依序不同的情形，於上述基準時 脈訊號的1個週期內形成從上述第1輸入時脈訊號開始直 到第Μ輸入時脈訊號爲止的第1電路，及 接受從上述第1輸入時脈訊號開始直到上述第Μ時脈 訊號爲止，也從自上述第1輸入時脈訊號開始直到第Μ輸 入時脈訊號爲止的各延遲量獲得以均等的延遲量依序延遲 的複數輸出時脈訊號的第2電路； 上述第2電路，係具備對應於Μ行ΧΝ列（Ν=3、 4、…）的複數邏輯閘電路，以使訊號被傳達於前述複數 邏輯閘電路的行方向與列方向的方式被配線的延遲電路。 •1 4 .如申請專利範圍第1 3項之半導體積體電路裝 置，其中， 經濟部中央標準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 上述第2電路係具有從對應於上述第1輸入時脈訊號 的第1邏輯閘電路群開始直到對應於上述第Μ輸入時脈訊 號的第Μ邏輯閘電路群爲止的Μ個邏輯閘電路群， ^ '各邏輯閘電路群係具有從第1邏輯閘電路開始直到第 Ν (Ν=3、4、5、…）邏輯閘電路爲止的Ν個邏輯閘 電路，上述邏輯閘電路分別具有第1輸入端子、第2輸入 端子以及輸出端子， 、於各邏輯閘電路群，從上述第1邏輯閘電路開始直到 第Ν邏輯閘電路爲止透過上述輸出端子與上述第1輸入端 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210Χ297公釐） -79- Α8 Β8 C8 D8 經濟部中央揉準局貝工消費合作社印製 六、申請專利範圍 子被縱向連續連接， 從上述第1輸入時脈訊號開始第Μ輸入時脈訊號分別 被連接於對應的邏輯閘電路群的第1邏輯閘電路的第1輸 入端子， 從上述第1邏輯閘電路群開始於第Μ - 1邏輯閘電路 群之每一個，第L (L=l、2、3、…）邏輯閘電路的 第1輸入端子，被連接至下一個邏輯閘電路群的第L邏輯 閘電路的第2輸入端子，' '上述第Μ邏輯閘電路群的指定邏輯閘電路的第1輸入 端子係被連接於上述第1邏輯閘電路群的指定邏輯閘電路 的第2輸入端子， - 從複數之上述第Ν邏輯閘電路的上述輸出端子獲得上 述複數輸出時脈訊號的半導體積體電路裝置。 1 5 種半導體積體電路裝置，其特徵爲：具有延 遲電路，該延遲電路係 -具備：複數個使被輸入至第1與第2輸入端子的2個 輸入訊號耦合的阻抗元件被設於上述第1與第2輸入端子 間，因應被供給於上述第1與第2輸入端子的輸入訊號形 成輸出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀的延遲電路，. 於第1訊號傳達方向呈第1個以外的第Κ個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第Κ個， (請先U讀背面之注意事項再填寫本頁) \/ tr·. 訂· -tec. 本紙張尺度適用中國國家揉丰（CNS ) A4规格（210X297公釐j -80- A8 Β8 C8 D8 六、申請專利範圍 A第2訊號傳達方向呈第L一1段的邏輯閘電路的輸出訊 號或是在第1段邏輯閘電路被供給輸入時脈訊號，於上述 邏輯閘電路手段K L的第2輸入端子在第1訊號傳達方向 呈前1個之第K_ 1個，在第2傳達方向呈相同的第L段 的被供給至邏輯閘電路之第1輸入端子的輸入訊號被供給 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其更呈 前段的邏輯閘電路，被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的邏輯閘電路之第1與第2輸入端子，通過 構成緩衝器電路的輸入電路被供給時脈訊號，於第1訊號 傳達方向被供給至從第2個直到最後一個爲止的各邏輯閘 電路的第1輸入端子的上述輸入時脈訊號，係藉由構成上 述緩衝器電路的輸入電路於上述第1訊號傳達方向依序被 延遲者， 於上述第2訊號傳達方向係至少第複數段，從在第1 訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲得輸 出訊號之上述延遲電路。 16·如申請專利範圍第15項之半導體積體電路裝 置，其中，上述阻抗元件係由電容元件所構成。 本紙張尺度逍用中國國家標準（CNS ) A4規格（210X297公釐） -81 - 經濟部中央標準局員工消費合作社印装 B8 C8 D8 _ ' 六、申請專利範園 17. 如申請專利範圍第15項之半導體積體電路裝 置，其中，上述阻抗元件係由電阻元件所構成。 18. 如申請專利範圍第15項之半導體積體電路裝 置，其中，上述邏輯閘電路係NAND閘電路。 19. 如申請專利範圍第15項之半導體積體電路裝 置，其中，上述邏輯閘電路係N 0 R閘電路。 2 0 .如申請專利範圍第1 5項之半導體積體電路裝 置，其中，上述邏輯閘電路係共通連接2個反相器電路的 輸出端子者。 21.如申請專利範圍第1項之半導體積體電路裝置 ，其中，於上述第1訊號傳達方向呈最終段，於第2訊號 傳達方項第1段邏輯閘電路的第1輸入端子的輸入訊號， 係被供給至於第1訊號傳達方向係第1個，於第2訊號傳 達方向係第3段之邏輯閘電路的第2輸入端子者，在於第 1訊號傳達方向係第1個而於第2訊號傳達方向的第2段 邏輯閘電路的第1與第2輸入端子，被共通供給於第1及 第2訊號傳達方向爲第1個邏輯閘電路的輸出訊號。 2 2 .如申請專利範圍第1 5項之半導體積體電路裝 置，其中，於上述第2訊號傳達方向係第N段之被設於上 述第1訊號傳達方向的第1邏輯閘電路列，與於上述第2 訊號傳達方向係第N + 2段之被設於上述第1訊號傳達方 向的第2邏輯閘電路列，係沿著某條直線，而且鄰接上述 第1邏輯閘電路列的最終段與上述第2邏輯閘電路列的第 1段而被配置於半導體基板上， I紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -82 "~ (請先閲讀背面之注意事項再填寫本頁) tr-----. 經濟部中央標準局員工消費合作社印策 A8 B8 C8 .__ D8__ 六、申請專利範圍 於上述第2訊號傳達方向之第N+1段的被設於上述 第1訊號傳達方向的第3邏輯閘電路列其前半部與後半部 ，分別鄰接上述第1邏輯閘電路列的後半部與上述第2邏 輯聞電路列的前半部而被配置於上述半導體基板上。 2 3 種半導體積體電路裝置，其特徵爲具備震盪 電路，該震盪電路係： 具備複數之使被輸入至第1與第2輸入端子的2個輸 入訊號耦合的阻抗元件被設於上述第1與第2輸入端子間 ’因應被供給至上述第1與第2輸入端子的輸入訊號形成 k出訊號的邏輯閘電路，可以呈格子狀被配置於第1訊號 傳達方向與第2訊號傳達方向的震盪電路， 於上述第2訊號傳達方向，第1輸入端子與輸出端子 被連接爲環狀， 於在第1訊號傳達方向爲第1個，在第2訊號傳達方 向爲第L個的邏輯閘電路的第2輸入端子，係在第1訊號 傳達方向爲最終段的邏輯閘電路，被供給與被供給至第1 輸入端子的輸入訊號具同相關係的輸入訊號， 從被配列於上述第1訊號傳達方向的複數邏輯閘電路 的輸出端子獲得輸出訊號的震盪電路。 2 4 ·如申請專利範圍第2 3項之半導體積體電路裝 置，其中，於上述第2訊號傳達方向係第N段而被設於上 述第1訊號傳達方向的第1邏輯閘電路列，及於上述第2 訊號傳達方向係第N + 2段之被設於上述第1訊號傳達方 向的第2邏輯閘電路列，係沿著某條直線上，而且鄰接上 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） :83 - _________Q! (請先閲讀背面之注意事項再填寫本頁) -訂· v 線)- 經濟部中央標率局貝工消费合作社印装 六、申請專利祀園 述第1邏輯閘電路列的最終段與上述第2邏輯閘電路列的 第1段而被配置於半導體基板上， 於上述第2訊號傳達方向係第N+1段而被設於上述 第1訊號傳達方向的第3邏輯閘電路列其前半部與後半部 分別鄰接上述第1邏輯閘電路列的後半部與上述第2邏輯 閘電路列的前半部而被配置於半導體基板上 2 5 . —種半導體積體電路裝置，其特徵爲：具有延 遲電路，該延遲電路係 具備：複數個使被輸入至第1與第2輸入端子的2個 輸入訊號耦合的阻抗元件被設於上述第1與第2輸入端子 間，因應被供給於上述第1與第2輸入端子的輸入訊號形 成輸出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀的延遲電路， 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第Lg的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L-1段的邏輯閘電路的輸出訊 號或是在第1..段邏輯閘電路被供給輸入時脈訊號，於上述 邏輯閘電路手段K L的第2輸入端子在第1訊號傳達方向 呈前1個之第K_ 1.個，在第2傳達方向呈相同的第L段 的被供給至邏輯閘電路之第1輸入端子的輸入訊號被供給 > 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）· 84 - . 訂 1...線 (請先閲讀背面之注意事項再填寫本頁) 六、申請專利範圍 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其更呈 前段的邏輯閘電路，被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的邏輯閘電路之第1與第2輸入端子，通過 構成緩衝器電路的輸入電路被供給時脈訊號，於第1訊號 傳達方向被供給至0第2個直到最後一個爲止的各邏輯閘 電路的第1輸入端子的上述輸入時脈訊號，係藉由構成上 述緩衝器電路的輸入電路於上述第1訊號傳達方向依序被 延遲者， 具備：於上述第2訊號傳達方向係至少第複數段，從 在第1訊號傳達方向被配列的複數邏輯閘電路的輸出端子 獲得輸出訊號之上述延遲電路，及 選擇上述複數輸出訊號之一的多路轉換器（multiplexer )，及 經濟部中央標隼局員工消費合作社印裝 (請先Η讀背面之注意事項再填寫本頁) 被輸入至上述延遲電路的時脈訊號，及透過上述多路 轉換器被輸出的時脈訊號進行相位比較的相位比較器，及 接受上述相位比較器的輸出訊號，使形成上述多路轉· 換器的控制訊號透過上述多路轉換器被輸出的時脈訊號與 被輸入至上述延遲電路的時脈訊號同步的控制電路。 2 6 .如申請專利範圍第2 5項之半導體積體電路裝 置，其中，上述控制電路，係包含上下行計數電路，對應 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X297公嫠）-85- A8 B8 C8 D8 六、申請專利範圍 上述相位比較器的輸出而進行+1或是一1的計數動作， .將其計數結果解碼而形成上述多路轉換器的控制訊號。 2 7 種半導體積體電路裝置，其特徵爲：具備 於複數字（word)線與複數位元線的交點被矩陣配置 而呈的記億體陣列.，及選擇相關的記憶體陣列的記億體細 胞的位址選擇電路，及使發出對應於被從外部端子供給的 時脈訊號的內部時脈訊號的時脈產生電路，及與上述內部 時脈訊號同步將從上述記憶體細胞讀出的訊號輸出之輸出 入電路， __ ^ 上述時脈產生電路係具備：複數個使被輸入至第1與 第2輸入端子的2個輸入訊號耦合的阻抗元件被設於上述 第1與第2輸入端子間，因應被供給於上述第1與第2輸 入端子的輸入訊號形成輸出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀的延遲電路， 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L-1段的邏輯閘電路的輸出訊 號或是在第1段邏輯閘電路被供給輸入時脈訊號，於上述 邏輯閘電路手段K L的第2輸入端子在第1訊號傳達方向 呈前1個之第K 一 1個，在第2傳達方向呈相同的第L段 的被供給至邏輯閘電路之第1輸入端子的輸入訊號被供給 本紙張尺度適用中國國家揉準（CNS ) A4規格（210 X 297公釐） -86 - 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其更呈 前段的邏輯閘電路，被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的邏.輯閘電路之第1與第2輸入端子，通_ 構成緩衝器電路的輸入電路被供給時脈訊號，於第1訊號 傳達方向被供給至從第2個直到最後一個爲止的各邏輯閘 電路的第1輸入端子的上述輸入時脈訊號，係藉由構成上 述緩衝器電路的輸入電路於上述第1訊號傳達方向依序被 延遲者， 由在上述第2訊號傳達方向係至少第複數段，從在第 1訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲得 輸出訊號之上述延遲電路，及 選擇上述複數輸出訊號之一的多路轉換器，及 控制上述延遲電路使輸出上述內部時脈訊號的控制電 路等所構成。 2 8 .如申請專利範圍第2 7項之半導體積體電路裝 置，其中，上述控制電路，係包含計數電路，使對於上述 被輸入的時脈訊號在被指定的時脈數計數後產生選擇上述 ... ...、 延遲電路的複數輸出訊號之中的一個之控制訊號者。 2 9 .—種半導體記憶體系統，其特徵爲：具備複數 本紙張尺度適用中國囷家標準（CNS ) A4規格（210X297公釐)~ - (請先閲讀背面之注意事項再填寫本頁) ί· 訂 > 經濟部中央標率局貝工消费合作社印裝 B8 C8 D8 六、申請專利範圍 個 於複數字線與複數位元線的交點記憶體細胞被矩陣配 置而成的記憶體陣列，及選擇相關的記憶體陣列的記憶體 細胞的位址選擇電路，及使發出對應於被從外部端子供給 的時脈訊號的內部時脈訊號的時脈產生電路，及與上述內 部時脈訊號同步將從上述記憶體細胞讀出的訊號輸出之輸 出入電路等而成的半導體記憶裝置， 被搭載於上述各半導體記憶裝置的時脈產生電路，係 具備：複數個使被輸入至第1與第2輸入端子的2個輸入 訊號耦合的阻抗元件被設於上述第1與第2輸入端子間， 因應被供給於上述第1與第2輸入端子的輸入訊號形成輸 出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀的延遲電路， 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L — 1段的邏輯閘電路的輸出訊 號或是在第1段邏輯閘電路被供給輸入時脈訊號，於上述 邏輯閘電路手段K L的第2輸入端子在第1訊號傳達方向 呈前1個之第κ- 1個，在第2傳達方向呈相同的第L段 的被供給至邏輯閘電路之第1輸入端子的輸入訊號被供給 9 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 {請先《讀背面之注$項再埃疼本頁) ο 訂 本紙張尺度適用中國國家標率（CNS ) A4规格（2丨0><297公釐） -88- B8 C8 D8 六、申請專利範園 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其更呈 前段的邏輯閘電路’被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的邏輯閘電路之第1與第2輸入端子，通過 構成緩衝器電路的輸入電路被供給時脈訊號，於第1訊號 傳達方向被供給至從第2個直到最後一個爲止的各邏輯閘 電路的第1輸入端子的上述輸入時脈訊號，係藉由構成上 述緩衝器電路的輸入電路於上述第1訊號傳達方向依序被 延遲者， 由在上述第2訊號傳達方向係至少第複數段，從在第 1.訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲得 輸出訊號之上述延遲電路，及 選擇上述複數輸出訊號之一的多路轉換器，及 經濟部中央標準局貝工消費合作社印製 (請先《讀背面之注意事項再填寫本頁) 控制上述延遲電路使輸出上述內部時脈訊號的控制電 路等所構成者， 對於上述複數之半導體記憶裝置共通被設置的，具備 對於上述各半導體記憶裝置供給上述時脈訊號的記憶體控 制電路，以調整各半導體記億裝置與前述記億體控制電路 之間的訊號傳達延遲時間的方式使各半導體記億裝置的上 述時脈產生電路被控制的半導體記憶體系統。 3 0 . —種半導體記憶體系統，其特徵爲：具備複數 本紙張尺度逋用中國國家揉準（CNS ) A4规格（210X297公釐） -89- 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 個 具備於複數字線與複數位元線的交點記憶體細胞被矩 陣配置而成的記憶體陣列，及選擇相關的記億體陣列的記 億體細胞的位址選擇電路，依照由外部端子被供給時脈訊 號而進行資料的輸出輸入之複數半導體記憶裝置，及 被共通設於上述複數個半導體記憶裝置，接受共通時 脈訊號使產生上述時脈訊號的時脈產生電路而成之半導體 記億體模組， 被搭載於上述各記憶體模組的時脈產生電路， 係具備：複數個使被輸入至第1與第2輸入端子的2 個輸入訊號耦合的阻抗元件被設於上述第1與第2輸入端 子間，因應被供給於上述第1與第2輸入端子的輸入訊號 形成輸出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀的延遲電路， 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L - 1段的邏輯閘電路的輸出訊 號或是在第1段邏輯閘電路被供給輸入時脈訊號，於上述 邏輯閘電路手段K L的第2輸入端子在第1訊辦傳達方向 呈前1個之第K— 1個，在第2傳達方向呈相同的第L段 的被供給至邏輯閘電路之第1輸入端子的輸入訊號被供給 本紙張尺度逋用中國國家標準（qNS ) A4規格（210X297公釐） (請先W讀背面之注意事項再填寫本頁) r'_ 訂 經濟部中央標準局β：工消費合作社印裂 B8 C8 D8 六、申請專利範圍 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其更呈 前段的邏輯閘電路，被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的邏輯閘電路之第1與第2輸入端子，通過 構成緩衝器電路的輸入電路被供給時脈訊號，於第1.訊號 傳達方向被供給至從第2個直到最後一個爲止ώ各邏輯閘 電路的第1輸入端子的上述輸入時脈訊號，係藉由構成上 述緩衝器電路的輸入電路於上述第1訊號傳達方向依序被 延遲者， 由在上述第2訊號傳達方向係至少第複數段，從在第 1訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲得 輸出訊號之上述延遲電路，及 選擇上述複數輸出訊號之一的多路轉換器，及 控制上述延遲電路使輸出上述內部時脈訊號的控制電 路等構成者， 對於上述複數之半導體記憶模組共通被設置的，具備 對於上述各半導體記憶模組供給上述共通時脈訊號的記憶 體控制電路，以調整各半導體記憶模組與前述記憶體控制 電路之間的訊號傳達延遲時間的方式使各半導體記憶模組 的上述時脈產生電路被控制的半導體記憶體系統。 本紙張尺度逋用中國國家揉準（CNS > Α4規格（210X297公釐） (請先Η讀背面之注意事項再填寫本頁)A8 B8 C8 _ D8__ printed by the Central Bureau of Standards of the Ministry of Economic Affairs. 6. Patent application scope. 1 type of semiconductor integrated circuit device, which is characterized by: a semiconductor integrated circuit device with a rabbit delayed circuit. The delay circuit has: M signal lines that accept the M signal (M = 2, 3, 4, ...) input signals that are sequentially delayed from the first input signal, and from the signal corresponding to the first input signal. Delay circuits of the M logic gate circuits from the first logic gate circuit group to the M logic gate circuit group corresponding to the Mth input signal; each logic gate circuit group has a delay from the first logic blue circuit to The N logic gates up to the Nth (N = 3, 4, 5, ...) logic gate circuit. The above logic gate circuit has a first input terminal, a second input terminal, and an output terminal, respectively. Coupling components are provided between the first input terminal and the second input terminal, and each logic gate circuit group passes through the output terminal from the first logic gate circuit to the Nth logic gate circuit. The sub and the first input terminal are built vertically, and the μ signal lines are respectively connected to corresponding logic. The first input terminal of the first logic gate circuit of the gate circuit group starts from the first logic gate circuit group at Each of the M-1th logic gate circuit group, the first input terminal of the Lth (L = 1, 2, 3, ...) logic gate circuit is connected to the Lth logic gate circuit of the next logic gate circuit group. The second input terminal is the first input of the designated logic gate circuit of the Mth logic gate circuit group. The paper size is applicable to China National Standard (CNS) A4 specification (210X297 cm) -75-(Please read the note on the back first (Please fill in this page again for details). Order ----- Online 丨 Printed A8 B8 C8 D8 by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs VI. Patent Application Terminals are connected to the designated logic of the first logic gate circuit group The second input terminal of the gate circuit, '-a semiconductor integrated circuit device of the above-mentioned delay circuit which obtains sequentially delayed output signals from the above-mentioned output terminal of the above-mentioned Nth logic gate circuit. Half Volume circuit device, wherein said coupling element comprises a capacitive element are based. 3. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the affinity element is a resistor element. 4. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the logic circuit is a NA ND gate circuit. 5. The semiconductor integrated circuit device according to item 4 of the scope of patent application, wherein the coupling element is a capacitor element. 6. The semiconductor integrated circuit device according to item 1 of the patent application scope, wherein the logic gate circuit is a NOR gate circuit. 7. · If the semiconductor integrated circuit device of the first item of the patent application scope, wherein the above-mentioned logic gate circuit is constituted by a first inverter circuit and a second inverter circuit, the first inverter is The output terminal of the inverter circuit and the output terminal of the second inverter circuit are connected in common. 8. If the semiconductor integrated circuit device of item 1 of the patent application scope, wherein the "Lth of the Mth logic gate circuit group mentioned above" (L = 1, 2, 3, ...) The first input terminal of the logic gate circuit is connected to the second input terminal of the L + 2 logic gate circuit of the first logic gate circuit group. 9. For the semiconductor integrated circuit device under the scope of patent application No. 8, this paper size is applicable to China Gujia Ladder Standard (CNS) A4 specification (210X297 mm) -76-(Please read the precautions on the back before filling this page ) Order B8 C8 D8 6. The scope of patent application Among them, the first circuit column formed by the Lth logic gate circuit of each logic gate circuit group and the second circuit column formed by the L + 2 logic gate circuit are along the It is arranged on a straight line on the semiconductor substrate, and is arranged so that the Lth logic gate circuit of the Mth logic gate circuit group and the L + 2th logic gate circuit of the first logic gate circuit group are adjacent to each other. The first half and the second half of the third circuit column formed by the L + 1th logic gate group of the group are arranged along the second half of the first circuit line and the first half of the second circuit line, respectively. 1 〇.—a semiconductor integrated circuit device, characterized in that it is a semiconductor integrated circuit device with a delay circuit, the delay circuit has: —. Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the notes on the back and fill in this page again.) The input circuit is formed from the first input clock signal to the sequentially delayed (M = 2, 3, 4, ...) input clock signal, and from the corresponding input circuit. The first logic gate circuit group from the first input clock signal to the M logic gate circuit group corresponding to the M input clock signal from the first input clock signal group also starts from the first input clock signal. Each delay amount up to the Mth input clock signal is delayed to obtain a complex output clock signal that is sequentially delayed by an equal amount of delay. Each logic circuit group has a delay from the first logic gate circuit to the Nth ( (N = 3, 4, 5, ...) N logic gate circuits up to logic gate circuits, each of which has a first input terminal, a second input terminal, and an output terminal, and Road group, from the first logic gate circuit to the Nth logic gate circuit through the output terminal and the first input terminal. The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -77- A8 B8 C8 D8 6. The patent application scope is connected continuously in the vertical direction. Starting from the first input clock signal, the M input clock signal is connected to the first input terminal of the first logic gate circuit of the corresponding logic gate circuit group. From the first logic gate circuit group described above to each of the M-1 logic gate circuit groups, the first input terminal of the Lth (L = 1, 2, 3, ...) logic gate circuit is connected to the next logic gate The second input terminal of the Lth logic gate circuit of the gate circuit group, and the first input terminal of the designated logic gate circuit of the Mth logic gate circuit group are connected to the first input terminal of the designated logic gate circuit of the first logic gate circuit group. 2 input terminals,-a semiconductor integrated circuit device of the delay circuit that obtains the plurality of output clock signals from the plurality of output terminals of the Nth logic gate circuit. Printed by the Central Laboratories of the Ministry of Economic Affairs of the Shellfish Consumer Cooperatives (please read the precautions on the back before filling out this page) 11. If you apply for a semiconductor integrated circuit device with the scope of patent application No. 10, the above input circuits have acceptance criteria The clock signal forms a complex unit circuit from the above-mentioned first input pulse signal to the sequentially delayed clock signal of the M (M〒2, 3, 4, ...) input, which are respectively included in the aforementioned complex unit circuit. The characteristics of the circuit elements are sequentially different. "12. For example, the semiconductor integrated circuit device of the 11th scope of the patent application, in which the Mth input clock signal which is sequentially delayed from the first input clock signal is formed in Within one cycle of the above reference clock signal. 1 3. — A semiconductor integrated circuit device, characterized in that: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -78- 6. The scope of patent application is to accept the reference clock signal formation from the first The complex unit circuit from the input of the clock signal to the sequentially delayed clock signal of the Mth (M = 2, 3, 4, ...) input corresponds to the characteristics of the circuit elements included in the complex unit circuit. In the case of different sequences, a first circuit from the first input clock signal to the M input clock signal is formed within one cycle of the reference clock signal, and the first circuit is received from the first input clock signal. Up to the Mth clock signal, the second output of the complex output clock signal which is sequentially delayed with an equal delay amount is also obtained from each delay amount from the first input clock signal to the Mth input clock signal. Circuit; The above-mentioned second circuit is provided with a plurality of logic gate circuits corresponding to M rows × N columns (N = 3, 4, ...) so that signals are transmitted to the rows of the plurality of logic gate circuits. The delay circuits are wired in a direction and a column direction. • 14. If the semiconductor integrated circuit device of item 13 of the scope of patent application, which is printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) The above 2nd circuit system There are M logic gate circuit groups from the first logic gate circuit group corresponding to the first input clock signal to the Mth logic gate circuit group corresponding to the M input clock signal, ^ 'each logic gate The circuit group includes N logic gate circuits from the first logic gate circuit to the Nth (N = 3, 4, 5, ...) logic gate circuits, and the logic gate circuits each have a first input terminal and a second input. The terminals and output terminals are in each logic gate circuit group, from the first logic gate circuit to the Nth logic gate circuit, through the output terminal and the first input terminal. The paper standard is applicable to China National Standards (CNS) Α4 Specifications (210 × 297 mm) -79- Α8 Β8 C8 D8 Printed by the Central Labor Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 6. The scope of the patent application is continuously connected vertically, from the first input above When the pulse signal starts at the Mth input, the pulse signal is connected to the first input terminal of the first logic gate circuit of the corresponding logic gate circuit group, starting from the first logic gate circuit group and starting at the M-1th logic gate circuit group. Each, the first input terminal of the Lth (L = 1, 2, 3, ...) logic gate circuit is connected to the second input terminal of the Lth logic gate circuit of the next logic gate circuit group, ' The first input terminal of the designated logic gate circuit of the M logic gate circuit group is connected to the second input terminal of the designated logic gate circuit of the first logic gate circuit group,-from the above-mentioned output of the plurality of the Nth logic gate circuits. A semiconductor integrated circuit device having a terminal that obtains the complex output clock signal. 15 types of semiconductor integrated circuit devices are characterized in that they have a delay circuit that includes a plurality of impedance elements for coupling two input signals input to the first and second input terminals, Between the first and second input terminals, a logic gate circuit is formed according to the input signals supplied to the first and second input terminals, and the plurality of logic gate circuits can transmit signals in the first signal direction and the second signal. The delay circuit arranged in a grid pattern in the transmission direction is the Kth other than the first in the first signal transmission direction, and the above-mentioned first in the second signal transmission direction is disposed in the logic gate circuit means KL of the Lth stage. The 1st input terminal is the same as the 1st signal in the direction of signal transmission. (Please read the precautions on the back before filling in this page) \ / tr ·. Order · -tec. This paper size is suitable for Chinese countries. CNS) A4 specification (210X297 mm j -80- A8 Β8 C8 D8 VI. Patent application scope A The second signal transmission direction is the output signal of the logic gate circuit in the L-1 stage or the output signal of the logic gate circuit in the first stage Supply input clock Signal, the second input terminal of the above-mentioned logic gate circuit means KL is the first K_1 in the first signal transmission direction, and the same L segment in the second transmission direction is supplied to the first of the logic gate circuits. The input signal of the 1 input terminal is supplied, and the second input terminal of the logic gate circuit which is the first in the first signal transmission direction and the L-th section in the second signal transmission direction is the final section in the first signal transmission direction. In the above-mentioned second signal transmission direction, the logic gate circuit, which is in the front stage, is supplied with the input signal supplied to the first input terminal in the same phase relationship with the input signal supplied to the first input terminal there, which is economical. Printed by the Ministry of Standards and Staff ’s Consumer Cooperatives (please read the precautions on the back before filling out this page) The first signal transmission direction is the first paragraph, and the first signal transmission direction is the first logic gate circuit. The first and second input terminals are supplied with a clock signal through an input circuit constituting the buffer circuit, and are supplied in the first signal transmission direction to the first of each logic gate circuit from the second to the last. The above-mentioned input clock signal of the input terminal is delayed by the input signal constituting the buffer circuit in the first signal transmission direction in order, and at least the first plural stages in the second signal transmission direction, from the first The output terminals of the plurality of logic gate circuits arranged in the signal transmission direction obtain the above-mentioned delay circuit for outputting the signal. 16. The semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein the above-mentioned impedance element is composed of a capacitor element. Paper standard Chinese standard (CNS) A4 (210X297 mm) -81-Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs B8 C8 D8 _ 'VI. Patent Application Park 17. If the scope of patent application is 15th In the semiconductor integrated circuit device, the impedance element is composed of a resistance element. 18. The semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein the logic gate circuit is a NAND gate circuit. 19. The semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein the logic gate circuit is a NO gate circuit. 20. The semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein the logic gate circuit is connected to the output terminals of the two inverter circuits in common. 21. The semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the input signal of the first input terminal of the logic gate circuit of the first paragraph of the first paragraph of the first signal transmission direction is presented in the above-mentioned first signal transmission direction and the second signal is transmitted. , Which is supplied to the first signal transmission direction is the first, and the second signal transmission direction is the second input terminal of the logic gate circuit of the third stage, the first signal transmission direction is the first and the second input terminal is The first and second input terminals of the second stage logic gate circuit in the signal transmission direction are commonly supplied to the output signals of the first logic gate circuit in the first and second signal transmission directions. 2 2. If the semiconductor integrated circuit device according to item 15 of the scope of patent application, wherein the second signal transmission direction is the Nth first logic gate circuit row provided in the first signal transmission direction, and The second signal transmission direction in the above-mentioned second signal transmission direction is the second logic gate circuit row which is provided in the first signal transmission direction in the N + 2 paragraph, which is along a certain line and is adjacent to the final section of the first logic gate circuit train. It is arranged on the semiconductor substrate with the first paragraph of the second logic gate circuit column above. The I paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -82 " ~ (Please read the precautions on the back first) (Fill in this page again.) Tr -----. Printing policy A8 B8 C8 by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs __ D8__ VI. The scope of patent application is set in paragraph N + 1 of the above 2nd signal transmission direction. The first half and the second half of the third logic gate circuit row in the first signal transmission direction are respectively disposed on the semiconductor substrate adjacent to the second half of the first logic gate circuit row and the first half of the second logic gate circuit row. on. 2 and 3 types of semiconductor integrated circuit devices are characterized by including an oscillating circuit. The oscillating circuit is provided with a plurality of impedance elements for coupling two input signals input to the first and second input terminals. A logic gate circuit forming a k-output signal in response to the input signals supplied to the first and second input terminals between the second input terminal and the second input terminal may be arranged in a grid pattern in the first signal transmission direction and the second signal transmission direction. The oscillating circuit is a logic gate circuit in which the first input terminal and the output terminal are connected in a ring shape in the above-mentioned second signal transmission direction, and is the first in the first signal transmission direction and the L-th in the second signal transmission direction. The second input terminal is a logic gate circuit which is the final stage in the direction of the first signal transmission. The input signal supplied with the same relationship as the input signal supplied to the first input terminal is transmitted from the first signal arranged in the above. The output terminal of the complex logic gate circuit of the direction obtains the oscillating circuit of the output signal. 2 4 · The semiconductor integrated circuit device according to item 23 of the scope of patent application, wherein the second signal transmission direction is the Nth stage and the first logic gate circuit row is provided in the first signal transmission direction, and The second signal transmission direction in the above-mentioned second signal transmission direction is the second logic gate circuit row provided in the first signal transmission direction in paragraph N + 2. It is along a straight line and is adjacent to the above paper. The Chinese standard applies ( CNS) A4 specification (210X297 mm): 83-_________Q! (Please read the notes on the back before filling out this page)-Order · Line V)-Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The final stage of the first logic gate circuit sequence and the first stage of the second logic gate circuit sequence are arranged on a semiconductor substrate, and the second signal transmission direction is the N + 1th stage and is provided on the semiconductor substrate. The first half and the second half of the third logic gate circuit row in the first signal transmission direction are respectively arranged on the semiconductor substrate adjacent to the second half of the first logic gate circuit row and the first half of the second logic gate circuit row. 2 5 . — A kind of semiconductor The bulk circuit device is characterized by having a delay circuit including a plurality of impedance elements for coupling two input signals input to the first and second input terminals to the first and second inputs. Between the terminals, a logic gate circuit is formed in response to an input signal supplied to the first and second input terminals. The plurality of logic gate circuits may be arranged in the first signal transmission direction and the second signal transmission direction. The grid-shaped delay circuit has a Kth position other than the first in the first signal transmission direction, and is arranged on the first input terminal of the logic gate circuit means KL of the Lg in the second signal transmission direction on the first signal. The transmission direction is the same as the Kth, and the output signal of the logic gate circuit of the L-1 stage is transmitted in the second signal transmission direction or the input clock signal is supplied to the logic gate circuit of the 1st stage. The input of the second input terminal of the circuit means KL is the first K_1 in the first signal transmission direction, and the input of the first L input terminal of the logic gate circuit which is the same in the second transmission direction is input to the logic gate circuit. Signal It is supplied> Moreover, it is the first in the direction of the first signal transmission, and the paper size in the second signal applies the Chinese National Standard (CNS) A4 specification (210X297 mm) · 84-. Order 1 ... line ( (Please read the precautions on the back before filling this page) 6. The second input terminal of the logic gate circuit whose patent application scope is in the L-th direction is the final stage in the first signal transmission direction and in the above-mentioned second signal transmission direction The logic gate circuit, which is more advanced than that, has an input signal supplied to the first input terminal that is in phase relationship with the input signal supplied to the first input terminal. The input signal supplied to the first input terminal is the first in the second signal transmission direction. In the first stage, the first and second input terminals of the first logic gate circuit in the first signal transmission direction are supplied with the clock signal through the input circuit constituting the buffer circuit, and are supplied to 0 in the first signal transmission direction. The input clock signal of the first input terminal of each of the logic gate circuits from the second to the last is delayed by the input circuit constituting the snubber circuit in the first signal transmission direction in order. With the above-mentioned delay circuit for obtaining an output signal from the output terminal of the plurality of logic gate circuits arranged in the first signal transmission direction in at least the plurality of plural stages in the second signal transmission direction, and selecting one of the plurality of output signals Multiplexer (multiplexer), printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The clock signal input to the above delay circuit, and through the above multiplexer A phase comparator for phase comparison of the clock signal output from the converter, and a clock signal that receives the output signal of the phase comparator so that the control signal forming the multiplexer / translator is output through the multiplexer. A control circuit synchronized with a clock signal input to the delay circuit. 26. If the semiconductor integrated circuit device according to item 25 of the patent application scope, wherein the above control circuit includes an up-down counting circuit, the Chinese National Standard (CNS) Α4 specification (210X297 cm) is applicable to this paper size- 85- A8 B8 C8 D8 6. Scope of patent application The output of the phase comparator mentioned above is counted by +1 or -1. The count result is decoded to form the control signal of the multiplexer. 27 kinds of semiconductor integrated circuit devices, which are characterized by: a memory array that is arranged at the intersection of a complex digital (word) line and a complex bit line by a matrix; and a memory that selects the relevant memory array Address selection circuit of somatic cell, and clock generating circuit for generating internal clock signal corresponding to clock signal supplied from external terminal, and read out from said memory cell in synchronization with said internal clock signal I / O circuit for signal output, __ ^ The above-mentioned clock generation circuit is provided with a plurality of impedance elements for coupling two input signals input to the first and second input terminals to the first and second input terminals. At the same time, a logic gate circuit that forms an output signal in response to the input signals supplied to the first and second input terminals may be arranged in a grid in the first signal transmission direction and the second signal transmission direction. This delay circuit is printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). The Kth signal of the second signal transmission direction is arranged on the above-mentioned first input terminal of the logic gate circuit means KL of the Lth stage in the first signal transmission direction, and the Kth signal is the same in the first signal transmission direction. The output signal of the logic gate circuit in the L-1 stage or the input clock signal when the logic gate circuit in the first stage is supplied. The second input terminal of the above-mentioned logic gate circuit means KL is the first one in the direction of the first signal transmission. K-1, the same L-paragraph in the 2nd transmission direction, the input signal supplied to the first input terminal of the logic gate circuit is supplied to this paper standard applicable Chinese National Standard (CNS) A4 specification (210 X 297 mm) -86-Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of patent application and the logic gate circuit in the first signal transmission direction is the first, and the second signal transmission direction is in the L segment. The second input terminal of the second input terminal is the final stage in the first signal transmission direction, and the logic gate circuit which is in the previous stage in the second signal transmission direction is more advanced than the input signal of the first input terminal provided there. In-phase relationship The input signal supplied to the first input terminal is the first segment in the second signal transmission direction and the first logic in the first signal transmission direction. The first and second input terminals of the gate circuit are connected. _ The clock signal is supplied to the input circuit constituting the buffer circuit, and the above-mentioned input clock signal is supplied to the first input terminal of each logic gate circuit from the second to the last in the first signal transmission direction. The input circuit constituting the buffer circuit is delayed sequentially in the first signal transmission direction, and the second logic transmission circuit is at least a plurality of stages from the complex logic gate circuit arranged in the first signal transmission direction. The above-mentioned delay circuit which obtains an output signal from the output terminal, a multiplexer which selects one of the plurality of output signals, and a control circuit which controls the delay circuit so as to output the internal clock signal. 28. The semiconductor integrated circuit device according to item 27 of the scope of patent application, wherein the control circuit includes a counting circuit so that the input clock signal is generated after the specified clock number is counted and selected. ..., one of the plural output signals of the delay circuit to control the signal. 2 9 .—Semiconductor memory system, characterized in that it has multiple paper sizes that are applicable to the Chinese family standard (CNS) A4 specification (210X297 mm) ~-(Please read the precautions on the back before filling this page) ί · Order &print; B8, C8, D8, printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of the patent application is a memory array in which the memory cells at the intersection of the complex digital line and complex digital line are arranged in a matrix, and An address selection circuit for selecting a memory cell of a relevant memory array, and a clock generation circuit for emitting an internal clock signal corresponding to a clock signal supplied from an external terminal, and synchronizing the clock signal with the internal clock signal A semiconductor memory device including an input / output circuit of a signal output read from the memory cell is mounted on a clock generation circuit of each of the semiconductor memory devices, and includes a plurality of inputs for inputting to the first and second clock circuits. An impedance element coupled to the two input signals of the input terminal is provided between the first and second input terminals, and is correspondingly supplied to the output of the first and second input terminals. The signals form a logic gate circuit for outputting signals. The plurality of logic gate circuits are delay circuits that can be arranged in a grid pattern in the first signal transmission direction and the second signal transmission direction, and the first signal transmission direction is other than the first. The Kth signal of the second signal transmission direction is arranged on the above-mentioned first input terminal of the logic gate circuit means KL of the Lth stage in the first signal transmission direction, and the Kth signal is the same in the first signal transmission direction. The output signal of the logic gate circuit of the L-1 stage or the input clock signal when the logic circuit of the first stage is supplied. The second input terminal of the above-mentioned logic circuit means KL is the first one in the direction of the first signal transmission. The κ-1 of the L signal which is supplied to the first input terminal of the logic gate circuit in the same L-segment in the second transmission direction is supplied with 9 and the first signal is transmitted in the first signal transmission direction. Signal No. 2 (Please read "Notes on the back of the book before you hurt this page") ο The size of the paper is applicable to China National Standards (CNS) A4 specifications (2 丨 0 > < 297 mm) -88- B8 C8 D8 VI. Apply for patent Fan Yuanda The second input terminal of the logic gate circuit which is in the L-th stage is the final stage in the direction of the first signal transmission, and the logic gate circuit which is in the preceding stage in the second signal transmission direction is supplied and supplied there. The input signal of the first input terminal becomes the input signal supplied to the first input terminal in the same phase relationship. It is the first logic gate circuit in the second signal transmission direction and the first logic gate circuit in the first signal transmission direction. The first and second input terminals are supplied with a clock signal through the input circuit constituting the buffer circuit, and are supplied in the first signal transmission direction to the first input terminal of each logic gate circuit from the second to the last. The input clock signal is delayed by the input circuit constituting the buffer circuit in the first signal transmission direction in order, and the second signal transmission direction is at least a plurality of paragraphs from the first signal. The above-mentioned delay circuit that obtains an output signal from the output terminals of the plurality of logic gate circuits arranged in the transmission direction, and a multiplexer that selects one of the above-mentioned plurality of output signals, and is economical. Printed by the Central Standards Bureau Shellfish Consumer Cooperative (please read the “Cautions on the back side before filling out this page”) The control circuit that controls the delay circuit to output the internal clock signal is common to the above-mentioned plural semiconductor memory devices It is provided with a memory control circuit that supplies the clock signal to each of the semiconductor memory devices, and makes each semiconductor count 100 million in a manner that adjusts the signal transmission delay time between each semiconductor memory device and the aforementioned memory control circuit. A semiconductor memory system in which the above-mentioned clock generation circuit of the device is controlled. 3 0. — A semiconductor memory system, characterized in that it has multiple paper sizes and uses the Chinese National Standard (CNS) A4 specification (210X297 mm) -89- Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Scope of patent application A memory array with memory cells arranged at the intersections of complex digital lines and complex bit lines, and the address selection of memory cells that select the relevant memory cells array A circuit, a plurality of semiconductor memory devices for outputting and inputting data in accordance with a clock signal supplied from an external terminal, and a plurality of semiconductor memory devices commonly provided in the plurality of semiconductor memory devices, receiving a common clock signal to generate a clock that generates the clock signal A semiconductor memory module made of a circuit is mounted on the clock generating circuit of each of the memory modules, and includes a plurality of impedances for coupling two input signals input to the first and second input terminals. The component is placed between the first and second input terminals, and an output signal is formed in response to the input signals supplied to the first and second input terminals. A logic gate circuit, the plurality of logic gate circuits are delay circuits that can be arranged in a lattice pattern in the first signal transmission direction and the second signal transmission direction, and are Kth ones other than the first signal transmission direction, The first input terminal of the logic gate circuit means KL which is arranged in the second signal transmission direction in the second signal transmission direction is the same K-th in the first signal transmission direction, and is L-1 in the second signal transmission direction. The output signal of the logic gate circuit or the input clock signal is supplied to the first stage logic gate circuit. The second input terminal of the above-mentioned logic gate circuit means KL is the first K-th in the direction of the first signal office. One, the input signal supplied to the first input terminal of the logic gate circuit in the same L-segment in the second transmission direction is supplied to this paper size, using the Chinese National Standard (qNS) A4 specification (210X297 mm) ( Please read the precautions on the back before filling this page) r'_ Order Central Standards Bureau of the Ministry of Economic Affairs β: Industrial and consumer cooperatives print B8 C8 D8 6. The scope of patent application and the first signal transmission direction is the first, At news 2 The second input terminal of the logic gate circuit in the L signal transmission direction is in the final stage in the first signal transmission direction, and the logic gate circuit in the second signal transmission direction which is in the front stage is provided and supplied to The input signal of the first input terminal here is the input signal supplied to the first input terminal in the same phase relationship. It is the first logic gate in the second signal transmission direction and the first logic gate in the first signal transmission direction. The first and second input terminals of the circuit are supplied with a clock signal through the input circuit constituting the buffer circuit, and are supplied to the first of each logic gate circuit from the second to the last in the signal transmission direction. The above-mentioned input clock signal of the input terminal is delayed by the input signal constituting the buffer circuit in the first signal transmission direction in order, and the second signal transmission direction is at least a plurality of stages from the first 1 signal transmission direction, the above-mentioned delay circuit for obtaining an output signal from the output terminal of the plurality of logic gate circuits arranged, and a multiplexer selecting one of the above-mentioned plurality of output signals, and Components such as a control circuit that controls the delay circuit to output the internal clock signal are provided in common to the plurality of semiconductor memory modules, and include a memory control circuit that supplies the common clock signal to each of the semiconductor memory modules. A semiconductor memory system in which the clock generation circuit of each semiconductor memory module is controlled by adjusting the signal transmission delay time between each semiconductor memory module and the aforementioned memory control circuit. The size of this paper is based on the Chinese national standard (CNS > Α4 size (210X297 mm) (Please read the precautions on the back before filling this page) -91 - 經濟部中央標隼局貝工消費合作社印装 B8 C8 D8 六、申請專利範圍 31.—種時脈同步電路，係具備： 接收來自基本時脈訊號被延遲的第1時脈訊號，具有 第1時間分解能之使上述第1時脈訊號傳播的第1延遲電 路，及 比較對應於上述第1延遲電路的上述時間分解能的各 但延遲訊號的端緣，與上述基本時脈訊號的第1時脈端緣 ，檢測出兩端緣之時間上的一致之第1端緣檢測電路，及 選擇對應於藉由上述第1端緣檢測電路的檢測訊號而 被控制的上述第1延遲電路的延遲段的延遲訊號之第1多 路轉換器，及 接收透過上述第1多路轉換器而獲得的第2時脈訊號 ，使傳播具有較上述第1時間分解能更高精度的第2分解 能的上述第2時脈訊號的第2延遲電路，及 比較對應於上述第2延遲電路的上述時間分解能的各 段的延遲訊號的端緣，與上述基本時脈訊號的第2時脈端 緣，檢測出兩端緣之時間上的一致之第2端緣檢測電路， 及 選擇對應於藉由上述第2端緣檢測電路的檢測訊號而 被控制的上述第2延遲電路的延遲段的延遲訊號的第2多 路轉換器， 基於透過上述第2多路轉換器而獲得的第3時脈訊號 ，形成上述基本時脈訊號或者對應於上述.基本時脈訊號的 訊號與被同步化的內部時脈訊號而成的時脈同步電路：，其 特徵爲： ---------rI—IT— — 11 1^ ί.--線 (請先閱讀背面之注意Ϋ項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •92--91-Printed on B8, C8, D8, Shellfish Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs 6. Scope of patent application 31. A type of clock synchronization circuit, which: Receives the first clock signal delayed from the basic clock signal, A first delay circuit having a first time-resolving energy that allows the first clock signal to propagate, and an edge of each delayed signal that compares the time-resolving energy corresponding to the first delay circuit with the first edge of the basic clock signal 1 clock edge, a first edge detection circuit that detects the time coincidence between the two edges, and selects the first delay circuit corresponding to the first delay circuit controlled by the detection signal of the first edge detection circuit. The first multiplexer of the delay signal of the delay section and the reception of the second clock signal obtained through the first multiplexer, so as to propagate the second decomposition energy having a higher accuracy than the first time decomposition energy. The second delay circuit of the second clock signal, and the edge of the delay signal that compares the segments corresponding to the time resolution energy of the second delay circuit with the second clock of the basic clock signal Edge, detects a second edge detection circuit that is consistent in time at both edges, and selects a delay corresponding to a delay period of the second delay circuit controlled by the detection signal of the second edge detection circuit The second multiplexer of the signal is based on the third clock signal obtained through the second multiplexer, and forms the basic clock signal or corresponds to the above. The signal of the basic clock signal and the synchronized internal Clock synchronization circuit based on clock signal: Its characteristics are: --------- rI—IT— — 11 1 ^ ί .-- line (please read the note on the back before filling in this Page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) • 92- 六、申請專利範圍 上述第2延遲電路， 係具備：簿數個使被輸入至第1與第2輸入端子的2 個輸入訊號耦合的阻抗元件被設於上述第1與第2輸入端 子間，因應被供給於上述第1與第2輸入端子的輸入訊號 形成輸出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀， 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L·的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L - 1段的邏輯閘電路的輸出訊 號京是在第1段邏輯閘電路被供給輸入時脈訊號， 於上述邏輯閘電路手段K L的第2輸入端子在第1訊 號傳達方向呈前1個之第K- 1個，在第2傳達方向呈相 同的第L段的被供給至邏輯閘電路之第1輸入端子的輸入 訊號被供給， 經濟部中央榇準局男工消费合作社印策 ---------r·'— (请先W讀背面之注意事項再填寫本頁) 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其.更呈 .、、 L .. 前段的邏輯閘電路，被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的邏輯閘電路之第1與第2輸入端子，被供 本紙張尺度適用中國國家揉準（CNS〉A4規格（210X297公釐） -93- 經濟部中央標準局員工消費合作·社印製 A8 B8 C8 D8 六、申請專利範圍 給對應於上述第2時脈訊號的時脈訊號，於第1訊號傳達 方向被供給至從第2個直到最後一個爲止的各邏輯閘電路 的第1輸入端子的上述輸入時脈訊號，於上述第1訊號傳 達方向依序被延遲者， 具有在上述第2訊號傳達方向係至少第複數段，從在 第1訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲 得輸出訊號之上述第2延遲電路。 3 2 .如申請專利範圍第3 1項之時脈同步電路，其 中，進而含有與上述第1延遲電路同樣的電路構成之第3 、第4延遲電路，及 對應上述第4延遲電路而設的第3多路轉換器，及 與上述第2延遲電路同樣的電路構成之第5延遲電路 f 上述第1多路轉換器，係藉由上述第1端緣檢測電路 的檢測訊號而選擇上述第3延遲電路的各段的延遲訊號者 上述第3多路轉換器，係藉由上述第1端緣檢測電路 的檢測訊號而選擇上述第4延遲電路的各段的延遲訊號者 於上述第2延遲電路的輸入，被供給上述第1多路轉 換器的輸出訊號，形成被供給至上述第2端緣檢測電路的 延遲訊號者， 上述第2多路轉換器，係釋由上述第2端緣檢測電路 的檢測訊號而選擇上述箄5延遲電路的各段的延遲訊號者 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 、τ Γ -94 經濟部中央標隼局員工消費合作.社印製 六、申請專利範圍 0 3 3 .如申請專利範圍第3 .1或3 2項之時脈同步電 路，其中，構成上述第2延遲電路的延遲電路，於上述第 1訊號傳達方向呈最終段，於第2訊號傳達方向呈-第1段 的邏輯閘電路的第1輸入端子的第1輸入訊號，於第1訊 號傳達方向係第.i個，於第2訊號傳達方向被供給至第3 段邏輯閘電路的第2輸入端子者，於第1.訊號傳達方向係 第1個於第2訊號傳達方向的第2段邏輯閘電路的第1 .與 第2輸入端子，於第1及第2訊號傳達方向共通被供給第 1個邏輯閘電路的輸出訊號者》 3 4 .如申請專利範圍第3 2或3 3項之時脈同步電 路，其中，上述第1、第3及第4延遲電路，係縱列連接 CMO S反相器電路而被構成者。 35 .如申請專利範圍第32、33或34項之時脈 同步電路，其中，於上述第3延遲電路的輸入，通過第1 僞（dummy)延遲電路被供給輸入訊號， 上述第1僞延遲電路的輸出訊號通過以使從上述第2 延遲電路被輸出的延遲訊號成爲指定段數以後的方式設定 而進行時間調整的第2僞延遲.電路被供給至上述第1延遲 電路的輸入者。 36 .如申請專利範圍第32、33、34或35項 之時脈亂步電路，其中，上述第1與第2端緣檢測電路分 別於輸出部具有閂鎖電路，藉由指定的控制訊號而呈間歇 動作狀態，同時在非動作狀態使輸出被保持於上述閂鎖電 本纸張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） -95- {請先閲讀背面之注意事項再填寫本頁) 訂' 線6. Scope of Patent Application The above-mentioned second delay circuit includes: a plurality of impedance elements for coupling two input signals input to the first and second input terminals are provided between the first and second input terminals, The logic gate circuits that output signals are formed according to the input signals supplied to the first and second input terminals. The plurality of logic gate circuits can be arranged in a grid pattern in the first signal transmission direction and the second signal transmission direction. In the first signal transmission direction, it is Kth other than the first, and in the second signal transmission direction, the above-mentioned first input terminal of the logic gate circuit means KL · arranged in the Lth stage is the same in the first signal transmission direction. The K-th output signal of the logic gate circuit in the L-1 stage in the second signal transmission direction is the input clock signal when the logic gate circuit in the first stage is supplied. The input signal of the first input terminal in the first signal transmission direction is K-1, and the input signal of the first input terminal in the L-phase which is the same in the second transmission direction is supplied to the logic gate circuit. The Ministry of Economic Affairs central The printed policy of the Men's Workers Consumer Cooperative Bureau of the Bureau --------- r · '— (please read the precautions on the back before filling out this page). Also, the first signal transmission direction is the first. The second input terminal of the logic gate circuit with the 2nd signal transmission direction is in the L segment, and it is the final stage in the first signal transmission direction. The above 2nd signal transmission direction is more than the. The circuit, the input signal supplied to the first input terminal supplied there is in the same phase relationship, and the input signal supplied to the first input terminal is in the first paragraph in the direction of the second signal transmission, and is transmitted in the first signal. The first and second input terminals of the logic gate circuit whose direction is the first are used for this paper. The Chinese national standard (CNS> A4 specification (210X297 mm)) is used. The company prints A8 B8 C8 D8. 6. The scope of patent application is for the clock signal corresponding to the above-mentioned second clock signal. It is supplied to the first gate of each logic gate circuit from the second to the last. The above input clock signal of the 1 input terminal, Those who are sequentially delayed in the above-mentioned first signal transmission direction have at least a plurality of stages in the above-mentioned second signal transmission direction, and obtain the above-mentioned first output signal from the output terminals of the plurality of logic gate circuits arranged in the first signal transmission direction. 2 delay circuits 3 2. The clock synchronization circuit according to item 31 of the scope of patent application, which further includes third and fourth delay circuits having the same circuit configuration as the first delay circuit, and corresponding to the fourth delay. The third multiplexer provided by the circuit and the fifth delay circuit f having the same circuit configuration as the second delay circuit. The first multiplexer is based on the detection signal from the first edge detection circuit. The third multiplexer selects the delay signal of each segment of the third delay circuit. The third multiplexer selects the delay signal of each segment of the fourth delay circuit based on the detection signal of the first edge detection circuit. The input of the second delay circuit is supplied to the output signal of the first multiplexer to form a delay signal to be supplied to the second edge detection circuit, and the second multiplexer Device, which is based on the detection signal of the second edge detection circuit and selects the delay signal of each section of the above-mentioned 5 delay circuit. This paper size applies to Chinese national standards (CNS > A4 specification (210X297 mm) (please first Read the notes on the back and fill in this page), τ Γ -94 Consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs. Printed by the agency. 6. Patent application scope 0 3 3. If the scope of patent application is 3.1 or 32 A clock synchronization circuit, wherein the delay circuit constituting the second delay circuit has a final stage in the first signal transmission direction and a first input terminal of the logic gate circuit in the first stage in the second signal transmission direction. 1 The input signal is .i in the first signal transmission direction, and the second input terminal of the third stage logic gate circuit in the second signal transmission direction is the first in the 1 signal transmission direction. The first and second input terminals of the second logic gate circuit in the second signal transmission direction are shared with the output signals of the first logic gate circuit in the first and second signal transmission directions. 3 4. When the scope of the patent is 32 or 33 The pulse-synchronous circuit includes the above-mentioned first, third, and fourth delay circuits, which are constituted by connecting CMOS inverter circuits in series. 35. A clock synchronization circuit according to item 32, 33, or 34 of the scope of patent application, wherein the input to the third delay circuit is supplied with an input signal through a first dummy delay circuit, and the first dummy delay circuit is The second dummy delay whose time is adjusted by setting the delay signal outputted from the second delay circuit to a specified number of stages or more is provided to the input signal of the first delay circuit. 36. For example, a clocked chaotic circuit with the scope of patent application No. 32, 33, 34, or 35, wherein the above-mentioned first and second edge detection circuits each have a latch circuit at the output section, and are designated by a specified control signal. It is in an intermittent operation state, and at the same time in the non-operation state, the output is maintained at the above-mentioned latch paper size. Common Chinese National Standard (CNS) A4 specification (210X297 mm) -95- (This page) Order 'line 六、申請專利範園 路的檢測訊號。 經濟部中央標準局員工消費合也社印製 37 ·如申請專利範圍第31、32、33、34、 3 5或3 6項之時脈同步電路，其中，上述基本時脈訊號 係通過接受由外部端子所供給的外部時脈訊號的輸入緩衝 器電路而被輸入者， 通過上述第2多路轉換器的輸出訊號，係通過輸出段 驅動器被輸出者，上述外部時脈訊號與上述輸出段驅動器 的輸出訊號被同步化者。 3 8 .如申請專利範圍第3 6或3 7項之時脈同步電 路，其中，上述指定的控制訊號，係藉由計時器電路而以 一定的週期使其產生者。 - 39 種時脈同步電路，其係具備： 接受被從外部端子供給的時脈訊號的輸入緩衝器電路 ，及 使通過上述輸入緩衝器的時脈訊號延遲對應於上述輸 入緩衝器與輸出段驅動器的延遲時間的延遲時間的第1延 遲電路，及 選擇傳遞上述第1延遲電路的輸出訊號或是上述輸入 緩衝器的輸出訊號的開關電路，及 通過上述開關電路使輸入訊號延遲的第2延遲電路， 及 比較上述第2延遲電路的各段延遲訊號，與通過上述 輸入緩衝器被輸入的時脈訊號之延遲了1個時脈的時脈端 緣，檢.測出兩端緣在時間上的一致，具備保持其檢測結果 (谇先閲讀背面之注意事項再填寫本頁) -C. 訂 線. 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •96- 經濟部中央標準局員工消費合作社印裝 B8 C8 D8 々、申請專利範園 的閂鎖功能，藉由該檢測結果使輸出上述各段的延遲訊號 的選擇電路： 將上述開關電路連接於上述第1延遲電路側藉由上述 端緣檢測電路形成檢測訊號， 將上述開關電路切換至上述輸入緩衝器電路側，藉由 被保持於上述閂鎖功能的檢測結果使上述第2延遲電路的 延遲訊號通過上述輸出段驅動器而輸出的時脈同步電路， 其特徵爲： 上述第2’延遲電路 係具備：複數個使被輸入至第1與第2輸入端子的2 個輸入訊號耦合的阻抗元件被設於上述第1與第2輸入端 子間，因應被供給於上述第1與第2輸入端子的輸入訊號 形成輸出訊號的邏輯閘JI路， 上述複數齒邏輯閘手段係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀， 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L-1段的邏輯閩電路的輸出訊 號或是在第1.段邏輯閘電路被供給輸入時脈訊號， 於上述邏輯閘電路手段K L的第2輸入端子在第1訊 號傳達方向呈前1個之第K- 1個，在第2傳達方向呈相 同的第L段的被供給至邏輯閘電路之第1輸入端子的輸入 訊號被供給， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 線 經濟部中央標準局貝工消費合作社印策 A8 B8 C8 D8 六、申請專利範圍 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 .達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段，於上述第2訊號傳達方向較其更呈 前癌的邏輯閘電路，被供.給與被供給於該處之第„1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向呈第1個的..邏輯閘電路之第1與第2輸入端子，.被供 給對應於通過上述開關電路的輸入訊號的時脈訊號，於第 1訊號傳達方向被供給至從第2個直到最後一個爲止的各 邏輯閘電路的第1輸入端子.的上述輸入時脈訊號，於上述 第1訊號傳達方向依序被延遲者， 在上述第2訊號傳達方向係至少第複數段，從在第1 訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲得輸 出訊號。 40種時脈同步電路，其係具備： 接受被從外部端子供給的時脈訊號的輸入緩衝器電路 ，岌 使通過上述輸入緩衝器的時脈訊號延遲對應於上述輸 入緩衝器與輸出段驅動器的延遲時間的延遲時間的第1延 遲電路，及 接受上述第1延遲電路的輸出訊號使其延遲的2個延 遲電路，及 比較上述第2延遲電路的各段延遲訊號，與通過上述 (請先S讀背面之注意事項再填寫本頁) 訂 線 本紙張尺度適用中國國家標準（CNS ) A4洗格（210X297公釐） -98- 經濟部中央標準局貝工消费合怅社印製 B8 C8 D8 六、申請專利範圍 輸入緩衝器被輸入的時脈訊號之延遲了1個時脈的時脈端 緣，檢測出兩端緣在時間上的一致的端緣檢測電路，及 通過上述輸入緩衝器接受時脈訊號使其延遲的3個延 遲電路，及 藉由上述端緣檢測電路的檢測結果而將上述3個延遲 電路的延遲訊號通過輸出段驅動器而輸出的時脈同步電路 ，其特徵爲： 上述第2及第3延遲電路分別 係具備：複數個使被輸入至第1與第2輸入端子的2 個輸入訊號耦合的阻抗元件被設於上述第1與第2輸入端 子間，因應被供給於上述第1與第2輸入端子的輸入訊號 形成輸出訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 第2訊號傳達方向上被配置爲格子狀， 於第1訊號傳達方向呈第1個以外的第K個，於第2 訊號傳達方向被配置於第L段的邏輯閘電路手段K L的上 述第1輸入端子上於第1訊號傳達方向呈相同的第K個， 於第2訊號傳達方向呈第L -1段的邏輯閘電路的輸出_訊 號或是在第1段邏輯閘電路被供給輸入時脈訊號， 於上述邏輯閘電路手段K L的第2輸入端子在第1訊 號傳達方向呈前1個之第K - 1個，在第2傳達方向呈相 5的第L段的被供給至邏輯閘電路之第1輸入端子的輸入 訊號被供給， 而且，於第1訊號傳達方向呈第1個，於第2訊號傳 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） ---------r-------訂------Γ線 (請先閎讀背面之注意Ϋ項再填寫本頁) -99 - 經濟部中央標準局員工消費合作社印製 B8 C8 D8 六、申請專利範圍 達方向呈第L段的邏輯閘電路的第2輸入端子，於第1訊 號傳達方向呈最終段*於上述第2訊號傳達方向較其更呈 前段的邏輯閘電路，被供給與被供給於該處之第1輸入端 子的輸入訊號成爲同相關係的被供給至第1輸入端子的輸 入訊號， 於上述第2訊號傳達方向呈第1段，於第1訊號傳達 方向被供給至從第1個的直到最後一個爲止的各邏輯閘電 路的第1輸入端子的時脈訊號，於上述第1訊號傳達方向 依序被延遲者·， 在上述第2訊號傳達方向係至少第複數段，從在第1. 訊號傳達方向被配列的複數邏輯閘電路的輸出端子獲得輸 出訊號。 4 1 . 一種半導體積體電路裝置，其特徵爲：具備 於複數字（wo r d)線與複數位元線的交點被矩陣 配置而呈的記億體陣列，及 選擇上述記億體陣列的記憶體細胞的位址選擇電路， 及使發出對應於被從外部端子供給的外部時脈訊號的內部 時脈訊號的時脈同步電路，及 依照在上述時脈同步訊號所被產生的內部時脈訊號使 輸出上述記憶體細胞的讀出訊號的輸出電路， 上述時脈同步電路係具備： 從對應於上述外部時脈訊號的基本時脈訊號接受被延 遲的第1時脈訊號，使傳播具有第1時間分解能的上述第 1時脈訊號的第1延遲電路，及 ---------r------IT-----纖線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -100· 經濟部中央標準局員工消費合作杜印«. A8 B8 C8 D8 六、申請專利範園 比較對應於上述第1延遲電路的上述時間分解能的各 段延遲訊號的端緣，與上述基本時脈訊號的第1時脈端緣 ，檢測出兩端緣的時間上的一致之第1端緣檢測電路，及 藉由上述第1端緣檢測電路的檢測訊號而被控制，選 擇上述第1延遲電路的對應的延遲段的延遲訊號之第1多 路轉換器，及 接受通過上述第1多路轉換器獲得的第2時脈訊號使 傳播具有較上述第1時間分解能更高精度的時間分解能的 上述第2時脈訊號的第2延遲電路，及 比較對應於上述第2延遲電路的上述時間分解能的各 段的延遲訊號的端緣，與上述基本時脈訊號的第2時脈端 緣檢測出兩端緣的時間上的一致之第2時脈檢測電路，及 由上述第2時脈檢測電路的檢測訊號所控制選擇上述 第2延遲電路的對應的延遲段的延遲訊號的第2多路轉換 器； 形成基於通過上述第2多路轉換器獲得的第3時脈訊 號而被與上述外部時脈訊號同步化的上述內部時脈訊號之 時脈同步電路， 上述第2延遲電路係具備： 複數個使被輸入至第1與第2輸入端子的2個輸入訊 號耦合的阻抗元件被設於上述第1與第2輸入端子間’因 應被供給於上述第1與第2輸入端子的輸入訊號形成輸出 訊號的邏輯閘電路， 上述複數個邏輯閘電路係可以於第1訊號傳達方向與 本紙張尺度適用中國國家標準（CNS ) A4規格（2!0Χ297公釐） -101 - (請先閲讀背面之注意事項再填寫本頁) 訂 線 I6. The detection signal of Fanyuan Road for patent application. Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Goods Association. 37. For example, the clock synchronization circuit of the 31st, 32nd, 33rd, 34th, 35th, or 36th patent application scope, where the above basic clock signal is accepted by The external clock signal supplied from the external terminal is input by the input buffer circuit. The output signal of the second multiplexer is output by the output driver. The external clock signal and the output driver are output. The output signal is synchronized. 38. For example, the clock synchronization circuit of item 36 or 37 of the scope of patent application, wherein the specified control signal is generated by a timer circuit with a certain period. -39 types of clock synchronization circuits, which include: an input buffer circuit that receives a clock signal supplied from an external terminal, and a delay that the clock signal passing through the input buffer corresponds to the input buffer and the output driver A first delay circuit with a delay time of a delay time, a switch circuit that selects to transmit the output signal of the first delay circuit or the output signal of the input buffer, and a second delay circuit that delays the input signal by the switch circuit , And compare the delay signal of each segment of the second delay circuit with the clock edge delayed by one clock from the clock signal input through the input buffer, and detect. Consistent, have the test results (read the precautions on the back before filling this page) -C. Ordering. This paper size is applicable to China National Standard (CNS) A4 (210X297mm) • 96- Central Standard of the Ministry of Economic Affairs Bureau employee consumer cooperatives printed B8 C8 D8 々, latch function of patent application Fanyuan, delay the output of the above paragraphs based on the test results Signal selection circuit: the switch circuit is connected to the first delay circuit side, a detection signal is formed by the edge detection circuit, the switch circuit is switched to the input buffer circuit side, and is held by the latch function As a result of the detection, the clock synchronization circuit that outputs the delay signal of the second delay circuit through the output driver is characterized in that the second delay circuit is provided with a plurality of inputs to be input to the first and second inputs. An impedance element coupled to the two input signals of the terminal is provided between the first and second input terminals, and a logic gate JI circuit of an output signal is formed in response to the input signals supplied to the first and second input terminals. The logic gate means can be arranged in a grid pattern in the first signal transmission direction and the second signal transmission direction, the K signal other than the first signal transmission direction in the first signal transmission direction, and the second signal transmission direction in the second signal transmission direction. The above-mentioned first input terminal of the logic gate circuit means KL of the L segment is the same Kth in the first signal transmission direction, and is presented in the second signal transmission direction. The output signal of the logic circuit of the L-1 segment or the input clock signal when the logic gate circuit of the first segment is supplied. The second input terminal of the above-mentioned logic gate circuit means KL is the first one in the direction of the first signal transmission. The K-1 of the input signal which is supplied to the first input terminal of the logic gate circuit in the same L-segment in the second transmission direction is supplied. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). (Mm) (Please read the precautions on the back before filling out this page.) The Central Bureau of Standards of the Ministry of Economic Affairs, Ace B8, C8, D8, Pak Consumer Cooperative 6. The scope of patent application, and the first signal transmission direction is the first The second input terminal of the logic gate circuit which is the L segment in the direction of the second signal transmission is the final stage in the direction of the first signal transmission, and the logic gate circuit which is more cancerous in the direction of the second signal transmission than the above The input signal supplied to the 1st input terminal supplied there is in the same phase relationship, and the input signal supplied to the 1st input terminal is in the first paragraph in the direction of the second signal transmission. Signal transmission The first and second input terminals of the logic gate circuit are supplied with clock signals corresponding to the input signals passing through the switch circuit, and are supplied from the second signal transmission direction in the first signal transmission direction. The input clock signals of the first input terminal of each logic gate circuit up to the last one are sequentially delayed in the first signal transmission direction, and the second signal transmission direction is at least a plurality of paragraphs, from The first signal transmission direction obtains an output signal from the output terminals of the plural logic gate circuits arranged. 40 types of clock synchronization circuits, including: an input buffer circuit that receives a clock signal supplied from an external terminal, and delays the clock signal passing through the input buffer corresponding to the input buffer and the output stage driver. The first delay circuit of the delay time of the delay time, and the two delay circuits that receive the output signal of the first delay circuit to delay it, and compare the delay signals of each segment of the second delay circuit with those described above (please first S Read the notes on the reverse side and fill in this page again.) The paper size of the booklet is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) -98- Printed by the Central Bureau of Standards of the Ministry of Economics, Printed by Baker Consumer Consumers Co., Ltd. 6 The patent signal scope input buffer is delayed by a clock edge of the clock signal, and the edge detection circuit that detects the edges at both ends in time is consistent, and when it is received through the input buffer, 3 delay circuits for which the pulse signal delays them, and the delay signals of the 3 delay circuits are passed through the detection result of the edge detection circuit. The clock synchronization circuit outputted from the segment driver is characterized in that the second and third delay circuits each include a plurality of impedance elements for coupling two input signals input to the first and second input terminals. A logic gate circuit is provided between the first and second input terminals and forms an output signal in response to the input signals supplied to the first and second input terminals. The plurality of logic gate circuits can be connected in the first signal transmission direction and The second signal transmission direction is arranged in a grid pattern, the first signal transmission direction is K-th in addition to the first, and the second signal transmission direction is disposed in the L-stage logic gate circuit means KL. The Kth input signal on the input terminal is the same in the first signal transmission direction, and the output _ signal of the logic gate circuit in the L-1 segment in the second signal transmission direction or the input clock is supplied in the first logic gate circuit. The second input terminal of the above-mentioned logic gate circuit means KL is the first K-1 of the first signal transmission direction, and the L-th stage of the fifth transmission phase is supplied to the logic gate circuit. 1st input The input signal is supplied, and it is the first in the direction of the first signal transmission, and the paper size in the second signal uses the Chinese National Standard (CNS) A4 specification (210X297 mm) -------- -r ------- Order ------ Γ line (Please read the note on the back before filling this page) -99-Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs B8 C8 D8 2. The second input terminal of the logic gate circuit with the L range in the patent application direction is the final stage in the first signal transmission direction. The logic gate circuit in the second signal transmission direction that is in the front stage is provided to the The input signal supplied to the first input terminal there is in-phase, and the input signal supplied to the first input terminal is in the first paragraph in the second signal transmission direction, and is supplied to the slave signal in the first signal transmission direction. The clock signal of the first input terminal of each logic gate circuit from the first to the last one is sequentially delayed in the first signal transmission direction, and the second signal transmission direction is at least a plurality of stages, From the plural logic arranged in the direction of signal transmission An output terminal of the gate circuit output signal is obtained. 4 1. A semiconductor integrated circuit device, comprising: a memory array of billions of bodies formed at the intersection of a complex digital line and a complex bit line, and a memory for selecting the billions of arrays Address selection circuit of somatic cell, and clock synchronization circuit for transmitting internal clock signal corresponding to external clock signal supplied from external terminal, and internal clock signal generated in accordance with the above clock synchronization signal An output circuit for outputting a read signal of the memory cell, the clock synchronization circuit includes: receiving a delayed first clock signal from a basic clock signal corresponding to the external clock signal, so that the propagation has a first clock signal; The first delay circuit of the above-mentioned first clock signal with time resolution and --------- r ------ IT ----- fiber cable (please read the precautions on the back before filling (This page) This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) -100 · Consumption cooperation between employees of the Central Bureau of Standards of the Ministry of Economic Affairs «. A8 B8 C8 D8 1 delayed electricity A first edge detection circuit that detects the time edges of the delay signals of the segments of the time resolution and the first clock edge of the basic clock signal, and detects the time edges of the two edges are consistent, and uses the first The detection signal of the 1 edge detection circuit is controlled, the first multiplexer of the delay signal corresponding to the delay section of the first delay circuit is selected, and the second clock received by the first multiplexer is received. The signal causes the second delay circuit to propagate the second clock signal having the time resolution energy with higher accuracy than the first time resolution energy, and compares the ends of the delay signals of the segments corresponding to the time resolution energy of the second delay circuit Edge, a second clock detection circuit that coincides in time with the second clock edge of the basic clock signal to detect both edges, and is controlled by the detection signal of the second clock detection circuit to select the second clock The second multiplexer of the delay signal corresponding to the delay section of the two delay circuits; the third clock signal obtained by the second multiplexer is formed to be the same as the external clock signal. The stepped clock synchronization circuit of the internal clock signal, and the second delay circuit includes: a plurality of impedance elements for coupling two input signals input to the first and second input terminals are provided in the first Between the second input terminal and the input signal supplied to the first and second input terminals, a logic gate circuit is formed as an output signal. The above plurality of logic gate circuits can be used in the direction of the first signal transmission and the paper scale. National Standard (CNS) A4 Specification (2! 0 × 297 mm) -101-(Please read the precautions on the back before filling this page) Thread I 央 橾 车 局 貝 工 A8 B8 C8 D8 消 費 合 作 社· 印 製 、申請專利範圍 第 2 訊 號 傳 達 方 向 上被配置爲格子狀 於 第 1 訊 號 傳 達 方 向 呈 第 1個 以 外 的 第 K 個 • 於 第 2 訊 號 傳 達 方 向 被 配 置 於 第 L 段 的邏 輯 閘 電 路 手 段 K L 的 上 述 第 1 輸. 入 端 子 上於 第 1 訊 號 傳達 方 向 呈 相 同 的 第 K 個 於 第 2 訊 號 傳 達 方 向 呈 第 L — 1段 的 邏 輯 閘 電 路 的 輸 出 訊 號 或 是 在 第 1 段 邏 輯丨 葡電路被供給輸入時脈訊號， η 上 述 趣 輯 閘 電 路 手 段 K L的 第 2 輸 入 端 子 在 第 1 訊 號 傳 達 方 向 呈 刖 1 個 之 第 K — 1個 在 第 2 傳 達 方· 向 呈 相 同 的 第 L 段 的 被 供 給 至 邏 輯 閘 電路 之 第 1 輸 入 端 子 的 輸 入 訊 號 被 供 給 > 而 且 於 第 1 訊 號 傳 達 方 向呈 第 1 個 於 第 2 訊 號 傳 達 方 向 呈 第 L 段 的 趣 輯 閘 電 路 的第2 輸 入 端 子 9 於 第 1 訊- P|M 傳 達 方 向 呈 最 終 段 於 上 述 第2 訊 號 傳 達 方 向 較 其、更 呈. 前 段 的 趣 輯 閘 電 路 被 供 給與被供 給 於 該 處 之 第 1 輸 入 端 子 的 輸 入 訊 號 成 爲 同 相 關 係 的 被供 給 至 第 1 輸 入 端 子 的 輸 入 訊 號 ， 於 上 述 第 2 訊 號 傳 達 方 向 呈第 1 段 於 第 1 訊 號 傳 達 方 向 從 第 1 個 直 到 最 後 —* 個 爲 止的 各 遲 輯 閘 手 段 的 第 1 輸 入 端 子 的 上 述 輸 入 時 脈 訊 號 係於 上 述 第 1 訊 Dfte 傳 達 方 向 依序被延 遲 者 > 由 在 上 述 第 2 訊 號 傳 達 方 向係 至 少 第 複 數 段 1 從 在 第 1 訊 號 傳 達 方 向 被 配 列 的 複 數 邏輯 閘 電 路 的 輸 出 端 子 獲 得 輸 出 訊 號 〇 4 2 • 如 串 請 專 利 範 圍 第 4 1 項 Z 導 體 積 體 電 路 裝 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -102- 經濟部中央標準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 置，其中，進而包含有： 被/構成爲與上述第1延遲電路相同的電路構成的第3 、第4延遲電路，及 對應於上述第3延遲電路而被設置的第3多路轉換器 ，及 被構成爲與上述第2延遲電路相同的電路構成的第5 延遲電路； 上述第1多路轉換器，係藉由上述第1端緣檢測電路 的檢測訊號而選擇上述第3延遲電路的各段的延遲訊號者 ，. 上述第3多路轉換器，係藉由上述第1端緣檢測電路 的檢測訊號而選擇上述第4延遲電路的各段的延遲訊號者 於上述第2.延遲電路的輸入，被供給上述第1多路轉 換器的輸出訊號，形成被供給至上述第2端緣檢測電路的 延遲訊號者， . 上述第2多路轉換器，係藉由上述第2端緣檢測電路 的檢測訊號而選擇上述第5延遲電路的各段的延遲訊號者 〇 4 3 .如申請專利範圍第42項之半導體積體電路裝 置，其中，於上述第3延遲電路的輸入，通過第1僞延遲 電路被供給輸入訊號， 上述，第1僞延遲電路的輸出.訊號係以使從上述第2延 遲電路被輸出的延遲訊號成爲指定段述以後的方.式通過以 (請先閱讀背面之注意事項再填寫本頁) 訂. 線· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） •103- A8 68 C8 D8 六、申請專利範圍 進行.設定的方式而調整時間的第2僞延遲電路被供給致上 .述第1延遲電路的輸入者。 4 4、如申請專利範圍第4 3項之半導體積體電路裝 置，其中，上述基本時脈訊號，係通過接受從外部_端子被 供給外部時脈訊號的輸入緩衝器電路而被輸入者， 上述.第1僞·延遲電路，係因應時脈授權（clockenable I / )訊號而被設爲動作狀態與非動作狀態，在非動作、狀態將 •輸出訊號固定於一方之位準， 上述第Γ與第2端緣檢測電路係分別於輸出部具備閂 鎖電跨保持檢測結果者。 4 5 .如申請專利範圍第43、4 4項之半導體積體 電舍裝置，其中，上述第1僞延遲電路以及第1與第2端 緣檢測電路，係藉由被內藏於上述半導體積體電路裝置的 計時電路以一定的週期產生的控制訊號被間歇地設於動作 狀態。 經濟部中央標準局員工消費合体社印製 4 6 .如申請專利範圍第4 0、4 1、4 2、4 3或 4 4項之半導體積體電路裝置，其中，對應於被以上述時 脈同步電路形成的內部時脈訊號的升起端緣與降下端緣的 雙方，而進行從外部輸入資料或是向外部輸出資料》 -104 - (請先閲請背面之注意事項再填寫本頁) 本紙張尺度逍用中國國家標準（CNS ) A4規格（210X297公釐）Yangye Automobile Bureau Beigong A8 B8 C8 D8 Consumer Cooperative · Printed and patented. The second signal transmission direction is arranged in a grid pattern. The first signal transmission direction is the Kth other than the first one. • The second signal The transmission direction is the above-mentioned first input of the logic gate circuit means KL of the L segment. The input terminal is the same as the Kth logic gate on the first signal transmission direction and the Lth and 1th logic gate on the second signal transmission direction. The output signal of the circuit or the clock signal is supplied in the first stage logic. The Portuguese circuit is supplied with the input clock signal. Η The second input terminal of the above-mentioned interesting gate circuit means KL is 刖 1 K-1 in the first signal transmission direction. On the second transmitting side, the input signal to the first input terminal supplied to the logic gate circuit in the same L segment is supplied > and the first signal is transmitted in the first signal transmitting direction. The 2nd signal transmission direction is the second input terminal 9 of the fun gate circuit in the L segment. The 1st signal-P | M transmission direction is the final segment in the above 2nd signal transmission direction. The gate circuit is supplied with the input signal of the first input terminal supplied there. The input signal supplied to the first input terminal is in the same phase as the first signal transmission direction in the second signal transmission direction. The above-mentioned input clock signal of the first input terminal of each of the delayed gate means from the first to the last— * is delayed by the first signal Dfte in the transmission direction in sequence >> It is transmitted by the second signal The direction is at least the first plural segment. 1 The output signal is obtained from the output terminal of the complex gate circuit arranged in the first signal transmission direction. 4 2 • Please refer to item 41 of the scope of patents. Z-lead volume circuit assembly. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The scope of the patent application further includes: a third and a fourth delay circuit which are configured as the same circuit as the first delay circuit, and a third multiplexer provided corresponding to the third delay circuit. A converter, and a fifth delay circuit configured as the same circuit as the second delay circuit; the first multiplexer selects the third delay based on a detection signal from the first edge detection circuit; The delay signal of each segment of the circuit. The third multiplexer is selected by the detection signal of the first edge detection circuit and the delay signal of each segment of the fourth delay circuit is in the second. The input of the delay circuit is supplied to the output signal of the first multiplexer to form a delay signal to be supplied to the second edge detection circuit. The second The circuit converter is based on the detection signal of the second edge detection circuit and selects the delay signal of each segment of the fifth delay circuit. 4 3. For example, the semiconductor integrated circuit device of the 42nd patent application scope, where The input to the third delay circuit is supplied with an input signal through the first pseudo delay circuit, and the output and signal of the first pseudo delay circuit are such that the delay signal output from the second delay circuit becomes a specified paragraph. The future method is to order by (please read the precautions on the back before filling this page). Thread · This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) • 103- A8 68 C8 D8 VI. The scope of the patent application is performed. The second pseudo-delay circuit that adjusts the time in a set manner is supplied to the above-mentioned input person of the first delay circuit. 4 4. The semiconductor integrated circuit device according to item 43 of the scope of patent application, wherein the basic clock signal is input by receiving an input buffer circuit that is supplied with an external clock signal from an external terminal. The first pseudo-delay circuit is set to the operating state and the non-acting state in response to the clockenable I / signal. In the non-acting and state, the output signal is fixed at one level. The second edge detection circuits are each provided with a latch electric span holding detection result in the output section. 4 5. The semiconductor integrated electric house device as claimed in claims 43 and 44, wherein the first pseudo-delay circuit and the first and second edge detection circuits are built into the semiconductor product. The timing circuit of the body circuit device is intermittently set to an operating state with a control signal generated at a certain period. Printed by the Consumer Standards Agency of the Central Bureau of Standards of the Ministry of Economic Affairs 46. For example, the semiconductor integrated circuit device with the scope of application for patents No. 40, 4 1, 4, 2, 3, or 44, corresponding to the above-mentioned clock Both the rising and falling edges of the internal clock signal formed by the synchronization circuit are used to input or output data from the outside. -104-(Please read the precautions on the back before filling this page) The paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm)
TW087109413A 1997-07-04 1998-06-12 Semiconductor integrated circuit device, semiconductor memory system, and clock synchronization circuit TW378351B (en)

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