TW360949B - Dual damascene process - Google Patents
Dual damascene processInfo
- Publication number
- TW360949B TW360949B TW086119307A TW86119307A TW360949B TW 360949 B TW360949 B TW 360949B TW 086119307 A TW086119307 A TW 086119307A TW 86119307 A TW86119307 A TW 86119307A TW 360949 B TW360949 B TW 360949B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- forming
- photoresist layer
- covering
- hydrogentrioxy
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A dual damascene process comprises providing a semiconductor substrate, forming a semiconductor element thereon, and forming a first photoresist layer covering one contact of the semiconductor element; forming a first hydrogentrioxy silane layer covering the semiconductor element, and forming a first oxide layer covering the first hydrogentrioxy silane layer and the first photoresist layer, and performing a polishing step enabling the surface of the first oxide layer and the surface of the first photoresist layer having a same height, forming a second photoresist layer covering the first photoresist layer, and forming a second hydrogentrioxy silane layer covering the first oxide layer, forming a second oxide layer covering the second hydrogentrioxy silane layer and the second photoresist layer, and performing a polishing step enabling the surface of the second oxide layer and the surface of the second photoresist layer having a same height, next sequentially removing the second photoresist layer and the first photoresist layer thereby exposing an opening, forming a barrier adhesive layer covering the sidewall and the bottom of the opening, and forming a metal layer covering the barrier adhesive layer and filling up the opening, and finally performing a polishing step enabling the surface of the metal layer and the surface of the second oxide layer having a same height.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW086119307A TW360949B (en) | 1997-12-19 | 1997-12-19 | Dual damascene process |
| JP13531598A JPH11186274A (en) | 1997-12-19 | 1998-05-18 | Dual damascene technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW086119307A TW360949B (en) | 1997-12-19 | 1997-12-19 | Dual damascene process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW360949B true TW360949B (en) | 1999-06-11 |
Family
ID=21627447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW086119307A TW360949B (en) | 1997-12-19 | 1997-12-19 | Dual damascene process |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11186274A (en) |
| TW (1) | TW360949B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044202A (en) | 1999-07-30 | 2001-02-16 | Nec Corp | Semiconductor device and manufacture thereof |
| KR100346830B1 (en) * | 1999-09-29 | 2002-08-03 | 삼성전자 주식회사 | Method of manufacturing electrical interconnection for semiconductor device |
| JP2004304162A (en) | 2003-03-17 | 2004-10-28 | Seiko Epson Corp | Method of forming contact hole, method of manufacturing thin film semiconductor device, electronic device and method of manufacturing the same |
| JP4889933B2 (en) * | 2003-10-02 | 2012-03-07 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor element |
| WO2011018857A1 (en) | 2009-08-14 | 2011-02-17 | 富士通セミコンダクター株式会社 | Method for manufacturing semiconductor device |
-
1997
- 1997-12-19 TW TW086119307A patent/TW360949B/en active
-
1998
- 1998-05-18 JP JP13531598A patent/JPH11186274A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11186274A (en) | 1999-07-09 |
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