TW352449B - Method and apparatus for making single chip, contactless window ROM - Google Patents

Method and apparatus for making single chip, contactless window ROM

Info

Publication number
TW352449B
TW352449B TW086110768A TW86110768A TW352449B TW 352449 B TW352449 B TW 352449B TW 086110768 A TW086110768 A TW 086110768A TW 86110768 A TW86110768 A TW 86110768A TW 352449 B TW352449 B TW 352449B
Authority
TW
Taiwan
Prior art keywords
single chip
making single
contactless
rom
cell array
Prior art date
Application number
TW086110768A
Other languages
English (en)
Inventor
Yoshiaki Hisamune
Original Assignee
Nippon Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW352449B publication Critical patent/TW352449B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
TW086110768A 1996-07-30 1997-07-29 Method and apparatus for making single chip, contactless window ROM TW352449B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20072896 1996-07-30
JP11082097A JP3075211B2 (ja) 1996-07-30 1997-04-28 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
TW352449B true TW352449B (en) 1999-02-11

Family

ID=26450352

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086110768A TW352449B (en) 1996-07-30 1997-07-29 Method and apparatus for making single chip, contactless window ROM

Country Status (5)

Country Link
US (2) US6121670A (zh)
EP (1) EP0822598A1 (zh)
JP (1) JP3075211B2 (zh)
KR (1) KR100286733B1 (zh)
TW (1) TW352449B (zh)

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KR100290787B1 (ko) * 1998-12-26 2001-07-12 박종섭 반도체 메모리 소자의 제조방법
US6901006B1 (en) * 1999-07-14 2005-05-31 Hitachi, Ltd. Semiconductor integrated circuit device including first, second and third gates
US6275414B1 (en) * 2000-05-16 2001-08-14 Advanced Micro Devices, Inc. Uniform bitline strapping of a non-volatile memory cell
KR100379506B1 (ko) * 2000-07-19 2003-04-10 주식회사 하이닉스반도체 비휘발성 메모리 소자의 제조방법
JP2002050705A (ja) 2000-08-01 2002-02-15 Fujitsu Ltd 半導体記憶装置及びその製造方法
US6570810B2 (en) 2001-04-20 2003-05-27 Multi Level Memory Technology Contactless flash memory with buried diffusion bit/virtual ground lines
US7061801B1 (en) 2001-04-20 2006-06-13 Samsung Electronics Co., Ltd. Contactless bidirectional nonvolatile memory
KR100416599B1 (ko) * 2001-05-31 2004-02-05 삼성전자주식회사 집적도와 독출동작 속도를 향상시키고 전력소모를감소시킬 수 있는 메탈 프로그래머블 롬의 메모리셀 구조
US6480422B1 (en) 2001-06-14 2002-11-12 Multi Level Memory Technology Contactless flash memory with shared buried diffusion bit line architecture
KR100438403B1 (ko) * 2001-09-05 2004-07-02 동부전자 주식회사 플랫 셀 메모리 소자의 제조방법
EP1363324A1 (en) * 2002-05-16 2003-11-19 STMicroelectronics S.r.l. Method for manufacturing non-volatile memory device
US6962852B2 (en) * 2003-03-19 2005-11-08 Promos Technologies Inc. Nonvolatile memories and methods of fabrication
US6995060B2 (en) * 2003-03-19 2006-02-07 Promos Technologies Inc. Fabrication of integrated circuit elements in structures with protruding features
US6962851B2 (en) * 2003-03-19 2005-11-08 Promos Technologies, Inc. Nonvolatile memories and methods of fabrication
US6974739B2 (en) * 2003-05-16 2005-12-13 Promos Technologies Inc. Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit
US7214585B2 (en) * 2003-05-16 2007-05-08 Promos Technologies Inc. Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges
US6902974B2 (en) * 2003-05-16 2005-06-07 Promos Technologies Inc. Fabrication of conductive gates for nonvolatile memories from layers with protruding portions
US7101757B2 (en) * 2003-07-30 2006-09-05 Promos Technologies, Inc. Nonvolatile memory cells with buried channel transistors
US7060565B2 (en) * 2003-07-30 2006-06-13 Promos Technologies Inc. Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates
US7052947B2 (en) * 2003-07-30 2006-05-30 Promos Technologies Inc. Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates
US7169667B2 (en) * 2003-07-30 2007-01-30 Promos Technologies Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate
US6951782B2 (en) * 2003-07-30 2005-10-04 Promos Technologies, Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions
US6885044B2 (en) * 2003-07-30 2005-04-26 Promos Technologies, Inc. Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates
US6992929B2 (en) * 2004-03-17 2006-01-31 Actrans System Incorporation, Usa Self-aligned split-gate NAND flash memory and fabrication process
JP4566086B2 (ja) 2005-03-31 2010-10-20 富士通セミコンダクター株式会社 半導体装置の製造方法
CN1851922B (zh) 2005-04-22 2011-05-11 松下电器产业株式会社 半导体装置及其制造方法
KR100680455B1 (ko) * 2005-06-30 2007-02-08 주식회사 하이닉스반도체 Ｎａｎｄ형 플래쉬 메모리 소자, 그 제조 방법 및 그 구동방법
KR100851756B1 (ko) * 2007-06-08 2008-08-11 주식회사 동부하이텍 이미지 센서 및 그 제조방법
JP2012199313A (ja) * 2011-03-18 2012-10-18 Toshiba Corp 不揮発性半導体記憶装置
US10535670B2 (en) * 2016-02-25 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same

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JPS60223165A (ja) * 1984-04-19 1985-11-07 Toshiba Corp 半導体装置の製造方法
US4561170A (en) * 1984-07-02 1985-12-31 Texas Instruments Incorporated Method of making field-plate isolated CMOS devices
JPH0821682B2 (ja) * 1987-04-24 1996-03-04 株式会社日立製作所 半導体装置の製造方法
US4882294A (en) * 1988-08-17 1989-11-21 Delco Electronics Corporation Process for forming an epitaxial layer having portions of different thicknesses
JP2523409B2 (ja) * 1990-05-02 1996-08-07 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2651044B2 (ja) * 1990-10-29 1997-09-10 松下電子工業株式会社 半導体記憶装置の製造方法
JPH04164372A (ja) * 1990-10-29 1992-06-10 Toshiba Corp 半導体集積回路
JP2853426B2 (ja) * 1991-12-20 1999-02-03 日本電気株式会社 半導体記憶装置の製造方法
US5346842A (en) * 1992-02-04 1994-09-13 National Semiconductor Corporation Method of making alternate metal/source virtual ground flash EPROM cell array
JPH06283721A (ja) * 1992-03-06 1994-10-07 Oko Denshi Kofun Yugenkoshi 不揮発性メモリ・セル、アレー装置、製造方法、及びそのメモリ回路
DE69313816T2 (de) * 1993-02-11 1998-03-26 St Microelectronics Srl EEPROM-Zelle und peripherer MOS-Transistor
JPH06349826A (ja) * 1993-04-13 1994-12-22 Toshiba Corp 半導体装置およびその製造方法
JPH06334155A (ja) * 1993-05-27 1994-12-02 Sharp Corp 半導体記憶装置およびその製造方法
JP3307496B2 (ja) * 1993-12-27 2002-07-24 三菱電機株式会社 不揮発性半導体記憶装置の製造方法
JPH07240473A (ja) * 1994-03-01 1995-09-12 Fujitsu Ltd 半導体記憶装置およびその製造方法
US5661053A (en) * 1994-05-25 1997-08-26 Sandisk Corporation Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
US5828120A (en) * 1996-02-23 1998-10-27 Nippon Steel Corporation Semiconductor device and production method thereof
US5886376A (en) * 1996-07-01 1999-03-23 International Business Machines Corporation EEPROM having coplanar on-insulator FET and control gate
US5780340A (en) * 1996-10-30 1998-07-14 Advanced Micro Devices, Inc. Method of forming trench transistor and isolation trench

Also Published As

Publication number Publication date
JPH1098170A (ja) 1998-04-14
KR980012635A (ko) 1998-04-30
US6121670A (en) 2000-09-19
EP0822598A1 (en) 1998-02-04
JP3075211B2 (ja) 2000-08-14
KR100286733B1 (ko) 2001-09-07
US6214669B1 (en) 2001-04-10

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