TW351812B - Procedures for entry to and exit from a built-in-self-test unit in a semiconductor memory - Google Patents

Procedures for entry to and exit from a built-in-self-test unit in a semiconductor memory

Info

Publication number
TW351812B
TW351812B TW086105237A TW86105237A TW351812B TW 351812 B TW351812 B TW 351812B TW 086105237 A TW086105237 A TW 086105237A TW 86105237 A TW86105237 A TW 86105237A TW 351812 B TW351812 B TW 351812B
Authority
TW
Taiwan
Prior art keywords
enable signal
entry
built
self
generating unit
Prior art date
Application number
TW086105237A
Other languages
Chinese (zh)
Inventor
Kuong-Hua Hii
Danny R Cline
Theo L Powell
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW351812B publication Critical patent/TW351812B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

An entry and exit control circuit employed to execute a built-in-self-test in a semiconductor memory, the control circuit includes: an enable signal generating unit; an overvoltage detecting device linked with the terminal of the semiconductor unit, the said overvoltage detecting device will employ a first signal to the enable signal generating unit in response to the overvoltage on the said terminal, the said first signal and the said enable signal generating unit enter a waiting mode, and when the overvoltage employed on the said terminal changes from the first mode to the second mode, the control signal detecting unit will apply the second signal to the enable signal generator to create enable signal from the enable signal generating unit while in a waiting mode.
TW086105237A 1996-04-29 1997-04-23 Procedures for entry to and exit from a built-in-self-test unit in a semiconductor memory TW351812B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1640696P 1996-04-29 1996-04-29

Publications (1)

Publication Number Publication Date
TW351812B true TW351812B (en) 1999-02-01

Family

ID=21776972

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105237A TW351812B (en) 1996-04-29 1997-04-23 Procedures for entry to and exit from a built-in-self-test unit in a semiconductor memory

Country Status (3)

Country Link
JP (1) JPH1055700A (en)
KR (1) KR970071845A (en)
TW (1) TW351812B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7005873B2 (en) * 2002-12-31 2006-02-28 Agere Systems Inc. Built-in self-test hierarchy for an integrated circuit

Also Published As

Publication number Publication date
KR970071845A (en) 1997-11-07
JPH1055700A (en) 1998-02-24

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