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A trench isolation method for a semiconductor device, which comprises the following steps: (a) sequentially forming a pad layer, a mask layer and a buffer layer on a semiconductor substrate; (b) adding a pattern to the buffer layer, the mask layer and the pad layer, thereby forming a buffer layer pattern, a mask layer pattern and a pad layer pattern, which define an active region; (c) removing the buffer layer pattern; (d) etching the semiconductor substrate to a predetermined depth, using the mask layer pattern as the mask thereby forming a trench region; (e) forming an oxide layer on the inner wall of the trench region and the surface of the mask layer pattern; (f) depositing an insulation material layer for filling the trench region; (g) annealing the insulation material layer at 1,000 to 1,400 DEG C for 0.5 to 8 hours thereby densifying the insulation material layer; (h) planarizing the insulation material layer and the oxide layer by using a chemical mechanical polishing method until exposing the mask layer pattern; and (i) sequentially removing the mask layer pattern and the pad layer pattern.
TW085112289A1996-05-211996-10-08Trench isolation method for semiconductor device
TW349261B
(en)
Method for manufacturing shallow trench isolation structure without producing microscratches on surface of shallow trench isolation structure (revised edition)