TW348234B - A data processing system having a self-aligning stack pointer and method therefor - Google Patents

A data processing system having a self-aligning stack pointer and method therefor

Info

Publication number
TW348234B
TW348234B TW086101555A TW86101555A TW348234B TW 348234 B TW348234 B TW 348234B TW 086101555 A TW086101555 A TW 086101555A TW 86101555 A TW86101555 A TW 86101555A TW 348234 B TW348234 B TW 348234B
Authority
TW
Taiwan
Prior art keywords
data processing
processing system
stack pointer
self
method therefor
Prior art date
Application number
TW086101555A
Other languages
English (en)
Inventor
C Circello Joseph
Gokingco Jefferson
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW348234B publication Critical patent/TW348234B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
TW086101555A 1996-04-15 1997-02-12 A data processing system having a self-aligning stack pointer and method therefor TW348234B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/632,187 US5761491A (en) 1996-04-15 1996-04-15 Data processing system and method for storing and restoring a stack pointer

Publications (1)

Publication Number Publication Date
TW348234B true TW348234B (en) 1998-12-21

Family

ID=24534453

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101555A TW348234B (en) 1996-04-15 1997-02-12 A data processing system having a self-aligning stack pointer and method therefor

Country Status (8)

Country Link
US (1) US5761491A (zh)
EP (1) EP0802481A1 (zh)
JP (1) JP3707581B2 (zh)
KR (1) KR100440361B1 (zh)
CN (1) CN1168505A (zh)
IE (1) IE970146A1 (zh)
IL (1) IL120665A0 (zh)
TW (1) TW348234B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761491A (en) * 1996-04-15 1998-06-02 Motorola Inc. Data processing system and method for storing and restoring a stack pointer
US5983370A (en) * 1996-10-30 1999-11-09 Texas Instruments Incorporated Four state token passing alignment fault state circuit for microprocessor address misalignment fault generation having combined read/write port
US6317796B1 (en) * 1997-10-06 2001-11-13 Sun Microsystems, Inc. Inline database for receiver types in object-oriented systems
US6009517A (en) 1997-10-06 1999-12-28 Sun Microsystems, Inc. Mixed execution stack and exception handling
US6065110A (en) * 1998-02-09 2000-05-16 International Business Machines Corporation Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue
US6341344B1 (en) * 1998-03-20 2002-01-22 Texas Instruments Incorporated Apparatus and method for manipulating data for aligning the stack memory
US20010049710A1 (en) * 2000-05-16 2001-12-06 Curey Randall K. Partitioned executive structure for real-time programs
GB2369464B (en) * 2000-11-27 2005-01-05 Advanced Risc Mach Ltd A data processing apparatus and method for saving return state
US7340495B2 (en) * 2001-10-29 2008-03-04 Intel Corporation Superior misaligned memory load and copy using merge hardware
US7437537B2 (en) * 2005-02-17 2008-10-14 Qualcomm Incorporated Methods and apparatus for predicting unaligned memory access
US20070061551A1 (en) * 2005-09-13 2007-03-15 Freescale Semiconductor, Inc. Computer Processor Architecture Comprising Operand Stack and Addressable Registers
US20080162522A1 (en) * 2006-12-29 2008-07-03 Guei-Yuan Lueh Methods and apparatuses for compaction and/or decompaction
US20080162879A1 (en) * 2006-12-29 2008-07-03 Hong Jiang Methods and apparatuses for aligning and/or executing instructions
GB2471138B (en) * 2009-06-19 2014-08-13 Advanced Risc Mach Ltd Handling integer and floating point registers during a context switch
GB2478733B (en) * 2010-03-15 2013-08-14 Advanced Risc Mach Ltd Apparatus and method for handling exception events
GB2482710A (en) * 2010-08-12 2012-02-15 Advanced Risc Mach Ltd Enabling stack access alignment checking independently of other memory access alignment checking
US20230195470A1 (en) * 2021-12-22 2023-06-22 Vmware, Inc. Behavioral implementation of a double fault stack in a computer system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN150275B (zh) * 1977-10-25 1982-08-28 Digital Equipment Corp
US4250546A (en) * 1978-07-31 1981-02-10 Motorola, Inc. Fast interrupt method
JPS57196357A (en) * 1981-05-29 1982-12-02 Toshiba Corp Data processor
US4488227A (en) * 1982-12-03 1984-12-11 Honeywell Information Systems Inc. Program counter stacking method and apparatus for nested subroutines and interrupts
EP0153764B1 (en) * 1984-03-02 1993-11-03 Nec Corporation Information processor having an interruption operating function
US5201043A (en) * 1989-04-05 1993-04-06 Intel Corporation System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking
US5640548A (en) * 1992-10-19 1997-06-17 Motorola, Inc. Method and apparatus for unstacking registers in a data processing system
US5481719A (en) * 1994-09-09 1996-01-02 International Business Machines Corporation Exception handling method and apparatus for a microkernel data processing system
US5634046A (en) * 1994-09-30 1997-05-27 Microsoft Corporation General purpose use of a stack pointer register
US5761491A (en) * 1996-04-15 1998-06-02 Motorola Inc. Data processing system and method for storing and restoring a stack pointer

Also Published As

Publication number Publication date
KR100440361B1 (ko) 2004-10-12
IL120665A0 (en) 1997-08-14
JPH1083305A (ja) 1998-03-31
IE970146A1 (en) 1997-10-22
KR970071301A (ko) 1997-11-07
US5761491A (en) 1998-06-02
CN1168505A (zh) 1997-12-24
JP3707581B2 (ja) 2005-10-19
EP0802481A1 (en) 1997-10-22

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees