TW337036B - Poly-wafer stacked package - Google Patents

Poly-wafer stacked package

Info

Publication number
TW337036B
TW337036B TW086113708A TW86113708A TW337036B TW 337036 B TW337036 B TW 337036B TW 086113708 A TW086113708 A TW 086113708A TW 86113708 A TW86113708 A TW 86113708A TW 337036 B TW337036 B TW 337036B
Authority
TW
Taiwan
Prior art keywords
poly
wafer
stacked package
wafer stacked
backing
Prior art date
Application number
TW086113708A
Other languages
Chinese (zh)
Inventor
Jiann-Tuo Perng
Original Assignee
Utron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Utron Technology Inc filed Critical Utron Technology Inc
Priority to TW086113708A priority Critical patent/TW337036B/en
Application granted granted Critical
Publication of TW337036B publication Critical patent/TW337036B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

A poly-wafer stacked package, which comprises: a backing as the packaging substrate; a first wafer the electric circuit ends of which are directly coupled to the backing by solder balls; and a second wafer located on the first wafer, the electric circuit end of which is coupled to the backing by wiring.
TW086113708A 1997-09-19 1997-09-19 Poly-wafer stacked package TW337036B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW086113708A TW337036B (en) 1997-09-19 1997-09-19 Poly-wafer stacked package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086113708A TW337036B (en) 1997-09-19 1997-09-19 Poly-wafer stacked package

Publications (1)

Publication Number Publication Date
TW337036B true TW337036B (en) 1998-07-21

Family

ID=58263183

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113708A TW337036B (en) 1997-09-19 1997-09-19 Poly-wafer stacked package

Country Status (1)

Country Link
TW (1) TW337036B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951774B2 (en) 2001-04-06 2005-10-04 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US7919873B2 (en) 2001-09-17 2011-04-05 Megica Corporation Structure of high performance combo chip and processing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951774B2 (en) 2001-04-06 2005-10-04 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US7919873B2 (en) 2001-09-17 2011-04-05 Megica Corporation Structure of high performance combo chip and processing method
US7960842B2 (en) 2001-09-17 2011-06-14 Megica Corporation Structure of high performance combo chip and processing method
US7960212B2 (en) 2001-09-17 2011-06-14 Megica Corporation Structure of high performance combo chip and processing method
US8124446B2 (en) 2001-09-17 2012-02-28 Megica Corporation Structure of high performance combo chip and processing method

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