TW332296B - Non-volatile semiconductor memory having read-line selection transistor with shrunk area of selection transistor - Google Patents

Abstract

A semiconductor memory at least comprises: (1) A first bit line, a second bit line, and a third bit line formed in parallel, word lines formed perpendicular to the first to third bit lines; (2) A first memory transistor with its source-drain path formed between the first bit line and the second bit line, with its gate connected to the word line, and a second memory transistor with its source-drain path formed between the first second bit line and the third bit line, and with its gate connected to the word line; (3) A first selection transistor with its source-drain path formed between the first node and one end part of the first bit line and its gate connected to a first selection line, a second selection transistor with its source-drain path formed between the first node and one end part of the second bit line and its gate connected to a second selection line, a third selection transistor with its source-drain path formed between the second node and another end part of the second bit line and its gate connected to the third selection line, and a fourth selection transistor with its source-drain formed between the second node and another end part of the third bit line and its gate connected to the fourth selection line, at least source-drain path orientation of the second and third selection transistors parallel to the word line.