TW328635B - The manufacturing method for IC with twin-well process - Google Patents
The manufacturing method for IC with twin-well processInfo
- Publication number
- TW328635B TW328635B TW085111982A TW85111982A TW328635B TW 328635 B TW328635 B TW 328635B TW 085111982 A TW085111982 A TW 085111982A TW 85111982 A TW85111982 A TW 85111982A TW 328635 B TW328635 B TW 328635B
- Authority
- TW
- Taiwan
- Prior art keywords
- silicon
- photoresist pattern
- nitride
- well
- alignment mark
- Prior art date
Links
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
A manufacturing method for IC with twin-well process includes the following steps: (a) Form silicon-oxide pad and silicon-nitride on P-type Si semiconductor substrate; (b) Use lithography technology to form alignment mark photoresist pattern; (c) Use alignment mark photoresist pattern as mask, and use etching technology to etch silicon-nitride of alignment mark field to form silicon-nitride alignment mark, and the field besides alignment mark field is the P-type Si semiconductor substrate covered by silicon-nitride; (d) Remove alignment mark photoresist pattern; (e) Use lithography technology to form N-well photoresist pattern on well-region; (f) Use N-well photoresist pattern as ion implantation mask, and through silicon-nitride and silicon-oxide pad layer to proceed N-type ion implantation to form N doped region on P-type substrate; (g) Remove N-well photoresist pattern; (h) Use lithography technology to form P-well photoresist pattern on well-region; (i) Use P-well photoresist pattern as ion implantation mask, and through silicon-nitride and silicon-oxide pad layer to proceed P-type ion implantation to form P doped region on P-type substrate; (j) Remove P-well photoresist pattern; (k) Use lithography technology to form active area photoresist pattern on P-type Si substrate, and the portion of silicon-nitride is exposed by active area photoresist pattern at well-region; (l) Use active area photoresist pattern as etching mask, and use plasma etching technology to etch portion of exposed silicon-nitride to form opening; (m) At oxygen-contained & high-temperature environment, use residual silicon-nitride as oxidation mask to form field oxide on opening region, and simultaneously to finish the deep implantation driving-in; (n) Remove residual silicon-nitride and silicon-oxide pad layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW085111982A TW328635B (en) | 1996-10-01 | 1996-10-01 | The manufacturing method for IC with twin-well process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW085111982A TW328635B (en) | 1996-10-01 | 1996-10-01 | The manufacturing method for IC with twin-well process |
Publications (1)
Publication Number | Publication Date |
---|---|
TW328635B true TW328635B (en) | 1998-03-21 |
Family
ID=58262449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085111982A TW328635B (en) | 1996-10-01 | 1996-10-01 | The manufacturing method for IC with twin-well process |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW328635B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6391700B1 (en) * | 2000-10-17 | 2002-05-21 | United Microelectronics Corp. | Method for forming twin-well regions of semiconductor devices |
-
1996
- 1996-10-01 TW TW085111982A patent/TW328635B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6391700B1 (en) * | 2000-10-17 | 2002-05-21 | United Microelectronics Corp. | Method for forming twin-well regions of semiconductor devices |
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