TW328635B - The manufacturing method for IC with twin-well process - Google Patents

Abstract

A manufacturing method for IC with twin-well process includes the following steps: (a) Form silicon-oxide pad and silicon-nitride on P-type Si semiconductor substrate; (b) Use lithography technology to form alignment mark photoresist pattern; (c) Use alignment mark photoresist pattern as mask, and use etching technology to etch silicon-nitride of alignment mark field to form silicon-nitride alignment mark, and the field besides alignment mark field is the P-type Si semiconductor substrate covered by silicon-nitride; (d) Remove alignment mark photoresist pattern; (e) Use lithography technology to form N-well photoresist pattern on well-region; (f) Use N-well photoresist pattern as ion implantation mask, and through silicon-nitride and silicon-oxide pad layer to proceed N-type ion implantation to form N doped region on P-type substrate; (g) Remove N-well photoresist pattern; (h) Use lithography technology to form P-well photoresist pattern on well-region; (i) Use P-well photoresist pattern as ion implantation mask, and through silicon-nitride and silicon-oxide pad layer to proceed P-type ion implantation to form P doped region on P-type substrate; (j) Remove P-well photoresist pattern; (k) Use lithography technology to form active area photoresist pattern on P-type Si substrate, and the portion of silicon-nitride is exposed by active area photoresist pattern at well-region; (l) Use active area photoresist pattern as etching mask, and use plasma etching technology to etch portion of exposed silicon-nitride to form opening; (m) At oxygen-contained & high-temperature environment, use residual silicon-nitride as oxidation mask to form field oxide on opening region, and simultaneously to finish the deep implantation driving-in; (n) Remove residual silicon-nitride and silicon-oxide pad layer.