TW326532B - Method and apparatus for proving erasing and programming protection for EEPROM - Google Patents

Method and apparatus for proving erasing and programming protection for EEPROM

Info

Publication number
TW326532B
TW326532B TW086102220A TW86102220A TW326532B TW 326532 B TW326532 B TW 326532B TW 086102220 A TW086102220 A TW 086102220A TW 86102220 A TW86102220 A TW 86102220A TW 326532 B TW326532 B TW 326532B
Authority
TW
Taiwan
Prior art keywords
value
electrically erasable
enable
charge pump
array
Prior art date
Application number
TW086102220A
Other languages
Chinese (zh)
Inventor
L Espinor George
I Catherwood Michael
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW326532B publication Critical patent/TW326532B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)
  • Storage Device Security (AREA)

Abstract

A method to operate electrically erasable PRAM array includes receiving the erase or clean requirement of electrically erasable PROM array, and a series of processes to erase or program electrically erasable PRAM array. The series of processes to erase or program electrically erasable PROM array includes: 1) to enable a read access and a block protect value of a block protect buffer; 2) to inhibit erasing or programming process in electrically erasable PROM array when the block protect value is the first value; 3) to enable subsequent process in electrically erasable PROM array when the block protect value is the second value; 3) to enable a write access of the charge pump to provide a charge pump enable value; to enable charge pump if the charge pump enable value is right.
TW086102220A 1996-05-10 1997-02-24 Method and apparatus for proving erasing and programming protection for EEPROM TW326532B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/644,098 US5890191A (en) 1996-05-10 1996-05-10 Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory

Publications (1)

Publication Number Publication Date
TW326532B true TW326532B (en) 1998-02-11

Family

ID=24583447

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086102220A TW326532B (en) 1996-05-10 1997-02-24 Method and apparatus for proving erasing and programming protection for EEPROM

Country Status (4)

Country Link
US (1) US5890191A (en)
EP (1) EP0806772A3 (en)
JP (1) JPH1050078A (en)
TW (1) TW326532B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3173407B2 (en) * 1997-02-05 2001-06-04 日本電気株式会社 Microcomputer with built-in flash EEPROM
US6094651A (en) * 1997-08-22 2000-07-25 International Business Machines Corporation Discovery-driven exploration of OLAP data cubes
FR2770327B1 (en) * 1997-10-24 2000-01-14 Sgs Thomson Microelectronics ELECTRICALLY PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY INCLUDING A PROTECTIVE AREA FOR READING AND / OR WRITING AND ELECTRONIC SYSTEM INCORPORATING THE SAME
US6823435B1 (en) 1997-11-20 2004-11-23 Advanced Micro Devices, Inc. Non-volatile memory system having a programmably selectable boot code section size
FR2771839B1 (en) * 1997-11-28 2000-01-28 Sgs Thomson Microelectronics PROGRAMMABLE AND ELECTRICALLY ERASABLE NON-VOLATILE MEMORY
US6571268B1 (en) 1998-10-06 2003-05-27 Texas Instruments Incorporated Multiplier accumulator circuits
FR2788875B1 (en) * 1999-01-22 2001-03-30 Commissariat Energie Atomique DEVICE AND METHOD FOR TESTING A REPROGRAMMABLE NON-VOLATILE MEMORY
US7549056B2 (en) 1999-03-19 2009-06-16 Broadcom Corporation System and method for processing and protecting content
US7810152B2 (en) 2002-05-08 2010-10-05 Broadcom Corporation System and method for securely controlling access to device functions
US6789159B1 (en) 2002-05-08 2004-09-07 Broadcom Corporation System and method for programming non-volatile memory
US6654847B1 (en) 2000-06-30 2003-11-25 Micron Technology, Inc. Top/bottom symmetrical protection scheme for flash
WO2001075893A2 (en) * 2000-03-30 2001-10-11 Micron Technology, Inc. Symmetrical protection scheme for first and last sectors of synchronous flash memory
FR2811164B1 (en) * 2000-06-30 2003-08-29 St Microelectronics Sa INTEGRATED CIRCUIT WITH PROTECTION DEVICE
JP4671512B2 (en) * 2001-02-01 2011-04-20 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory
US6633964B2 (en) * 2001-03-30 2003-10-14 Intel Corporation Method and system using a virtual lock for boot block flash
US6772307B1 (en) 2001-06-11 2004-08-03 Intel Corporation Firmware memory having multiple protected blocks
DE10162308A1 (en) * 2001-12-19 2003-07-03 Philips Intellectual Property Method and arrangement for controlling access to EEPROMs and a corresponding computer program product and a corresponding computer-readable storage medium
EP1392052A1 (en) * 2002-05-08 2004-02-25 Broadcom Corporation System and method for secure controlling the configuration of device functions
US7187600B2 (en) * 2004-09-22 2007-03-06 Freescale Semiconductor, Inc. Method and apparatus for protecting an integrated circuit from erroneous operation
US7305544B2 (en) * 2004-12-10 2007-12-04 Intel Corporation Interleaved boot block to support multiple processor architectures and method of use
KR100634455B1 (en) * 2005-06-13 2006-10-16 삼성전자주식회사 Flash memory device capable of reducing program time
JP4584044B2 (en) * 2005-06-20 2010-11-17 ルネサスエレクトロニクス株式会社 Semiconductor device
EP2221825A1 (en) * 2009-02-05 2010-08-25 Thomson Licensing Non-volatile storage device with forgery-proof permanent storage option
US8261011B2 (en) * 2009-10-29 2012-09-04 Freescale Semiconductor, Inc. One-time programmable memory device and methods thereof
DE112019007425T5 (en) * 2019-05-31 2022-02-24 Micron Technology, Inc. Intelligent charge pump architecture for flash arrays

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752871A (en) * 1985-09-30 1988-06-21 Motorola, Inc. Single-chip microcomputer having a program register for controlling two EEPROM arrays
US4796235A (en) * 1987-07-22 1989-01-03 Motorola, Inc. Write protect mechanism for non-volatile memory
JPH0812646B2 (en) * 1989-03-03 1996-02-07 三菱電機株式会社 Semiconductor integrated circuit
US5199032A (en) * 1990-09-04 1993-03-30 Motorola, Inc. Microcontroller having an EPROM with a low voltage program inhibit circuit
US5267218A (en) * 1992-03-31 1993-11-30 Intel Corporation Nonvolatile memory card with a single power supply input
US5381369A (en) * 1993-02-05 1995-01-10 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device using a command control system
US5363334A (en) * 1993-04-10 1994-11-08 Microchip Technology Incorporated Write protection security for memory device
US5339279A (en) * 1993-05-07 1994-08-16 Motorola, Inc. Block erasable flash EEPROM apparatus and method thereof
US5592641A (en) * 1993-06-30 1997-01-07 Intel Corporation Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status
US5513136A (en) * 1993-09-27 1996-04-30 Intel Corporation Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations

Also Published As

Publication number Publication date
US5890191A (en) 1999-03-30
EP0806772A2 (en) 1997-11-12
EP0806772A3 (en) 1999-03-31
JPH1050078A (en) 1998-02-20

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees