A7 B7 五、發明説明（（ 發明费暑 本發明有閿一種相位檢波器，且較特別地，有關一種 應用於延遲鎖定遒路（Delay L〇cked L〇(*P).(下文中簡稱 為DLL)電路之相位檢波器，該延遅鎖定迴路電路镍使用 於一内部時脈産生器之中以用於一例如為藍巴士（Raabus) (美國Rambus公司商_ )DRAtU動態随機存取記億體）之同 步動態RAM(隨機存取記憶髏）（下文中簡稱為SDRAM)。 第4圖像一方塊圖，描繪一使用MSDRAM(闻步動態隨 機存取記億醱）及藍巴士 DRAK(動態随機存取記憶醱）之 DLL(延遲鎖定迺路）電路之實例，其中包含： 一値四相位時脈産品器41，供應以一頻率f之輪入時 脈1Q1用以産生四時脈11〇至113，其各具有2f之頻率且 相互具有ττ/2倍數之相位差； 一相位檢波器42，用以檢出輪入時脈10 1與一輸出時 脈1 0 3間之相位差； 一相位控制信號産生器44，用以産生相位控制信號114 舆115其相位控制值由一相對應於供應自相位檢波器42 之控制信號10 8舆1D9信號準位之預定值來增加或減少； —相移電路43，用以藉根據供應自相位控制信號産生 器4 4之相位控制信號1 1 4舆115^31波四時脈1 1 0至1 1 3以控制 中間時脈Η6輿117之相位；以及 一輸出電路4 5,用以自相移電路43所産生之中間信號 116與11?産生具有頻率f之输出時脈1〇3。 此處，相位檢波器42由一相位差異辨別電路11舆一用 本紙張尺度.適用中國國家樣準（CNS ) A4規格（210X297公釐） 請 先 閲 讀 背 之 注 意 事A7 B7 V. Description of the invention ((The invention has a phase detector, and more particularly, it relates to a delay-locked circuit (Delay L〇cked L〇 (* P). (Hereinafter referred to as DLL) phase detector of the circuit, the extended locked loop circuit nickel is used in an internal clock generator for a Rabus (Rambus, USA) _DRAtU dynamic random access memory Synchronous Dynamic RAM (Random Access Memory Skeleton) (hereinafter referred to as SDRAM). The fourth image is a block diagram depicting the use of MSDRAM (Wenbu Dynamic Random Access Memory) and Blue Bus DRAK ( An example of a dynamic random access memory (DLL) circuit of DLL (Delay Locking Circuit), which includes: a four-phase clock product generator 41, which supplies a round clock 1Q1 at a frequency f for generating four clocks 11〇 to 113, each having a frequency of 2f and mutually having a phase difference of ττ / 2 multiples; a phase detector 42 for detecting the phase difference between the in-cycle clock 10 1 and an output clock 1 0 3 ; A phase control signal generator 44 for generating a phase control signal 114 115 The phase control value is increased or decreased by a predetermined value corresponding to the control signal 108 and 1D9 signal level supplied from the phase detector 42;-The phase shift circuit 43 is used to generate according to the supplied phase control signal The phase control signal 1 1 4 and 115 ^ 31 wave four clocks 1 1 0 to 1 1 3 of the device 4 4 to control the phase of the intermediate clock H 6 and 117; and an output circuit 45 for the phase shift circuit 43 The generated intermediate signals 116 and 11? Produce an output clock 103 with a frequency f. Here, the phase detector 42 consists of a phase difference discriminating circuit 11 and a paper standard. Applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) Please read the notes on the back first
I 訂 經濟部中央標準局員工消费合作社印製 312871 A7 B7五、發明説明（> ) 移 轉 位 準 之 位 準 號 信 之 9 ο- 11 舆 8 ο 1 號 信 制 控。 等成 此組 制所 3 控 1 以路 倍持 制維 控地 各確 精 以 地用 格值 駸定 内.固 其 週於 各持 於維 ，位 中準 42號 器信 波之 檢[09 位I 相 在10 號 與 輿 而相 ， 由 值09 制 控 位10 相號 之倍 5 _ ua.n L控 據 11根 號内 信期 制遇 控各 位於 相傣 舆. 求精相控 要以此位 值産 制號 控信 te. 制 經濟部中央揉率局貝工消費合作社印裝 生器44來增加或減少β 繼缠上述DLL電路之實例，參照第5圖與第6圖説明 一習知應用於SDRAK或一監巴士 Uaiabus)DRAM之相位檢 波器42實例之形態。 第5圖像一電路圔，描繪一習知由相位差異辨別電路 11以及準位轉移電路13所組成之相位檢波器。此相位差 異辨別電路11包含：pMOS(p型金屬.氣化物半導體）電晶 體5l,55,56;nM0S(nM0S(n型金屬氣化物半導醱）52,53, 5 4，5 7，6 0至6 7 ;以及反相器5 8與5 9。此準位轉移電路1 1 包含：PMOS電晶體68至71 ;以及nMOS電晶體72至75。 首先，結合第6圖中所示之定時圖說明相位差異辨別 霄路1 1之作業。 當輸出時脈103於HIGH (高）準位期間（下文稱為"使不 能期間’·（ d i s a b 1 e d p e r i 〇 d ) } , η Μ 0 S 電晶醱 5 7，6 0 與 6 ! 〇N(導通}以及相互經由nMOS電晶膜57連接之倍號118與 119均經由iiMOS電晶體60與61接地時，第5圖中之信號 104舆105均如第6圓中所示被固定於HIGH(高}準位。 當輸出時脈103轉變為Low(低）準位畤，一電壓差發生 -4 - 本紙張尺度逍用中國國家標準（CNS ) Α4Λ格（2iOX297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部中央裸準局貝工消費合作社印装 A7 __ B7 一 五、發明説明（> ) 4*想壓1 〇 2之 於其各根據第5圏中之各輸入時脈101舆pI. Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Wait for this group to be controlled by 3 control 1 with the road control system to maintain the accuracy and use the grid value of the standard. Gu Qiyu is held in each dimension, and the position is checked by the No. 42 device [09] The phase I phase is on the 10th, and the phase is phased by the value 09. The control bit is the multiple of the phase 10 phase number. 5 _ ua.n L control data. Use this value to produce a production number control letter te. Ministry of Economic Affairs Central Kneading Rate Bureau Beigong Consumer Cooperative Printed Device 44 to increase or decrease the value of the example of the DLL circuit wrapped around the above, please refer to Figures 5 and 6 for a description The conventional detector is applied to an example of the phase detector 42 of SDRAK or Uaiabus (DRAM) DRAM. The fifth image, a circuit, depicts a conventional phase detector composed of a phase difference discrimination circuit 11 and a level shift circuit 13. This phase difference discriminating circuit 11 includes: pMOS (p-type metal. Vaporized semiconductor) transistors 51, 55, 56; nM0S (nM0S (n-type metal vaporized semiconductor semiconducting)) 52, 53, 5 4, 5 7, 6 0 to 6 7; and inverters 5 8 and 5 9. This level transfer circuit 1 1 includes: PMOS transistors 68 to 71; and nMOS transistors 72 to 75. First, combine the timing shown in Figure 6 The diagram illustrates the operation of the phase difference to distinguish Xiaolu 1 1. When the output clock 103 is in the HIGH level (hereinafter referred to as " disable period ”(disab 1 edperi 〇d)}, η Μ 0 S When the crystals 5 7, 6, 0 and 6! 〇N (on) and the multiples 118 and 119 connected to each other via the nMOS transistor 57 are grounded via the iiMOS transistors 60 and 61, the signal 104 and 105 in the fifth diagram They are all fixed at the HIGH level as shown in circle 6. When the output clock 103 changes to the Low level, a voltage difference occurs -4-This paper scale uses the Chinese National Standard (CNS) ) Α4Λ grid (2iOX297mm) (Please read the precautions on the back first and then fill out this page) Printed by the Central Naked Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative A7 __ B7 Description Ming (>) 4 * 1 square like laminated thereon in accordance with each of the two rings of the fifth clock input 101 of each of the map p
rtifil餺變為〇FF 信號118與113之間，而nMOS電晶髅57, 6fl_b w «ί治0 U (導通）0 (翻閉）以及nMGS電晶體53，54，64至67轉變為 嫌lg 1 〇 2時， 於此實例中，當輸入時脈101較低於參考 信號118呈較低於信號119。 ' 於第5圓之相位差異辨別罨路11中，其中戶：w 山-r fi?"製奮路 晶體55與56以及nMOS電晶體62輿63所建構之正 ，而此正反器電路係經由當輸出時麻1〇3於Low(低）準位時 而ON(導通〉中之電晶體51來供應以一電源供應電壓Vdd， / i 此時，信號118與11 9間之電壓差被放大，以及.因而各信 號104與105轉移至Low(低）準位β 亦卽，於輸出畤脈103之下降緣處，若输入時脈101較 高於參考電壓1Q2時，即，若輪出信號1〇3之相位延遲於 輸入時脈1 Q 1之相位時，則輸出自相位差異辨別電路U 之信號10 5轉移為Low(低）準位，而當輸出時脈103像相 位超前於輸入時脈1 0 1時.，則輸出自相位差異辨別電路· 11之信號104轉移為Low(低）準隹，如第6圔中所描繪。 現參照第5圔舆第6圖說明被供應以信锇1CU舆1〇5用 於産生控制信號108舆109之準位轉移電路13。 於一期間當输出時腌103傜於Low(低）準位且因而此相 位差異辨別電路1 1被使能（en a b 1 e d )時，則輸出自相位 差異辨別電路11之信號104與105之一呈Low(低）準位而 另一則呈HIGH(高）準位。 例如，若信號104呈Low(低）準位時，第5麵之準位轉 本紙張尺度適用中國困家橾率（CNS ) A4规格（210X297公釐） (锖先閱讀背面之注意事項本頁)rtifil becomes FF between signals 118 and 113, while nMOS transistors 57, 6fl_b w «ί 治 0 U (on) 0 (turn-off) and nMGS transistors 53, 54, 64 to 67 are converted to lg At 〇2, in this example, when the input clock 101 is lower than the reference signal 118, it is lower than the signal 119. 'In the phase difference discernment circuit 5 of the fifth circle, where the household: W Shan-r fi? &Quot; manufactured Fen Road crystals 55 and 56 and nMOS transistors 62 and 63 are constructed by the positive and negative circuit It is supplied with a power supply voltage Vdd through the transistor 51 in the ON state when the output 103 is at the Low level, and the voltage difference between the signals 118 and 119 Is amplified, and therefore, the signals 104 and 105 are transferred to the Low level β. Also, at the falling edge of the output pulse 103, if the input clock 101 is higher than the reference voltage 1Q2, that is, if the wheel When the phase of the output signal 103 is delayed from the phase of the input clock 1 Q 1, the signal 105 output from the phase difference discriminating circuit U is shifted to the Low level, and when the output clock 103 is phase-leading When the input clock is 101, the signal 104 output from the phase difference discriminating circuit 11 is transferred to a low (low) quasi-cow, as depicted in the sixth picture. Now refer to the fifth picture and the sixth picture to be supplied The osmium 1CU and 105 are used to generate the control signal 108 and the level transfer circuit 13 of 109. During a period of output, the output 103 is immersed in the Low level. And when the phase difference discriminating circuit 11 is enabled (en ab 1 ed), one of the signals 104 and 105 output from the phase difference discriminating circuit 11 has a Low level and the other has a HIGH level. For example, if the signal 104 is at Low level, the paper level of the 5th side is converted to the paper standard of China ’s Sleepy Family Rate (CNS) A4 specification (210X297mm). (Read the note on the back first Matters on this page)
A7A7
$'發明説明（Ο ^12871 移電路13之1^03電晶體71呈〇{}(導通）而1^03軍晶體呈0^ (晓閉）。因此，控制信號1Q9之信號準位轉移至電源供 鼴電壓彳(1(1,而因為pMOS電晶體69轉變為0FF(關閉）以及 閱槿具備信號105 HIGH(高）準位之nMOS電晶體73呈OFF (鞠閉），故控制信號1Q8之信號準位轉移為nMOS電晶體72 之鬥限電壓VU相反地，若信號1〇5轉變為Low(低}準位 時，輸出自準位轉移電路13之控制信號1Q9之信號準位 轉移為nMOS電晶體74之門限？！歷Vt而控制信號1〇8之佶 號準位Μ轉移至電源供應電壓Vdd，如第6圖中所示。 現說明當輸出時脈l〇3fHIGH(高）準位，亦即，當相 位差異辨別電路11為使不能之期間中第5圖之柑位檢波 器之作業。 於此期間中，信號10 4與10 δ•均維持於H1 6 H (高）準位， 锒設一種情況，印當信號104僳從L0W(低）準位轉變為 BIGH(高）準位jffii倍號保持於HIGH(高）準位。 具備轉變為OFF(關閉）之第5圖準位轉移電路之pMOS 電晶體71以及閘極由信號104轉變為HIGH(高）準位而轉 變為洸導通）之n« 0 s電晶體7 5，欲自準位轉移電路13輸 (請先閲讀背面之注$項再填寫本頁)$ 'Invention description (Ο ^ 12871 The 1 ^ 03 transistor 71 of the shift circuit 13 is 0 {} (conducted) and the 1 ^ 03 military crystal is 0 ^ (Xiao closed). Therefore, the signal level of the control signal 1Q9 shifts to The power supply voltage (1 (1, and because the pMOS transistor 69 is changed to 0FF (off) and the nMOS transistor 73 with the signal 105 HIGH (high) level is OFF (ju off), the control signal 1Q8 The signal level shifts to the bucket limit voltage VU of the nMOS transistor 72. Conversely, if the signal 105 transitions to the Low level, the signal level shift from the control signal 1Q9 output from the level shift circuit 13 is Threshold of the nMOS transistor 74 ?! Vt and the control signal 108 is shifted to the power supply voltage Vdd, as shown in Figure 6. Now, when the output clock l03fHIGH (high) level Bit, that is, when the phase difference discriminating circuit 11 is the operation of the orange detector in Fig. 5 during the disabled period. During this period, the signals 10 4 and 10 δ are maintained at H1 6 H (high) level Bit, set a case, the signal when the signal 104 is changed from L0W (low) level to BIGH (high) level jffii times the number remains at HIGH (high) level. The pMOS transistor 71 and the gate of the level transfer circuit in Fig. 5 which is turned OFF (turned off) are changed from the signal 104 to the HIGH level and turned into the ON state) n «0 s transistor 7 5, To lose 13 from the level transfer circuit (please read the note $ item on the back and then fill in this page)
—.1^1裝------1T—.1 ^ 1 installed ------ 1T
«Ϊ —^ϋ ^^1 · C 經濟部中央標準局員工消費合作社印策 信壓 制電 控限 之門 出之 4 7 髅 晶 5 ο Μ Π 至 降 下 始 開 位 準 费 倍 之 然 體 晶 S ο Μ η 當 仍 藉 棰 由 經 亦 於 持 保 而 制 控 來 8 ο £ 屬 電 應 供 源 電 以 應 供 號被 信70 之 S I Α ΜβΒ t 3 V 晶 壓電 雹 S tpf ο 棂 Μ 择 Ρ 門之 於中 持態 保狀 1 與 ft ο S 7 信體 制晶 控電 信 之 }故 通， 導dd 在 徊 徘 而 降 下 地 分 充 法 疾 _ 位 準 處 之 位 準 衡 平 之 p In n^— 準 標 I國 一國 中 用 適 度 尺 張 -紙 I本 |釐 9 2 A7 B7 五、發明説明（t 準位轉移電路13具有一蹰於控制信號iQ 8輿10 9之鏡形 態，亦即，控制信號10 8亦經由Μ極藉下降之控制倍號 109所控制之PM0S電晶醱69而闊始被供應以電源供應電壓 Vdd,兩控制信號與109之信號準位則平衡於一中間點 之處，如第6圖中所描繪。 - 因而，當輸出時脈103像於Low(低）準位時，由第5圖 之相位差異辨別電路1 1輿準位轉移霄路1 3所組成之習知 相位檢波器4 2之輸出控制I信號1 Q 8與1 0 9，則根據輸人時 脈1 0 1與輸出時脈1 0 3間之相位差異，輸出控制倍號之一 於電源供應電壓vdd處而另一則於M0S電晶體之門限電壓 vt處。 然而，在習知相位檢波器42中，當输出佶號103於HIGH (高）準位時，此二控制信號1〇8舆109均呈一中間準位。 如上述，應用於第4圖DLL電路之相位檢波器42需在 每一週期中输出維持於其固定準位之控制信號108舆109 ，用以在一遇期中精確地控制相位控儀I信號11 4舆1 1 5之 相位控制值。 請 先 閱 Λ 之 注 意 I 事I 項 袁，I I裝 不 頁 訂 經濟部中央標準局貝工消費合作杜印製 控因 位， 相值 藉制 以控 難位 很.相 器持 波維 檢輿 位制 相控 知中 習期 之週 圏一 5 在 第44 備器 具生 ，産 而號 然信 制 為. ο 1 此 脈 . 時近 出附 輸壓 於電 09間 1中 與， 8 1 10於 號徊 信棑 制均 控處 二位 此 5 之丨 應 供 所 為 高 每 之 大 題 問 號 佶 10制 脈控 時由 出經 輸流 此會 於流 ，電 且之 而要 必 1 每 之 處 位 準 ft- 控 所 值 間 中 高之 不 制 準 榡 家 ~國 I興 |中 I用 I適 I釐 29 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（k ) 之準位轉移電路13中之諸MOS電晶體，此為另一問題。 發明槪沭 因此，本發明一主要目的操提供一種相位檢波器，用 以檢出輸入時脈1 〇 1與輸出時脈1 0 3間之相位差異而充分 穩定地輸出控制信號，即使當輸出時脈103像於HIGH(高） 準位，也不會有任何不必要之電流散發。 為達成此目的，本發明應用於SDEAM或藍巴士（Raiabus) DRAM之DLL(延遲鎖定迴路）電路中用以檢出DLL電路之一. 輸入時脈與一輸出時脈間相位差異之相位檢波器，包含： 一供應以輸入時脈與輸出時脈之相位差異辨別電路， 用以辨別輪入時脈與輸出時脈間之相位差異，而輸出兩 信號以指示輸入時脈舆輸出時脈之相位何者超前； 一閂鎖電路（latch circuit),用以問鎖上述指示輸 入時脈與輸出時脈之相位何者超前之兩信號，供輸出兩 閂鎖倍號，各上述兩閂鎖信號穩定且互補地維持於各兩 固定準位處；以及 一準位轉移電路，用以根據供應自上述閂鎖電路之上 述兩閂鎖信號之狀態來産生使用於D L L電路中之控制佶 號。 此時，上述閂鎖電路可包含兩値正反器，各上述兩正 反器閂鎖各上述指示輸入時脈與輸出時脈之相位何者超 前之兩信號，用以藉供應於其時脈輸入端子之輸出時脈 來控制及輸出各上述兩閂鎖信號。 或者，上述閂鎖電路可包含兩値N A N D (非及）閘，各上 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) f 裝. 312871 A7 B7 五、發明説明（7 ) (請先閲讀背面之注意事項再填寫本頁) 述兩ΝΑΟ閘被供應以指示輸入時脈與輸出時脈之相位何 者超前之各上述兩信號於其一輸入端子處，而於其S — 輸入端子處則被供應以上述兩ΝΑΟ閛之另一锢之輸出， 用以輸出各上述閂鎖倍號。 因此，具備有一閂鎖電路配置於相位辨別電.路與準位 轉移電路之間，本發明之相位檢波器可産生出穩定地轉 移輿維持於其準位之互補控制倍號，即使是在相位辨 別電路被使不能之期間中，而且可抑制不必要之電流散 發於準位轉移電路中。 丽式簡沭 本發明上述，進一步之目的，特性舆優點將從考慮下 列説明，附加之申請專利範圍，以及其中相同之標號指 示相同或相對應部件之附圖而呈明顯。 第1圖傜一方塊圖，描繪本發明相位檢波器之一實施 例； 第2Α圖傜一方塊圖，描繪第1圖之閂鎖電路12之一實 例； 經濟部中央標準局員工消費合作社印製 第2Β圖傜一方塊圖，描繪第1圖之閂輯電路12之另實 例； 第3圖顯示定時圖，描繪實施例之諸倍號間之關傺； 第4圖僳一方塊圖，描繪一使用於SDRAM中之DLL電路 之實例； 第5圖像一電路圖，描繪一習知之相位檢波器； 第6圖像定時圖，描繪第5圖之相位差異辨別電路11 本紙張尺度適用中國國家梯率（CNS )%4规格（210X297公嫠） 312871 A7 B7 五、發明説明（艺） 之作業； 第7A圖僳一定時圖，量度供一以3.3V(伏特）電源供應 電壓舆4 ns (奈秒）時脈週期來作業之本發明相位檢波器； • » 以及 第7B麵樣一定時圖，量度供一相對應於第7圖相位檢 波器之習知相位檢波器。 較住宮掄例_沭 現將結合圖式說明本發明之實施例。 第1圖傺一方塊圖，描繪本發明相位檢波器之一實施 例，包含：一柑位相盖異辨別電路11 , 一閂鎖電路1 2以及 一準位轉移電路1 3。 當比較於第5圖之習知相位檢波器時，可易於理解在 第1圖實施例之相佞差異辨別電路11與準位轉移電路 1 3之間,被進一步地插置一閂鎖電路12以用於在DLL電路 一輸出信號10 3之毎一下降緣處閂鎖傳遞自相位差異辨 別電路11之信號10 4與1 05,以及分別輸出它們為閂鎖信 號 1G6舆 107。 經濟部中央標率局員工消費合作社印策 (請先聞讀背面之注意事項再填寫本頁) 第2A圖像一方塊匯，描繪閂鎖電路12之一實例，此電 路包含正反器14與15用於在輸出時脈103之各下降緣處 罔鎖倍號104與105以分別地被輸出為閂鎖信號106舆107。 第3圖顯示定時圖，描繪此實施例之諸信號間之鼸僳。 現參照第1.至3圖說明此實施例之作業，省略重複說 明有關相同於第5圖習知相位檢波器之相對應電路之相 位差異辨別電路1 1以及準位轉移電路1 3。 -ΙΟ- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 _B7_ 五、發明説明（9 ) 相類似於第5圖之習知相位檢波器，當DLL電路之輸 出時脈103於高準位時，兩者均於高準位之倍號104與10 5 自相位差異辨別電路11输出。 於輸出時脈103之每一下降緣處，信號104舆105之一 根據輸入時脈101與輸出時脈10 3間之相位差異而轉變為 L 〇 w (低）準位，而S —則保持於Η I G Η (高）準位。它們均 分別由正反器14與來閂鎖以被輸出為閂鎖信號106與 107,而正反器14舆15亦由輪出時脈103之毎一下降緣所 控制。 因此，當輸出時脈1D3之相位延遲於輸入時脈101之相 位時，輸出自閂鎖電路12而被供應至準位轉移電路13之 閂鎖信號1Q6.與107均穩定地分別維持於HIGH {高）準，位與 Low(低）準位，且當輸出畤脈103超前於輸入時脈畤，它 4 們均穩定地分別維持於Low (低）準位舆HIGH (窩）準位， 如第3圖中所示。 供應以穩定地維持於HIGH (高）與Low (低）準位之 閂鎖信號106與107,準位轉移霄路13可穩定地轉移舆維 持控制信號108與109為電源供應電壓Vd(i與M0S電晶醸之 門限電壓。 而且，即使在相位差異辨別鬣路11之使不能期間，亦 即，當输出時脈103於HIGH(高）準位並没有不必要 之電流散發，而此電流係由第5圈習知相位檢波器中控 制信號10 8與109徘徊於一中間準位處所造成。 第7 A画傜一定時圖，量度用於一以:3 . 3T；i電源供應電 -1 1- 本紙張又度逍用中國國家橾準（CNS ) A4規格（210X297公釐） A7 312871 B7 五、發明説明（…） (讀先閲讀背面之注意事項再填寫本頁) 壓舆4ns之時脈作業之本發明相位檢波器，而第7B.圖樣 一定時圖，量度供一相對應於第7A圖之相位檢波器而無 閂鎖電路12之習知相位檢波器。從第7A圖舆7B圖之電流 值201與202,本發明之相位檢波器中之平均電流散發從 習知相位檢波器中之2.5βΑ(毫安培）降低至1.5 aiA。 第2 B圖像一方塊圖，描繪第1圖之閂鎖電號12之另一 由N AN D閛17與18所組成之實例。 於第2δ圖之實例中，並不需要供應輸出時脈103,當 傳遞自相位辨別電路1 1之信號1 0 4與1 D 5均於Η I G Η (高）準 位時，分別為NAND閘18與17之輸出之閂鎖信號10 6與107 僳維持於其前一狀態而彼此互補。當信號104與105之一 轉變為Low(低）準位時，各正反器17與18輸出各輸入信 號之相反邏輯為各罔鎖信號1 0 6與1 07。 因此，於此實例中，閂鎖信號1D6輿107亦根據輸入時 脈101舆輸出時脈103間之相位差異而維持於其準位而無 於關於輸出時脈1 03之信號準位，且準位轉移電路1 3可 穩定地轉移與維持控制信號108 ,109有如第2圖之實例 而不會有不必要之電流散發。 經濟部中央標準局員工消費合作社印裝 如上述，具備一閂鎖電路1 2配置於相位辨別電路1 1舆 準位轉移電路13之間，本發明之相位檢波器可産生互補 之控制信號穩定地轉移舆維持於其準位，卽使當相位辨 別電路1 1係於使不能之期間内，且可抑制準位轉移電 路中不必要之電流散發。 -1 2 - 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐）«Ϊ — ^ ϋ ^^ 1 · C The Ministry of Economic Affairs, Central Standards Bureau, Employee Consumer Cooperative, printed a letter to suppress the limits of the electronic control 4 7 Skull Crystal 5 ο Μ Π To the beginning of the lower level, the body crystal S ο Μ η should still be controlled by the government through the insurance and the holding 8 ο £ The main electricity should be supplied by the source and the supply number should be the 70 SI Α Μ βΒ t 3 V crystal piezoelectric hail S tpf ο 棂 Μ select Ρ The door is in the state of holding the state 1 and ft ο S 7 credit system crystal control telecommunications} reason, lead dd to hover down and fully charge the law _ the level of the balance of the level p In n ^ — Standard I country to country with moderate ruler-paper I | 9 9 A7 B7 V. Description of the invention (t The level transfer circuit 13 has a mirror shape that is within the control signal iQ 8 and 10 9, that is, the control The signal 108 is also supplied with the power supply voltage Vdd through the PMOS transistor 69 controlled by the M-pole by the falling control multiple 109, and the two control signals and the signal level of 109 are balanced at an intermediate point , As depicted in Figure 6.-Therefore, when the output clock 103 looks like Low At the time, the output of the conventional phase detector 4 2 consisting of the phase difference discriminating circuit 1 1 and the level shifting road 1 3 in FIG. 5 controls the I signals 1 Q 8 and 1 0 9 according to the input time The phase difference between pulse 101 and output clock 103, one of the output control multiples is at the power supply voltage vdd and the other is at the threshold voltage vt of the MOS transistor. However, in the conventional phase detector 42 In the middle, when the output number 103 is at the HIGH level, the two control signals 108 and 109 are both at an intermediate level. As described above, the phase detector 42 applied to the DLL circuit in FIG. 4 needs to be The control signals 108 and 109, which are maintained at their fixed levels during one cycle, are used to accurately control the phase control value of the phase controller I signal 11 4 and 1 1 5 during an encounter period. Please read Λ Note I first Item I, item II and page II do not set the page to control the control position of the Belgian consumer cooperation in the Central Standards Bureau of the Ministry of Economic Affairs, and the phase value is used to control the difficult position. The phase device holds the wave and checks the position system. Zhi Zhouyi 1 was born on the 44th equipment, and it was produced with the belief that it was made. Ο 1 This vein. Time is coming out Transmitting voltage in the electricity 09 room 1 and 8 1 10 in the control system of the No. 2 control unit of the two digits of this 5 should be supplied by the main question is high every time the question mark is 10 when the pulse system is controlled by the output flow Yuliu, electricity and it must be 1 at every level ft- control value between the high and low standards of the home ~ Guo Ixing | China I use I appropriate I 29 29 Ministry of Economic Affairs Central Standards Bureau employee consumption cooperative printing A7 B7 V. Description of the invention (k) The MOS transistors in the level transfer circuit 13 are another problem. Therefore, a main objective of the present invention is to provide a phase detector for detecting the phase difference between the input clock 101 and the output clock 103 to output the control signal sufficiently and stably, even when output Pulse 103 resembles the HIGH level, and no unnecessary current is dissipated. To achieve this purpose, the present invention is applied to a DLL (Delay Locked Loop) circuit of SDEAM or Raiabus DRAM to detect one of the DLL circuits. A phase detector of phase difference between an input clock and an output clock , Including: a phase difference discriminating circuit supplied with input clock and output clock, used to discriminate the phase difference between the input clock and output clock, and outputting two signals to indicate the phase of input clock and output clock Which is ahead; a latch circuit, which is used to ask the two signals which indicate the phase of the above-mentioned input clock and output clock, which are used to output two latch multiples, and each of the above two latch signals is stable and complementary Ground is maintained at two fixed levels; and a level transfer circuit is used to generate the control number used in the DLL circuit according to the state of the two latch signals supplied from the latch circuit. At this time, the latch circuit may include two flip-flops, and each of the two flip-flops latches two signals indicating which phase of the input clock and the output clock is ahead, for supplying the clock input The output clock of the terminal controls and outputs each of the above two latch signals. Alternatively, the above latch circuit may include two NAND gates, each of which is compliant with the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page) f 312871 A7 B7 V. Description of the invention (7) (Please read the precautions on the back before filling in this page) The two NAO gates are supplied to indicate which phases of the input clock and the output clock are ahead of each of the above two signals. At one of its input terminals, at its S-input terminal, it is supplied with the output of the other of the two NAOs, for outputting each of the latch multiples. Therefore, with a latch circuit configured between the phase discrimination circuit and the level transfer circuit, the phase detector of the present invention can generate a complementary control multiple that stably transfers and maintains its level, even in the phase During the period when the discrimination circuit is disabled, it is possible to suppress unnecessary current from being dissipated in the level transfer circuit. The above-mentioned, further objects, features and advantages of the present invention will be apparent from consideration of the following description, additional patent application scope, and drawings in which the same reference numerals indicate the same or corresponding parts. Figure 1 is a block diagram depicting an embodiment of the phase detector of the present invention; Figure 2A is a block diagram depicting an example of the latch circuit 12 of Figure 1; Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Figure 2B is a block diagram depicting another example of the latch circuit 12 of Figure 1. Figure 3 shows a timing diagram depicting the relationship between the multiples of the embodiment; Figure 4 is a block diagram depicting a An example of a DLL circuit used in SDRAM; 5th image a circuit diagram depicting a conventional phase detector; 6th image timing diagram depicting the phase difference discrimination circuit of FIG. 11 (CNS)% 4 specification (210X297 gong) 312871 A7 B7 5. The description of the invention (art) operation; Figure 7A: A fixed time chart, measuring a 3.3V (volt) power supply voltage and 4 ns (nanoseconds) ) The phase detector of the present invention operating at a clock cycle; • »and a fixed time diagram of the 7B pattern, measuring a conventional phase detector corresponding to the phase detector of FIG. 7. Example of comparison of residence_ 歭 The embodiment of the present invention will now be described with reference to the drawings. Fig. 1 is a block diagram depicting an embodiment of the phase detector of the present invention, including: a phase difference detection circuit 11, a latch circuit 12 and a level transfer circuit 13. When comparing with the conventional phase detector of FIG. 5, it can be easily understood that a latch circuit 12 is further inserted between the phase difference detection circuit 11 and the level transfer circuit 13 of the embodiment of FIG. The signals 104 and 105 transmitted from the phase difference discriminating circuit 11 are latched at each falling edge of an output signal 103 of the DLL circuit, and they are respectively output as latch signals 1G6 and 107. Printed by the Employee Consumer Cooperative of the Central Standard Rating Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). The 2A image is a block diagram depicting an example of a latch circuit 12, which includes flip-flops 14 and 15 is used to lock the multiples 104 and 105 at each falling edge of the output clock 103 to be output as latch signals 106 and 107, respectively. Figure 3 shows a timing diagram, depicting the signal between the signals of this embodiment. The operation of this embodiment will now be described with reference to FIGS. 1. to 3, omitting the repetitive description of the phase difference discriminating circuit 11 and the level shifting circuit 13 of the corresponding circuit similar to the conventional phase detector of FIG. -ΙΟ- This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 _B7_ 5. Description of the invention (9) Similar to the conventional phase detector shown in Figure 5, the output clock 103 of the DLL circuit At the high level, both are output from the phase difference discriminating circuit 11 at the multiples 104 and 10 5 of the high level. At each falling edge of the output clock 103, one of the signals 104 and 105 changes to L 〇w (low) level according to the phase difference between the input clock 101 and the output clock 103, while S-remains At Η IG Η (high) level. They are respectively latched by the flip-flops 14 and Lai to be output as the latch signals 106 and 107, and the flip-flops 14 and 15 are also controlled by each falling edge of the clock 103. Therefore, when the phase of the output clock 1D3 is delayed from the phase of the input clock 101, the latch signals 1Q6 and 107 that are output from the latch circuit 12 and supplied to the level transfer circuit 13 are stably maintained at HIGH { High level, Low level and Low level, and when the output pulse 103 leads the input clock pulse, they are all stable at Low level and HIGH level, such as Shown in Figure 3. Latch signals 106 and 107 that are stably maintained at the HIGH and Low levels, the level shifting road 13 can stably transfer the sustain control signals 108 and 109 to the power supply voltage Vd (i and The threshold voltage of the M0S transistor. Furthermore, even during the period when the phase difference discriminates the disabling of Hylu 11, that is, when the output clock 103 is at the HIGH level, there is no unnecessary current dissemination, and this current is It is caused by the control signals 108 and 109 hovering at an intermediate level in the conventional phase detector in the fifth circle. The seventh time draws a picture of the Tai, the measurement is used for one: 3.3T; i power supply -1 1- This paper uses the Chinese National Standard (CNS) A4 specification (210X297mm) A7 312871 B7 V. Invention description (…) (Read the precautions on the back and then fill out this page) When pressing 4ns The phase detector of the present invention for pulse operation, and FIG. 7B. The pattern is a fixed time diagram, measuring a conventional phase detector corresponding to the phase detector of FIG. 7A without the latch circuit 12. From FIG. 7A and 7B The current values 201 and 202 in the figure are the average current emission in the phase detector of the present invention The 2.5βΑ (milliampere) in the conventional phase detector is reduced to 1.5 aiA. The second B image is a block diagram depicting the latched electrical signal 12 of the first image. The other is composed of N AN D 17 and 18 In the example of Figure 2δ, there is no need to supply the output clock 103, when the signals 1 0 4 and 1 D 5 transmitted from the phase discrimination circuit 1 1 are at the level of Η IG Η (high), respectively The latch signals 106 and 107, which are the outputs of the NAND gates 18 and 17, are maintained in their previous state and are complementary to each other. When one of the signals 104 and 105 changes to Low level, each flip-flop 17 and 18 The opposite logic of outputting each input signal is each blocking signal 1 0 6 and 1 07. Therefore, in this example, the latch signal 1D6 and 107 are also maintained according to the phase difference between the input clock 101 and the output clock 103 Because of its level and not about the signal level of the output clock 103, and the level transfer circuit 13 can stably transfer and maintain the control signal 108, 109 as in the example of FIG. 2 without unnecessary current Distribute. Printed and printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs as described above, with a latch circuit 12 configured for phase discrimination Between the differential circuit 11 and the level transfer circuit 13, the phase detector of the present invention can generate complementary control signals to stably transfer the signal to maintain its level, so that when the phase discrimination circuit 11 is disabled, , And can suppress unnecessary current dissipation in the level transfer circuit. -1 2-This paper size is applicable to China National Standard (CNS) Α4 specification (210Χ297mm)