TW310462B - Manufacturing method of four-layer fin-type capacitor structure - Google Patents

Abstract

A dynamic random access memory(DRAM) device comprises of: (1) one metal oxide semiconductor field effect transistor(MOSFET) with one drain, one source and one gate; (2) one bit line connected to the source; (3) one capacitor connected to the drain, in which the capacitor has four-layer parallel fine-type shape.

Description

310462 經濟部中央樣率局貝工消費合作社印製 五、發明説明（/ ) 發明背景 發明領域 本發明係關於一種獨特的動態糴檄存取記镰讎(DRAM)元件結構 及其製法，更仔細地說，係關於一種dram的四屬垂直雄型電容器結 構及其製法。 相關申請案 申誚案號名爲「垂直鳍型電容器結構的製進方法J的專 利申請案與本案一起提出申請，其中包含了與本申鼸案相欄的資料。 道件申請案的內容可作爲本案的參考。 朁知技蕕 一個DRAM記慊雠一般都包倉一儸電晶齷和一儸電容器。二 進位的資料(例如，0或0即透過電荷的形式儺存在電容器中。電容器 無法將電荷備存得很好，如果沒有定期(比方毎2毫秒)加以更新，電 荷就會流失。但是，電容器可以很快連地儲存和擷資料(以電荷的 形式）。 園1中，說明了一個典型的DRAM細胞元100。圓1的DRAM細胞 元100包含一個金屬氣化物半導讎場效電晶鼸(MOSFET)102和一個電 容器104。有一條字元線連至MOSFET 102的襴欏G，位元線連至 MOSFET 102的源楹S，電容器104則連至MOSFET 102的汲極D。 DRAM細胞元100的狀饑是由電容器是否傭存有電荷來決定的。 DRAM細胞元是由字元線所定址(_)的。當DRAM細胞元已經被觸 動時，就可以黷取裏面的資料，或蹿資料寫入細胞元。當讀取DRAM 細胞元100時，位元線可以決定源極S處是否具有一個電壓，而顬示 出電容器104內是否具有電荷。如果要將資料寫入DRAM細胞元時， 也是利用位元線將電荷加於電容器104上，或將電荷從電容器104上去 (請先閱讀背面之注意事項再填寫本頁) '訂 " 本紙張尺度適用t國圃家梯準（CNS ) A4规格（2丨0X297公着) 310462 經濟部中央揉準局貝工消费合作社印製 五、發明説明（β )除。 隨蕃DRAM技術的精進，一傭DRAM細胞元的晶片面稽愈來愈 小。這樣一來，毎II位面稍就可以騸進更多的DRAM細胞元，使同樣 面積的記嫌嫌陣列可以儲存更多的資料。但是，晶片面積縮小以後， 傳統T型的電容器或填實的節點電容器都變得太小，以致電容値都不 足。要製造一個具有足夠電容値的電容器，可以將電荷儀存一段足夠 的時間，是愈來愈困難了。 要提高DRAM細胞元電容器的鬌容値，有兩個方法。一個方法是 降低電容器有效介電層的厚度；另一個方法是加電容器的表面面 積。DRAM細胞元通常會在兩層濃摻雜的複晶矽和/或矽電楹之間， 夾入介電材料*相僂未來超薄介電材料的品質與儀存能力將會大大地 影響DRAM細胞元的性能。但是，使用超薄的介電材料，固然可以提 高電容値，但也會臛重地影響到元件的保持時間(即兩次更新之間的 時間）。這是因爲當膜雇薄於50埃時，直接載子穿瞇的效癱會使漏電 流變得很大。因此，若要設計更小的DRAM細胞元，最好是增加 DRAM的表面面稍，使霞容値得以提高到足使電荷鑛存一段足夠的時 間。在設計DRAM細胞元時，一方面最好使細胞元整儀的大小愈小愈 好，另一方面爾容器的表面面積則是愈大愈好，道兩個互相衝突的設 計特性，使得設計這樣的DRAM細胞元仍是一項挑戰，有待克服。 本發明的一個目的是提出一種DRAM，因爲提高了電容器的表面 面稍，所以具有更高的電容値。 本發明的另一個目的是提出一種DRAM，具有四層垂酶籣型的電 容器結構。 發明的籣要說明 (請先閱讀背面之注意事項再填寫本頁) % 訂 i 本紙張尺度逋用中國國家樣準（CNS ) A4规格（210X297公釐） 經濟部中喪樣準局興工消费合作社印装 A7 B7 五、發明説明（>) 爲達成本發明的道些目的，本發明提出了一種玀特的DRAM，具 有四靥平行鰌型的電容器結構，並且提出製進這種DRAM的有效方 法° 本發明DRAM細胞元的第一資施例髑始時，先要預儀一面具有第 一導電型的矽基板。基板上定義了場氣化物(FOX) *以便隔關各 DRAM細胞元。基板上也製作了汲楹和源楹。在汲楣和源欏之間的基 板表面上，並有鬭欏匾。闞楹區包含了一屬闕播«I化物、一層Poly-1、一層矽化鎢(WSi)層、一層氣化層和一雇Si02_SiN。在閜楹區的 側壁上覆蓋了 8丨02或8丨>1的空間子。在闞極匾上則是一雇TEOS(四乙 基矽酸鹽)或BPSG(碥磷矽醸鹽)作成的絕緣眉。具有第二導電型的 P〇丨y-2層與源楹和汲欐匾接觸。遂雇Po丨y-2雇會形成位元線，並與源 極區接觸。在位元線上則覆躉WSi、氣化層或薄薄的TEOS和Si3N4之 類的SiyNx等膜靥。位元線的側壁也由SiyNx空鬮子所驪義。 具有四層平行鳙型結構的電容器着與汲欏接觸。道愐電容器包含 了一樣摻雜成籮二導電型的Poly-3.1和Poly-3.1、諸如鼴化膜/氧化膜 (NO)或氧化膜/氮化膜/氣化膜(0N0)等類薄薄的介電屬、和摻雜成 第二導電型的P〇ly-4雇。 本發明DRAM細胞元的籮一實施侧，係由以下的步驟製作的： 1. 在基板內定義出FOX匾，以隔關相鄰的細胞元。 2. 在毎一個細胞元內，以Poly-Ι眉製作一個_欏。 3. 在闞棰的側壁上製作鼸楹空間子，並且利用闕極和颶欏空間子 作爲光軍，在基板臑出來的1城內製作一個導霉躍，形成 DRAM的源楹和汲欏匾。 4. 用TEOS覆蓋住細胞元*加上光羅後進行鈾刻，露出源櫬和汲楹 區，只在緊鄰源樋區的鬵楹上留下TEOS。 (請先閲讀背面之注f項再填寫本百) 一裝·310462 Printed by the Beigong Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs V. Description of the Invention (/) Background of the Invention Field of the Invention The present invention relates to a unique dynamic memory access memory DRAM device structure and its manufacturing method, which is more careful That is to say, it relates to a dram vertical male capacitor structure and its manufacturing method. The application filed in the related application is entitled "The Method of Making Vertical Finned Capacitor Structure J." The patent application filed with this case, which contains the information in the column corresponding to this application. The content of the Dao application can be As a reference for this case. It is generally known that a DRAM memory device generally includes a battery and a capacitor. Binary data (for example, 0 or 0 is stored in the capacitor through the form of charge. The capacitor cannot The charge is well stored. If it is not updated regularly (for example, every 2 milliseconds), the charge will be lost. However, the capacitor can quickly store and retrieve data (in the form of charge). Park 1 shows that A typical DRAM cell 100. The DRAM cell 100 of circle 1 contains a metal vapor semiconductor semiconductor field effect transistor (MOSFET) 102 and a capacitor 104. There is a word line connected to the MOSFET 102 襕 椤 G , The bit line is connected to the source S of the MOSFET 102, and the capacitor 104 is connected to the drain D of the MOSFET 102. The state of the DRAM cell 100 is determined by whether the capacitor has charge stored. The DRAM cell is determined by the word Yuan line (_). When the DRAM cell has been touched, you can retrieve the data inside or write the data to the cell. When reading the DRAM cell 100, the bit line can determine whether there is a source S A voltage, and it shows whether there is a charge in the capacitor 104. If you want to write data to the DRAM cell, you also use the bit line to add charge to the capacitor 104, or to charge the capacitor 104 (please read the back first Please pay attention to this page and then fill out this page) 'Order' This paper size is applicable to the national nursery standard (CNS) A4 specification (2 丨 0X297 published) 310462 Printed by the Ministry of Economic Affairs Central Bureau of Economic Development Beigong Consumer Cooperatives V. Inventions Explain (β) division. With the advancement of DRAM technology, the wafer surface of one DRAM cell is getting smaller and smaller. In this way, each II plane can enter more DRAM cells and make the same area. The suspicion array can store more data. However, after the chip area is reduced, the traditional T-type capacitor or the filled node capacitor becomes too small, so that the capacitance value is insufficient. To make a capacitor with sufficient capacitance value It can be more and more difficult to store the charge meter for a sufficient period of time. There are two methods to improve the capacitance of the DRAM cell capacitor. One method is to reduce the thickness of the effective dielectric layer of the capacitor; the other method is The surface area of the capacitor. The DRAM cell is usually sandwiched between two layers of densely doped polycrystalline silicon and / or silicon pedestal, sandwiching a dielectric material. * The quality and storage capacity of ultra-thin dielectric materials in the future will be Will greatly affect the performance of the DRAM cell. However, the use of ultra-thin dielectric materials, although it can improve the capacitance value, but it will also seriously affect the retention time of the device (that is, the time between two updates). This is because when the membrane is thinner than 50 angstroms, the effective paralysis of direct carrier penetration can cause large leakage currents. Therefore, if you want to design a smaller DRAM cell, it is better to increase the surface of the DRAM slightly so that the Xia Rongyue can be increased enough to allow the charge deposit to stay for a sufficient time. When designing a DRAM cell, on the one hand, it is better to make the size of the cell device as small as possible, on the other hand, the larger the surface area of the container, the better. The two conflicting design characteristics make the design like this The DRAM cell is still a challenge that needs to be overcome. An object of the present invention is to propose a DRAM which has a higher capacitance value because the surface of the capacitor is slightly increased. Another object of the present invention is to propose a DRAM having a four-layer vertical enzyme-type capacitor structure. The invention must be explained (please read the precautions on the back and then fill out this page)% Set the size of this paper to use the Chinese National Standard (CNS) A4 specification (210X297mm). Printed A7 B7 V. Description of the invention (>) In order to achieve some of the purposes of the invention, the present invention proposes a special DRAM with a parallel capacitor structure of four solar cells, and proposes an effective method of making such a DRAM Method ° At the beginning of the first embodiment of the DRAM cell of the present invention, a silicon substrate with a first conductivity type on one side is pre-measured. Field gasification (FOX) * is defined on the substrate to isolate each DRAM cell. Ji Ying and Yuan Ying were also made on the substrate. On the surface of the base plate between Ji Lin and Yuan Liao, there is a plaque of Liao Liao. The Kanying District contains a genus Queboide I, a layer of Poly-1, a layer of tungsten silicide (WSi), a layer of gasification, and a Si02_SiN. The side walls of the Huai area are covered with space of 8 丨 02 or 8 丨> 1. On the Kanji plaque is an insulating eyebrow made of TEOS (Tetraethyl Silicate) or BPSG (Phosphorosilicate). The P〇y-2 layer having the second conductivity type is in contact with the source jade and the Ji plaque. When employed, Poiy-2 will form a bit line and make contact with the source region. On the bit line, it is covered with WSi, a vaporized layer, or thin TEOS and SiyNx and other films such as Si3N4. The side walls of the bit line are also defined by SiyNx empty pits. A capacitor with a four-layer parallel big-head structure is in contact with Ji Lu. Dao capacitors include Poly-3.1 and Poly-3.1 which are doped into the same two-conductivity type, such as thin film / oxide film (NO) or oxide film / nitride film / gasification film (ON0), etc. The dielectric genus, and doped into the second conductivity type P〇ly-4 hire. An implementation side of the DRAM cell of the present invention is made by the following steps: 1. A FOX plaque is defined in the substrate to isolate adjacent cell cells. 2. In each cell, make a _ 椤 with Poly-Ι eyebrow. 3. Make the yin space on the side wall of Kan, and use the yoke and hurricane space as the light army to make a guide fungus in the 1 city out of the substrate to form the source and plaque of DRAM . 4. Cover the cell with TEOS * and add Guangluo to carry out uranium engraving, exposing the source and jiying areas, leaving only TEOS on the yingying area next to the source qiao area. (Please read note f on the back and then fill in the hundred) One pack ·

*1T 本紙張尺度遑用中國國家標丰（CNS )八4规格（210X297公着） 經濟部中央樣隼局貝工消費合作社印f. 31G462 A7 __B7 五、發明説明（//) 5. 沉積一眉Poly-2眉，與露出來的汲極和源欐鼴接觸。接觸到源 極區的P〇ly-2眉並形成位元線。在位元線上覆蓮一層厚厚的氧 化眉’將用來製作平行的鳙型電容器。最後在位元線的側壁上 形成位元線的空間子。 6. 在整個細胞元上-包括汲楹匾和厚雕的觐化臢上翳出來的Poly_ 2層-沉積一雇Poly-3,1層。 7. 用氣化屑覆躉轚個細胞元。蝕去這眉氧化層的一部份，露出部 份的Poly-3.1雇，並在P〇ly-3層的側壁上形成氣化物空間子。然 後在整個細胞元上-包括露出來的Pdy-3.1眉和氣化物空間子_ 沉積一眉Poly-3.2層。 8. 苒一次用氧化層覆蓋璧個細臃元。然後蝕去部份的氣化靥，露 出Poly-3.1靥和Poly-3.2層的頂面。 9. 触去Pdy-3.1雇和Poly-3.2層頂面鼸出的部佾，將Poly-3層分隔成 許多獨立的電容器電棰。 10. 最後蝕去氣化厚層和氣化物齣鰌型空間子，在此電糰上沉稹一 靥介髦眉，在介電屢上再沉積一雇P〇ly-4層後，就形成了第二 電容器電楹。 附圖的簡要說明 本發明在說明時，係參考了以下的附圈： 圖1是一個DRAM的籣圓； 圖2是本發明DRAM第一實施例的樣割面醒； 圖3是本發明一個實施例中四層平符鐮型電容器的容穰銳明圖； 圖4A至圖4J說明了製進國2之DRAM的一個較佳資施例。 較佳實施例的詳細說明 圖2的播剖面圖說明了本發明具有四層平行鳙型電容器之DRAM 本紙張尺度遙用中國國家櫺季（CNS ) A4规格<21〇X 297公釐> ~ (請先閲讀背面之注意事項再填离本頁) 訂 經濟部中央標準局属工消费合作社印製 A7 B7 五、發明説明（ί ) 的較佳實施例。圖2中的兩個DRAM緬胞元共用一懦源欏。虛線C所 包含的是一個細胞元的結構。在遒锢資施例中，細胞元200是製作在 P型的矽基板202上。基板202內定義了場氣化物(FOX)區204 ’以便隔 開各DRAM細胞元。基板內也製作了汲楹和源楹區(D、S)。在汲棰和 源極之間的基板表面上，並有蘭極區(G)。閘欏區包含了一屬鬧極氣 化物206、一眉Poly-Ι層、一眉矽化鏞(WSi)靥208、一靥氧化層210、 和一層Si02SSiN212。在闞楹區的側壁上覆蓋了別〇2或5丨!>1的空間子 214。在閘極區上則是一層TE0S或BPSG作成的絕綠眉216。具有第二 導電型的Poly-2眉與源極和汲極接謂。道屬P〇ly-2層與源櫬接觸的部 位並形成位元線。在位元線上則覆通WSi 218、熱氣化饜或TE0S薄層 220、以及Si3N4之類的SiyNx222。位元線的側壁則由SiyHx空間子224 所覆蓋。 具有四層平行鳍型結構的電容器230會與接觸滠樋匾的P〇ly-2雇 接觸。這個電容器包含了一樣摻雜成第二導電型的p〇1y-31和p〇iy-3.1、諸如氮化膜/觐化膜(NO)或氣化膜/氮化膜/氧化膜(ΟΝΟ)等 類薄薄的介電眉232、和摻雜成第二導電型的P〇ly-4層。匯3是四雇平 行鳍型電容器230的容積說明騙。 圖4A至圔4J的横剖面圓說明了製造圖2之DRAM的較佳實施方 法。請注意，爲了使匾面的說明更爲清晰，圓4A至跚4J中省略了一 些膜雇。舉例來說，闞捶氣化雇就沒有在附疆中表現出來。 圖4A中有一面P型的矽基板202，但熟習此技藝的人士都可瞭解N 型基板也一樣適用。如果使用N型基板，在遒裏所說明的導電型也要 隨之改變成相反的導電型。 在基板202上，先利用熱氣化法，成長一層羅約150至350埃的氣 化墊膜402，然後再利用化學氣相沉積法(CVD)，在觐化蟄膜402上沉 (請先閲讀背面之注意事項再填寫本頁) 裝- 訂 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央標準局員工消费合作社印製 A7 B? 五、發明説明（/ ) 稽一層厚約1000至2000埃的氮化矽(SiyNx)膜404。利用微膨技術與電 漿蝕刻去除部份的氣化蘧臟402和蘸化膜404後，就會在匾4A中選定 的部位上鱷出基板來。 躧4B中，露出來的部位上已經長成場氧化物邐(F〇X)2〇4。成長 FOX時，最好利用熱氣化法。接著用通蝕刻去除瘋化矽臟，最後再去 除氣化墊膜。 圖4C中，已在基板上利用熟氣化法成長了羅約5〇至150埃的闞楹 氧化膜206。然後利用CVD法，在闌極氧化膜上成長一層厚約500至 1500埃的Poly-Ι雇，最好是複晶矽層。摻雜遒層P〇iy_i眉畤，暴例來 說，可以利用同步氣髓摻雜源，使Poly-l眉摻雜成N型的導鼋型。接 著利用CVD法，在摻雜的Po〖y-l雇上沉積一層厚約500至1500埃的矽 化鎢(WSi)208。隨即在WSi層的頂面上成長一層厚約1〇〇至500埃的氣 化眉210。然後再利用CVD在氯化眉210上，沉積一靥庫約1000至 2000埃諸如Si3N4的SiyNx212。道眉氱化眉210是爲了釋放應力，因爲 SiyNx與WSi層的熱膨腿係謙不一樣，所以必須避免SiyNx直接沉積在 WSi層上。最後利用微影技術將道些膜層用光軍加以覆蓋後，再以反 應離子蝕刻法(RIE)蝕去，形成DRAM細胞元的曙欏區。 圖4D中，在整個細胞元上，已經利用CVD法沉積了一屬揮約500 至1000埃的第二SiyNx或8丨02屬。非均向性地蝕鋪邋膜層後，就在閘 極區的側壁上形成了空間子214。接蕃就可以利用任何已知的方式形 成汲楹和源極區。 圖4E中，已經利用CVD法，沉稍了一層霞約1〇〇〇至5000埃的 TE0S或BPSG(硼磷矽酸鹽)絕緣勝216。接蕃利用微影枝術將道眉 TEOS或BPSG遮蔽後，再以RIE進行蝕刻，只在緊鄰源檷匾的閑棰上 留下TE0S，並霣出汲楹和源楹區。 (請先鬩讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國國家梯準（CNS ) A4规格（210X297公釐） A7 310462 五、發明説明、 圖4F中，在轚個細胞元上，已經利用CVD法沉犢了一雇厚約500 至1500埃的Poly-2層，最好是複晶矽化物眉。Pdy，2層利用詞步摻雜 氣體源加以摻雜後，具有N型的導電型。p〇ly-2雇與露出來的汲權和 源楹接觸。在摻雜的P〇ly-2層上，接著利用CVD法沉稍一層厚約500 至1500埃的矽化鎢(WSi)層218。在WSi雇上，再成長一曆厚約100至 500埃的热氧化眉或TEOS薄屬220。接下來，在颯化靥220上，再沉積 一雇厚約1000至2000埃Si3N4—類的SiyNx或Si02222，所用的方法可 以是CVD。然後在3丨^5(眉222上，再以CVD法沉稹一層厚約3000至 10000埃的氣化厚層410，可以是SiO。最後利用檄影技術將道SiO、 SiyNx、TEOS和WSi等膜層遮蔽後，再以RIE或電漿蝕刻進行鈾刻。 所留下的膜眉會覆蓋在源楹上方的Poly-2位元鐮匾域。其餘鏞出來的 P〇ly-2蝕去部份後，會呈現凹下的狀態，因而在汲極匾上方留下Poly-2的凹窪部位。 圓4G中，在整個細胞元上，利用CVD法沉積了一屬厚約300至 1000埃的第二SiyNx層。非均向性地蝕刻這膜屬後*就在位元線的側 壁上形成了空間子224。接蕃在整個元上，利用CVD法沉積一屑 厚約300至1000埃的Poly-3.1眉。然後利用同步摻雜氣體源加以接雜， 使Pdy-3.1雇具有N型的導電型。需注意的是，道雇Poly-3J層會接觸 到接觸汲極的P〇ly-2眉，形成一個接觸汲檷區的導電區。接著在Poly-3.1 層上的整個細胞元上 ，利用 CVD 法沉稽一層 TEOS 等類的倮形氣化 雇420。 圖4H中，已經非均向性地蝕去了載化層420，在Poly-3.1層的側 壁上形成氣化物麒型空間子422，但_時也鼸出部份的P〇丨y-3.1層。接 著在整個的細胞元上，利用CVD法沉積一靥ϋ約300至1000埃的Poly-3.2眉。道眉Pdy-3.2層會覆蠆在鰌型空間子422上並與露出來的Poly- 本紙張尺度逋用中國國家梂準（CNS ) A4规格<21〇X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部中央標準局貝工消费合作社印製 經濟部中央標窣局貝工消费合作社印装 Λ7 B7 五、發明説明（/ ) 3.1層接觸。這層Poly-3.2屬也_利用闺歩的摻雜雛體源，摻雜成N型 的導電型。 接著在整個的細胞元上，利用CVD或旋佈的沉積法，沉穰第二屬 的氧化層424，可用的材料有SOG、聚乙醢胺、光祖或BPSG，填滿 P〇ly-3靥內的凹窪處，並高到圖中虛^|所表示的地方。利用RIE對觐 化層進行平坦化和回鈾刻之後，就露出圓州中Poly-3.1和Poly-3.2靥 的頂面。 圓41中，Poly-3.1和Pdy-3.2靥露出的部位已經利用RIE回蝕刻過 了。道道蝕刻的步驟使得P〇丨y-3層隔絕成許多獨立的電容器電裡。填 在凹窪處並形成籣型空間子似2的氧化層也利用氧化物對權晶矽、或 高分子對複晶矽的選擇性RIE和SiN的蝕刻去除了。阀時也蝕去了氣 化厚層410。在Poly-3屬上並沉穣一層HSG(半球晶粒複晶矽），使電極 的表面楹不平滑，更增加了表面面積。隨即利用RIE，對道層HSG回 .......................... 蝕刻。最後，利用光罩遮蔽P〇ly-3屬後，在以RIE蝕刻，使Poly_2沿線 上相鄰的電容器得以隔関。然後在Poly-3靥上，利用CVD沉穡一層厚 約40至60埃、諸如ΟΝΟ或NO的介電濯232。 圖4冲，已經在介電屬232上，利用CVD法沉稍了一層薄約1000 至2000埃的Poly-4層，最好是複晶矽。道屬P〇ly-4屬並利用岡步的摻 雜氣體源，摻雜成N型的導電型。摟著利用微影枝術，將Pdy-4層遮 蔽後，再進行回蝕刻。 接下來完成這個細胞元製程所讎嬰的後段製翟，是大家熟知的， 在道裏不作詳細的說明。 我們提出了一種利用四層平行鰌型電容器提裹電容値的DRAM。 同時，我們也提出了兩種有效方法，可以用来製逢道種雜有籣狀結構 的 DRAM。 本紙張尺度適用中國阃家棣率（CNS ) A4规格（210X297公釐） ~ ~ (請先閲绩背面之注意事項再填寫本頁) *?τ Γ A 7 _B7 五、發明説明（/ ) 以上本發的實施例只最用來擧例說明本發明，熟習本技藝的人 士仍可以設計出許多不同的資施例，卻仍不離翮以下申讅專利範的 精神與範圍。 (請先聞讀背面之注意^項再填寫本頁) •裝. -1° 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國國家樑準（CNS ) A4规格（210X297公釐）* 1T The size of this paper is not in accordance with China National Standard (CNS) 84 specifications (210X297 publication). Printed by the Central Sample Falcon Bureau of the Ministry of Economic Affairs Beigong Consumer Cooperative Society f. 31G462 A7 __B7 5. Description of the invention (//) 5. Deposit 1 Eyebrow Poly-2 eyebrow, in contact with the exposed Ji Ji and Yuan Zhen. It contacts the Ply-2 eyebrow in the source region and forms a bit line. A thick layer of oxidized eyebrows covered with lotus on the bit line will be used to make parallel big-head capacitors. Finally, the space of the bit line is formed on the side wall of the bit line. 6. On the entire cell-including Jiying plaque and thick carved plaques on the surface of the Poly_ 2 layer-deposit a layer of Poly-3, 1 layer. 7. Cover the cells with vaporized debris. A part of the oxide layer of the eyebrow is etched away, a part of Poly-3.1 is exposed, and a vapor space is formed on the side wall of the Poly-3 layer. Then deposit a poly-3.2 layer on the entire cell, including the exposed Pdy-3.1 eyebrow and the vaporization space. 8. Ran once covered with an oxide layer to cover a small element. Then evaporate part of the vaporized Tatium, exposing the top surfaces of the Poly-3.1 Tallium and Poly-3.2 layers. 9. Touch the Pdy-3.1 and Poly-3.2 layer tops to separate the Poly-3 layer into many independent capacitors. 10. Finally, the thick vaporized layer and the vaporized gas space were etched away, and Shen Zhenyi and Shimei Jiemei were deposited on this cluster, and a layer of P〇ly-4 was deposited on the dielectric repeatedly. The second capacitor is electrically connected. Brief Description of the Drawings In describing the present invention, the following reference ring is referred to: FIG. 1 is a DRAM circle; FIG. 2 is a sample cut surface of the first embodiment of the DRAM of the invention; FIG. 3 is a diagram of the invention The embodiment of a four-layer flat-shaped sickle-shaped capacitor is shown in Figures 4A to 4J illustrating a preferred embodiment of the DRAM made in the country 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The broadcast cross-sectional view of FIG. 2 illustrates the DRAM of the present invention having four-layer parallel big-head capacitors. The paper size is remotely used. China National Season (CNS) A4 Specification < 21〇X 297mm > ~ (Please read the precautions on the back before filling out this page) Order A7 B7 printed by the Industrial and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. The preferred embodiment of the invention description (ί). The two DRAM cells in Figure 2 share a cowardly source. The dotted line C contains the structure of a cell. In the embodiment, the cell 200 is fabricated on a P-type silicon substrate 202. A field vaporization (FOX) region 204 'is defined in the substrate 202 to isolate each DRAM cell. Jiying and Yuanying areas (D, S) were also made in the substrate. On the surface of the substrate between the drain and the source, there is a blue pole region (G). The Zhazi area contains a genus of anomalous vapor 206, a layer of Poly-I, a layer of Wye 208, a layer of oxide 210, and a layer of Si02SSiN212. On the side wall of the Kanding area is covered a space 214 of 〇2 or 5 丨!> 1. Above the gate area is a layer of green eyebrow 216 made of TEOS or BPSG. The Poly-2 eyebrow with the second conductivity type is connected to the source and the drain. It belongs to the position where the P〇ly-2 layer contacts the source and forms a bit line. On the bit line, it is covered with WSi 218, thermal vaporization or TEOS thin layer 220, and SiyNx222 such as Si3N4. The sidewall of the bit line is covered by the SiyHx space 224. A capacitor 230 with a four-layer parallel fin structure will be in contact with Ply-2 contacting the plaque. This capacitor contains p〇1y-31 and p〇iy-3.1, which are doped into the second conductivity type, such as nitride film / porous film (NO) or vaporized film / nitride film / oxide film (ΟΝΟ) A thin dielectric eyebrow 232 and the like, and a Poly-4 layer doped into the second conductivity type. Sink 3 is a description of the capacity of four parallel fin capacitors 230. The cross-sectional circles of FIGS. 4A to 4J illustrate the preferred method of manufacturing the DRAM of FIG. Please note that in order to make the explanation of the plaque surface clearer, some of the films are omitted from Yuan 4A to Yuan 4J. For example, Kan Hao's gasification employment did not show up in Fujiang. In FIG. 4A, there is a P-type silicon substrate 202, but those skilled in the art can understand that the N-type substrate is also applicable. If an N-type substrate is used, the conductivity type described in Hiroshi should also be changed to the opposite conductivity type. On the substrate 202, first use a thermal vaporization method to grow a layer of vaporization pad film 402 of about 150 to 350 Angstroms, and then use chemical vapor deposition (CVD) to sink on the varnish film 402 (please read first Note on the back and then fill out this page) Binding-The standard paper size is in accordance with the Chinese National Standard (CNS) A4 (210X297mm) A7 B printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (/) A silicon nitride (SiyNx) film 404 with a thickness of about 1000 to 2000 angstroms. After the micro-expansion technique and plasma etching are used to remove part of the vaporized dirt 402 and the dipping film 404, the substrate is crocodile on the selected part of the plaque 4A. In Li 4B, a field oxide (F〇X) 2〇4 has grown on the exposed part. When growing FOX, it is best to use the thermal gasification method. Next, through etching to remove the crazy silicon dirt, and finally remove the vaporization pad film. In FIG. 4C, a metal oxide film 206 having a thickness of about 50 to 150 angstroms has been grown on the substrate by a cooked gasification method. Then use CVD method to grow a layer of Poly-I with a thickness of about 500 to 1500 Angstroms on the stopper oxide film, preferably a polycrystalline silicon layer. The doped layer P〇iy_i eyebrow, for example, can be used to synchronize the medullary doping source, the Poly-l eyebrow is doped into an N-type conduction type. Next, a layer of tungsten silicide (WSi) 208 with a thickness of about 500 to 1500 angstroms is deposited on the doped Po 〖y-l using the CVD method. A vaporized eyebrow 210 with a thickness of about 100 to 500 angstroms is then grown on the top surface of the WSi layer. Then using CVD on the chlorinated eyebrow 210, depositing a library of about 1000 to 2000 Angstroms such as Si3N4 SiyNx212. The eyebrow 210 is for stress relief. Because the thermal expansion of the SiyNx and WSi layers is different, it is necessary to avoid the direct deposition of SiyNx on the WSi layer. Finally, using photolithography technology to cover these film layers with Guangjun, and then etched away by reactive ion etching (RIE) to form the DRAM cell area. In FIG. 4D, on the entire cell, a second SiyNx or 820 genera with a genus of about 500 to 1000 angstroms has been deposited by CVD. After anisotropically etching the sloppy film layer, a space 214 is formed on the sidewall of the gate region. You can use any known method to form the Jiying and source regions. In FIG. 4E, a CVD method has been used to deposit a layer of TEOS or BPSG (borophosphosilicate) insulation from about 1,000 to 5,000 angstroms. After using the shadowing technique to cover the eyebrow TEOS or BPSG, Jiefan then etched it with RIE, leaving only TEOS on the idle place next to the source plaque, and then the Jiying and Yuanying areas. (Please read the precautions on the back before filling in this page). The size of the bound paper is applicable to China National Standard (CNS) A4 (210X297mm) A7 310462 5. Description of the invention, Figure 4F, in the cell Primarily, a Poly-2 layer with a thickness of about 500 to 1500 Angstroms has been deposited by CVD, preferably polycrystalline silicide. Pdy, layer 2 is doped with word step doping gas source and has N-type conductivity. p〇ly-2 hired to come into contact with the exposed Jiquan and Yuanying. On the doped Poly-2 layer, a layer of tungsten silicide (WSi) 218 with a thickness of about 500 to 1500 angstroms is deposited by CVD. On WSi employment, grow a thermal oxide eyebrow or TEOS thin genus about 100 to 500 Angstroms thick. Next, a second layer of Si3N4-type SiyNx or Si02222 with a thickness of about 1,000 to 2,000 angstroms is deposited on the tantalum 220. The method used may be CVD. Then on the 3 ~ ^ 5 (eyebrow 222, a CVD thick layer 410 of about 3000 to 10,000 Angstroms thick is deposited by CVD, which can be SiO. Finally, the SiO, SiyNx, TEOS and WSi etc. After the film layer is masked, uranium engraving is performed by RIE or plasma etching. The left eyebrow will cover the Poly-2 bit sickle plaque field above the source. The P〇ly-2 etched away from the remaining yam After copying, it will be in a concave state, so that the concave part of Poly-2 is left above the Jiji plaque. In the round 4G, a genera with a thickness of about 300 to 1000 Angstroms is deposited on the entire cell by CVD method The second SiyNx layer. After anisotropically etching the film, a space 224 was formed on the side wall of the bit line. Then, on the entire element, a chip with a thickness of about 300 to 1000 angstroms was deposited by CVD. Poly-3.1 eyebrows. Then use the synchronous doping gas source to do the impurity, so that Pdy-3.1 has N-type conductivity. It should be noted that the Dao Poly-3J layer will contact the P-ly contacting the drain 2 eyebrows, forming a conductive area that contacts the Jilu area. Then, on the entire cell on the Poly-3.1 layer, a layer of TEOS and other inert gas is deposited by CVD method 420. In Fig. 4H, the carrier layer 420 has been anisotropically etched away, and a vaporized gas space 422 is formed on the side wall of the Poly-3.1 layer, but part of the P〇 丨y-3.1 layer. Then, on the entire cell, a poly-3.2 eyebrow is deposited by CVD with a thickness of about 300 to 1000 Angstroms. The pdy-3.2 layer of the eyebrow will be covered on the typhoon-shaped space 422 and exposed Incoming Poly-This paper is based on China National Standards (CNS) A4 Specification < 21〇X297mm) (Please read the notes on the back before filling out this page) -Finishing and ordering Consumer Cooperatives Printed by the Ministry of Economic Affairs Central Standardization Bureau Beigong Consumer Cooperatives Printed Λ7 B7 V. Description of Invention (/) 3.1-layer contact. This layer of Poly-3.2 is also doped into an N-type conductivity by using the dopant body source of the girl. Then, on the entire cell, using CVD or spin-on deposition method, the second layer of oxide layer 424 Shen Shen, available materials are SOG, polyethylene acetamide, optical progenitor or BPSG, filled with P〇ly-3 The dimples in the tars are as high as the imaginary ^ | in the figure. After using RIE to planarize and uranium engraving, the top surfaces of Poly-3.1 and Poly-3.2 in Yuanzhou are exposed. In circle 41, the exposed parts of Poly-3.1 and Pdy-3.2 have been etched back by RIE. The step of etching makes the P〇 丨 y-3 layer isolated into many independent capacitors. The oxide layer that fills the depressions and forms lacquer-like space 2 is also removed by the selective RIE and SiN etching of the oxide on the polycrystalline silicon or the polymer on the polycrystalline silicon. The valve also etched away the vaporized thick layer 410. A layer of HSG (Hemispherical Grain Polycrystalline Silicon) is deposited on Poly-3 to make the surface of the electrode uneven and increase the surface area. Immediately using RIE, the HSG of the track layer is etched back .......................... Finally, after masking the P〇ly-3 genus with a photomask, it was etched by RIE, so that the adjacent capacitors along the Poly_2 line could be isolated. Then on Poly-3, a layer of dielectric material 232 such as ΟΝΟ or NO is deposited by CVD with a thickness of about 40 to 60 angstroms. As shown in Figure 4, a layer of Poly-4 with a thickness of about 1000 to 2000 Angstroms has been deposited on the dielectric 232 by CVD, preferably polycrystalline silicon. Dao belongs to P〇ly-4 genus and uses Gangbu's doped gas source to dope into N-type conductivity. After using lithography technique to mask the Pdy-4 layer, etch back. Next, the completion of the post-production process of this cell-cell manufacturing process is well known and will not be described in detail in the Dao. We have proposed a DRAM that uses four layers of parallel solar capacitors to wrap the capacitance. At the same time, we have also proposed two effective methods that can be used to make DRAMs with vine-like structures. The size of this paper is applicable to China's national family rate (CNS) A4 specification (210X297mm) ~ ~ (please read the notes on the back of the performance first and then fill in this page) *? Τ Γ A 7 _B7 V. Invention description (/) or more The embodiments of the present invention are only used to exemplify the present invention. Those skilled in the art can still design many different embodiments, but still do not deviate from the spirit and scope of the following patent application. (Please read the notes on the back ^ item before filling in this page) • Installed. -1 ° Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy

Claims (1)

A8SC8D8 A、申請專利範圍 1·一種動態隨機存取記慊體(DRAM)元件，係包含： a. —個金屬氣化物半導鼸場效電晶髓(MOSFET) »具有一個汲楹 一個源極和一個閘極; b. —條位元線， c· 一個電容器連 2.根據申請專利範i a.該MOSFET，另外又包含了 (1) 一面基板，具有第一導電型； (2) 該汲極和源極係定義在該基板內； (3) 該閘極區具有第一複晶矽化物眉，位在該汲欏和濂權之間，並 位在該基板上； (4) 一個空間子，覆邏在駭關欏的側轚上； b·—層第二複晶矽化物眉，具有與第一_電型相反的第二導電型， 並與該汲極和源極接觸；該位元線包含了該第二襪晶矽化物雇與 該源楹接觸的部位； c. 一個空間子，覆蓋在該位元線的讕壁上；並且 d. 該電容器與接觸汲檷區的第二權晶矽化物層接觸，該電容器係包A8SC8D8 A. Patent scope 1. A dynamic random access memory (DRAM) device, which includes: a.-A metal vaporized semiconducting field effect electric crystal (MOSFET) »has one source and one source And a gate; b. — A bit line, c. A capacitor connected 2. According to patent application i a. The MOSFET, in addition, includes (1) a substrate with a first conductivity type; (2) the The drain and source are defined in the substrate; (3) The gate region has a first polycrystalline silicide eyebrow, located between the drain and the right, and located on the substrate; (4) a Spacer, covered on the side wall of the phoenix; b · -layer of the second polycrystalline silicide eyebrow, has a second conductivity type opposite to the first electrical type, and is in contact with the drain and the source; The bit line includes the portion where the second sock crystal silicide is in contact with the source jade; c. A space covering the bit wall of the bit line; and d. The second power crystal silicide layer contacts, the capacitor is packaged f有四層平行鼸型的外型 中： (請先聞讀背面之注意事項再填其本頁)f has a four-layer parallel mullet-shaped appearance. (Please read the precautions on the back before filling this page) 經濟部中央揉準局員工消费合作社印製 (1) 一個第一電楹，具有第二導轚型，並具有四雇平行觼型的外 型； (2) —層介電層，覆驀該第一電捶的第一面；以及 (3) —個第二電楹，覆邏該介電雇，並與該第_電檷的第一面相 對。 3.根據申請專利範圔第2項之1}態_蟣存取記慯雠元件，其中該鬮樋 包含了一雇與該基板接觸的曙極氯化眉、一厢覆蓋在該間極氣化 本纸張尺度適用中國鬮家標率（CNS ) A4规格（210X297公釐）Printed by the Employee Consumer Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs (1) A first electrical connector, with a second lead type, and a four-arm parallel-type appearance; (2)-a dielectric layer, covering the The first side of the first electrical hammer; and (3) A second electrical jack, which covers the dielectric and opposes the first surface of the first electrical pole. 3. According to the 1st state of the second item of the patent application, access to the memory element, in which the switch contains a chlorinated eyebrow that is in contact with the substrate, and the compartment is covered in the polar gas The standard of this paper is applicable to the Chinese standard rate (CNS) A4 specification (210X297mm) 經濟部中央揉率局負工消费合作社印策 六、申請專利範園 層上並摻雜成第二導電型的第一複晶砂化物(Pdy4)雇、一靥覆蓋 在該P〇bM層上的矽化鎢(WSi)層、一層位在WS_上的氧化層、和 一層位在該氧化眉上的氮化矽層。 4. 根據申誚專利範園第2項之動態讎機灕取Ιδ植嫌元件，其中胲鬧極 空間子包含了一眉m化矽層。 5. 根據申請專利範圍第2項之動態鼸檐存取記慊黼元件，其中駭位元 線包含了：一眉與該源欐匾接觸並摻雜成第二導電型的第二複晶砂 化物(P〇ly-2)層、一眉位在該P〇ly-2繼上的矽化鎢(WSi)靥、一層位 在該WSi眉上的氣化眉、和一層位在駭氣化屬上的鼴化矽靥。 6. 根據申請專利範圍第2項之動態鳙檐存取記嫌鼸元件，其中該覆躉 位元線側壁的空間子包含一雇氮化發眉。 7. 根據申誚專利範園第2項之動態隨檐存取記嫌Μ[元件，其中該第一 電楹包含了第三複晶矽層，而第二電欏則包會了鳙四複晶砂層，該 第三和第四複晶矽層都摻雜成第二導電型；並且讅介電屬係由ΟΝΟ 和NO中選擇其中之一。 8. —種動態隨機存取記慊髓(DRAM)元件的製進方法，其步驟係包 含： a. 在一面具有與第一導罨型相反之第二導電型的碁板上，製作一個 具有第一導電型的閜楹； b. 利用該Μ捶作爲光簞，在駭基板內形成一個薄欏匾和一個汲楣 區； c. 用一層具有第一導電型的導電材料覆蠆住該元件，並且部份蝕刻 該導電材料，形成一條位元線，與胲激楹摟觸•並且形成一個凹 下的膜層，與該檷源欏接觸； (請先閲讀背面之注f項再填寫本I)The Ministry of Economic Affairs, Central Bureau of Labor and Insurance Cooperative Printing Co., Ltd., the sixth, the patent application layer and doped into the second conductivity type of the first polycrystalline sand (Pdy4) employed, a layer covered on the P〇bM layer A tungsten silicide (WSi) layer, an oxide layer on WS_, and a silicon nitride layer on the oxide eyebrow. 4. According to Item 2 of the Shenzhuang Patent Fan Garden, the dynamic device is used to extract Ιδ plant components, in which the anodic polar space contains a silicon layer. 5. According to item 2 of the scope of the patent application, the dynamic eaves access memory element, where the bit line includes: a second eyelet contacting the source plaque and doped into a second conductivity type second polycrystalline sand Compound layer (P〇ly-2), a layer of tungsten silicide (WSi) on the P〇ly-2 layer, a layer of gasified eyebrows on the WSi eyebrow, and a layer on the gasification genus The mole of silicon on the surface. 6. According to item 2 of the scope of the patent application, the dynamic eaves access memory device, wherein the space covering the side wall of the bit line contains a nitrided eyebrow. 7. According to item 2 of the Shenzhuang Patent Fan Garden, the dynamic access control is based on the M [element, in which the first electro-panel contains a third polycrystalline silicon layer, and the second electro-conductor contains a large number of complexes. In the crystal sand layer, the third and fourth polycrystalline silicon layers are all doped into the second conductivity type; and the dielectric system is selected from ΟΝΟ and NO. 8. A method of manufacturing a dynamic random access memory (DRAM) device, the steps of which include: a. On one side of a second board with a second conductivity type opposite to the first one, fabricate a The first conductivity type 楹; b. Use the M hammer as a photocell to form a thin plaque and a lintel area in the substrate; c. Cover the element with a layer of conductive material having the first conductivity type , And partially etch the conductive material to form a bit line, which is in contact with the ginseng and forms a concave film layer, which is in contact with the source of 椷 源; (Please read note f on the back before filling in this I) 本紙張尺度逋用中鼷困家標率（CNS ) Α4规格（210X297公兼) A8 BS CS D8 娌濟部中央標率局Μ工消费合作社印製 六、申請專利範圍 d. 用一種可蝕刻的材料將整個元件覆蓋住，並蝕刻該可蝕刻的材 料，沿著該位元線形成平行線，並霪出與駭汲樋區接觸的導電材 料； e. 在該平行線上形成第一電容器電欏的第一部份，並與接觸駭汲極 區的導電材料接觸； f. 在該第一部份上沉積一層可蝕刻的材料； g. 非均向性地蝕刻該可蝕刻的材料，在該第一部份的側壁上形成鰭 型的空間子，並露出該第一部份的其他都位； h. 形成該第一電容器電極的第二部份，與該鰌型空間子和該第_部 份露出的部位接觸； i. 在該第一電容器電極上沉積一層介電層；並且 j. 在該介電層上形成第二電容器電裡。 9. 根據申請專利範国第8項的方法，其中該製作_的步驟又包含以 下的步驟： a. 在該基板的表面上成畏一層閜楹龈化眉； b. 在該閘楹氣化眉上沉穑第一播晶矽化物層(Poly-】）； c. 將該第一複晶矽化物層接雜成第一導電型； d. 在該接雜的第一複晶矽化物眉上沉積一履矽化鏈屬(WSi); e. 在該WSi上沉稽一眉氧化層； f. 在該氧化屑上沉稍一眉龈化矽靥；並且 g. 蝕刻該閘極氧化屬、第一複晶矽化物層 '矽化鎢WSi靥、氧化層 和氮化矽眉，形成一個閑欏區。 10. 根據申誚專利範醒第9項的方法，其中該製作蹐樋的步驟又包含以 下的步驟： a.在該閘楹區上沉積一雇第二氮化砂層；並且 (請先闥讀背面之注意事項再填寫本頁) 、言This paper scale is printed with the standard of China National Standards (CNS) Α4 specification (210X297 public) A8 BS CS D8 Printed by the Central Bureau of Standards and Scale of the Ministry of Economic Affairs, M Industry and Consumer Cooperatives 6. The scope of patent application d. Use an etchable The material covers the entire element, and the etchable material is etched, parallel lines are formed along the bit line, and the conductive material in contact with the Haji area is formed; e. Forming the first capacitor electrical lumen on the parallel line The first part, and in contact with the conductive material in contact with the drain-drain region; f. Deposit a layer of etchable material on the first part; g. Anisotropically etch the etchable material in the A fin-shaped space is formed on the side wall of the first part, and all other positions of the first part are exposed; h. A second part of the electrode of the first capacitor is formed, together with the 鰌 type space and the _ The partially exposed part is in contact; i. Deposit a dielectric layer on the first capacitor electrode; and j. Form a second capacitor on the dielectric layer. 9. The method according to item 8 of the patent application country, in which the step of making _ includes the following steps: a. A layer of gingivalized eyebrows is formed on the surface of the substrate; b. Gasification at the gate Shen Biao first seed crystal silicide layer (Poly-)); c. The first polycrystalline silicide layer is mixed into the first conductivity type; d. The first polycrystalline silicide eyebrow on the splice Deposited on a silicide chain genus (WSi); e. Shen Ji-eyebrow oxide layer on the WSi; f. Sink a little eyebrow gingival silicon on the oxide debris; and g. Etching the gate oxide genus, first The polycrystalline silicide layer 'tungsten silicide WSi, oxide layer, and silicon nitride eyebrow form an idle area. 10. According to the method of item 9 of the patent application, the step of making the switch includes the following steps: a. Deposit a second layer of nitrided sand on the gate area; and (please read first (Notes on the back then fill out this page) 、 言 本紙張尺度逋用中國國家櫟準（CNS ) Α4规格（210X297公§ ) 經濟部中央揲準局貝工消费合作社印装 m C8 D8 六、申請專利範圍 b.非均向性地蝕刻該第二氮化矽層。 11. 根據申誚專利範園第8項的方法，其中該利用導電材料覆蘿住元件 的步驟另外尚包含： a. 在該元件上沉積一屬第二複晶砂化物屬(Poly-2);並且 b. 將該第二複晶矽化物層摻雜成第一導電型。 12. 根據申請專利範圍第8項的方法，其中該形成位元線的步驟另外尚 包含： a. 在該摻雜的第二複晶矽化物靥上沉積一靨矽化鏞靥(WSi)上； b. 在WSi眉上成長一層氣化層； c. 在該氣化眉上沉積一層SiyNjf ;並且 d. 蝕刻該第二複晶矽化物層、WSi層、氧化雇和親化矽曆，形成該 位元線。 13. 根據申請專利範圍第8項的方法，其中該形成第一電容器電棰之第 一部份的步驟係包含： a.在該平行線上沉積第三襯晶矽眉(Pdy-3.1)，並與駭汲檷接觸；並 且 d.將第三複晶矽化物層摻雜成第_導電型。 14. 根據申誚專利範圍第8項的方法，其中該形成第一電容器電極之第 二部份的步驟係包含： a. 在該第一電容器電極之籣一部份上沉糖第三複晶矽層(Pdy-3.2)， 並與該汲楹接觸；並且 b. 將該第三複晶砂化物眉接雜成第一導電型。 15. 根據申謂專利範圍第8項的方法，其中該形成第一電容器電棰之第 二部份的步驟在蝕刻該第三複晶矽化物靥的頂面之後，另外又包 含：在該第一電容器電插上沉積一雇半球晶粒的複晶矽。 (請先閲讀背面之注f項再填寫本頁) •裝. '1T 本纸張尺度適用中國國家襟準（CNS ) A4规格（2丨0X297公釐} A8B8C8S 六、申請專利範圍 16.根據申請專利範園第8項的方法，其中該形成第二電容器電極的步 驟係包含： a. 在該介電眉上沉積第四複晶矽層(Pdy-4); b. 將該第四複晶矽層摻雜成第一導電型；並且 c·蝕刻該摻雜的第四複晶矽眉。 ----------„__— — ------1T (請先閱讀背面之注$項再填寫本頁) 經濟部中央榡準局貝工消费合作社印製 本紙張又度適用中國國家標率（CNS ) A4规格（210X297公*)The size of this paper is printed in China National Oak Standard (CNS) Α4 (210X297) § Printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs Beigong Consumer Cooperative Society m C8 D8 6. Scope of patent application b. Anisotropically etch the second Silicon nitride layer. 11. The method according to item 8 of Shenzhuang Patent Fan Garden, wherein the step of covering the element with a conductive material additionally includes: a. Depositing a second polycrystalline sanding genus (Poly-2) on the element ; And b. Doping the second polysilicide layer into the first conductivity type. 12. The method according to item 8 of the patent application scope, wherein the step of forming a bit line further includes: a. Depositing a tungsten silicon lutetium tungsten (WSi) on the doped second polycrystalline silicide tantalum (WSi); b. grow a vaporized layer on the WSi eyebrow; c. deposit a layer of SiyNjf on the vaporized eyebrow; and d. etch the second polycrystalline silicide layer, WSi layer, oxidized and affinity silicon calendar to form the Bit line. 13. The method according to item 8 of the patent application scope, wherein the step of forming the first part of the first capacitor electrode includes: a. Depositing a third crystal-lined silicon eyebrow (Pdy-3.1) on the parallel line, and Contact with Haoji Ji; and d. Doping the third polycrystalline silicide layer into the first conductivity type. 14. The method according to claim 8 of the patent application scope, wherein the step of forming the second part of the first capacitor electrode includes: a. Depositing sugar on the part of the first capacitor electrode to form a third polycrystal A silicon layer (Pdy-3.2), and is in contact with the jiying; and b. The third polycrystalline sand is mixed into a first conductivity type. 15. The method according to claim 8 of the patent scope, wherein the step of forming the second part of the first capacitor electrode after etching the top surface of the third polycrystalline silicide tantalum, further includes: A capacitor is electrically plugged with polycrystalline silicon deposited with a hemispherical grain. (Please read note f on the back and then fill out this page) • Installed. '1T This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 0X297mm) A8B8C8S VI. Patent application scope 16. According to the application The method of Item 8 of Patent Fanyuan, wherein the step of forming the second capacitor electrode includes: a. Depositing a fourth polycrystalline silicon layer (Pdy-4) on the dielectric eyebrow; b. Depositing the fourth polycrystalline silicon layer The silicon layer is doped into the first conductivity type; and c. Etching the doped fourth polycrystalline silicon eyebrow. ---------- „__— — ------ 1T (please read first Note $ on the back and then fill in this page) The paper printed by the Beigong Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economy is again applicable to China ’s National Standard Rate (CNS) A4 specification (210X297 g *)