TW308730B - Manufacturing method of porous dielectric in integrated circuit and integrated circuit thereof - Google Patents

Abstract

A manufacturing method of porous dielectric in integrated circuit comprises of the following steps: (1) supplying one semiconductor substrate with component structure, on which there is at least one pattern first metal layer capped; (2) depositing one SiO2 capping on the first metal layer; (3) depositing one silicon nitride layer capping on the SiO2 layer; (4) depositing one silicon-containing metal layer capping on the silicon nitride layer; (5) etching the silicon-containing metal layer, making the contained silicon left on the silicon nitride surface, forming silicon nodule;(6) etching to remove the silicon nitride where is not capped by those silicon nodules, leaving pillar silicon nitride under those silicon nodules; (7) with spin-on-glass coating on the silicon nitride, and via baking, curing forming one spin-on-glass layer surrounding those pillar silicon nitride;(8) removing the silicon nodule and those pillar silicon nitride, leaving void in the spin-on-glass layer; (9) depositing one second SiO2 capping on the spin-on-glass layer, finishing the porous dielectric in the integrated circuit.

Description

308730 A7 B7 五、發明説明（i ) 本發明係關於一種降低積體電路金屬化後產生之熱應 力之方法，特別關於一種在介電質層内形成孔洞以降低積 體電路金屬化後產生之熱應力之方法。 本發明關於一種減低金屬化之積體電路元件内熱應力 之方法，特別關於金屬層生成後，藉由控制積體電路之金 屬間介電質層及護層内孔洞之生成而降低熱應力之方法。 爲防止產生電遷移及應力遷移等現象，在傳統之積體 電路製程之設計上，金屬層上下之各層都沒有孔洞，例如 習知技術中13乂61111^3等在113?3161^ 5,099,304揭露之技 術中所不希望形成之孔洞。 熱應力之生成係由於各層在熱膨脹係數之差異所引起 ，應力大小可以下式表之。308730 A7 B7 5. Description of the invention (i) The present invention relates to a method for reducing thermal stress generated after metallization of an integrated circuit, in particular to a method of forming holes in a dielectric layer to reduce the generation of metalized integrated circuits The method of thermal stress. The present invention relates to a method for reducing thermal stress in metalized integrated circuit components, and particularly to reducing thermal stress by controlling the formation of holes in the intermetal dielectric layer and protective layer of the integrated circuit after the formation of the metal layer method. In order to prevent the phenomenon of electromigration and stress migration, in the design of the traditional integrated circuit process, there is no hole in each layer above and below the metal layer, for example, 13 × 61111 ^ 3 in the conventional technology is disclosed in 113? 3161 ^ 5,099,304 Undesirable holes in technology. The generation of thermal stress is caused by the difference in thermal expansion coefficient of each layer, and the stress can be expressed by the following formula.

St:(af-as)(Tr-T〇)E 其中：St: (af-as) (Tr-T〇) E where:

St爲室溫度下受測層之應力大小； af爲受測層之熱膨脹係數； 經濟部中央棣率局貝工消費合作社印製 as爲基板（此處基板定義爲受測層以下各層之總和）之 熱膨脹係數；St is the stress level of the tested layer at room temperature; af is the thermal expansion coefficient of the tested layer; printed by the Beigong Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs as the substrate (here the substrate is defined as the sum of the layers below the tested layer) Coefficient of thermal expansion;

Tr爲受測層熱處理或形成時之溫度， T〇爲室溫，即量測應力之溫度；以及 E爲薄層之楊氏係數。 製程中冷熱循環皆會使各層產生熱應力，此應力之力小甚 至高達5X109達因/平方公分。太大之應力容易造成金屬 層應力遷移（stress migration)、介電質斷裂及矽基板之 83. 3.10,000 本紙張尺度適用中國國家棣率（CNS ) A4规格（210X297公釐） —3 308730 A7 B7 五、發明説明（2.) 結晶缺陷。 在此次微米之多層超大型積體電路（submic^n multi revel VLSI circuit)上金屬間介電質是很重要的— 層。金屬間介電質層廣泛地採用二氧化矽與旋覆玻璃（ spin- on -glass)構成之三明治結構。第1圖續·示一習知 積體電路之一部分，其中，半導體基板1〇上形成場氧化區 12,而其他元件結構，如閘極14及源/汲極區15亦形成於 基板10上。金屬接觸窗口穿透絕緣層16通至半導體基板】〇 ，一第一金屬層20沈積、定義出圖案以達成接觸。圖中顯 示在第一金屬層20上有一傳統之三明治結構，二氧化矽21 位於三明治結構之最底層，而後次序形成旋覆玻璃23及二 氧化矽25。在金屬間介電質層21/23/25之三明治結構上開 有數個窗口，在金屬間介電質層21/23/25沈積並定義圖案 之第一金屬層30,透過這些窗口與第一金屬層20接觸。除 此之外，還有一沈積於第二金屬層上之護層31(未標示）。 第2圖中顯示金屬化後熱應力釋出所形成之孔洞。Tr is the temperature at which the layer under test is heat-treated or formed, T〇 is room temperature, ie the temperature at which the stress is measured; and E is the Young's coefficient of the thin layer. During the process, the cold and heat cycles will cause thermal stress on each layer. The force of this stress is as small as 5X109 dynes / cm2. Too much stress can easily cause stress migration, dielectric fracture, and silicon substrate 83. 3.10,000 This paper scale is applicable to China National Atomic Rate (CNS) A4 specification (210X297 mm) — 3 308730 A7 B7 5. Description of the invention (2.) Crystal defects. The inter-metal dielectric on the micron multi-layer super large integrated circuit (submic ^ n multi revel VLSI circuit) is very important-layer. The inter-metal dielectric layer widely uses a sandwich structure composed of silicon dioxide and spin-on-glass. FIG. 1 continues to show a part of a conventional integrated circuit in which a field oxide region 12 is formed on the semiconductor substrate 10, and other device structures such as the gate electrode 14 and the source / drain region 15 are also formed on the substrate 10 . The metal contact window penetrates through the insulating layer 16 and leads to the semiconductor substrate. A first metal layer 20 is deposited and patterned to achieve contact. The figure shows that there is a conventional sandwich structure on the first metal layer 20. The silicon dioxide 21 is located at the bottom of the sandwich structure, and then the spin-on glass 23 and the silicon dioxide 25 are formed in this order. Several windows are opened on the sandwich structure of the inter-metal dielectric layer 21/23/25. The first metal layer 30 is deposited and defined in the inter-metal dielectric layer 21/23/25, and through these windows and the first The metal layer 20 is in contact. In addition, there is a protective layer 31 (not shown) deposited on the second metal layer. Figure 2 shows the holes formed by thermal stress relief after metallization.

Sliwa，Jr.等人於 US Patent 5,119,164 曾揭露一種 在旋覆破璃内形成孔洞，孔洞造成旋覆玻璃碎裂以減低應 力之方法。本發明提供一種在旋覆玻璃上形成孔洞之新方 法0 本發明之主要目的在於提供一種有效且適於生產之方 法’用以降低積體電路金屬化後之熱應力。 本發明之另一目的在於提供一種在積體電路製程中形 成多孔狀之介電質層以減少熱應力之方法。 本紙張碰顧 + Be( CNS ) A4«iS- ( 210X297^* ) ——4 — (請先間績背面之注意事項再填寫本頁) 裝·Sliwa, Jr. et al. In US Patent 5,119,164 disclosed a method of forming holes in the clad glass, which caused the clad glass to crack to reduce stress. The present invention provides a new method for forming holes in a spin-on glass. The main object of the present invention is to provide an effective and suitable method for production to reduce the thermal stress after metallization of integrated circuits. Another object of the present invention is to provide a method for forming a porous dielectric layer in an integrated circuit manufacturing process to reduce thermal stress. This paper touches + Be (CNS) A4 «iS- (210X297 ^ *) ——4 — (Please pay attention to the matters on the back of the performance and fill out this page)

r______Τ' l SI I IM 經濟部中央揉準局貝工消費合作社印装 83. 3. !〇,〇〇〇 308730 A7 B7 五 、發明説明（ 經濟部中央橾準局貝工消费合作社印裝 本發明之上述目的係藉由提供一種在金屬間介電質層 内產生孔洞之方法而達成，其步驟爲：提供一具有元件結 構之半導體基板，該元件結構具有一己定義圖案之第一金 屬層；沈積一第一二氧化矽層於第一金屬層上；沈積—氮 化矽層於二氧化矽層上；沈積一含矽金屬層於氮化矽層上 ，蝕去含矽金屬層，使金屬層所含之矽留在氮化矽層表面 上形成矽結塊；蝕去氮化矽層未被矽結塊覆蓋之部分，留 下矽結塊下方之柱狀氮化矽；以旋覆玻璃塗佈於該二氧化 矽層上。烘乾，硬化，形成一旋覆玻璃層；去除矽結塊及 柱狀氮化矽，於旋覆玻璃層上形成孔洞；以及沈積一第二 二氧化矽層於旋覆玻璃層上，以完成多孔狀之金屬間介電 質層。 爲使本發明之目的、特徵、和優點能更明顯易懂，下 文特舉一較佳實施例，並配合所附圖示，作詳細説明如下 簡單之囷式説明： 第1及2圖爲説明習知製程之積體電路橫截面圖。 第3及6圖爲説明本發明製程之積體電路橫截面圖。 實施例 第3圖所示爲一具有已完成一部份之積體電路之半導 基板10，一般而言，此半導體基板以採用單晶矽基板爲較 佳。在此半導體基板10上具有場氧化區12,並以習知之方 法形成閘極14及源/汲極區等元件。在矽基板之表面形成 一護層或一絕緣層16,其可爲薄氧化層與厚硼矽玻璃或厚 ^紙張尺度逍用中國國家梂準（CNS ) A4規格（21〇χ297公釐） ~ 5 — 83.3.1〇.°00 (請先聞讀背面之、注意事項再填窩本頁) .人-裝. 訂 308730 A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明説明（4.) 骑矽玻璃或厚硼嶙矽玻璃所構成之複數層。上述護層或絕 緣層16内之玻璃層係以習知之方法形成於晶圓表面作爲平 坦化之'用。 (以傳統之顯像及蚀刻技術完成第3圖中由穿過絕緣 層16通至基板10或其他各處之接觸窗。沈積一金屬層2〇 定義圖案並完成接觸）。 以下係關於本發明多孔介電質潛之製程。三明治結構 之金屬間介電質層之第一層22係爲一以電漿強化化學氣相 沈積法（plasma enhanced chemical vapor deposition 以下簡稱PECVD)沈積之二氧化矽層22。此二氧化矽層22之 沈積厚度介於1000至7000埃之間。 接著，在二氧化矽層22上形成一層氮化矽層24。氮化 矽層是PECVD法沈積成厚度介2000至8000埃之薄層。再以 一金屬，例如含有l-4wt%矽之鋁矽合金（以下簡稱A卜Si( 1-4% ))沈積於氮化矽層24上，在金屬線内加入少量矽可 防止銘經由金屬接觸孔穿突入（Spike into)碎基底。室溫 下，矽在鋁中之溶解度小於01%，因此，當合金由進行沈 積之高溫冷卻至室溫時，矽即由合金中沈澱析出。析出之 梦隨機分佈於鋁之晶界及鋁與基底層之介面上。矽沈澱物 大小視沈積時鋁矽合金内矽之原含量及沈積條件而定，以 在300至400°C沈積之A卜Si(2% )爲例，其矽沈澱物之大小 約爲0.2至0.5" m。熟習此技藝之人士皆知，蝕刻金屬時 碎很難被触去，故經常可以在金屬蝕刻後發現矽晶結塊（ silicon nodules )的存在。室溫下，鋁在矽中之溶解度 n^—. nn ·ϋ n -^i t^n n (請先閲讀背面4.注意事項再填寫本頁) 訂 本紙張Λ/t適用中目目家轉（CNS)八4胁（训x2974S#) -6 - 83. 3.10,000r ______ Τ 'l SI I IM The Ministry of Economic Affairs Central Bureau of Accuracy Bureau Beigong Consumer Cooperative Printed 83. 3. 〇〇, 〇〇〇308730730 A7 B7 V. Description of the invention (The Ministry of Economic Affairs Central Bureau of Precision Industry Beigong Consumer Cooperative printed this invention The above object is achieved by providing a method for creating holes in an intermetal dielectric layer. The steps are: providing a semiconductor substrate with a device structure having a first metal layer with a defined pattern; deposition A first silicon dioxide layer on the first metal layer; depositing a silicon nitride layer on the silicon dioxide layer; depositing a silicon-containing metal layer on the silicon nitride layer, etching away the silicon-containing metal layer to make the metal layer The contained silicon is left on the surface of the silicon nitride layer to form a silicon agglomerate; the part of the silicon nitride layer not covered by the silicon agglomerate is etched away, leaving the columnar silicon nitride under the silicon agglomerate; coated with spin-on glass Lay on the silicon dioxide layer. Dry and harden to form a spin-on glass layer; remove silicon agglomerates and columnar silicon nitride to form holes in the spin-on glass layer; and deposit a second silicon dioxide layer On the spin-on glass layer to complete the porous gold In order to make the purpose, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the accompanying drawings, which are described in detail as follows: Figures 1 and 2 are cross-sectional views of integrated circuits illustrating conventional processes. Figures 3 and 6 are cross-sectional views of integrated circuits illustrating processes of the present invention. Figure 3 of the embodiment shows a completed part For the semiconductor substrate 10 of the integrated circuit, in general, the semiconductor substrate is preferably a single crystal silicon substrate. The semiconductor substrate 10 has a field oxide region 12, and the gate electrode 14 and the gate electrode 14 are formed by a conventional method. Source / drain regions and other components. A protective layer or an insulating layer 16 is formed on the surface of the silicon substrate, which can be a thin oxide layer and a thick borosilicate glass or thick ^ paper size to use the Chinese National Standards (CNS) A4 specifications (21〇χ297mm) ~ 5 — 83.3.1〇. ° 00 (please read the back of the page, precautions before filling the nest page). People-installation. Order 308730 A7 B7 shellfish consumption of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the cooperative V. Description of the invention (4.) The complex composed of riding silicate glass or thick borosilicate glass Several layers. The glass layer in the protective layer or insulating layer 16 is formed on the surface of the wafer by a conventional method for planarization. (The traditional imaging and etching techniques are used to complete the Figure 3 by passing through the insulating layer 16 leads to the contact window of the substrate 10 or other places. Deposit a metal layer 20 to define the pattern and complete the contact). The following is the process of the porous dielectric latent process of the present invention. The sandwiched structure of the intermetal dielectric layer One layer 22 is a silicon dioxide layer 22 deposited by plasma enhanced chemical vapor deposition (PECVD). The thickness of the silicon dioxide layer 22 is between 1000 and 7000 angstroms . Next, a silicon nitride layer 24 is formed on the silicon dioxide layer 22. The silicon nitride layer is deposited as a thin layer between 2000 and 8000 Angstroms by PECVD. Then deposit a metal, such as aluminum silicon alloy containing 1-4wt% silicon (hereinafter referred to as A Bu Si (1-4%)) on the silicon nitride layer 24, adding a small amount of silicon in the metal wire can prevent the metal from passing through the metal The contact hole penetrates (Spike into) the broken substrate. At room temperature, the solubility of silicon in aluminum is less than 01%. Therefore, when the alloy is cooled to room temperature from the high temperature of the deposition, silicon is precipitated from the alloy. The separated dreams are randomly distributed on the grain boundaries of aluminum and the interface between aluminum and the base layer. The size of the silicon precipitate depends on the original content of silicon in the aluminum-silicon alloy and the deposition conditions. Taking A Si (2%) deposited at 300 to 400 ° C as an example, the size of the silicon precipitate is about 0.2 to 0.5 " m. Those who are familiar with this technique know that the chips are difficult to touch when etching metal, so it is often possible to find the presence of silicon nodules after metal etching. At room temperature, the solubility of aluminum in silicon n ^ —. Nn · ϋ n-^ it ^ nn (please read the back 4. Please note before filling out this page) The order paper Λ / t is applicable to Zhongmumujiazhuan ( CNS) Eight 4 threats (training x2974S #) -6-83. 3.10,000

五 '發明説明（5.) 經濟部中央梯準局貝工消费合作社印製 甚小，故碎晶結塊之成份幾近純珍，故於習知金屬化製程 必須附加一清除梦晶結塊之步裸。 然而，上述之矽晶結塊對本發明之製程相當重要，在 成金屬層後，接著以活性離子蝕去鋁，在氮化矽層24上留 下晶矽結塊26。 請參閱第4圖，對氮化矽層進行活性離子蝕刻或電浆 蝕刻，例如使用射頻功率約爲;[50瓦，壓力約爲邠^以^ 之氦氣及SFe氣體蝕去未被矽結塊覆蓋部分之氮化矽層24 ，留下柱狀之氮化矽24。 藉旋轉晶圓將旋覆玻璃均勻塗佈於半導體晶圓表面， 使旋覆玻璃填入積體電路之低窪處，達到平坦化之效果。 旋覆玻璃可以採用碎酸鹽或碎氧貌，其厚度約爲1〇〇〇至 5000埃之間。 進行低溫烘乾及硬化步驟，驅離大部分的溶劑，其中 ，進行烘乾及硬化之溫度分別爲12〇°C及40(TC左右。 沈積形成旋覆玻璃後蚀去碎晶結塊蓋住之柱狀氮化發 ，此步驟可在15CTC左右以磷酸進行蚀刻。除去柱狀氣化 矽後在旋覆玻層上留下許多垂直的孔洞29,如第5圖所示 。三明治結構之金屬間介電質層中最後一層爲二氧化矽層 30,其係是以PECVD或PVD法沈積成厚度介於2000至7000埃 之二氧化矽。孔洞29之大小係由矽結塊之大小所決定，一 般之大小約爲0.2至0.5jum之間，而二氧化矽30係爲步階 覆蓋率小於100%之未摻雜矽玻璃。孔洞愈小則步階覆蓋 率愈小。以PECVD或PVD法沈積之未摻雜矽玻璃之步階覆 本紙張尺度逍用中國國家標準（CNS ) A4规格（210X297公釐） —7 ~ (請先閲讀背面之注意事項再填寫本頁) •裝. 83. A7 ___________B7_ _ 五、發明説明（6.) 蓋率可以藉著控制壓力及功率等參數而調整，藉以在孔洞 20内形成大小介於0,05至0.3# m之空洞（別丨扣），完成多孔 狀之金屬間介電質層。 ’ 以傳統之顯衫及蚀刻技術在金屬間介質層22/28/30上 形成通至第一金屬之接觸窗，如第6圖所示，接著沈積第 二金屬並定義圖案，完成第二金屬層之金屬化。 本發明雖以若干較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脱離本發 神和範固内，當可作些許之更動與潤飾，因此本猾 護範固當視後附之申請專利範圍所界定者爲準。月之保 I---- - ---f — . ^ II 訂 I η 一 (請先閼讀背ϊ/a,意事項再填·ή'Γ本頁} 經濟部中央標準局貝工消费合作社印製Fifth, the description of the invention (5.) Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs is very small, so the composition of the broken crystal agglomerates is almost pure, so in the conventional metallization process, a clearing of the dream crystal agglomeration must be added. Step naked. However, the above-mentioned silicon crystal agglomeration is very important to the process of the present invention. After the metal layer is formed, aluminum is etched away with active ions, and the crystalline silicon agglomeration 26 is left on the silicon nitride layer 24. Please refer to Figure 4 for the active ion etching or plasma etching of the silicon nitride layer, for example, using a radio frequency power of about; [50 watts, a pressure of about ^ ^ to ^ helium and SFe gas etched without silicon junction The block covers part of the silicon nitride layer 24, leaving columnar silicon nitride 24. By rotating the wafer, the spin glass is evenly coated on the surface of the semiconductor wafer, so that the spin glass is filled into the low-pits of the integrated circuit to achieve a flattening effect. The spin-on glass can adopt broken acid salt or broken oxygen appearance, and its thickness is about 1000 to 5000 angstroms. Carry out the low-temperature drying and hardening steps to drive off most of the solvent. Among them, the drying and hardening temperatures are about 12 ° C and 40 ° C. After the formation of spin-on glass, the broken crystals are etched away to cover This column can be etched with phosphoric acid at around 15CTC. After removing the columnar vaporized silicon, many vertical holes 29 are left on the spin-on glass layer, as shown in Figure 5. The metal of the sandwich structure The last layer of the inter-dielectric layer is the silicon dioxide layer 30, which is deposited by PECVD or PVD to form silicon dioxide with a thickness between 2000 and 7000 Angstroms. The size of the holes 29 is determined by the size of the silicon agglomerates , The general size is about 0.2 to 0.5jum, and silicon dioxide 30 is undoped silicon glass with step coverage less than 100%. The smaller the hole, the smaller the step coverage. PECVD or PVD method Step-by-step coverage of the undoped silicon glass deposited on paper. The Chinese national standard (CNS) A4 specification (210X297mm) is used-7 ~ (please read the precautions on the back and fill in this page) • Pack. 83. A7 ___________B7_ _ V. Description of invention (6.) Coverage rate can be controlled by pressure and Adjust the power and other parameters to form a hole (without buckle) with a size of 0,05 to 0.3 # m in the hole 20 to complete the porous inter-metal dielectric layer. A contact window leading to the first metal is formed on the intermetal dielectric layer 22/28/30, as shown in FIG. 6, then a second metal is deposited and a pattern is defined to complete the metallization of the second metal layer. Several preferred embodiments are disclosed above, but it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and retouching without departing from the original spirit and Fan Gu, so this skill protects Fan Gu Subject to the definition of the scope of the attached patent application. Monthly guarantee I -------- f —. ^ II Order I η one (please read back ϊ / a first, then fill in the matters concerned) ή'Γthis page} Printed by Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs

Claims (1)

A8 B8 C8 308730 第83105015號申請專利範圍修正本D8修正日 、申請專利範圍 1. 一種積體電路之多孔狀金屬層間介電質層的製造方 法，包括下列步驟： 提供一具有元件結構的半導體基底，其上至少覆蓋有 一已定義圖案的第一金屬鼷； 沈積一二氣化矽層覆蓋在該第一金羼層上； 沈積一氮化矽層覆蓋在該二氣化矽層上； 沈積一含矽金靨層覆蓋在該氮化矽層上； 蝕刻該含矽金屬層，使其所含之矽留存在該氮化矽層 表面上，形成矽晶結塊； 蝕刻去除該氮化矽層未被該些矽晶結塊蓋住的部分， 留下在該些矽晶結塊下方之柱狀氮化矽； 以旋覆玻璃塗佈於該二氣化矽層上，並經烘烤、硬化 形成一旋覆玻璃層，其環嬈該些柱狀氮化矽； 去除該矽晶結塊及該些柱狀氮化矽，以留下在該覆玻 璃層内的孔洞；以及 沈積一第二二氣化矽層覆在該旋覆玻璃層上，完成該 積體電路内該多孔狀介電質層。 2. 如申請專利範圍第1項所述的方法，其中該第一二 氣化矽層傜以化學氣相沈積法沈積形成，其厚度是介於1000 埃至7000埃。 3. 如申請專利範圍第1項所述的方法，其中該氮化矽層 係以化學氣相沈積法沈積形成，其厚度是介於2000埃至800 0 埃。 4. 如申諳專利範圍第1項所述的方法，其中該含矽金羼 本紙張尺度適用中國國家揉率（CNS ) A4規格（210X297公釐} (請先閲讀背面之注意事項再填寫本頁) l!i 經 濟 部 t2^ 央 揉 準 局 貝 工 消 費 合 作 社 印 裝 308730 A8 B8 C8 D8 、申請專利範圍 層的沈積厚度是介於2000埃至10000埃。 5. 如申請專利範圍第1項所述的方法，其中該含矽金屬 層傜以活性離子蝕刻而形成矽晶結塊。 5 (請先閱讀背面之注意事項再填寫本頁) 6. 如申請專利範圍第1項所述的方法，其中該含矽金靨 靥傜以電子自旋共振法蝕刻而形成矽晶結塊。 7. 如申請專利範圔第1項所述的方法，其中該氮化矽層 僳以活性離子蝕刻而留下在該些矽晶结塊下方的柱狀氮化矽 Ο 8. 如申諳專利範圍第1項所述的方法，其中該氮化矽層 係以霄漿蝕刻而留下在該些矽晶結塊下方的柱狀氮化矽。 9. 如申諳專利範圍第1項所述的方法，其中該旋覆玻璃 層沈積的厚度是介於1000埃至5000埃。 10. 如申諳專利範圍第1項所述的方法，其中該些柱狀 氮化矽是以1501C左右的熱磷酸溶液蝕刻去除的。 11. 如申請專利範圍第1項所述的方法，其中該第二二 氣化矽層沈積的厚度是介於2000埃至7000埃。 12. 如申請專利範圍第1項所述的方法，其中該些介電 質層内的孔洞使該基底承受的熱應力降低二到三個级數。 經濟部中央標準局貝工消费合作社印製 13. —種消除熱應力的積體電路结構，其包括： 一具有元件結構的半導體基底，其上至少覆蓋有一已定 義圖案的笫一金雇層； 一具有接觸開口的多孔狀之金靨間介電質層，其包括 一第一二氣化矽層，覆蓋在該第一金屬層上； 一旋覆玻瑰層，覆蓋在該第一二氣化矽層上，其中該 -2 - 本紙張尺度逋用中國國家橾率（CNS > Μ規格（210X297公釐） 六、申請專利範圍 A8 B8 C8 D8 屬.， 電體 其的 金觴 體積 ，受 之接 積該 構承 狀靥 該除 结所 .，孔JB成消 路底 上多金 構來 電基 璃該一 ，用 體該 玻在第 上洞 積使 覆蓋該 層孔 的， 旋覆與 靨的 述洞 該 ，口 金層 所孔 在層開 二質 項的 蓋鼷觸 第電13層 及覆金接 該介 第質。 以，二該 在間 圍電數 ; 層第由 蓋颺 範介级 洞矽的經 覆金 利間値 孔化案並 ，於 專靨三 有氣圖， 層位。請金到 具二義上 護些力申該二 層二定層 面該應如於低 璃第已質 表中熱 .位降 玻一 一電 一其的14些力 覆 介及 ，，路 該應 旋 間以 路電 中熱 (請先閲讀背面之注意事項再填寫本頁) 經濟部t2央揉率局貝工消费合作社印製 本紙張尺度適用中國國家揉準（CNS ) A4規格（210 X 297公釐）A8 B8 C8 308730 No. 83105015 Patent scope amendment version D8 Amendment date, patent scope 1. A method for manufacturing a porous metal interlayer dielectric layer of an integrated circuit, including the following steps: providing a semiconductor substrate with a device structure , On which at least a first metal foil with a defined pattern is covered; a second vaporized silicon layer is deposited over the first gold layer; a silicon nitride layer is deposited over the second vaporized silicon layer; a The silicon-containing gold layer covers the silicon nitride layer; the silicon-containing metal layer is etched so that the silicon it contains remains on the surface of the silicon nitride layer to form silicon crystal agglomerates; the silicon nitride layer is etched away The part not covered by the silicon crystal agglomerates is left columnar silicon nitride under the silicon crystal agglomerates; coated on the two vaporized silicon layers with spin-on glass and baked, Hardening to form a spin-on-glass layer, which encircles the columnar silicon nitrides; removes the silicon crystal agglomerates and the columnar silicon nitrides to leave holes in the glass-clad layer; and Shen Jiyi The two-two gasified silicon layer covers the spin-on glass layer, Within the integrated circuit into the porous dielectric layer. 2. The method as described in item 1 of the scope of the patent application, wherein the first and second vaporized silicon layers are deposited by chemical vapor deposition with a thickness ranging from 1000 angstroms to 7000 angstroms. 3. The method as described in item 1 of the patent application range, wherein the silicon nitride layer is formed by chemical vapor deposition, and its thickness is between 2000 angstroms and 80000 angstroms. 4. The method as described in item 1 of the patent scope of application, in which the paper standard containing silicon gold is applicable to the Chinese national rubbing rate (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling in this Page) l! I Ministry of Economic Affairs t2 ^ Central Bureau of Accreditation Bureau Beigong Consumer Cooperative Printing 308730 A8 B8 C8 D8, the thickness of the layer of the patent application range is between 2000 Angstroms and 10000 Angstroms. 5. If the patent application item 1 The method described, in which the silicon-containing metal layer is etched with active ions to form silicon crystal agglomerates. 5 (please read the precautions on the back before filling this page) 6. The method as described in item 1 of the patent application scope ， Wherein the silicon-containing gold and tungsten are etched by electron spin resonance to form silicon crystal agglomerates. 7. The method as described in item 1 of the patent application, in which the silicon nitride layer is etched by reactive ion Columnar silicon nitride left under the silicon crystal agglomerates. 8. The method as described in item 1 of the patent application, in which the silicon nitride layer is etched with a slurry to leave the silicon Columnar silicon nitride beneath the crystal agglomerates. 9. As patented The method of item 1 of the scope, wherein the thickness of the spin-on glass layer is between 1000 angstroms and 5000 angstroms. 10. The method of claim 1 of the patent scope, wherein the columnar silicon nitrides It is etched and removed by hot phosphoric acid solution around 1501C. 11. The method as described in item 1 of the patent application, wherein the thickness of the second vaporized silicon layer is between 2000 angstroms and 7000 angstroms. The method described in item 1 of the patent application scope, wherein the holes in the dielectric layers reduce the thermal stress on the substrate by two to three levels. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 13. An integrated circuit structure that eliminates thermal stress includes: a semiconductor substrate with a device structure covered with at least a first patterned layer of a defined pattern; a porous intermetallic dielectric with contact openings Layer, which includes a first and second vaporized silicon layer, covering the first metal layer; a spin-on glass rose layer, covering the first and second vaporized silicon layer, wherein the -2-the paper size Use the Chinese national rate (CNS > M specifications ( 210X297mm) 6. The scope of patent application is A8 B8 C8 D8 genus. The size of the gold body of the electric body is subject to the accumulation of the structure and the removal of the structure. The hole JB forms a multi-gold structure call base on the bottom of the road. If the glass is covered with holes in the first hole to cover the hole in the layer, the hole in the hole is twisted with the hole, the hole in the gold layer is covered with a layer of the qualitative element, and the cover touches the thirteenth layer and the gold is covered. Then the second layer should be connected. The second layer should be surrounded by electricity; the layered layer should be merged with the gold-covered hole in the gold layer of the gold layer, and it will have gas charts in the special layer. Please go to Gu Yiyi to protect some of the two layers and two fixed layers. It should be as hot as in the low-quality glass. It should be covered by the glass and the power of the four layers should be introduced. Rotating between roads and heating (please read the precautions on the back before filling in this page) The paper printed by the Ministry of Economic Affairs t2 central rubbing bureau Beigong Consumer Cooperative. The paper scale is applicable to the Chinese national standard (CNS) A4 specification (210 X 297 Mm)