A6 B6 五、發明説明（1 ) (請先閲讀背'&之注意事項再填寫本頁) 相Μ申謫之前後對照 本申請是在 37 C.F.R. Sections 1.53 及 1.78(a)之下 提出做為專利申請糸列號碼07/995,849之延績而該專利申 請是在1992年12月23日提出且其後被捨棄。 發明背景 1. 發明領域 本發明概言之係RS於零交越臨限偵測器且，更明確的說 ，係闢於用Μ提供代表同步取樣窗内偵測位置'之數位输出 信號之數位零交越偵測器。 2. 相關技術說明 在資料儲存技術中，二進位資料被編碼及以一糸列光學 或磁性轉變之型式儲存在光學或磁性介質。儲存資料之擷 取需要在記錄頻道有偵測和解碼糸統Κ便自邮接儲存介質 之磁性$光學換能器產生之自同步類比信號波形中重規原 始二進位資料和同步時鐘。從事本技術領域者已對相闞於 由自同步資料信號擷取同步時鐘和資料之問題提出許多解 決方法。這呰問題包含分辨真正轉變和只是雜訊脈衝及同 步資料時鐘信號之精確重現Μ便允許相位編碼資料之準確 解碼。此種記錄頻道之一重要姐件是波形轉變或”零交越 ” （zero-crossing)偵測器，而其為準確決定各自同步波 形轉變之精確相對時序或相位所必需。 本技術領域所知之類比脈衝偵測器具有類比電子裝置之 一般缺點。他們很貴，笨重且易随著時間受校準漂移之影 饗。尤有甚者，類化脈衝偵測器通常只適用於一段狹窄且 -3- 本紙張义度通用中國國家標準（CNS)甲-1规格（210 X 297公兑）A6 B6 V. Description of the invention (1) (Please read the notes before filling in this page and fill in this page) Before and after the application, please refer to this application under 37 CFR Sections 1.53 and 1.78 (a) The patent application is a serial number extension of 07 / 995,849 and the patent application was filed on December 23, 1992 and was subsequently abandoned. BACKGROUND OF THE INVENTION 1. Field of the Invention The general description of the present invention pertains to RS in a zero-crossing threshold detector and, more specifically, to the use of M to provide a digital output signal representing the detected position within the synchronous sampling window. Zero crossing detector. 2. Relevant technical description In data storage technology, binary data is encoded and stored in an optical or magnetic medium in the form of a row of optical or magnetic transformations. The retrieval of stored data requires re-regulation of the original binary data and synchronous clock in the self-synchronized analog signal waveform generated by the magnetic $ optical transducer of the storage medium that has detected and decoded the recording channel in the recording channel. Those skilled in the art have proposed many solutions to the problem of extracting synchronized clocks and data from self-synchronized data signals. This problem includes distinguishing between true transitions and accurate reproduction of only noise pulses and synchronized data clock signals. This allows accurate decoding of phase-encoded data. One important component of such recording channels is the waveform transition or "zero-crossing" detector, which is necessary to accurately determine the precise relative timing or phase of the respective synchronized waveform transition. Analog pulse detectors known in the art have the general disadvantages of analog electronic devices. They are expensive, bulky, and subject to calibration drift over time. What's more, the generalized pulse detector is usually only suitable for a narrow and -3--copy paper universal Chinese national standard (CNS) A-1 specification (210 X 297 public exchange)
js;rfrf[·.中夾栉準/CJG工消¢合作社印K A6 B6 五、發明説明（2 ) 事先決定之頻道資料率，而對儲存介質資料擷取糸統之頻 道資料率造成嚴格限制。本技術領域所知之資料鼷衝或轉 變相位偵测器之數位建構通常依賴為人热知之類比偵測技 術之離散信號實例。例如，首先將類化信號波形利用為人 熟知之鎖相迴路（Phase-Locked Loop)技術加Μ取樣及數 位化。然後Μ數位方式處理這些取樣Κ便除去不要之頻率 分量並重現同步時鐘和資料。吾人清楚感覺本技術領域需 要頻道波形轉變相位偵测器之全面數位化建構'且其能在一 廣大範圍之資料率內準確偵測記錄頻道資料信號波形内之 自同步資料脈衝。最需要的是在中等非同步取樣率下能準 確偵測同步資料，因為高速取樣技術非常昂貴。 本技術領域已有横擬類比記錄頻道功能之數位電腦程式 但瑄些技術需要高取樣率Μ致即時硬體之建構昂貴且困難 。數位律構所涉及之部份困難可藉由降低非同步類比信號 取樣率來加Μ克眼。不幸的是，降低之非同步取樣率會導 致零交越偵潮時間之不定度增加。此會造成記錄頻道之抖 動（jitter)畸變及增加之誤碼率（BU Error Rate， Ο 從事本技術領域者已努力藉由改進取樣間之内插 (i n t e r ρ 〇丨a t i ο η ) Μ便在較低之取樣率降低抖動。例如， 在美國專利第4,412,339號中，1>61^「11.^1{"1^等人提出 意欲降低數位移頻鍵控數據機（FSK modem)之同步畸變之 零交越内插器。Alfke等人指出藉由增加一高速内部時鐘 以在各輪入取樣對間沿一線性斜率逐步增加偵測器直到偵 -4- 本紙張凡度適用中园國家標準（CNS)4规格（210 X 297公货> (請先閲讀背今之注意事項再塡寫本頁) .裝. 訂. 經濟部中央標準局8工消赀合作社印" Α6 Β6 五、發明説明（3 ) 出—正負號改變可改進零交越偵測之精確度。因此，他們 之技術需要使較高取樣率不適用之相同高速數位裝置。尤 有甚者，雖然Alfke等人教導使用數位裝置，但他們之零 交越内插器之输出是一簡單之類比時序Μ而該W會受到與 影響類比零交越偵測器實例相同之類比錯誤源之影響。 在美國專利第4, 165,491號中，Arthur P. Geffon提出 一種用Μ在有雑訊之下偵澜資料信號之零交越點之電路。 Geff on提出一種用以消除假定因雜訊而引起之'零交越之脈 衝檢定技術。他既無考慮也無建議用Μ偵測數位化取樣信 號零交越之方法。 在美國專利第4,749,879號中，Donald S. Peterson等 人提出一種用K發現二進位煸碼類化信號波形之信號波形 轉變之信號轉赛偵测方法。Pete「son等人提出使用第二微 分步驟Μ便提供可改進他們之類比霉路之雜訊免疫力之第 二導得信號。他們既無考慮也無建議用Μ偵澜數位化取樣 信號波形臨限轉變之装置。在美國專利第3,593,166; 3,916,328; 3,955,102； 4,132,909； 4,151,427； 4,268,764; 4,480,200; 4,795,915 和 5,001,364 號中有 提出其他類似之改良型類比偵測器。吾人仍清楚感覚本技 術領域箱要一數位零交越偵測器且其融入数位内插技術以 便在相當低之非同步取樣率之下提供準確轉變時序輸出。 此需求在必須完全建構在低功率單晶片數位積體電路而不 使用類比元件之現代數位記錄頻道尤其重要。吾人清楚感 覺本技術領域之相關未解決問題和缺陷而本發明以下述之 本紙張尺度適用中國國家標準（CNS)甲4规烙（210 X 297公铨〉 ! ^------扣衣--------，^-----I ^ ---I. ---------— (請先閱讀背而之注意事項再塡寫本頁) ， 3uC〇48 A6 B6 ......... _____________ ______________ .. ___________· «_ 五、發明説明（^ ) 方式將其解決。 發明摘要 本發明是設計用於非同步數位頻道之零交越臨限偵测器 。它接收將自同步資料編碼於其中之數位化信號波形並输 出#交越在取樣遇期内之相對位置·如果有任何零交越的 話。此數位轤出是企阃用Μ回復内含之資料和時鐘信號且 是在一種可直接為共同未決之專利申請所提出之離散時序 〆 控制迴路（Discrete Time Control Loop, DTCL)所使用之 梨式。該共同未決之專利申請之作者是Hutchins等人 (Assignee Docket No· SA9-91-099)而其名稱是 "Discrete Time Control Loop Method And Apparatus For Clocking Data In An Asynchronous Channel"且在 1992年10月28日提出申請而專利申請號碼是07/967,588 ’ 在此全郭提出做為參考。 本發明之非同步數位臨限偵測器（ADTD)利用下列三步驟 來估計單一取樣間隔内之零交越抵達時間。首先*偵測器 賴由檢杳相鄰取樣對有無正負號改變K決定是否有零交越 發生。第二步，將取樣率由較高之取樣率轉換成較低之取 樣率，目較低之取樣率正好是較高之取樣率之一半。在如 此做時，ADT0首先決定新且較長取樣週期之那一半包含該 零交越。最後，ADTD賴由解決一線性内插公式W決定次格 時間估計；亦即·較短取樣遇期内之零交越比例位置& ( 阃1 (b))。偵測器输出是代表零交越在較長取樣週期之 估計绳過時間部份之η-位元數位信號（圖1 U)之t/Td) ° -6 — 本紙張尺度通H1中國國家標準（CNS)甲·4蜆烙（2丨〇 X 297公贷） (請先閲讀背而之注意事項再塡寫本頁) -裝· 訂. 經濟部中央標準局U工消费合作社印製 A6 ____B6_五、發明説明（5 ) 本發明之目的之一是改菩在較低非同步取樣率下之零交 越準確度。本發明之另一 ^的是在不依賴類比元件下於數 位取樣潦中偵测臨限交叉。 本發明之一特色和儍點是零交越偵測是Μ η -位元數位# 钼之塑式加Μ表示，而該字姐之準確度與類比信號時序考 慮無關。 前述車項，速同本發明之其它目的，特色和儍點將在參 照下列規格，申請專利範圍和附圖時變得更明/顯。 圖形簡述 為了更完整得瞭解本發明，現在參照下列顯示於附圖之 較佳實例之詳细說明I其中： 圃1展示一取樣間隔内之信號波形零交越； 圖2提供展示本發明之ADTD與記錄頻道之其它組件間之 藺係之方塊鼷； 阃3提供本發明之ADTD脈衝偵測器姐件較佳實例之方塊 阃； 圖4提供本發明之ADTD 2Χ-至-IX轉換器姐件較佳實例 之方塊國； _ 5提供本發明之AOTD時序產生器姐件較佳實例之方塊 _ ;及 _ 6提供本發明之A I) Τ [)效能之範例。 較佳實例說明 圖Μ展示阃1(b)之取樣間隔Ts = Td/2與圖1(a)之自同步 資料間隔Td間之闞係。本發明之ADTD決定次格時間估計ΐ -7- 本纸張尺度適用中國囤家標準（CNS) f 4规格（210 X 297公贷） (請先閱讀背3之注意事項再場寫本頁) ;裝- .可. Λ A6 B6 五、發明説明（6 ) (請先閲讀背卞：/注意事項再填寫本頁) (圃（1(b))並將其轉換成比率t/Td之一數位表示法（圃1 (a ))。 鬭2顯示本發明之ADTD 10與光學或磁性資料儲存介質 12間之闞係。展示一尖峰偵測頻道建構做為示範。介質 12之磁性或光學轉變是由換能器14JW本技術領域所知之任 何有用方式加K感測。換能器输出信號16送至一般都是多 個之類比功能ΐδ。這些功能包含前置放大 〆 (preamplification.)，自動谓益控制（Automatic Gain Control, AGC)，和反混淆（低通，anti-alias, lowpass)濾波。導致之類比資料信號波形20送至波形前置 處理器22以本技術領域所知之任何有用方式實行信號微分 ，脈衝檢定（pulse qalification)及類比至數位/A/D)轉 換。A/D轉換盛24之A/D取樣率是由取樣時鐘產生器26所 控制，而該產生器以信號波形20自同步資料率之二倍產生 取樣時鐮信號Fe = 2Fd。數位取樣信號{S} Μ取樣匯流排 28送至ADTD 10 。脈衝檢定器30產生一脈衡檢定旗標而該 旗檷是以線32送至ADTD 10 。脈衝檢定旗檷Κ本技術領域 所知之任何有用方式分辨信號脈衝和雜訊脈衝且在每個包 含檢定脈衝或轉變之取樣間隔被設定。 圖2之ADTD實例10包括一脈衝偵測器34，一 2χ-至-1χ 轉換器3 6及一時序產生器38。轉換器36以二種時鋪率運作 :得自產生器26之取樣率F1»和資料時鎳率P 6^-/2 。 ADTD 1 0提供二数位输出。在資料睹流排40上提供代g資 料時鏡間隔（t/Td)內臨限轉麥之相對位置之數位信號並Μ -8- 本·纸張尺度通用中國國家標準（CNS)甲4规格（210 X 297 H ) 經濟部中夾標準马Π工消贷>作钍印製 Λ6 B6 五、發明説明（7 ) 線42傳送賑斷偵測旗禰（PDF)。嫌42在包含檢定臨限轉變 偵测之全部資料時鐘間隔Td内都是高位準。 鬪2展示饋入離散時序控制迴路（DTCL)44M便皤後根據 上述Hutch ins等人專利申請實行謅回頻道處理之匯流排 40和線42。也可使用任何其他逋合之方法以自A DTD 10在 择潦排40和嫌42之数位_出擷取資料和同步時鐘信號，例 如在數位至類比轉換後緊接著鎖相迴路信號處理。 在波形前置處理器22中，信號徴分器46W本/技術領域所 知之任何有用方式微分資料信號波形20M便轉換波形尖峰 成零交越轉變。在介質12是由磁帶驅動器48之磁帶或直接 存取儲存裝置（DASD)50之磁碟面所組成之情形下·回復之 資料是以尖峰或脈衝出現在波形20中。此種脈衡之偵測褥 要信號微分器46之微分。但是，如果介質是例如光碟52之 光學介声，可將信號加Μ脈寬調變 (Pulse-Width-Modulated, PWM)M使回復之資料是編碼成 通過一可變但事先決定之臨限之波形轉變。對此種應用， 並不需要信號微分器46且應以本技術領域所知之某適合型 式之臨限追蹤信號處理加Μ取代。無論是二者何一，脈衝 倬測器3 4必須實際偵出通過零點之信賊波形轉變。在運作 時，參照國3可更加瞭解脈衝偵測器34° 在圖3中，線32之脈衝檢定旗標是儲存在暫存器54。暫 存器56為脈衝檢定旗榑儲存一延遲一次值&或閘 (OR-gate) 58在線60上提供致能檢定旗標 > 而該旗標在目 » 前之（第i個）或前一（第i-Ι個）取樣間隔Τ»有檢定之偵 -9 - 本紙張尺度適用中國國家標準（CNS)甲4規丨各（2〗0 X 297公垃〉 (請先閱讀背而之注意事項再塡寫本頁) -—裝- .可. 經^部中央標>|1-/.;4工消#合作社印製 Α6 Β6 五、發明説明（8 ) 澜下是高位準。 陳流排28之數位信號被分成捸28a之正負號位元和匯流 排28b之其餘7 -位元尾數（mantissa)。暫存器66和68儲存 目前取樣之正負號S,和前一取樣Si-i之正負號做為比較。' 互斥或閛（X0R-gate)70在線72提供偵測旗檷而該旗檷只要 在S,μ和51間有一正負號改變就是髙位準。及Μ (AND-gate)7 4结合線60之致能檢定旗標及埭72之轉變偵測 旗榑K在输出線76提供偵测旗檷DF ^ ◊ ’ 7-位元暫存器78和80之作用為姐合代表相鄰取樣對 (S,-,，S,)之數位信號對yk)。因此，目前之數位 信號yk經由陳流排82傳送（而其正負號是在線82a上傳送 )及延遲一次數位信號經由匯流排86傅送（而其正負 號是在線86a上）。匯流排82和86及旗標線76傅送相鄰數 位信號對和相關之偵测旗標至轉換器36 (圖1)。 參照_4可更加瞭解轉換器36。轉換器36充當將一數位 信號對.以單一數位信號取代之”萃取器”（deciraator)。输 入暫存器90和92是Μ相同時鐘率Fe加Μ定時。暫存器90儲 存延遲之信號值。暫存器92儲存DF\偵測旗標，而該 旗檑標示目前T«間隔内之偵出。陳流排82之目前信號74直 接傅送罕多工器94之第一输入。延遲之信號yk_·!傅送至多 T器94之第二输人及另一多工器96之第一輸人。提供 給多丁器96之第二蝓人。yk-2只是再延遲額外一 俩取樣時鐮間隔T«。最後，如阃4所示提供偵測旗標D F , 辛二多工器98和100之第一輸人且提供固定之二進位”〇” -10- 本紙張又/1通用中國國家標準（CNS)甲4規恪（210 X 297公;12 ) (請先閲讀背面之注意事項再瑣寫本頁) 丨裝. *1Τ. 經濟部中央標箏局Π工消赀合作社印製 A6 B6 五、發明説明（9) 或"厂’至他們之第二输入。因此，當偵測旗檷DFi經由取 樣時鍺F»定時而通過暫存器92時，多工器94- 100之输入傳 送至暫存器102 ，104 ，106和108 。暫存器102-108是 Μ暫存器90-92時鐘率之一半加Μ定時。因此，可瞭解轉 換器36選擇零交越出現之次格之相鄰數位信號及偵測旗檷 (假設毎一標稱取樣遇期最多只會出現一個零交越）。 轉換器36根據零交越出現之標稱取樣週期Td = 2 Τβ之那一 半設定零交越時間估計之最高有效位元（MSB)%轉換器 36也在睹流排110保有目前數位信號yk及在匯流排112保 有延遲數位信號yn Μ代表檢定相鄰取樣對，Sd。 保有此取樣對二Τβ取樣間隔並將其送至時序產生器38K便 實行另外之處理。線114之MSB也保持Td = 2 Ta時間並將其 送至時序產生器38做為如下討論之最終轉變時間比率之最 高有效贫元（MSB)。最後•線116之偵測旗檷DFt是線 76之DF,之半徑等效值。亦即，如果在二相邮取樣間隔 2Te = Td内任何地方存有檢定臨限轉變偵出，則線116被設 定。 »5展示時序產生器38之詳细實例。產生器38之目的是 藉由解決一內插方程式Μ估計零交越抵達時間而該方程式 表示轉變偵測及代表相鄱取樣對，St)之數位信號 yk)間之關係且該取樣對是保存在暫存器102和 104 (_4 )。此對是Μ睹流排U0和112輸入至產生器 3 8。分離择流排1】0之8 -位元數位信號Μ使MS Β在圖5之 線Π 0 b而其餘7 -位元尾敵刖是在陳流排1 1 〇 a。同樣地，在 -11- 本纸張又度適用中國國家標準（CNS)甲4蜆格（210 X 297公;立） (請先閱讀背'-s之注意事項再填寫本頁) --- ---- — — —— — -- -1 ί - -- - - I. - I I^1-^n !— ! n - i n · _ . 第82108302號牟利申請· 中文説明書修正页（84年1 _ β鑪炙 Α6 Β6 - ----- — _y 五、·發明説明（το) 阃5-之择流排112b提供該7最低有效位元（LSB)。來自匯 流排丨12之MSB (圖4 )是不需要的，因為已被隱含在線 1 J 6之D F i和線1 1 0 b之正負號位元之姐合内。 產生器38解決任何代表偵測和取樣對（S,-:，S,)關係之… 有用内插公式。發明者們偏好一簡單線性内插方程式·· k-l 其中yk是取樣Si之中間數位信號等效值。 t/Td- 對一有效零交越，yk之正負號和之正負號έ好相反 而使上述方程式能改寫成 C/Td=^yjy\.x\ · 此可 (請先閉-背3之注念事項再磷寫本頁) 4 fi|; 十 央 由謂除正負號位元間化稍早之内 存圈5内•首先在分母信號隨 l.yk-yk-i丨這是ϋ由多工器120 加Μ完成。當線1 I 0 b之y X具有正 -前信之絕對倌而多工器·122 . 對堉。如果yx仝正負號是負的， 二補？ί (2s-cqmplenient)。相加 數位信號以便在匯流排118提供 然後利用仟何有用裝置，例如 分母信號118 。對映126是Μ本 方式運作，例如2 5 6位元檢視表 流排1 2 8上提供1 2 -位元榆出倒 遲之信號^ - η之ΓΕ負號而定修改 位信號y ^，ft存陣流排1 3 2上提 插方程式之 流排1 1 8決 和1 2 2及相 號時，多工 選擇延遲之 則選擇這兩 器1 2 4將二 分母傜號1 y 利用倒数對 技術領域所 (lookup t a 數倍號。相 多工器1 22 供y k ^之絕 計算。 定分母 加器1 2 4如下 器1 20選擇目 信號h ^之絕 個數位信號之 所選之7-位元 映1 26 ，轉換 知之任何有用 b丨e )，並在匯 加器1 3 0視延 所選之延遲數 對值相乘器 r工·ν1'$τ合作杜印《 本紙張尺度迺用中因a家標芈（CNS)甲·》規恪（210 X 297公岔） A6 B6 經濟邾中央桴箏局8工消費合作社印紫 五、發明説明（) 134將_流排128之12-位元倒數输出信號與匯潦排132 之7 -位元分子相乘並除去所得结果之14 LSB而在匯流排 136上留下5 -位元零交越信號。然後將此信號儲存在暫存 器138内一取樣間隔以便提供使運作與產生器38其他部扮 同步所需之額外延遲。最終，在匯流排40上提供输出零交 越估計信號t/Td，而線40a之MSB指示二相郾取樣遇期 Ts之中何者包含該事件。 發明者們已利用匯流排28之8-位元输入取樣'顯示給定 之取樣是否超過線32檢定臨限之追蹤臨限位元並在匯流排 40上繪出6-位元時間估計及在線42上输出有效取樣旗標 (PDF)，模擬圖2-5所掲示之較佳實例。若MCMOS II技 術加W建構，ADTD 10需要大約1500閘。此較佳實例也已 建構於一磁帶資料儲存系統。 發明f們也已使用APL模擬此建構以決定實際之ADTD效 能能夠多近地匹配一簡單理論線性内插公式。提供所有可 能之相鄰數位對信號組合給一 APL位元電路横擬。然後將 榉擬之ADTD 10輸出與線性内插公式之理論解加K比較（ 阃5 )而其結果刖繪於圖6 。 在圖6 A中，y k是固定在0 . 5而y k - α則是在可能值之所有 範圖變化（所有範圍都正規化成1 )。模擬之结果與理論结 果非常接近。在_6B中，“^是固定在0.5而y^lj是在可 能倩之所有範圍變化。再一次 > 在可能输入之所有範圍模 擬之A0TD效能都與期望之蝓出非常接近。圖6a和6b之各二 曲線間之差異是由最化錯誤所引起的。 -13- 本纸张又度適用中國國家標準（CNS)甲4规格（210 X 297公泣） (請先閲讀背'-5之注意事項再填寫本頁) .裝. -ΤΓ— I ― — 1 五、發明説明（12 ) A6 B6 很列 會下 者於 域限 領受 術只 技將 本明 悉發 热本 通， 普此 明因 說.。 些改 埴修 於和 鑑例 ，實 地他 見其 易現 而發 顯易 容 包- 其 時 看 來 圓 附 和 格 規 之 述 上 合 结。 當改 而修 ，和 e 例 範宵 利稱 專此 請有 申所 之含 (請先閱讀背面之注意事項再ii寫本頁) 裝—. 訂. 本纸張又度適用中國國家標準（CNS)甲4规格（210 X 297公；ί )js; rfrf [·. 中 中 栉 准 / CJG Industrial Consumers ¢ Cooperative Society K A6 B6 V. Description of the invention (2) The channel data rate determined in advance, which severely limits the channel data rate of the storage media data retrieval system . The digital construction of data-bump or transition phase detectors known in the art generally relies on discrete signal examples of analog detection techniques known as thermal. For example, first use the well-known phase-locked loop (Phase-Locked Loop) technology plus M sampling and digitization for the waveform of the analog signal. Then, processing these samples K digitally removes unnecessary frequency components and reproduces the synchronous clock and data. We clearly feel that this technical field requires a comprehensive digital construction of the channel waveform transition phase detector, and it can accurately detect the self-synchronized data pulses in the recorded channel data signal waveform within a wide range of data rates. What is most needed is accurate detection of synchronized data at moderate asynchronous sampling rates because high-speed sampling techniques are very expensive. There have been digital computer programs in this technical field that horizontally analogize the function of recording channels, but these technologies require a high sampling rate and the construction of real-time hardware is expensive and difficult. Some of the difficulties involved in digital construction can be increased by reducing the sampling rate of the asynchronous analog signal. Unfortunately, the reduced asynchronous sampling rate will result in an increase in the uncertainty of the zero-crossing tide detection time. This will cause jitter distortion and increased bit error rate (BU Error Rate, Ο of the recording channel). Those skilled in the art have made efforts to improve the interpolation between samples (inter ρ 〇 丨 ati ο η). Lower sampling rate reduces jitter. For example, in US Patent No. 4,412,339, 1> 61 ^ "11. ^ 1 {" 1 ^ et al. Proposed to reduce the synchronization of FSK modem Distorted zero-crossing interpolator. Alfke et al. Pointed out that by adding a high-speed internal clock to gradually increase the detector along a linear slope between each round of sampling pairs until the detection of this paper is applicable to the Central Park countries Standard (CNS) 4 specifications (210 X 297 public goods > (please read the precautions before writing this page). Installed. Ordered. Central Bureau of Standards, Ministry of Economic Affairs 8 Industrial Consumer Affairs Cooperative Print " Α6 Β6 5 3. Description of the invention (3) Out—The sign change can improve the accuracy of zero-crossing detection. Therefore, their technology requires the same high-speed digital device that is not suitable for higher sampling rates. This is especially true, although Alfke et al. Teaching to use digital devices, but their zero-crossing interpolation The output of the detector is a simple analog timing M and the W will be affected by the same analog error source as the instance of the impact analog zero-crossing detector. In US Patent No. 4, 165,491, Arthur P. Geffon proposed a ΜThe circuit for detecting the zero-crossing point of the data signal under the presence of a signal. Geff on proposed a pulse verification technique to eliminate the assumption of 'zero-crossing caused by noise. He neither considered nor suggested it Μ The method of detecting the zero-crossing of a digitally sampled signal. In US Patent No. 4,749,879, Donald S. Peterson et al. Proposed a signal transfer detection using K to detect the transition of a signal waveform of a binary coded signal waveform Method. Pete "son et al. Proposed to use the second differential step Μ to provide a second derived signal that can improve the noise immunity of their analogous mildew. They neither considered nor suggested using M to detect digitally sampled signals Waveform threshold transition device. Other similar improvements have been proposed in US Patent Nos. 3,593,166; 3,916,328; 3,955,102; 4,132,909; 4,151,427; 4,268,764; 4,480,200; 4,795,915 and 5,001,364 Analog detectors. I still clearly understand that this technical field requires a digital zero-crossing detector and it incorporates digital interpolation techniques to provide accurate transition timing output at a relatively low asynchronous sampling rate. This requirement is necessary Modern digital recording channels built entirely on low-power single-chip digital integrated circuits without using analog components are particularly important. I clearly feel that the related unresolved problems and defects in this technical field and the present invention is applicable to the Chinese National Standard (CNS) A 4 regulation (210 X 297 Gongquan) according to the following paper standards: ^ ------ Clothing --------, ^ ----- I ^ --- I. ----------- (please read the precautions before writing this page), 3uC〇 48 A6 B6 ......... _____________ ______________ .. ___________ «_ V. Invention description (^) Method to solve it. Summary of the invention The present invention is designed for the zero-crossing threshold of asynchronous digital channels Detector. It receives the digitized signal waveform that encodes the self-synchronized data in it and outputs the #crossover relative position within the sampling period. If there is any zero crossover, this digital error is a reply with M. The contained data and clock signal are in the form of a discrete time control loop (DTCL) that can be directly proposed for a co-pending patent application. The author of the co-pending patent application is Hutchins et al. (Assignee Docket No. SA9-91-099) and its name is " Discrete Time Control Loop Method And Apparatus For Clocking Data In An Asynchronous Channel " and filed on October 28, 1992 and the patent application number is 07 / 967,588 'is hereby submitted as a reference. The non-synchronous digital threshold detector of the present invention (ADTD) uses the following three steps to estimate the zero-crossing arrival time within a single sampling interval. First, the detector determines whether a zero-crossing occurs by detecting whether the adjacent sample pair changes the sign of K or not. The second step, Convert the sampling rate from a higher sampling rate to a lower sampling rate. The lower sampling rate is exactly one-half of the higher sampling rate. When doing so, ADT0 first decides which half of the new and longer sampling period Including the zero crossing. Finally, ADTD relies on solving a linear interpolation formula W to determine the sub-lattice time estimate; that is, the proportional position of zero crossing in the shorter sampling period & (阃 1 (b)). The output of the detector is the η-bit digital signal (t / Td) of the part of the estimated rope-over time of the zero-crossing over a longer sampling period (Figure 1 U) ° -6 — This paper standard is passed through the H1 Chinese national standard ( CNS) A · 4 Clam (2 丨 〇X 297g ) (Please read the precautions before writing this page)-Binding · Order. A6 ____B6_ printed by the U Industry and Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) One of the purposes of the present invention is to change The zero-crossing accuracy of Bodhisattva at a lower asynchronous sampling rate. Another aspect of the present invention is to detect threshold crossings in digital sampling without relying on analog components. One of the features and stupidity of the present invention is that the zero-crossing detection is represented by M η-位数 位 # molybdenum plus M, and the accuracy of the word sister has nothing to do with analog signal timing considerations. The aforementioned vehicle items, the speed of which is the same as other purposes of the present invention, features and stupid points will become more apparent / obvious when referring to the following specifications, patent scope and drawings. BRIEF DESCRIPTION OF THE FIGURES For a more complete understanding of the present invention, reference is now made to the following detailed description I of the preferred examples shown in the accompanying drawings. Among them: Garden 1 shows the zero-crossing of the signal waveform within a sampling interval; FIG. 2 provides an illustration of the present invention. The block between the ADTD and other components of the recording channel; block 3 provides a block example of a preferred example of the ADTD pulse detector device of the present invention; FIG. 4 provides the ADTD 2Χ-to-IX converter device of the present invention The block country of the preferred example of the software; _5 provides the block of the preferred example of the AOTD timing generator of the invention_; and_6 provides the example of the AI) T [) performance of the invention. DESCRIPTION OF THE PREFERRED EXAMPLE FIG. M shows the relationship between the sampling interval Ts = Td / 2 of threshold 1 (b) and the self-synchronization data interval Td of FIG. 1 (a). The ADTD of the present invention determines the sub-frame time estimation l -7- This paper scale is applicable to the China Standard (CNS) f 4 specifications (210 X 297 public loan) (please read the precautions on the back 3 before writing this page) ; Install-. May. Λ A6 B6 V. Description of invention (6) (please read the back first: / Notes and then fill out this page) (Nurse (1 (b)) and convert it to one of the ratio t / Td Digital representation (Pool 1 (a)). Y2 shows the relationship between the ADTD 10 of the invention and the optical or magnetic data storage medium 12. A peak detection channel construction is shown as an example. The magnetic or optical transformation of the medium 12 It is K sensor sensing in any useful way known in the art by the transducer 14JW. The transducer output signal 16 is sent to generally multiple analog functions δ. These functions include preamplification. Automatic Gain Control (Automatic Gain Control, AGC), and anti-aliasing (anti-alias, lowpass) filtering. The resulting analog data signal waveform 20 is sent to the waveform preprocessor 22 to any known in the art Useful ways to implement signal differentiation, pulse qalification and analogy to Bit / A / D) conversion. The A / D sampling rate of the A / D converter 24 is controlled by the sampling clock generator 26, and the generator generates the sickle signal Fe = 2Fd when sampling with the signal waveform 20 from twice the synchronous data rate. The digital sampling signal {S} M sampling bus 28 is sent to ADTD 10. The pulse verifier 30 generates a pulse balance verification flag and the flag is sent to the ADTD 10 via the line 32. Pulse verification flags are any useful means known in the art to distinguish between signal pulses and noise pulses and are set at each sampling interval that contains verification pulses or transitions. The ADTD example 10 of FIG. 2 includes a pulse detector 34, a 2χ-to-1x converter 36, and a timing generator 38. The converter 36 operates at two time-out rates: the sampling rate F1 »obtained from the generator 26 and the data-time nickel rate P 6 ^-/ 2. ADTD 10 provides two-digit output. Provide a digital signal of the relative position of the threshold to the wheat in the mirror interval (t / Td) on the data viewing stream 40 on behalf of the data and M -8- This paper standard is common Chinese National Standard (CNS) A 4 specifications (210 X 297 H) The Ministry of Economic Affairs Zhongji Standard Ma Jigong Consumer Loan> Printed thorium Λ6 B6 V. Invention description (7) Line 42 transmits relief detection flag (PDF). It is suspected that 42 is the high level in all data clock intervals Td including the detection threshold transition detection. Fig. 2 shows the bus 40 and the line 42 that are fed into the discrete timing control loop (DTCL) 44M and then implement the loopback processing according to the above-mentioned Hutch ins et al. Patent application. It is also possible to use any other combination method to extract the data and synchronous clock signals from the digital bits 40 and 42 of the A DTD 10, for example, after digital-to-analog conversion, followed by phase-locked loop signal processing. In the waveform preprocessor 22, the signal divider 46W differentiates the data signal waveform 20M in any useful manner known in the art to convert the waveform spike to a zero-crossing transition. In the case where the medium 12 is composed of the tape of the tape drive 48 or the disk surface of the direct access storage device (DASD) 50, the recovered data appears in the waveform 20 as spikes or pulses. The detection of such a pulse balance requires differentiation of the signal differentiator 46. However, if the medium is an optical media such as optical disc 52, the signal can be pulse-width-modulated (PWM) M so that the returned data is encoded to pass a variable but predetermined threshold Waveform transition. For such applications, the signal differentiator 46 is not required and should be replaced by a suitable type of threshold tracking signal processing plus M known in the art. Either way, the pulse detector 34 must actually detect the waveform transition of the signal thief passing through the zero point. In operation, refer to Country 3 for a better understanding of the pulse detector 34 °. In FIG. 3, the pulse verification flag of line 32 is stored in register 54. The register 56 stores a delayed value & or gate (OR-gate) 58 for the pulse test flag and provides the enable test flag on line 60 > and the flag is before the current »(i) The previous (i-Ιth) sampling interval Τ »Certified Detective-9-This paper scale is applicable to China National Standard (CNS) A 4 regulations, each (2〗 0 X 297 public waste> (please read the back Please pay attention to this page and write this page) -—installed-. Available. ^ 部 中央 标> | 1-/ .; 4 工 消 #Cooperative printed by Α6 Β6 V. Description of invention (8) Lanxia is high The digital signal of the Chen bus 28 is divided into the sign bit of the 28a and the remaining 7-bit mantissa of the bus 28b. The registers 66 and 68 store the sign S of the current sample and the previous sample The sign of Si-i is used as a comparison. 'Mutually exclusive or X (R0-gate) 70 provides detection flags on line 72 and the flag is high as long as there is a sign change between S, μ and 51. and Μ (AND-gate) 74 Combined with the enable detection flag of line 60 and the change detection flag of Dai 72. K provides the detection flag DF ^ ◊ '7-bit registers 78 and 80 on output line 76 The role of the sister to represent the neighbor To - digital signal (S, ,, S,) of the yk). Therefore, the current digital signal yk is transmitted via the bus 82 (and its sign is transmitted on the line 82a) and the delayed one-bit signal is transmitted via the bus 86 (and its sign is on the line 86a). The bus bars 82 and 86 and the flag line 76 send adjacent pairs of digital signals and associated detection flags to the converter 36 (Figure 1). Refer to _4 to learn more about the converter 36. The converter 36 serves as a "deciraator" that replaces a digital signal pair with a single digital signal. Input registers 90 and 92 are at the same clock rate Fe plus M timing. The register 90 stores the delayed signal value. The register 92 stores the DF \ detection flag, and the flag indicates the detection within the current T «interval. The current signal 74 of the Chen bus 82 is directly connected to the first input of the multiplexer 94. The delayed signal yk_ !! is sent to the second loser of the multi-T device 94 and the first loser of the other multiplexer 96. Provided to the second slug of Ding 96. yk-2 just delays the sickle interval T «for an additional two samples. Finally, provide the detection flag DF as shown in 鈃 4, the first loser of Xiner multiplexers 98 and 100 and provide a fixed binary "〇" -10- This paper is also / 1 General Chinese National Standard (CNS ) A4 gauge (210 X 297; 12) (Please read the precautions on the back before writing this page) 丨 installed. * 1Τ. Printed A6 B6 by the Central Standards Bureau of the Ministry of Economic Affairs, Co., Ltd. Invention description (9) or " factory 'to their second input. Therefore, when the detected flag DFi passes through the register 92 at the timing when the germanium F »is sampled, the input of the multiplexer 94-100 is transferred to the registers 102, 104, 106, and 108. The registers 102-108 are one half of the M register 90-92 clock rate plus M timing. Therefore, it can be understood that the converter 36 selects the adjacent digital signal of the next cell where the zero crossing occurs and detects the banner (assuming that at most one nominal sampling period will only have one zero crossing). The converter 36 sets the most significant bit (MSB)% of the estimated zero-crossing time based on the half of the nominal sampling period Td = 2 Tβ at which the zero-crossing occurs. The converter 36 also sees that the current digital signal yk and The delayed digital signal yn M held on the bus 112 represents the test adjacent sample pair, Sd. Keeping this sampling to two Tβ sampling intervals and sending it to the timing generator 38K, another process is performed. The MSB of line 114 also maintains Td = 2 Ta time and sends it to the timing generator 38 as the highest effective poor element (MSB) of the final transition time ratio discussed below. Finally, the detection flag DFt of line 116 is the equivalent value of the radius of DF of line 76. That is, if there is a detection threshold change detected anywhere within the two-phase post sampling interval 2Te = Td, line 116 is set. »5 shows a detailed example of the timing generator 38. The purpose of the generator 38 is to estimate the zero-crossing arrival time by solving an interpolating equation M which represents the relationship between the transition detection and the digital signal yk) representing the phase sampling pair, St) and the sampling pair is saved In registers 102 and 104 (_4). This pair is the input of generators U0 and 112 to the generator 38. Separating the selective flow bank 1] The 8-bit digital signal M of 0 causes MS B to be on the line Π 0 b of FIG. 5 and the remaining 7-bit tail enemy is on the Chen bank 1 1 0 a. Similarly, in -11- this paper is again applicable to the Chinese National Standard (CNS) A4 Clam (210 X 297 Gong; Li) (please read the notes on the back's before filling this page) --- ---- — — —— —--1 ί----I.-II ^ 1- ^ n! —! N-in · _. Profit-making application No. 82108302 · Chinese manual amendment page (84 Year 1 _ Beta Furnace Α6 Β6------ — _y 5. Description of the invention (το) The 5-selective bus 112b provides the 7 least significant bits (LSB). The MSB from the bus 丨 12 (Figure 4) is not needed because it has been implied by the sign of the sign bit of line 1 J 6 DF i and line 1 1 0 b. The generator 38 solves any representative detection and sampling pairs (S ,-:, S,) relationship ... Useful interpolation formula. The inventors prefer a simple linear interpolation equation ·· kl where yk is the equivalent value of the intermediate digital signal of the sampled Si. T / Td- effective zero crossing The more, the sign of yk and the sign of yk are reversed, so that the above equation can be rewritten as C / Td = ^ yjy \ .x \. This is possible (please close-memorize matters before 3 and write this page) 4 fi |; Shiyang Youwei divided the sign bit interdigitation earlier Circle 5 • First, the denominator signal follows l.yk-yk-i, which is ϋ completed by the multiplexer 120 plus M. When the line 1 I 0 b of y X has a positive-absolute absolute multiplier · 122. Yes. If yx is negative with the sign, two's complement? Ί (2s-cqmplenient). Add digital signals to provide at the bus 118 and then use any useful device, such as the denominator signal 118. The map 126 is Μ this mode of operation, for example, 2 5 6-bit view table row 1 2 8 provides 1 2-bit elm out of the late signal ^-η ΓΕ negative sign depends on the modified bit signal y ^, ft store array stream When row 1 3 2 is used to insert the equation row 1 1 8 and 1 2 2 and the phase number, the multiplexer selects the delay. These two devices are selected 1 2 4 and the two denominators are numbered 1 y. (lookup ta number multiple. Phase multiplexer 1 22 for absolute calculation of yk ^. Fixed denominator adder 1 2 4 as follows 1 20 Select the selected 7-bit map of the absolute digital signal of the target signal h ^ 1 26, any useful knowledge of conversion b 丨 e), and in the adder 1 3 0 depending on the selected delay number logarithmic multiplier r work · ν1 '$ τ cooperation Du Yin "The paper size Zhongyinjiajiashen (CNS) A · "Regulations (210 X 297 Gongcha) A6 B6 Economical Central Chuzheng Bureau 8 Industrial and Consumer Cooperatives printed purple five, invention description () 134 will _ 排 排 128 of 12- The bit reciprocal output signal is multiplied by the 7-bit numerator of the bus 132 and the 14 LSB of the resulting result is removed leaving a 5-bit zero crossover signal on the bus 136. This signal is then stored in the buffer 138 at a sampling interval to provide the additional delay required to synchronize operation with the other parts of the generator 38. Finally, the output zero-crossover estimation signal t / Td is provided on the bus 40, and the MSB of the line 40a indicates which of the two-phase sampling period Ts contains the event. The inventors have used the 8-bit input sampling of the bus 28 to show whether the given sample exceeds the tracking threshold of the test threshold of line 32 and plot the 6-bit time estimate and online 42 on the bus 40 The effective sampling flag (PDF) is output on the top to simulate the preferred example shown in Figure 2-5. If MCMOS II technology plus W construction, ADTD 10 requires about 1500 gates. This preferred example has also been constructed in a magnetic tape data storage system. The inventors have also used APL to simulate this construction to determine how closely the actual ADTD performance can match a simple theoretical linear interpolation formula. Provide all possible adjacent digital pair signal combinations to an APL bit circuit. Then compare the output of ADTD 10 proposed by Qi Yu with the theoretical solution of the linear interpolation formula plus K (阃 5) and the results are plotted in Fig. 6. In Fig. 6A, y k is fixed at 0.5 and y k-α is the change in all norms of possible values (all ranges are normalized to 1). The simulation results are very close to the theoretical results. In _6B, "^ is fixed at 0.5 and y ^ lj is changed in all ranges of possible Qian. Once again> AOTD performance simulated in all ranges of possible input is very close to the expected slug. Figure 6a and The difference between the two curves of 6b is caused by the optimization error. -13- This paper is again applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297 public tears) (please read back '-5 (Notes to fill out this page). 装. -ΤΓ— I ― — 1 V. Description of the invention (12) A6 B6 It ’s very common for those who are in the field to receive the surgery and know how to get fever Because of the fact that some changes were made in He Jian, he found it easy to see in the field, and it appeared to be easy to contain-at the time, it seemed to be combined with the description of the specifications. If you want to use it, please include it in the application (please read the precautions on the back and then ii write this page). Binding-. This paper is again applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297); )