五、發明説明（！ A7 B7 經濟部中央標準局貝工消費合作社印製 本發明係有關一種曼徹斯待碼用解碼裝置，κ及特別 有關一種改良式曼徹斯特碼用解碼装置，它能夠與一接收 時鐘信號同步地、接收一非同步曼徹斯特碼、Μ及將其解 碼成一不回零（NRZ)碼和一同步時鐘信號。 曼撤斯待编碼可使一串列二進位資料與一同步時鐘信 號結合，Μ便能在同步通訊条統之間，產生一單一信號。 亦即，其在執行上係使一二進位資料NRZ，與一507,同步疑 點（dubiety)之傳輪時鐘信號，經由專或邏輯處理而成。 由於該曼徹斯特编碼之蓮作所致，一 NRZ資料之邏輯 ” Γ，係表示成一二進位位元碼之” 1, 0”，其中之第一位 數為高邏輯位準，Μ及第二位數為低邏輯位準，而邏輯 ”0”則係表示成”0,1"，其中之第一位數為低邏輯位準，Μ 及第二位數爲高通輯位準。亦即，上述碼轉換之動作，係 在一二進位位元碼之曼徹斯特碼中進行的。 此外，第1圖係顯示一具有時鐘信號周期102之典型曼 徹斯特碼的波形100，各時鐘信號周期102係界定包含一具 有一高邇輯位準碼位元格104和一低通輯位準位元格106， Μ及各資料位元格係包含該等下降緣移位” A, C, E , G , I , Κ ,Μ,Ο"與上昇緣移位B,D,F,H,J,L和Ν。 此外，一發生在各時鐘信號周期102之中央部分的移 位，係持用Μ傳送一對應之資料，而發生在各時鐘信號周 期上昇緣處之移位D,G,I,K和Ν，則係與該資料之傳送無關 所以，一可接收該碼之通訊条统，將會偵测一發生在 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、vs Γ 5 經濟部中央標準局員工消费合作社印裝 Α7 Β7 五、發明説明（2 ) 各時鐘信號周期102之中央部分的移位點、備妥一同步曼 徹斯特碼、以及解碼出該NRZ資料與該接收之時鐘信號Rx CLK ° 第2圖顯示一傳統式曼徹斯特碼解碼裝置，其包含： 一緩衝器10,它可經由其一輸入端子接收一曼徹斯特碼， 並且輸出一非反相曼徹斯特碼和一反相曼徹斯特碼；一延 遲裝置20,它可接收該緩衝器10所蝓出之非反相曼徹斯特 碼，並且使該曼徹斯待碼分別延遲一 1/2碼周期和3/4碼周 期；一第一正反器30,它可經由其時鑊信號端子，接收該 缓衝器10所輸出之反相曼徹斯特碼，並且取樣該延遲裝置 20所_出而延遲3/4碼周期之該曼徹斯特碼，Μ及輪出一 移位偵測信號；一第二正反器40,它可經由一時鐘信號端 子，接收該缓衝器10所輪出之反相曼徹斯特碼，並且在該 非反相曼徹斯特碼之上昇緣處，取樣該延遲裝置20所輓出 而延遲1/2碼周期之曼徹斯特碼，Μ及繪出一移位偵測信 號；一SR正反器50,它可將上述該第一正反器30所輸出之 移位偵測信號所設定之NRZ碼，輪出给該第一正反器30之 重置端子R，以及可經由其重置端子R，接收該第二正反器 40所輪出之移位偵測信號而加Μ反相，並且將如此反相之 信號，輪出给該第二正反器40之設定端子S ; —專或邏輯 閘60,而其一端係接地，其另一端係用Κ接收該SR正反器 50之非反相所綸出端子Q蝓出之NRZ碼，並Μ邏輯專或處理 如此接收之NRZ碼，Κ及可輪出上述解碼過之NRZ碼；一延 遲匹配缓衝器70， 它可接收上述經過該延遲裝置20延遲 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本買) " 6 Α7 Β7 294873 五、發明説明（3 ) 1/2時鐘信號周期之曼徹斯特碼；以及一專或邏輯閘80， 它可經由其一端子接收上述經由該延遲匹配緩衝器70延遲 之曼徹斯特碼，並可經由其另一端子，接收該SR正反器50 所之非反相輪出端子Q蝓出之NRZ碼，以及可產生一接收時 建信號Rx CLK。 今將參考第1至3圖說明上述傳統式曼徹斯特碼解碼裝 置之蓮作情形。 首先，當輓入一如第3圖所示之曼撤斯特碼300時，該 接牧之曼徹斯特碼，將會經由該曼徹斯特解碼装置200之 缓衝器10加Μ緩衝並放大。上述非反相之曼徹斯特碼300 ，將會分別繪入至該等延遲裝置20和和第二正反器40，Μ 及上述反相之曼徹斯特碼302，將會輪入至該第一正反器 30 〇 繼而，該延遲裝置20將接收來自該缓衝器10之非反相 曼徹斯特碼300，並且分別使該曼徹斯待碼300延遲一 3/4 時鐘信號周期和一 1/2時鑲信號周期，Μ及將上述延遲3/4 時鐘信號周期之曼徹斯特碼306，蠄出給該等第一正反器 30和第二正反器40之輪入端子D，將上述延遲1/2時鐘信號 周期之曼徹斯特碼304 ,鑰出給該延遲匹配緩衝器70。 此時，該曼榭斯特碼300 ,將會在所有資料格之中央 部分產生一移位，而由於該等第一正反器30與第二正反器 40,係一種蓮作於一輸入至其時鐘信號端子之倍號的上昇 移位處的霣路，該等第一正反器30與第二正反器40,在變 化上係依據在各資料格之中央部分處所測得之信號緣或移 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明（4 ) 位狀態而定，K及其輸出將不會因各資料格之邊界處所表 示之信號緣或移位狀態而改變。 繼而，該第一正反器30將會經由其時鐘信號端子，接 收該缓衝器10所輪出之反相曼徹斯特碼302， Μ及將會在 一上昇移位處，取樣上述經該延遲裝置20延遲3/4時鐘信 號周期之曼徹斯特碼306，並且將該移位偵測信號310，輸 出給該SR正反器50之設定端子S。 繼而，該第二正反器40將會經由其時鐘信號端子，接 收自該緩衝器10輪出之非反相曼徹斯特碼300， Μ及在一 上昇移位處，取樣上述經該延遲裝置20延遲3/4時鐘信號 周期之曼徹斯特碼306，並且將該移位偵測信號，輪出給 該SR正反器50之重置端子R。 趄而，該等第一正反器30與第二正反器40,將會依據 Μ下規則，鑰出一移位偵測信號。亦即，如第1圖所示輪 出一移位偵測信號130。 Α.當在該曼徹斯特碼波形1〇〇之時鏞信號周期102的中 央部分處所測得之移位係一上昇移位Β，以及該波形100之 狀態在一二進位位元格（箭頭108所指處）期間係一低邏 輯位準時，該移位偵测信號將會由一高邏輯位準變換至一 低邏輯位準。 Β.當該測得之移位係一上昇移位Η，以及該波形100之 狀態在一二進位位元格（箭頭110所指處）期間係一高酱 輯位準時，該移位偵測信號將會保持其先前之狀態。 C .當該測得之移位係一下降移位Β，Κ及該波形100之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 8 經濟部中央揉準局員工消費合作杜印製 Α7 Β7 五、發明説明（5 ) 狀態在一二進位位元格（箭頭112所指處）期間係一低運 輯位準時，該移位偵測信號將會保持其先前之狀態。 D ·當該測得之移位係一下降移位B，Μ及該波形100之 狀態在一二進位位元格（箭頭114所指處）期間係一高邏 輯位準時*該移位偵測信號將會由一低邏輯位準變換至一 高遛輯位準。 所Μ，依據上述之規則，當該第一正反器30在該反相 曼徹斯特碼302之一上昇移位處，亦即，在曼徹斯特碼300 之一下降移位處，取樣上述延遲3/4時鐘信號周期之曼徹 斯特碼306， Μ及所取樣之資料為”1”時，該曼徹斯特碼 300在隨後之二進位位元格期間，將會保持為”1”之狀態， Μ及該第一正反器30將會使該移位偵測倍號自”0”轉變至 ”1”（在該信號310之點308處），並且鑰出给該SR正反器 50之端子S，Μ及該SR正反器50將會被設定為”1”，並且經 由其非反相輪出端子Q*輪出一高邏輯位準之NRZ碼，Μ便 重置該第一正反器30,而該第一正反器30之非反柑輸出端 子Q將會輪出一 ”0”。 同時，當上述在該曼徹斯特碼300之下降移位處所取 樣之資料為”0”時，由於該曼徹斯持碼300在隨後之二進位 位元格期間並非為狀態”1”，該第一正反器30將會保持為 狀態”0”，並且將一移位偵測信號”0”輸出至其非反相幟出 端子Q。 繼而，當該第二正反器40在該反相曼撤斯特碼300之 一上昇移位處，取樣上述延遲3/4時鐘信號周期之曼徹斯 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 9 A7 B7 五、發明説明（6 ) 特碼306，Μ及此時所取樣之資料為”0”時，該非反相曼榭 斯特碼300在随後之二進位位元格期間，將會保持為”0”之 狀態，Μ及該第一正反器30將會使該移位偵測信號自” Γ 轉變至”0”，並且輓出給該SR正反器50之重置端子R，以及 該SR正反器50將被重置為一偵测信號” Γ，並且經由其反 相繪出端子，輸出一高遍輯位準信號，Μ便設定該第二正 反器40，而該第二正反器40之反相输出端子Q將會_出一 ”0”之移位偵测信號。 同時，當上述在一上昇移位處所取樣之資料為”1”時 ，由於該曼徹斯特碼300在随後之二進位位元格期間並非 為”0”，該第二正反器40將會保持為狀態”1”，並且經由其 反相幢出端子Q輸出”0”。此一情況係發生於該第二正反器 40,在一位於該等位元格邊界之上昇移位處，取樣一曼徹 斯特碼之一時刻。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 繼而，該第三正反器50將會依據該等第一正反器30與 第二正反器40所繪出之一移位偵測信號，在其非反相輪出 端，輪出不使該NRZ碼，Μ及上述一端子接地之專或邏輯 閘60,將會經由其另一端子，接收該SR正反器50所綸出之 NRZ碼，並將如此接收之碼加M0R邏輯處理，而輪出一NRZ 資料。 此外，該延邐匹配级衝器70,將會接收一經由該延遲 裝置20延遲一 1/2時鐘信號周期之受徹斯特碼304 ,並且可 將一因該等正反器裝置30和40所致，信號延遲而受到延遲 之匹配信號317，輪出给該專或邏輯閘80之一端子，Μ及 本紙張尺度逋用中國國家梯準（CNS ) Α4規格（210X297公釐） 10 - 10 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（7 ) 該專或邏輯閘80，將會接收一未被該正反器50反相之NRZ 碼，以及將會接收一經由其另一端子，接收該延遲匹配缓 衝器70所_出之匹配信號307，並將如此接收之碼加以專 或邐輯處理，而輪出一接收時鐘信號Rx_CLK。 然而，該傳統式曼徹斯特碼解碼裝置，係採用一鎖相 迴路（PLL)，來接收該移位曼徹斯特碼，而與一同步狀 態匹配。當不採用該PLL時，便需要有某棰可使該曼徹斯 特碼延遲之程序，以致增加了晶片之尺寸，且需要有更精 確的製造程序，故其生產力將會降低。 因此，本發明之一目地旨在提供一種曼徹斯特碼用解 碼裝置，它可克服在一傳統式曼徹斯持碼用解碼裝置中所 逋遇的種種問題。 本發明之另一目地旨在提供一種改良型曼榭斯特碼用 解碼裝置，它能夠接收一非同步曼徹斯特碼、使與一接收 時鐘信號同步、而解碼成一NRZ碼和一同步時鐘信號。 爲完成Μ上諸目地，所設之曼徹斯特碼用解碼裝置包 含：一第一解碼装置，它可藉著使一傳送之非同步曼徹斯 特碼與一時鏟信號之移位同步，而取樣一同步曼徹斯特碼 ，除以該時鐘信號而計算出該同步時鐘信號，以及就該等 同步曼谢斯特碼與同步時鐘信號，進行專或S輯蓮算，而 計算出一NRZ碼；一容許度檢核單元，它可接收一來自該 第一解碼裝置之同步曼徹斯特碼，順序偵測一依據時鐘信 號移位之位元值，Μ及檢核一相對於在該曼榭斯特碼之一 位元格中央部分移位的容許度；一多工器單元，它可依據 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） {請先閱讀背面之注意事項再填寫本頁) 訂 11 A7 B7V. Description of the invention (! A7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This invention relates to a decoding device for Manchester to be coded, and in particular to an improved decoding device for Manchester codes, which can be combined with a Receive the clock signal synchronously, receive an asynchronous Manchester code, M and decode it into a non-zero return (NRZ) code and a synchronous clock signal. Mantos to be encoded can make a series of binary data and a synchronous clock Signal combination, M can generate a single signal between the synchronous communication system. That is, it executes a binary data NRZ, and a 507, synchronous duplication of the wheel clock signal, through It is processed by special logic or logic. Due to the lotus code of Manchester encoding, the logic “Γ” of a NRZ data is expressed as “1, 0” of a binary bit code, and the first digit is high Logic level, M and the second digit are the low logic level, and the logic "0" is expressed as "0,1", where the first digit is the low logic level, M and the second digit are Qualcomm editing level. That is, on The code conversion operation is performed in a binary code of Manchester code. In addition, FIG. 1 shows a waveform 100 of a typical Manchester code with a clock signal period 102, and each clock signal period 102 is defined to include a It has a high-level edit code bit grid 104 and a low-pass edit level bit grid 106, M and each data bit grid includes these falling edge shifts "A, C, E, G, I, Κ, Μ, Ο " and rising edge shifts B, D, F, H, J, L and N. In addition, a shift that occurs at the central portion of each clock signal period 102 is transmitted using M to correspond to Data, and the shifts D, G, I, K, and N that occur at the rising edge of each clock signal period are not related to the transmission of the data. Therefore, a communication system that can receive the code will detect a Occurred in this paper scale applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 mm) (please read the precautions on the back before filling out this page), vs Γ 5 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Α7 Β7 5. Description of the invention (2) The shift point of the central part of each clock signal period 102 is prepared Synchronizing Manchester code and decoding the NRZ data and the received clock signal Rx CLK ° Figure 2 shows a traditional Manchester code decoding device, which includes: a buffer 10, which can receive a Manchester code through an input terminal thereof , And output a non-inverted Manchester code and an inverted Manchester code; a delay device 20, which can receive the non-inverted Manchester code from the buffer 10, and delay the Manchester waiting codes by 1 respectively / 2 code period and 3/4 code period; a first flip-flop 30, which can receive the inverted Manchester code output by the buffer 10 through its time wok signal terminal, and sample the delay device 20_ The Manchester code delayed by 3/4 code period, M and a shift detection signal are output; a second flip-flop 40, which can receive the output of the buffer 10 through a clock signal terminal Invert the Manchester code, and at the rising edge of the non-inverted Manchester code, sample the Manchester code pulled by the delay device 20 and delay by 1/2 code period, M and draw a shift detection signal; an SR is Inverter 50, it can be The NRZ code set by the shift detection signal output by the first flip-flop 30 is rounded out to the reset terminal R of the first flip-flop 30, and the reset terminal R can receive the first The shift detection signal rounded by the two flip-flops 40 is inverted by adding M, and the inverted signal is rounded out to the setting terminal S of the second flip-flop 40;-the exclusive OR logic gate 60, The other end is grounded, and the other end uses K to receive the NRZ code from the non-inverted output terminal Q of the SR flip-flop 50, and the NRZ code so received by M logic or K can be processed The above decoded NRZ code; a delay matching buffer 70, which can receive the above delay through the delay device 20. This paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) (please read the note on the back first Please fill out the item to buy this) " 6 Α7 Β7 294873 5. Description of the invention (3) Manchester code of 1/2 clock signal period; and a special or logic gate 80, which can receive the above-mentioned delay matching buffer through one of its terminals 70 is the delayed Manchester code and can be received via its other terminal SR flip-flop 50 to round out the non-inversion terminal Q of the slug out of the NRZ code, and build a signal Rx CLK may be generated when a receiver. Now, the above-mentioned conventional Manchester code decoding device will be described with reference to FIGS. 1 to 3. First, when a Manchester code 300 as shown in FIG. 3 is loaded, the grazing Manchester code will be buffered and amplified by the buffer 10 of the Manchester decoding device 200. The above-mentioned non-inverted Manchester code 300 will be drawn into the delay devices 20 and the second flip-flop 40, respectively, and the above-mentioned inverted Manchester code 302 will be rounded to the first flip-flop 30 〇 Then, the delay device 20 will receive the non-inverted Manchester code 300 from the buffer 10, and respectively delay the Manchester waiting code 300 by a 3/4 clock signal period and a 1/2 time setting signal Period, Μ and the Manchester code 306 which delays the above 3/4 clock signal period to the rounded-in terminal D of the first flip-flop 30 and the second flip-flop 40, delays the above by 1/2 clock signal The Manchester code 304 of the period is keyed out to the delay matching buffer 70. At this time, the Manchester code 300 will generate a shift in the central part of all data grids, and since the first flip-flop 30 and the second flip-flop 40 are a lotus as an input The first forward inverter 30 and the second forward inverter 40 are based on the signal measured at the central part of each data grid. The standard of margin or copy paper is applicable to China National Standard (CNS) Α4 specification (210Χ297mm) (please read the precautions on the back before filling in this page). Printed by consumer cooperatives Α7 Β7 V. Invention description (4) Depending on the bit status, K and its output will not change due to the signal edge or shift status indicated at the boundary of each data grid. Then, the first flip-flop 30 will receive the inverted Manchester code 302 rounded off by the buffer 10 through its clock signal terminal, M and will be at an ascending shift, sampling the above-mentioned delay device 20. Manchester code 306 delayed by 3/4 clock signal period, and the shift detection signal 310 is output to the setting terminal S of the SR flip-flop 50. Then, the second flip-flop 40 will receive the non-inverted Manchester code 300, M and a rising shift from the buffer 10 through its clock signal terminal, and sample the above delay by the delay device 20 The Manchester code 306 of 3/4 clock signal period, and the shift detection signal is rounded out to the reset terminal R of the SR flip-flop 50. Then, the first flip-flop 30 and the second flip-flop 40 will generate a shift detection signal according to the following rules. That is, a shift detection signal 130 is output as shown in FIG. Α. The shift measured at the central portion of the Yung signal period 102 at the time of the Manchester code waveform 100 is a rising shift B, and the state of the waveform 100 is in a binary bit grid (arrow 108) When the period is a low logic level, the shift detection signal will change from a high logic level to a low logic level. Β. When the measured shift is a rising shift Η, and the state of the waveform 100 is a high level during a binary bit grid (pointed by the arrow 110), the shift detection The signal will maintain its previous state. C. When the measured shift is a descending shift Β, K and the waveform 100, the paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X297mm) (please read the notes on the back before filling in this Page) Order 8 The Ministry of Economic Affairs Central Bureau of Accreditation and Employee Consumption Cooperation Du Printed Α7 Β7 V. Description of the Invention (5) The state is a low level of motion during a binary digit (pointed by arrow 112). The shift detection signal will maintain its previous state. D. When the measured shift is a falling shift B, the state of the M and the waveform 100 is a high logic level during a binary bit grid (pointed by arrow 114) * the shift detection The signal will change from a low logic level to a high logic level. Therefore, according to the above rule, when the first flip-flop 30 is at a rising shift of one of the inverted Manchester codes 302, that is, at a falling shift of one of the Manchester codes 300, the delay 3/4 is sampled When the Manchester code 306, M of the clock signal period and the sampled data are "1", the Manchester code 300 will remain at the state of "1" during the subsequent binary bit lattice, M and the first positive The inverter 30 will change the shift detection multiple from "0" to "1" (at the point 308 of the signal 310), and the key is output to the terminals S, M and the SR flip-flop 50 The SR flip-flop 50 will be set to "1", and a NRZ code with a high logic level is rounded out through its non-inverting round-out terminal Q *, and M will reset the first flip-flop 30, and the The non-inverting output terminal Q of the first flip-flop 30 will output a "0". At the same time, when the data sampled at the downshift of the Manchester code 300 is "0", since the Manchester code 300 is not in the state "1" during the subsequent binary bit lattice, the first The flip-flop 30 will maintain the state "0" and output a shift detection signal "0" to its non-inverted flag terminal Q. Then, when the second flip-flop 40 samples the above-mentioned delayed 3/4 clock signal period of the Manchester paper standard at the rising shift of the inverse Manchester code 300, the Chinese National Standard (CNS) is applied Α4 specifications (210 X 297 mm) (please read the precautions on the back before filling in this page) Order 9 A7 B7 5. Description of invention (6) Special code 306, Μ and the sampled data at this time is "0" , The non-inverted Manchester code 300 will remain in the state of "0" during the subsequent binary bit lattice, and the M and the first flip-flop 30 will cause the shift detection signal to "Γ changes to" 0 ", and it is pulled out to the reset terminal R of the SR flip-flop 50, and the SR flip-flop 50 will be reset to a detection signal" Γ, and is drawn through its inverse Terminal, output a high-pass level signal, M sets the second flip-flop 40, and the inverting output terminal Q of the second flip-flop 40 will output a "0" shift detection signal . Meanwhile, when the data sampled at an ascending shift position is "1", since the Manchester code 300 is not "0" during the subsequent binary bit lattice, the second flip-flop 40 will maintain It is in the state "1", and outputs "0" via its inverted terminal Q. This situation occurs when the second flip-flop 40 samples a Manchester code at an ascending shift at the boundary of the bit grids. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Then, the third flip-flop 50 will be based on the first flip-flop 30 and the second flip-flop 40 One of the shift detection signals drawn, at its non-inverted round out end, round out the NRZ code, M and the dedicated OR logic gate 60 with one terminal grounded, will be received through the other terminal The NRZ code produced by the SR flip-flop 50 is added to the MOR logic to process the received code, and a NRZ data is output in turn. In addition, the delay matching stage stimulator 70 will receive a received Chester code 304 delayed by a 1/2 clock signal period through the delay device 20, and may be responsible for the positive and negative device 30 and 40 As a result, the signal is delayed and the delayed matching signal 317 is rounded out to one terminal of the dedicated or logic gate 80. Μ and the size of this paper use the Chinese National Standard (CNS) Α4 specification (210X297 mm) 10-10 A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of invention (7) The dedicated or logic gate 80 will receive an NRZ code that is not inverted by the flip-flop 50, and will receive a The other terminal receives the matching signal 307 from the delay matching buffer 70, and processes the code thus received for special or editing, and in turn generates a receiving clock signal Rx_CLK. However, the conventional Manchester code decoding device uses a phase-locked loop (PLL) to receive the shifted Manchester code and match it with a synchronization state. When the PLL is not used, there is a need for a procedure that can delay the Manchester code, which increases the size of the chip and requires a more precise manufacturing process, so its productivity will be reduced. Therefore, an object of the present invention is to provide a decoding device for Manchester codes, which can overcome various problems encountered in a conventional decoding device for Manchester codes. Another object of the present invention is to provide an improved decoding device for Manchester codes, which can receive an asynchronous Manchester code, synchronize with a received clock signal, and decode into an NRZ code and a synchronized clock signal. In order to accomplish the above objectives, the set of decoding devices for Manchester code includes: a first decoding device, which can sample a synchronous Manchester code by synchronizing the transmission of an asynchronous Manchester code with the shift of the instantaneous shovel signal , Divide the clock signal to calculate the synchronous clock signal, and perform a special or S series calculation on the synchronous Manchester code and the synchronous clock signal, and calculate an NRZ code; a tolerance check unit , It can receive a synchronous Manchester code from the first decoding device, sequentially detect a bit value shifted according to the clock signal, Μ and check a relative to the center of a bit lattice in the Manchester code Tolerance of partial displacement; a multiplexer unit, which can be adapted to the Chinese National Standard (CNS) A4 specifications (210X297mm) according to the paper size. {Please read the precautions on the back before filling out this page) Order 11 A7 B7
煩請委员明示本案是否變更實質内容 五、發明説明（8 ) 該容許度檢核單元所輸出之偵測信號，來選擇_出該第一 解碼單元所輸出之一 NRZ碼與該同步時鐘信號；一同步信 號偵測單元，它可接收該多工器單元所輪出之一 NRZ碼和 一同步信號，Μ及可偵測一依據一同步倍號移位之NRZ碼 的位元值，並且可輸出一同步信號；以及一第二解碼單元 ，它可接收該多工器單元所輪出之一NRZ碼和一同步時鐘 信號，Μ及可依據該同步信號偵測單元所輸出之一同步信 號，來計算該NRZ資料和該同步時鑊信號。 第1圖係一傳統式曼徹斯特碼之波形圖； 第2圖係一傳統式曼徹斯特碼解碼装置之方塊圖； 第3圖係第2圖之各元件的時序圖； 第4圖係一依據本發明所製曼徹斯特碼解碼裝置之方 塊圖； 第5圖係第4圖依據本發明之各元件，進行一接收之非 同步曼徹斯特碼之理想移位的時序圖； 第6圖係第4圖依據本發明之各元件，一接收之非同步 曼徹斯特碼移位120ns前的時序圖；而 第7圖則係一接收之非同步曼徹斯特碼移位l〇ns後的 時序圖。 第4圖顯示一依本發明所製之曼徹斯待碼用解碼裝置 ，其包含：一第一解碼單元100,它可藉使—傳送之非同 步曼徹斯特碼與一時鐘信號CL0CK_R之移位同步，而取樣 一同步曼徹斯特碼，再除以該時鏟倍號CL0CK_R，而計算 該同步時鐘信號，並就該等同步曼榭斯特碼與同步時鐘信 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 本紙張尺度適用中國國家標準（CNS ) A4规格U10X 297公釐） 12 -1 〇 _ 煩賴孝是否變更實質内容 A7 B7 五、發明説明（9 ) 號，進行專或通輯蓮算，Μ及可計算出一NRZ碼；一容許 度檢核單元200 ,它可接收一來自該第一解碼單元1〇〇之同 步碼，順序偵测一依據一時嬗信號移位之位元值，Μ及可 檢核一相對於在一位元格中央部分移位的容許度；一多工 器300 ,它可依據該容許度檢核單元200所输出之一偵测信 號，來選擇_出該第一解碼單元所輪出之一 NRZ碼和一同 步信號；一同步信號偵测單元400 *它可接收該等來自該 多工器300之NRZ碼和同步信號，Μ及可偵测一依據一同步 信號Sync移位之NRZ碼的位元值；Μ及一第二解碼單元500 ，它可接收該等來自該多工器300之NRZ碼與同步信號Sync ，以及可依據該同步信號偵测單元400所輸出之一同步信 號Sync，來計算一 NRZ資料和一接收時鐘信號Rx_CLK。 該第一解碼單元100包含：一第一正反器11，它可接 收該等非同步曼徹斯特碼和時鐘信號CL0CK_R，在該時鐘 信號CL0CK_R之一上昇緣處，取樣該非同步曼徹斯待碼， Μ及可在其非反相鑰出端子，繪出該同步曼徹斯特碼；一 第二正反器12,它可保存上述依據該時鐘信號而反相之同 步信號，以及可在其非反相_出端子，_出上述除得1/2 之同步信號；一專或邏揖閘13,它可使該第一正反器11所 輸出經由其一端子所接收之同步曼徹斯特碼，與該第二正 反器12所輸出經由其另一端子所接收之同步時鐘信號 CL0CK_1，進行專或邏輯蓮算，以及可偵測一NRZ碼NRZ_1 ;一第三正反器15,它可接收該非同步曼徹斯待碼和上述 被該反相器14反相之時鐘信號CL0CK_R，以及可在該反相 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁)May members please indicate whether the substance of the case is changed? V. Description of the invention (8) The detection signal output by the tolerance checking unit to select _ a NRZ code output by the first decoding unit and the synchronous clock signal; Synchronization signal detection unit, which can receive a NRZ code and a synchronization signal from the multiplexer unit, M and can detect the bit value of an NRZ code shifted according to a synchronization multiple, and can output A synchronization signal; and a second decoding unit, which can receive a NRZ code and a synchronization clock signal from the multiplexer unit, and M can synchronise a synchronization signal output from the detection unit according to the synchronization signal, to Calculate the NRZ data and the Wok signal during synchronization. Figure 1 is a waveform diagram of a conventional Manchester code; Figure 2 is a block diagram of a conventional Manchester code decoding device; Figure 3 is a timing diagram of the components of Figure 2; Figure 4 is a diagram according to the present invention Block diagram of the manufactured Manchester code decoding device; FIG. 5 is a timing diagram of FIG. 4 according to the components of the present invention, an ideal shift of a received asynchronous Manchester code; FIG. 6 is a diagram of FIG. 4 according to the present invention For each element, a received unsynchronized Manchester code is shifted by 120 ns; and Figure 7 is a received unsynchronized Manchester code shifted by 10 ns. FIG. 4 shows a decoding device for Manchester to be coded according to the present invention, which includes: a first decoding unit 100, which can synchronize the shift of the asynchronous Manchester code transmitted with a clock signal CL0CK_R , And sample a synchronous Manchester code, and then divide by the current shovel number CL0CK_R, and calculate the synchronous clock signal, and the synchronous Manchester code and synchronous clock letter (please read the notes on the back before filling in this Page) The paper standard printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) A4 specification U10X 297 mm) 12 -1 _ _ Whether Lai Xiao changes the substance A7 B7 V. Description of invention (9 ) No., perform special or general calculations, M and can calculate a NRZ code; a tolerance checking unit 200, it can receive a synchronization code from the first decoding unit 100, sequentially detect a basis The bit value of the instantaneous transmutation signal, M and the checkable tolerance relative to the shift in the central part of the bit grid; a multiplexer 300, which can check the output of the verification unit 200 according to the tolerance A detection signal to select_ A NRZ code and a synchronization signal rounded by the first decoding unit; a synchronization signal detection unit 400 * It can receive the NRZ codes and synchronization signals from the multiplexer 300, M and can detect a basis The bit value of the NRZ code shifted by a synchronization signal Sync; M and a second decoding unit 500, which can receive the NRZ code and the synchronization signal Sync from the multiplexer 300, and can detect based on the synchronization signal A synchronizing signal Sync output from the unit 400 calculates an NRZ data and a received clock signal Rx_CLK. The first decoding unit 100 includes: a first flip-flop 11 that can receive the asynchronous Manchester code and the clock signal CL0CK_R, and sample the asynchronous Manchester pending code at one rising edge of the clock signal CL0CK_R, Μ and its non-inverted key out terminal, draw the synchronous Manchester code; a second flip-flop 12, it can save the above-mentioned synchronous signal inverted according to the clock signal, and can be in its non-inverted _ Out terminal, _ out of the above synchronization signal divided by 1/2; a special or logic gate 13, it can make the first flip-flop 11 output the synchronous Manchester code received through one of its terminals, and the second The flip-flop 12 outputs the synchronous clock signal CL0CK_1 received through its other terminal for exclusive or logical calculation, and can detect a NRZ code NRZ_1; a third flip-flop 15 which can receive the asynchronous Manchester Siwait code and the above-mentioned clock signal CL0CK_R inverted by the inverter 14 and the Chinese standard (CNS) A4 specification (210X 297mm) that can be applied to the paper size of the inverter (please read the notes on the back (Fill in this page again)
•1T 經濟部中央標準局員工消費合作社印製 13 五、發明説明（ 10 A7 B7 經濟部中央標準局員工消費合作社印製 時鐘信號CL0CK_R之一上昇緣處取樣該同步曼徹斯特碼； 一第四正反器16，它可依據一反相時鐘信號CL0CK_R，保 存上述輸出之反相同步信號* Μ及可在其非反相輸出端子 ,蠄出上述除得1/2之同步信號a〇CK_2 ; —專或邏輯閘17 ，它可使該第三正反器17輸出經由其一端子所接收之同步 曼徹斯特碼S_MANCHESTER_2，與該第四正反器16所輸出經 由其另一端子所接收之同步時鐘信號CL0CK_2，進行專或 邏輯蓮算，以及可輪出一NRZ碼NRZ_2。 該容許度檢核單元200包含：一可緩衝儲存該時鐘信 號CL0CK_Rt缓衝器21;-第五正反器22,它可接收一來 自該第一正反器11之同步曼徹斯特碼S_MANCHESTER_1，以 及可依據該緩衝器21所輪出之時鐘信號CL0CK_R，順序使 該同步曼徹斯特碼S_MANCHESTER_1之位元值移位一個位元 ;一第六正反器23,它可接收該第五正反器22所移位之同 步受徹斯特碼S_MANCHESTER_1，以及可依據該緩衝器21所 繪出之時鐘信號CL0CK_R，順序使該同步曼徹斯待碼 S_MANCHESTER_1之位元值移位一個位元；一第七正反器24 ，它可接收該第六正反器23所移位之同步曼徹斯特碼 S_MANCHESTER_1，Μ及可依據該緩衝器21所輪出之時鐘信 號CL0CK_R，順序使該同步曼徹斯特碼S_MANCHESTER_1之 位元值移位一値位元；一 NAND-邏輯閘25,它可接收該等 第五正反器22、第六正反器23和第七正反器24所移位之位 元值，Μ及可偵测該位元值” 1, 1, Γ ;-可使該NAND-運輯 閘25之偵測信號反相之反相器26 ; — N0R-邐輯閘27 ,它可 (請先閱讀背面之注意事項再填寫本頁)• 1T printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 13 V. Description of the invention (10 A7 B7 The synchronous Manchester code is sampled at one of the rising edges of the clock signal CL0CK_R printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs; 16, it can be based on an inverted clock signal CL0CK_R, save the output of the inverted synchronization signal * Μ and its non-inverted output terminal, the above-mentioned divided by 1/2 of the synchronization signal a〇CK_2;-special OR logic gate 17, which enables the third flip-flop 17 to output the synchronized Manchester code S_MANCHESTER_2 received through one of its terminals, and the fourth flip-flop 16 to output the synchronized clock signal CL0CK_2 received through the other terminal , Perform special or logical lotus calculation, and can round out an NRZ code NRZ_2. The tolerance checking unit 200 includes: a buffer 21 that can buffer the clock signal CL0CK_Rt;-a fifth flip-flop 22, which can receive A synchronous Manchester code S_MANCHESTER_1 from the first flip-flop 11 and the clock signal CL0CK_R rounded off by the buffer 21 to sequentially place the synchronous Manchester code S_MANCHESTER_1 The value of the element is shifted by one bit; a sixth flip-flop 23, which can receive the shifted synchronization Chester code S_MANCHESTER_1 by the fifth flip-flop 22, and the clock drawn according to the buffer 21 The signal CL0CK_R sequentially shifts the bit value of the synchronous Manchester pending code S_MANCHESTER_1 by one bit; a seventh flip-flop 24, which can receive the synchronized Manchester code S_MANCHESTER_1 shifted by the sixth flip-flop 23, M and according to the clock signal CL0CK_R rounded by the buffer 21, sequentially shift the bit value of the synchronous Manchester code S_MANCHESTER_1 by one bit; a NAND-logic gate 25, which can receive the fifth positive and negative 22, the sixth flip-flop 23 and the seventh flip-flop 24 shifted bit value, M and the bit value can be detected "1, 1, Γ;-can make the NAND-operation gate 25 Inverter 26 with inverted detection signal; —N0R-Ziji Gate 27, it can (please read the notes on the back before filling this page)
、1T 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 14、 1T The size of this paper is in accordance with Chinese National Standard (CNS) Α4 specification (210X 297mm) 14
五、發明説明（U Α7 Β7 經濟部中央標準局員工消费合作社印製 接收該等在該第五正反器22、第六正反器23和第七正反器 24之非反相端子Q處移位之位元值，Μ及可偵測一位元值 ”0,0,0” ； 一 OR-邏輯閘28，它可經由其一端子接收上述被 該反相器26反相之偵測信號，並且可經由其另一端子接收 該N0R-邏輯閘27所輸出之偵測信號，以及可檢核該曼徹斯 特碼S_MANCHESTER_1之疑點的規格（容許度）；Μ及一第 八正反器29，它可依據該0R-邏輯閘28之輪出信號，在其 非反相蝓出端子，輪出該電壓Vcc，而做為一控制信號。 該多工器300包含：一第一多工器31，它可接收來自 該第一解碼單元100之專或邏輯閘13和17的NRZ碼NRZ_HD NRZ_2, Μ及可依據該容許度檢核單元200所輪出之一控制 信號，選擇轜出該NRZ碼；Μ及一第二多工器32,它可接 收來自該等第二和第四正反器12和16之同步信號CL0CK_1 和CL0CK_2，Μ及可依據該容許度檢核單元200所_出之一 控制信號，選擇輪出一同步信號。 該同步信號偵測單元400包含：一反相器41，它可使 該第二多工器32所輸出之同步時鐘信號反相；一第九正反 器42,它可依據一反相同步時鐘信號，順序將該第一多工 器31所輸出之NRZ碼NRZ_1的位元值移位一個位元；一第十 正反器43，它可接收上述依據該反相器41所反相之同步時 鐘信號而被該第九正反器42移位之NRZ碼NRZ_1，Μ及可將 該等位元值移位一値位元；一NAND-邏輯閘44,它可經由 其一端子接收上述被該第十正反器43移位之位元值，並且 可接收上述被該第九正反器42移位之位元值，Μ及可偵測 (請先閱請背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家橾隼（CNS ) Μ規格（210X297公釐） 15 經濟部中央樣準局員工消費合作社印製 Α7 Β7 五、發明説明（12) 一同步位元值；一反相器45，它可使該NAND-邏輯閘44之 輪出反相；以及一第十一正反器46,它可依據該反相器45 之繪出信號，輪出上述做爲一同步信號的電壓Vcc。 該第二解碼單元500包含：一霉閂裝置51，它可接收 該第一多工器31所輪出之NRZ碼，Μ及可依據該第十一正 反器46所輪出之同步信號Sync輪出一 NRZ資料；以及一電 閂裝置52,它可接收該第二多工器32所輪出之一同步信號 Sync，Μ及可依據該第十一正反器46所輪出之一同步信號 Sync，輸出一接收時鐘信號RX_CLK。 此外，有一載波感測信號（CRS)，通常會输入至除該 第六正反器23外之所有正反器的反相CDN端子和該第六正 反器23之反相SDN端子處，而該第六正反器23之反相CDN端 子則係施Μ電源電壓。 今將參考第4至7圖解釋一依本發明所製之曼徹斯特碼 解碼裝置的蓮作情形。 首先，如第5圖所示，當有一10 Mbps之非同步碼傳送 至其鑰入側時，該外加之反相CRS信號，將會由一低邏輯 位準改變至一高運輯位準，並且施加至除該第六正反器23 外之所有正反器的反相CDN端子和該第六正反器23之反相 SDN端子處，故所有正反器均將被致能。 雜而，該第一正反器11將會接收一 10'Mbps之非同步 曼徹斯特碼和一 20 Mhz時鏟信號CL0CK_R，並且在該20 Mhz時鏟信號CL0CK_R之一上昇緣處，取樣該非同步曼徹斯 特碼MANCHESTER_CODE，Μ及將輪出一同步曼徹斯特碼， 本紙張尺度適用中國國家梯準（CNS ) Α4規格（210Χ297公釐） 16 (請先閱讀背面之注意事項再填寫本頁) 訂 ^ 經濟部中央揉準局負工消费合作社印装 A7 B7 五、發明説明（13 ) 而該第二正反器12，將會使上述依據該20Mhz時鐘信號 CLOCK_R而反相之同步信號，保存至其一輸入端子D處，Μ 及將會輸出上述除得1/2之10 Mhz同步信號CL0CK_1。 繼而，該專或邏輯閘13,將會使該第一正反器11所輪 出經由其一端子所接收之同步曼徹斯特碼S_MANCHESTER_1 ，與該第二正反器12所输出經由其另一端子所接收之同步 時鐘信號CL0CK_1，進行專或邏輯蓮算，並且將偵測一NRZ 碼NRZ—1。 此外，該第三正反器15,將會接收一 10 Mbps非同步 曼撇斯持碼MANCHESTER_CODE，和一被該反柑器14反相之 20 Mhz時鐘信號CL0CK_R，Μ及將會在該20Mhz反相時鐘信 號CL0CK_R之一上昇緣處，取樣該同步曼徹斯特碼S_MANCH ESTER _2，並且輪出一同步曼徹斯特碼MANCHESTER_CODE ，而該第四正反器16,將會使上述依據一20Mhz反相時瘇 信號CL0CK_Ri反相之同步時鐘信號，保存至其一峨入端 子D，、並且輸出上述除得1/2之10 Mhz同步信號CL0CK_2。 所Μ，該專或邏輯閛17,將會使該第三正反器17所_ 出經由其一端子所接收之同步曼徹斯特碼S_MANCHESTER_2 ，與該第四正反器16所輸出經由其另一端子所接收之同步 時鐘信號CL0CK_2,進行專或酱緝蓮算，並且將會輪出一 NRZ碼 NRZ_2。 猶而，該該容許度檢核單元200之缓衝器21，將會緩 衝儲存該20Mhz時鐘信號CL0CK_R，以及該第五正反器22, 將會接收該緩衝器21所蝓出之20Mhz時鐘信號CL0CK_R，和 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） ----------------訂------飞 (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明説明（14 該第一正反器11所_出之同步曼徹斯特碼S_MANCHESTER_1 ，並且將會在該20 Mhz時鐘信號(^0(：!(_卩之一上昇移緣處 ，順序使該同步曼徹斯特碼S_MANCHESTER_1之位元值移位 —個位元，Μ及該第六正反器23,將會接收該第五正反器 22依據該缓衝器21所輸出之20Mhz時鐘信號CLOCK_R所移位 之同步曼徹斯特碼S_MANCHESTER_1，Μ及順序使該位元值 移位一個位元，而該第七正反器24,將會接收該第六正反 器23依據該缓衝器22所輪出之20 Mhz時鐘信號(^0(：1(_11而 移位之同步曼徹斯特碼5_>1纟卩(：肫5了£!1_1，Μ及將會順序使 該位元值移位一値位元。 繼而，該NAND-遛輯閘25,將會接收該等第五正反器 22、第六正反器23和第七正反器24所移位之同步曼徹斯特 碼S_MANCHESTER_1的位元值，以及可偵測該同步曼徹斯特 碼技離該疑點之容許度規格的位元值”1,1,1”，而該N0R-邏輯閘27,將會接收該等在該第五正反器22、第六正反器 23和第七正反器24之所移位之同步受徹斯特碼 S_MANCHESTER_1的位元值，Κ及可偵測該同步曼徹斯特碼 技離該疑點之容許度規格的位元值”0,0,0”。 亦卽，如第6和7圖所示，在一發生在該傳送非同步曼 徹斯特碼之位元格中央部分之移位超前或落後l〇ns發生的 情況下，由於該同步曼徹斯特碼S_MANCHESTER_1之位元值 ，在100 ns間可能是一高邏輯位準或一低邏輯位準之波形 ，該等”1, 1, Γ和”0,0,0”將會被偵测到，故該多工器 300之_出將會受到控制，以致該正確取樣之同步曼徹斯 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I----l·---装------訂------^ (請先閱讀背面之注意事項再填寫本頁) 18 i、發明説明（ 15 A7 B7 經濟部中央揉準局貝工消费合作社印裝 特碼將會被選到。 繼而，該OR-通輯閘28,將會經由其一端子接收上述 被該反相器26反相之偵測信號，並且可經由其另一端子接 收該NOR-邏輯閘27所輸出之偵測信號，Μ及將會檢核該曼 徹斯特之疑點確係技離該容許度規格， 並且將其轅出给該第八正反器29之時鐘信號端子，而該第 八正反器29，將會依據該OR-邏輯閘28之偵測信號，將該 電壓Vcc做為一控制信號，輸出給該多工器300之第一多工 器31和該第二多工器32之閃控端子S。 亦即，當該0R-邏輯閘28之輪出值係”1”時，該第八正 反器29將會在其非反相_出端子，輸出一高邏輯位準控制 信號，Μ致該曼徹斯特碼之位元值，可在一下降緣處被偵 測到，而在該0R-運輯閘28之輸出值係”0”之情況下，亦即 ，該同步曼徹斯特碼之疑點係正常，該第八正反器29將會 在其非反相輪出端子，輪出一低邏輯位準控制倍號，Μ致 該曼徹斯持碼之位元值，可以在一上昇緣處被偵測到。 所Μ，該多工器300之第一多工器31，將會經由其輸 入端子10,接收該專或S輯閘13所輸出之NRZ碼NRZ_1，Μ 及經由其輸入端子II，將會接收該專或邏輯閘17所_出之 NRZ碼NRZ_2, Κ及當繪入至該第八正反器29之閃控端子S 的控制信號係一低邏輯位準時，該第一多工器31將會輸出 上述在該20 Mhz接收時鐘信號CL0CK_R之上昇緣處所测得 之NRZ碼NRZ_h 而當上述輪入至其閃控端子S之控制倍號 係一高邏輯位準時，該多工器31將會輪出上述在該20 Mhz (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家揉準（CNS ) Μ規格（210X297公釐） 19 經濟部中央揉準局貞工消費合作社印装 294373 Α7 Β7 五、發明説明（16 ) 接收時鐘佶號CLOCK_R之下降緣處所測得之NRZ碼NRZ_2 。 此外，該第二多工器32,將會經由其输入端子10,接 收該第二正反器12所_出之之10 Mhz同步信號CL0CK_h 以及經由其輪入端子II，接收該第四正反器16所输出之之 10 Mhz同步信號CLOCK_2,以及當上述輸入至其閃控端子S 之控制信號係一低邏輯位準時，該第二多工器32將會蝓出 該同步信號CL0CK_1，而當上述蝓入至其閃控端子S之控制 信號係一高通辑位準時，該多工器32將會轅出該同步信號 CL0CK_2 〇 首先，當上述輪入至其閃控端子S之控制信號係一高 邐輯位準時，該同步信號偵测單元400之第九正反器42， 將會經由其蠄入端子D，接收該第一多工器31所輪出之NRZ 碼NRZ_2， Μ及接收該第二多工器32所輸出而經由該反相 器41和其時鐘信號端子之同步信號CL0CK_2，並且將會依 據該同步時鐘信號CL0CK_2，順序將該NRZ碼NRZ_2的位元 值移位一個位元值，而該第十正反器43,則會接收上述被 該第九正反器42移位之同步時鐘信號CL0CK_2， Μ及將會 依據該反相同步信號CL0CK_2，順序將該NRZ碼NRZ_1之位 元值移位一個位元。 缈而，該NAND-邐輯閘44,將會經由其一端子接收該 第九正反器42所輪出之NRZ碼NRZ_2的位元值，以及將會經 * * . · 由其另一端子接收該第十正反器43所輪出之NRZ碼NRZ_2 的位元值，並且在偵測到該同步位元值”1,Γ時，輸出該 低邏輯位準同步位元位準信號。 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） 20 (請先閲讀背面之注意事項再填寫本頁) 訂 A7 B7 經濟部中央標隼局負工消費合作社印製 五、發明説明（17 ) 繼而，該低邏輯位準同步位元位準信號，將會被反相 器45反相，並且_出至該第十一正反器46之時鐘信號端子 ，而該第十一正反器46將會受到該反相器45之綸出的時鐘 控制，在其非反相輓出端子輪出該電壓Vcc，並且做為一 同步信號Sync，施加至該第二解碼單元500之輪入端子D處 〇 所Μ，該第二解碼箪元500之電閂裝置51，將會依據 該第十一正反器46所輸出之一高邏輯位準同步信號Sync， 輓出該第一多工器31所轅出之NRZ碼NRZ_2,並且將會計算 該NRZ資料NRZ DATA，而該電閂装置52,將會依據該第十 一正反器46所輪出之一高邏辑位準同步信號Sync，輪出該 第二多工器32所输出之同步信號CL0CK_2，並且計算該接 收時鐘信號RX_CLK，以致該等NRZ資料NRZ DATA與条统所 需之同步時鐘信號RX_CLK，得以自一LAN控制單元（未示 出）輓出。 同時，當上述輪入至該閃控端子S之控制信號係一低 邏輯位準時，該同步信號偵测單元4〇〇之第九正反器42， 將會經由其一輸入端子D，接收該第一多工器31所輪出之 NRZ碼NRZ_1，Μ及將會經由其時鐘端子，接收該第二多工 器32所鑰出而通過該反相器41之同步時鐘信號，並且將會 顒序接收該第九正反器42所移位之NRZ碼NRZ_1，Μ及依據 一反相同步時鐘信號CLOCK_l，使該NRZ碼NRZ_1之位元值 移位一値位元。 趙而，該NAND-邏輯閘44,將會經由其一端子接收該 ^-訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4規格（21〇χ297公瘦） f A7 B7 五、發明説明（ 18 經濟部中央橾準局負工消費合作社印装 第九正反器42所輪出之NRZ碼NRZ_1的位元值，以及經由其 另一端子接收該第十正反器43所輸出之NRZ碼NRZ_1的位元 值，而當上述測得之同步位元值係” 1, 1 ”時，該NAND-邏輯 閛44將會輪出一低邏輯位準信號。 此外，該反相器45將會使一低邏輯位準信號反相成一 高邏辑位準信號，並且輸入至該第十一正反器46之時鐘端 子，Μ及該第十一正反器46將會依據該反相器45所輸出之 一高邏輯位準信號，將詼電壓Vcc鍮出給該第二解碼單元 500，而做為一同步位準偵测信號。 所Μ，該第二解碼單元500之霣閂裝置51，將會接收 該第一多工器31所_出之NRZ碼NRZ_1，Μ及依據該第十一 正反器46所輪出之一高邏輯位準同步信號Sync， _出該 NRZ碼NR2_1，並且計算該NRZ資料NRZ DATA，而該電閂裝 置52將會依據該電閂器52所輪出之一高通輯位準同步信號 Sync，輪出該第二多工器32所輪出之同步時鐘信號CL0CK_1 ，以及計算該同步接收時鐘信號RX_CLK，而該等NRZ資料 NRZ DATA與条统所需之同步時鐘信號RX_CLK，將會自一 LAN控制單元（未示出）輪出。 誠如上文所述，此種曼徹斯特碼解碼装置，可不使用 鎖相迺路（PLL)，僅藉由一較簡單該電路結構，便足Μ 將該等NRZ資料和同步接收時鐘信號解碼，而解決其製造 程序困難及使用延遲單元所致晶片尺寸之增加等缺點，並挤 且可偵測該LAN控制器所需之同步信號。 雖然為例示計，已揭示了本發明之較佳實施例，本技 (請先閱讀背面之注意事項再填寫本頁) 装· 訂 泉 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 22 〇〇 - 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（19 ) 藝之專業人員將可理解，在不違離所附申請專利範圍所說 明本發明之精神與範圍下，將可有各種變更形式、附加裝 置、與代替品。 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁)5. Description of the invention (U Α7 Β7 Printed and received by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs at the non-inverting terminal Q of the fifth flip-flop 22, sixth flip-flop 23 and seventh flip-flop 24 The shifted bit value, M and the detectable bit value "0,0,0"; an OR-logic gate 28, which can receive the detection detected by the inverter 26 through its one terminal Signal, and can receive the detection signal output by the NOR-logic gate 27 through the other terminal, and can check the specification (allowance) of the suspect point of the Manchester code S_MANCHESTER_1; M and an eighth flip-flop 29, It can be used as a control signal according to the round-off signal of the OR-logic gate 28 at its non-inverted slug output terminal. The multiplexer 300 includes: a first multiplexer 31 , It can receive the NRZ codes NRZ_HD NRZ_2, M from the exclusive OR gates 13 and 17 of the first decoding unit 100, and can select one of the NRZ codes according to a control signal rounded by the tolerance checking unit 200 ; M and a second multiplexer 32, which can receive the synchronization signal CL0 from the second and fourth flip-flops 12 and 16 CK_1 and CL0CK_2, M and can select a synchronization signal in turn according to a control signal from the tolerance checking unit 200. The synchronization signal detection unit 400 includes: an inverter 41, which enables the first The synchronous clock signal output by the two multiplexers 32 is inverted; a ninth flip-flop 42 can sequentially sequence the bits of the NRZ code NRZ_1 output by the first multiplexer 31 according to an inverted synchronous clock signal The value is shifted by one bit; a tenth flip-flop 43, which can receive the NRZ codes NRZ_1, M and NRZ_1 shifted by the ninth flip-flop 42 according to the synchronous clock signal inverted by the inverter 41 The equal bit value can be shifted by one bit; a NAND-logic gate 44, which can receive the bit value shifted by the tenth flip-flop 43 through one of its terminals, and can receive the above-mentioned bit value The shifted bit value of the ninth flip-flop 42, Μ and detectable (please read the notes on the back before filling this page). The size of the paper is applicable to the Chinese National Falcon (CNS) Μ specification (210X297 mm ) 15 Printed Α7 Β7 by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economy V. Description of the invention (12) One synchronization bit Value; an inverter 45, which can invert the round of the NAND-logic gate 44; and an eleventh flip-flop 46, which can round out the above actions based on the drawn signal of the inverter 45 It is a synchronous signal voltage Vcc. The second decoding unit 500 includes: a mold latch device 51, which can receive the NRZ code rounded by the first multiplexer 31, M and can be based on the eleventh flip-flop The Sync signal Sync in 46 rounds out a NRZ data; and an electric latch device 52, which can receive a Sync signal Sync in round out of the second multiplexer 32, M and can be based on the eleventh positive and negative A synchronizing signal Sync, which is output by the receiver 46, outputs a receiving clock signal RX_CLK. In addition, a carrier sense signal (CRS) is usually input to the inverting CDN terminal of all flip-flops except the sixth flip-flop 23 and the inverting SDN terminal of the sixth flip-flop 23, and The inverse CDN terminal of the sixth flip-flop 23 is applied with a power supply voltage. Now, a lot of operations of the Manchester code decoding apparatus according to the present invention will be explained with reference to FIGS. 4 to 7. First, as shown in Figure 5, when a 10 Mbps asynchronous code is sent to the key input side, the applied inverted CRS signal will change from a low logic level to a high logic level. And it is applied to the inverting CDN terminal of all flip-flops except the sixth flip-flop 23 and the inverting SDN terminal of the sixth flip-flop 23, so all flip-flops will be enabled. In other words, the first flip-flop 11 will receive a 10'Mbps asynchronous Manchester code and a 20 Mhz time shovel signal CL0CK_R, and sample the asynchronous Manchester at the rising edge of the 20 Mhz time shovel signal CL0CK_R. The code MANCHESTER_CODE, Μ and a synchronous Manchester code will be issued in turn. This paper standard is applicable to China National Standards (CNS) Α4 specification (210Χ297mm) 16 (Please read the precautions on the back before filling this page) Order ^ Central Ministry of Economic Affairs A7 B7 printed by the Ministry of Industry and Consumers Cooperative Association 5. Description of the invention (13) The second flip-flop 12 will save the above synchronization signal inverted according to the 20Mhz clock signal CLOCK_R to one of its input terminals At D, M and will output the above-mentioned divided 10 Mhz sync signal CL0CK_1. Then, the exclusive OR logic gate 13 will cause the first flip-flop 11 to cycle through the synchronous Manchester code S_MANCHESTER_1 received through one of its terminals, and the second flip-flop 12 output through its other terminal. The received synchronous clock signal CL0CK_1 performs exclusive or logical calculation, and will detect an NRZ code NRZ-1. In addition, the third flip-flop 15 will receive a 10 Mbps asynchronous synchronous MANCHESTER_CODE, and a 20 Mhz clock signal CL0CK_R inverted by the flip-flop 14 and M will be inverted at the 20 Mhz At the rising edge of one of the phase clock signals CL0CK_R, the synchronous Manchester code S_MANCH ESTER _2 is sampled, and a synchronous Manchester code MANCHESTER_CODE is wheeled out, and the fourth flip-flop 16 will make the above-mentioned clock signal CL0CK_Ri based on a 20Mhz inverted phase The inverted synchronous clock signal is saved to one of its input terminals D, and outputs the above-mentioned divided 10 Mhz synchronous signal CL0CK_2. Therefore, the exclusive or logical device 17 will cause the third flip-flop 17 to output the synchronous Manchester code S_MANCHESTER_2 received via one of its terminals, and the fourth flip-flop 16 to output via its other terminal The received synchronous clock signal CL0CK_2 will be counted as a special or sauce, and a NRZ code NRZ_2 will be output. Instead, the buffer 21 of the tolerance checking unit 200 will buffer and store the 20Mhz clock signal CL0CK_R, and the fifth flip-flop 22, will receive the 20Mhz clock signal from the buffer 21 CL0CK_R, and the size of this paper is applicable to China National Standard Falcon (CNS) A4 specification (210X297mm) ---------------- Order ------ Fly (please read the back first Note to fill out this page) A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (14 The first positive and negative converter 11_ Synchronous Manchester code S_MANCHESTER_1 out of the 11th, and will be in the 20 Mhz The clock signal (^ 0 (:! (_ I at one of the rising shift edges sequentially shifts the bit value of the synchronized Manchester code S_MANCHESTER_1—one bit, M and the sixth flip-flop 23, will receive the The fifth flip-flop 22 shifts the bit value by one bit according to the synchronized Manchester code S_MANCHESTER_1, M shifted by the 20 Mhz clock signal CLOCK_R output from the buffer 21, and the seventh flip-flop 24 , It will receive the 20 Mhz clock signal (^ 0 (: 1 (_11 and Synchronized Manchester code for shifting 5_ > 1 獟 卩 (: 肫 5 了 £! 1_1, Μ and will sequentially shift the bit value by one bit. Then, the NAND-walk gate 25, will receive The bit value of the synchronized Manchester code S_MANCHESTER_1 shifted by the fifth flip-flop 22, the sixth flip-flop 23 and the seventh flip-flop 24, and the tolerance for detecting that the synchronized Manchester code deviates from the suspect point The bit value of the specification is "1,1,1", and the NOR-logic gate 27 will receive the location of the fifth flip-flop 22, sixth flip-flop 23 and seventh flip-flop 24 The synchronization of the shift is affected by the bit value of the Manchester code S_MANCHESTER_1, K and the bit value "0,0,0" which can detect the tolerance specification of the synchronized Manchester code from the suspect point. Also, such as the 6th As shown in Fig. 7, in a situation where the shift in the central part of the bit grid of the transmitted asynchronous Manchester code is ahead or behind by 10 ns, the bit value of the synchronous Manchester code S_MANCHESTER_1 is 100 ns. The waveform may be a high logic level or a low logic level. These "1, 1, Γ and" 0,0,0 "will be detected, so The output of the multiplexer 300 will be controlled so that the correctly sampled synchronous Manchester paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) I ---- l · --- ------ Subscribe ------ ^ (Please read the precautions on the back before filling out this page) 18 i. Description of the invention (15 A7 B7 Special code printed by Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs Will be selected. Then, the OR-gate gate 28 will receive the detection signal inverted by the inverter 26 through one terminal, and may receive the detection output from the NOR-logic gate 27 through the other terminal. Signal, Μ and will check that Manchester ’s suspicion is indeed within the tolerance specification, and output it to the clock signal terminal of the eighth flip-flop 29, and the eighth flip-flop 29, will According to the detection signal of the OR-logic gate 28, the voltage Vcc is used as a control signal and output to the first multiplexer 31 of the multiplexer 300 and the flash control terminal S of the second multiplexer 32. That is, when the round-off value of the OR gate 28 is "1", the eighth flip-flop 29 will output a high logic level control signal at its non-inverting_out terminal. The bit value of the Manchester code can be detected at a falling edge, and in the case where the output value of the OR gate 28 is "0", that is, the suspected point of the synchronized Manchester code is normal, The eighth flip-flop 29 will output a low logic level control multiple at its non-inverted round-out terminal, so that the bit value of the Manchester code can be detected at a rising edge Measured. Therefore, the first multiplexer 31 of the multiplexer 300 will receive the NRZ code NRZ_1 output by the dedicated or S series gate 13 via its input terminal 10, and M and its input terminal II will receive When the NRZ code NRZ_2, K from the dedicated OR logic gate 17 and the control signal drawn to the flash terminal S of the eighth flip-flop 29 are at a low logic level, the first multiplexer 31 will The NRZ code NRZ_h measured at the rising edge of the 20 Mhz received clock signal CL0CK_R will be output. When the control multiple number rounded to its flash terminal S is a high logic level, the multiplexer 31 will Round out the above at 20 Mhz (please read the precautions on the back before filling out this page). The paper size is applicable to China National Standard (CNS) Μ Specification (210X297mm). Printed 294373 Α7 Β7 V. Description of the invention (16) NRZ code NRZ_2 measured at the falling edge of the received clock number CLOCK_R. In addition, the second multiplexer 32 will receive the 10 Mhz synchronization signal CL0CK_h from the second flip-flop 12 through its input terminal 10 and the fourth forward and reverse through its in-cycle terminal II The 10 Mhz synchronization signal CLOCK_2 output by the multiplier 16, and when the control signal input to the flash control terminal S is a low logic level, the second multiplexer 32 will output the synchronization signal CL0CK_1, and when When the control signal input to the flash terminal S is a high-pass level, the multiplexer 32 will output the synchronization signal CL0CK_2. First, when the control signal input to the flash terminal S is a At the high level, the ninth flip-flop 42 of the synchronizing signal detection unit 400 will receive the NRZ code NRZ_2, Μ, and the received NRZ code from the first multiplexer 31 via its input terminal D The synchronization signal CL0CK_2 output by the second multiplexer 32 via the inverter 41 and its clock signal terminal, and will sequentially shift the bit value of the NRZ code NRZ_2 by one bit according to the synchronization clock signal CL0CK_2 Value, and the tenth flip-flop 43, will receive the above Nine flip-flop shift of the synchronous clock signal 42 CL0CK_2, Μ and will according to the inverted sync signal CL0CK_2, the order of the bit cell values of the NRZ code is shifted by one bit NRZ_1. Then, the NAND-gate gate 44 will receive the bit value of the NRZ code NRZ_2 from the ninth flip-flop 42 through one of its terminals, and it will pass * *. Receiving the bit value of the NRZ code NRZ_2 from the tenth flip-flop 43, and outputting the low logic level synchronization bit level signal when the synchronization bit value "1, Γ is detected. The paper scale adopts the Chinese National Standard (CNS) A4 specification (210X297mm) 20 (Please read the notes on the back before filling out this page) Order A7 B7 Printed by the Central Standard Falcon Bureau of the Ministry of Economic Affairs, the Consumer Labor Cooperative. (17) Then, the low logic level synchronization bit level signal will be inverted by the inverter 45 and output to the clock signal terminal of the eleventh flip-flop 46, and the eleventh positive The inverter 46 will be controlled by the clock of the inverter 45, and the voltage Vcc will be wheeled out at its non-inverted pull-out terminal, and used as a synchronization signal Sync, applied to the wheel of the second decoding unit 500 At the terminal D, the electric latch device 51 of the second decoding element 500 will be based on the eleventh flip-flop 46 A high logic level synchronization signal Sync is output to pull out the NRZ code NRZ_2 from the first multiplexer 31, and the NRZ data NRZ DATA will be calculated, and the electric latch device 52 will be based on the first A high logic level synchronization signal Sync is output by the eleven flip-flop 46, the synchronization signal CL0CK_2 output by the second multiplexer 32 is output, and the received clock signal RX_CLK is calculated so that the NRZ data NRZ The synchronization clock signal RX_CLK required for DATA and the system can be pulled out from a LAN control unit (not shown). At the same time, when the control signal rounded to the flash terminal S is a low logic level, the synchronization The ninth flip-flop 42 of the signal detection unit 400 will receive the NRZ code NRZ_1, M and NRZ coded by the first multiplexer 31 through its input terminal D and will receive through its clock terminal The second multiplexer 32 sends out the synchronous clock signal through the inverter 41, and will receive the NRZ code NRZ_1, M shifted by the ninth flip-flop 42 in sequence and according to an inverse synchronization The clock signal CLOCK_l shifts the bit value of the NRZ code NRZ_1 by one bit. Zhao Er, the NAND-logic gate 44 will receive the ^ -order through one of its terminals (please read the precautions on the back before filling in this page). This paper standard uses the Chinese National Standard (CNS) A4 specification (21〇 χ297 public thin) f A7 B7 V. Description of invention (18 The bit value of the NRZ code NRZ_1 from the ninth flip-flop 42 printed by the Negative Consumers Cooperative of the Ministry of Economic Affairs, Central Central Bureau of Preservation and Printing and its reception via the other terminal The bit value of the NRZ code NRZ_1 output by the tenth flip-flop 43, and when the measured sync bit value is "1, 1", the NAND-logic device 44 will round out a low logic bit Quasi-signal. In addition, the inverter 45 will invert a low logic level signal into a high logic level signal and input it to the clock terminal of the eleventh flip-flop 46, M and the eleventh flip-flop 46 will output the high voltage level Vcc to the second decoding unit 500 according to a high logic level signal output from the inverter 45 as a synchronous level detection signal. As a result, the latch device 51 of the second decoding unit 500 will receive the NRZ code NRZ_1 from the first multiplexer 31, and the height according to the eleventh flip-flop 46 Logic level synchronization signal Sync, the NRZ code NR2_1 is calculated, and the NRZ data NRZ DATA is calculated, and the electric latch device 52 will be based on a high-pass edited level synchronization signal Sync that the electric latch device 52 rotates. The synchronous clock signal CL0CK_1 output by the second multiplexer 32 and the synchronous received clock signal RX_CLK are calculated, and the NRZ data NRZ DATA and the synchronous clock signal RX_CLK required by the system will be controlled from a LAN The unit (not shown) came out. As mentioned above, this type of Manchester code decoding device can eliminate the use of phase-locked loop (PLL), and only a simpler circuit structure can fully resolve the NRZ data and synchronous reception clock signal. The manufacturing process is difficult and the increase in the size of the chip caused by the use of the delay unit, etc., and it can detect the synchronization signal required by the LAN controller. Although it is an illustrative example, the preferred embodiment of the present invention has been disclosed. This technique (please read the precautions on the back and then fill out this page). The size of the paper for spring printing is applicable to China National Standard (CNS) A4 (210X 297 Mm) 22 〇- A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (19) Art professionals will understand that the spirit of the invention described in the appended patent application is not violated Under the scope, there will be various modifications, additional devices, and alternatives. The paper size is applicable to China National Standard (CNS) A4 (210X297mm) (please read the precautions on the back before filling this page)
23 經濟部中央標準局貝工消费合作杜印製 A7 B7 五、發明説明（20 ) 元件檷號對照 10.. .缓衝器 32… .第二多工器 11.. .第一正反器 40... .第二正反器 12.. .第二正反器 41... .反相器 13.. .專或邏輯閘 42. · · .第九正反器 14.. .反相器 43... .第十正反器 15.. .第三正反器 44... .NAND-遍輯閭 16.. •第四正反器 45·.. .反相器 17.. .專或邏輯閘 46... .第十一正反器 20.. .延遲装置 50... .SR正反器 21.. .緩衝器 51··.. .電閂装置 22.. .第五正反器 52 .. ..電閂装置 23. _ •第六正反器 60 .. ..專或邏輯閘 24.. .第七正反器 70 .. ..延遲匹配緩衝器 25.. .NAND-邏輯閘 80 .. ..專或邏輯閘 26 · .反相器 100.. ..第一解碼單元 27.. ..N0R-邏輯閛 200.. ..容許度檢核單元 28.. ..0R-邏輯閘 300.. ..多工器 29.. ..第八正反器 400.. ..同步信號偵測單元 30.. ..第一正反器 500.. ..第二解碼單元 31.. ..第一多工器 (請先閲讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） 2423 A7 B7 printed by Beigong Consumer Cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (20) Comparison of element numbers 10. Buffer 32 ... Second multiplexer 11. First flip-flop 40 ... .. The second flip-flop 12 ... The second flip-flop 41. .. Inverter 13 ... Special OR logic gate 42 ... · The ninth flip-flop 14 ... Phaser 43 ... Tenth flip-flop 15 ... Third flip-flop 44 ... .NAND-Pass-up 16 .. • Fourth flip-flop 45 ... Inverter 17. . Special or logic gate 46 ... Eleventh flip-flop 20 ... Delay device 50 ... SR flip-flop 21 .... Buffer 51 ... Electric latch device 22. . Fifth flip-flop 52... Electric latch device 23. _ • Sixth flip-flop 60... Dedicated OR logic gate 24... 7th flip-flop 70... 25 .. NAND-logic gate 80 ... exclusive OR logic gate 26. Inverter 100 ... first decoding unit 27 ... N0R-logic gate 200 ... tolerance check Unit 28: ..0R-logic gate 300 ... multiplexer 29 ... eighth flip-flop 400 ... synchronization signal detection unit 30 ... first flip-flop 500 ... .. the second decoding unit 31. .. the first multiplexer ( Please read the precautions on the back before filling in this page) The size of this paper is applicable to China National Standard (CNS) A4 (210X297mm) 24