TW202420550A - Semiconductor packages having test pads - Google Patents

Abstract

A semiconductor package, includes:a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

Description

具有測試墊的半導體封裝Semiconductor package with test pad

[相關申請案的交叉參考][Cross reference to related applications]

本申請案主張2022年11月1日於韓國智慧財產局提出申請的韓國專利申請案第10-2022-0143844號的優先權及權益，所述韓國專利申請案的全部揭露內容併入本案供參考。This application claims priority to and benefits of Korean Patent Application No. 10-2022-0143844 filed on November 1, 2022 with the Korean Intellectual Property Office, and all disclosures of the Korean Patent Application are incorporated herein by reference.

本發明概念是有關於一種具有測試墊的半導體封裝。The present invention concept relates to a semiconductor package with a test pad.

隨著對高效能、高速及/或多功能半導體裝置的需求增大，半導體裝置的積體程度不斷提高。在製造具有與半導體裝置的高積體度的趨勢對應的精細圖案的半導體裝置時，需要實施具有精細寬度或精細分離距離的圖案。另外，需要安裝於半導體封裝中的半導體裝置高度積體化。As the demand for high-performance, high-speed and/or multifunctional semiconductor devices increases, the integration level of semiconductor devices continues to increase. When manufacturing semiconductor devices with fine patterns corresponding to the trend of high integration of semiconductor devices, it is necessary to implement patterns with fine widths or fine separation distances. In addition, semiconductor devices mounted in semiconductor packages need to be highly integrated.

本發明概念的態樣是提供一種具有微型化測試墊的半導體封裝。An aspect of the inventive concept is to provide a semiconductor package with a miniaturized test pad.

根據實例性實施例，一種半導體封裝可包括：基底晶片，具有前表面及與所述前表面相對的後表面，所述基底晶片包括設置於所述基底晶片的所述前表面上的凸塊墊、晶圓測試墊及封裝測試墊；連接結構，設置於所述基底晶片的所述前表面上且連接至所述凸塊墊；以及半導體晶片，堆疊於所述基底晶片的所述後表面上。所述晶圓測試墊中的每一者的尺寸可小於所述封裝測試墊。According to an exemplary embodiment, a semiconductor package may include: a base wafer having a front surface and a rear surface opposite to the front surface, the base wafer including a bump pad, a wafer test pad, and a package test pad disposed on the front surface of the base wafer; a connection structure disposed on the front surface of the base wafer and connected to the bump pad; and a semiconductor chip stacked on the rear surface of the base wafer. Each of the wafer test pads may be smaller in size than the package test pad.

根據實例性實施例，一種半導體封裝可包括：基底晶片，具有前表面及與所述前表面相對的後表面，所述基底晶片包括設置於所述基底晶片的所述前表面上的凸塊墊、晶圓測試墊及封裝測試墊；連接結構，設置於所述基底晶片的所述前表面上且連接至所述凸塊墊；以及半導體晶片，堆疊於所述基底晶片的所述後表面上且包括測試墊。所述晶圓測試墊中的每一者的尺寸可小於所述封裝測試墊且大於或等於所述測試墊。According to an exemplary embodiment, a semiconductor package may include: a base wafer having a front surface and a rear surface opposite to the front surface, the base wafer including a bump pad, a wafer test pad, and a package test pad disposed on the front surface of the base wafer; a connection structure disposed on the front surface of the base wafer and connected to the bump pad; and a semiconductor chip stacked on the rear surface of the base wafer and including a test pad. The size of each of the wafer test pads may be smaller than that of the package test pad and larger than or equal to that of the test pad.

根據實例性實施例，一種半導體封裝可包括：基底晶片，具有前表面及與所述前表面相對的後表面；半導體晶片，堆疊於所述基底晶片的所述後表面上；連接結構，設置於所述基底晶片的所述前表面上；以及模塑層，覆蓋所述基底晶片及所述半導體晶片。所述基底晶片可包括：基底主體；貫穿電極，穿透過所述基底主體；內部電路結構，設置於所述基底主體下方且包括內部互連件；以及基底背部結構，設置於所述基底主體上。所述內部電路結構可包括設置於所述前表面上的凸塊墊、電性連接至所述內部互連件中的至少一者的晶圓測試墊及電性連接至所述半導體晶片中的至少一者的封裝測試墊。所述晶圓測試墊中的每一者的尺寸可小於所述封裝測試墊。According to an exemplary embodiment, a semiconductor package may include: a base wafer having a front surface and a rear surface opposite to the front surface; a semiconductor chip stacked on the rear surface of the base wafer; a connection structure disposed on the front surface of the base wafer; and a molding layer covering the base wafer and the semiconductor chip. The base wafer may include: a base body; a through electrode penetrating through the base body; an internal circuit structure disposed below the base body and including internal interconnects; and a base back structure disposed on the base body. The internal circuit structure may include a bump pad disposed on the front surface, a wafer test pad electrically connected to at least one of the internal interconnects, and a package test pad electrically connected to at least one of the semiconductor chips. Each of the wafer test pads may be smaller in size than the package test pad.

在下文中，將參考以下附圖闡述本發明概念的較佳實例性實施例。相似的編號通篇皆指代相似的元件。Hereinafter, preferred exemplary embodiments of the present inventive concept will be described with reference to the following drawings. Like numbers refer to like elements throughout.

將理解，當一個元件被稱為「連接」或「耦合」至另一元件或者「位於」另一元件上時，所述一個元件可直接連接或耦合至所述另一元件或直接位於所述另一元件上，抑或可存在中間元件。相比之下，當元件被稱為「直接連接」或「直接耦合」至另一元件或被稱為「接觸（contacting）」另一元件或與另一元件「接觸（in contact with）」（或使用任何形式的詞語「接觸（contact）」）時，則在接觸點處不存在中間元件。It will be understood that when an element is referred to as being "connected" or "coupled" to another element or being "located on" another element, the element may be directly connected or coupled to or located directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or as being "contacting" or "in contact with" another element (or any form of the word "contact") is used), there are no intervening elements at the point of contact.

本文中在指代定向、佈局、位置、形狀、尺寸、量或其他量度時所使用的例如「相同」、「相等」、「平面」或「共面」等用語未必意指恰好完全相同的定向、佈局、位置、形狀、尺寸、量或其他量度，而是旨在囊括在可能例如由於製造製程出現的可接受變化內的幾乎完全相同的定向、佈局、位置、形狀、尺寸、量或其他量度。本文中可使用用語「實質上」來強調此含義，除非上下文或其他陳述另有指示。Terms such as "same", "equal", "planar", or "coplanar" used herein when referring to an orientation, layout, position, shape, size, amount, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other measurement, but are intended to encompass nearly exactly the same orientation, layout, position, shape, size, amount, or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize this meaning unless the context or other statements indicate otherwise.

圖1是根據實例性實施例的半導體封裝的剖視圖。FIG. 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖2是以分解方式說明圖1中所示的一些組件的剖視圖。FIG. 2 is a cross-sectional view illustrating some of the components shown in FIG. 1 in an exploded manner.

參考圖1及圖2，根據本揭露的實例性實施例的半導體封裝10可包括連接結構20、基底晶片100以及依序堆疊於基底晶片100上的第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500、以及模塑層M。半導體封裝10可經由連接結構20安裝於封裝基板12上。1 and 2 , a semiconductor package 10 according to an exemplary embodiment of the present disclosure may include a connection structure 20, a base chip 100, and a first semiconductor chip 200, a second semiconductor chip 300, a third semiconductor chip 400, and a fourth semiconductor chip 500 sequentially stacked on the base chip 100, and a molding layer 24. The semiconductor package 10 may be mounted on a package substrate 12 via the connection structure 20.

本揭露的半導體封裝10可以是高頻寬記憶體（high bandwidth memory，HBM）封裝。在實例性實施例中，基底晶片100可以是與第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500不同類型的半導體晶片。舉例而言，基底晶片100可以是邏輯晶片，且第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500可以是記憶體晶片。邏輯晶片可包括微處理器、類比裝置或數位訊號處理器。記憶體晶片可包括揮發性記憶體晶片，例如動態隨機存取記憶體（dynamic random access memory，DRAM）或靜態隨機存取記憶體（static random access memory，SRAM）；或非揮發性記憶體晶片，例如相變隨機存取記憶體（phase-change random access memory，PRAM）、磁阻式隨機存取記憶體（magnetoresistive random access memory，MRAM）、鐵電隨機存取記憶體（ferroelectric random access memory，FeRAM）或電阻式隨機存取記憶體（resistive random access memory，RRAM）。The semiconductor package 10 disclosed herein may be a high bandwidth memory (HBM) package. In an exemplary embodiment, the base chip 100 may be a semiconductor chip of a different type from the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500. For example, the base chip 100 may be a logic chip, and the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 may be memory chips. The logic chip may include a microprocessor, an analog device, or a digital signal processor. The memory chip may include a volatile memory chip, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM); or a non-volatile memory chip, such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

基底晶片100可經由連接結構20安裝於封裝基板12上。基底晶片100可包括基底主體105、貫穿電極110、內部電路結構120及基底後表面結構130。基底主體105可包含半導體材料，例如第IV族半導體、第III-V族化合物半導體或第II-VI族化合物半導體。貫穿電極110可在垂直方向上延伸，且可穿透過基底主體105。舉例而言，連接結構20中的每一者可以是焊料球或凸塊，且可由導電材料（例如金屬）形成。The base wafer 100 may be mounted on the package substrate 12 via the connection structure 20. The base wafer 100 may include a base body 105, a through electrode 110, an internal circuit structure 120, and a base rear surface structure 130. The base body 105 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The through electrode 110 may extend in a vertical direction and may penetrate through the base body 105. For example, each of the connection structures 20 may be a solder ball or a bump, and may be formed of a conductive material such as a metal.

內部電路結構120可設置於基底主體105下方，且可連接至連接結構20。內部電路結構120可包括內部互連件122、下部絕緣層124、凸塊墊BP、晶圓測試墊WTP及封裝測試墊PTP。內部互連件122可設置於多個層中，且貫穿電極110可電性連接至內部互連件122中的至少一者。另外，凸塊墊BP可連接至內部互連件122中的至少一者，且封裝測試墊PTP可電性連接至內部互連件122中的至少一者。The internal circuit structure 120 may be disposed below the substrate body 105 and may be connected to the connection structure 20. The internal circuit structure 120 may include an internal interconnect 122, a lower insulating layer 124, a bump pad BP, a wafer test pad WTP, and a package test pad PTP. The internal interconnect 122 may be disposed in a plurality of layers, and the through electrode 110 may be electrically connected to at least one of the internal interconnects 122. In addition, the bump pad BP may be connected to at least one of the internal interconnects 122, and the package test pad PTP may be electrically connected to at least one of the internal interconnects 122.

下部絕緣層124可覆蓋基底主體105的下表面及內部互連件122。下部絕緣層124亦可部分地覆蓋貫穿電極110的側表面。凸塊墊BP可暴露出，而非被下部絕緣層124完全覆蓋。凸塊墊BP可接觸連接結構20，且將連接結構20電性連接至內部互連件122中的至少一者。基底晶片100的上面設置有凸塊墊BP且面向封裝基板12的下表面可被稱為基底晶片100的前表面FS。The lower insulating layer 124 may cover the lower surface of the base body 105 and the internal interconnects 122. The lower insulating layer 124 may also partially cover the side surface of the through-electrode 110. The bump pad BP may be exposed, rather than being completely covered by the lower insulating layer 124. The bump pad BP may contact the connection structure 20 and electrically connect the connection structure 20 to at least one of the internal interconnects 122. The lower surface of the base wafer 100 on which the bump pad BP is disposed and which faces the package substrate 12 may be referred to as the front surface FS of the base wafer 100.

晶圓測試墊WTP可用於判斷內部電路結構120是否有缺陷，且可設置於基底晶片100的前表面FS上。晶圓測試墊WTP可隱埋於下部絕緣層124中，但可暴露出而非被下部絕緣層124完全覆蓋。在實例性實施例中，晶圓測試墊WTP的下表面可與基底晶片100的前表面FS共面。晶圓測試墊WTP可電性連接至內部互連件122中的至少一者。晶圓測試墊WTP可不接觸連接結構20。The wafer test pad WTP can be used to determine whether the internal circuit structure 120 is defective, and can be disposed on the front surface FS of the base wafer 100. The wafer test pad WTP can be buried in the lower insulating layer 124, but can be exposed rather than completely covered by the lower insulating layer 124. In an exemplary embodiment, the lower surface of the wafer test pad WTP can be coplanar with the front surface FS of the base wafer 100. The wafer test pad WTP can be electrically connected to at least one of the internal interconnects 122. The wafer test pad WTP may not contact the connection structure 20.

封裝測試墊PTP可用於判斷第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500是否有缺陷，且可設置於基底晶片100的前表面FS上。封裝測試墊PTP可隱埋於下部絕緣層124中，但可暴露出而非被下部絕緣層124完全覆蓋。在實例性實施例中，封裝測試墊PTP的下表面可與基底晶片100的前表面FS共面。封裝測試墊PTP可經由貫穿電極110中的至少一者電性連接至第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500中的至少一者。封裝測試墊PTP可不接觸連接結構20。The package test pad PTP can be used to determine whether the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 are defective, and can be disposed on the front surface FS of the base chip 100. The package test pad PTP can be buried in the lower insulating layer 124, but can be exposed instead of being completely covered by the lower insulating layer 124. In an exemplary embodiment, the lower surface of the package test pad PTP can be coplanar with the front surface FS of the base chip 100. The package test pad PTP can be electrically connected to at least one of the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 via at least one of the through electrodes 110. The package test pad PTP may not contact the connection structure 20.

根據本揭露的實例性實施例，晶圓測試墊WTP可被形成為小於封裝測試墊PTP。晶圓測試墊WTP及封裝測試墊PTP兩者皆可被形成為大於凸塊墊BP。另外，晶圓測試墊WTP可被設置成距基底晶片100的前表面FS的中心部分較封裝測試墊PTP更遠。作為另外一種選擇，晶圓測試墊WTP與基底晶片100的和晶圓測試墊WTP相鄰的側表面之間的距離可小於封裝測試墊PTP與基底晶片100的和封裝測試墊PTP相鄰的側表面之間的距離。According to an exemplary embodiment of the present disclosure, the wafer test pad WTP may be formed to be smaller than the package test pad PTP. Both the wafer test pad WTP and the package test pad PTP may be formed to be larger than the bump pad BP. In addition, the wafer test pad WTP may be disposed to be farther from the center portion of the front surface FS of the substrate chip 100 than the package test pad PTP. Alternatively, the distance between the wafer test pad WTP and the side surface of the substrate chip 100 adjacent to the wafer test pad WTP may be smaller than the distance between the package test pad PTP and the side surface of the substrate chip 100 adjacent to the package test pad PTP.

基底背部結構130可設置於基底主體105上。基底背部結構130可包括內部互連件132、上部絕緣層134、接合墊136及鈍化層138。內部互連件132可設置於貫穿電極110上且可電性連接至貫穿電極110。上部絕緣層134可覆蓋基底主體105的上表面及內部互連件132。上部絕緣層134亦可部分地覆蓋貫穿電極110的側表面。The substrate back structure 130 may be disposed on the substrate body 105. The substrate back structure 130 may include an internal interconnect 132, an upper insulating layer 134, a bonding pad 136, and a passivation layer 138. The internal interconnect 132 may be disposed on the through electrode 110 and may be electrically connected to the through electrode 110. The upper insulating layer 134 may cover the upper surface of the substrate body 105 and the internal interconnect 132. The upper insulating layer 134 may also partially cover the side surface of the through electrode 110.

接合墊136可設置於上部絕緣層134上且可經由內部互連件132電性連接至貫穿電極110。鈍化層138可覆蓋上部絕緣層134且可覆蓋接合墊136的側表面。接合墊136可不被鈍化層138完全覆蓋，且接合墊136的上表面可暴露出。在實例性實施例中，接合墊136的上表面可與鈍化層138的上表面共面。接合墊136可將貫穿電極110電性連接至第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500中的至少一者。基底晶片100的上面設置有接合墊136且面向第一半導體晶片200的上表面可被稱為基底晶片100的後表面BS。The bonding pad 136 may be disposed on the upper insulating layer 134 and may be electrically connected to the through electrode 110 via the internal interconnect 132. The passivation layer 138 may cover the upper insulating layer 134 and may cover the side surface of the bonding pad 136. The bonding pad 136 may not be completely covered by the passivation layer 138, and the upper surface of the bonding pad 136 may be exposed. In an exemplary embodiment, the upper surface of the bonding pad 136 may be coplanar with the upper surface of the passivation layer 138. The bonding pad 136 may electrically connect the through electrode 110 to at least one of the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500. An upper surface of the base wafer 100 on which the bonding pad 136 is disposed and which faces the first semiconductor wafer 200 may be referred to as a back surface BS of the base wafer 100 .

第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500可依序堆疊於基底晶片100的後表面BS上。進一步參考圖2，第一半導體晶片200可包括半導體主體205、貫穿電極210、內部電路結構220、上部絕緣層230、接合墊232及鈍化層234。半導體主體205可包含半導體材料，例如第IV族半導體、第III-V族化合物半導體或第II-VI族化合物半導體。貫穿電極210可在垂直方向上延伸且可穿透過半導體主體205。The first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400 and the fourth semiconductor chip 500 may be sequentially stacked on the back surface BS of the base chip 100. Further referring to FIG. 2, the first semiconductor chip 200 may include a semiconductor body 205, a through electrode 210, an internal circuit structure 220, an upper insulating layer 230, a bonding pad 232 and a passivation layer 234. The semiconductor body 205 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor or a Group II-VI compound semiconductor. The through electrode 210 may extend in a vertical direction and may penetrate through the semiconductor body 205.

內部電路結構220可設置於半導體主體205下方，且可連接至基底晶片100的基底後表面結構130。內部電路結構220可包括內部互連件222、下部絕緣層224、接合墊226、測試墊TP及鈍化層228。內部互連件222可設置於多個層中，且貫穿電極210可電性連接至內部互連件222中的至少一者。另外，接合墊226及測試墊TP可電性連接至內部互連件222中的至少一者。The internal circuit structure 220 may be disposed below the semiconductor body 205 and may be connected to the substrate rear surface structure 130 of the substrate wafer 100. The internal circuit structure 220 may include an internal interconnect 222, a lower insulating layer 224, a bonding pad 226, a test pad TP, and a passivation layer 228. The internal interconnect 222 may be disposed in a plurality of layers, and the through electrode 210 may be electrically connected to at least one of the internal interconnects 222. In addition, the bonding pad 226 and the test pad TP may be electrically connected to at least one of the internal interconnects 222.

下部絕緣層224可覆蓋半導體主體205的下表面及內部互連件222。下部絕緣層224亦可部分地覆蓋貫穿電極210的側表面。鈍化層228可設置於下部絕緣層224下方，且可覆蓋下部絕緣層224的下表面。接合墊226及測試墊TP可設置於下部絕緣層224下方，且可暴露出而不會被鈍化層228完全覆蓋。舉例而言，接合墊226的下表面及測試墊TP的下表面可與鈍化層228的下表面共面。第一半導體晶片200的接合墊226可接觸基底晶片100的接合墊136，且可將基底晶片100電性連接至內部互連件222中的至少一者。測試墊TP可接觸基底晶片100的鈍化層138，但可不電性連接至基底晶片100。測試墊TP可不接觸基底晶片100的接合墊136。The lower insulating layer 224 may cover the lower surface of the semiconductor body 205 and the internal interconnect 222. The lower insulating layer 224 may also partially cover the side surface of the through electrode 210. The passivation layer 228 may be disposed below the lower insulating layer 224 and may cover the lower surface of the lower insulating layer 224. The bonding pad 226 and the test pad TP may be disposed below the lower insulating layer 224 and may be exposed without being completely covered by the passivation layer 228. For example, the lower surface of the bonding pad 226 and the lower surface of the test pad TP may be coplanar with the lower surface of the passivation layer 228. The bonding pad 226 of the first semiconductor wafer 200 may contact the bonding pad 136 of the base wafer 100 and may electrically connect the base wafer 100 to at least one of the internal interconnects 222. The test pad TP may contact the passivation layer 138 of the base wafer 100 but may not be electrically connected to the base wafer 100. The test pad TP may not contact the bonding pad 136 of the base wafer 100.

上部絕緣層230、接合墊232及鈍化層234可設置於半導體主體205上。上部絕緣層230可覆蓋半導體主體205的上表面，且可部分地覆蓋貫穿電極210的側表面。接合墊232可設置於上部絕緣層230上且可電性連接至貫穿電極210。鈍化層234可覆蓋上部絕緣層230且可覆蓋接合墊232的側表面。接合墊232可不被鈍化層234完全覆蓋，且接合墊232的上表面可暴露出。舉例而言，接合墊232的上表面可與鈍化層234的上表面共面。The upper insulating layer 230, the bonding pad 232, and the passivation layer 234 may be disposed on the semiconductor body 205. The upper insulating layer 230 may cover the upper surface of the semiconductor body 205 and may partially cover the side surface of the through electrode 210. The bonding pad 232 may be disposed on the upper insulating layer 230 and may be electrically connected to the through electrode 210. The passivation layer 234 may cover the upper insulating layer 230 and may cover the side surface of the bonding pad 232. The bonding pad 232 may not be completely covered by the passivation layer 234, and the upper surface of the bonding pad 232 may be exposed. For example, the upper surface of the bonding pad 232 may be coplanar with the upper surface of the passivation layer 234 .

第二半導體晶片300及第三半導體晶片400可包括與第一半導體晶片200的組件相同的組件。舉例而言，第二半導體晶片300及第三半導體晶片400中的每一者可包括半導體主體305及405、分別穿透過半導體主體305及405的貫穿電極310及410、以及測試墊TP。半導體主體305及405可與半導體主體205完全相同，且貫穿電極310及410可與貫穿電極210完全相同。可省略對第二半導體晶片300及第三半導體晶片400的詳細說明。The second semiconductor chip 300 and the third semiconductor chip 400 may include the same components as those of the first semiconductor chip 200. For example, each of the second semiconductor chip 300 and the third semiconductor chip 400 may include semiconductor bodies 305 and 405, through electrodes 310 and 410 respectively penetrating the semiconductor bodies 305 and 405, and a test pad TP. The semiconductor bodies 305 and 405 may be identical to the semiconductor body 205, and the through electrodes 310 and 410 may be identical to the through electrode 210. A detailed description of the second semiconductor chip 300 and the third semiconductor chip 400 may be omitted.

第四半導體晶片500可包括半導體主體505及設置於半導體主體505下方的內部電路結構520。第四半導體晶片500的半導體主體505可包含與第一半導體晶片200的半導體主體205相同的材料。內部電路結構520可包括內部互連件522、下部絕緣層524、接合墊526、測試墊TP及鈍化層528。第四半導體晶片500的內部電路結構520可具有與第一半導體晶片200的內部電路結構120的結構實質上相同的結構。第四半導體晶片500的接合墊526可接觸第三半導體晶片400的接合墊。第四半導體晶片500的測試墊TP可接觸第三半導體晶片400的鈍化層。第四半導體晶片500的測試墊TP可不接觸第三半導體晶片400的接合墊。The fourth semiconductor chip 500 may include a semiconductor body 505 and an internal circuit structure 520 disposed below the semiconductor body 505. The semiconductor body 505 of the fourth semiconductor chip 500 may include the same material as the semiconductor body 205 of the first semiconductor chip 200. The internal circuit structure 520 may include an internal interconnect 522, a lower insulating layer 524, a bonding pad 526, a test pad TP, and a passivation layer 528. The internal circuit structure 520 of the fourth semiconductor chip 500 may have a structure substantially the same as that of the internal circuit structure 120 of the first semiconductor chip 200. The bonding pad 526 of the fourth semiconductor chip 500 may contact the bonding pad of the third semiconductor chip 400. The test pad TP of the fourth semiconductor wafer 500 may contact the passivation layer of the third semiconductor wafer 400. The test pad TP of the fourth semiconductor wafer 500 may not contact the bonding pad of the third semiconductor wafer 400.

圖3是圖1中所說明的基底晶片的自下方觀察的平面圖。FIG. 3 is a plan view of the base wafer illustrated in FIG. 1 as viewed from below.

參考圖3，凸塊墊BP、晶圓測試墊WTP及封裝測試墊PTP設置於基底晶片100的前表面FS上。當在平面圖中觀察時，凸塊墊BP可具有圓形形狀，且晶圓測試墊WTP及封裝測試墊PTP可具有正方形或矩形形狀。然而，其實例性實施例並不僅限於此，且在一些實例性實施例中，晶圓測試墊WTP及封裝測試墊PTP可具有例如三角形、菱形、圓形等形狀或類似形狀。如上文所述，晶圓測試墊WTP及封裝測試墊PTP可大於凸塊墊BP，且晶圓測試墊WTP可小於封裝測試墊PTP。舉例而言，晶圓測試墊WTP的面積可小於封裝測試墊PTP的面積。舉例而言，晶圓測試墊WTP可具有：第一側表面WTPa，具有第一寬度W1a；及第二側表面WTPb，具有第二寬度W1b，其中第一寬度W1a可以是約40微米至約60微米，且第二寬度W1b可以是約100微米至約150微米。相鄰的晶圓測試墊WTP之間的距離D1可以是約10微米至約30微米。在此，相鄰的晶圓測試墊WTP之間的距離D1可指的是相鄰的晶圓測試墊WTP的相對側之間的距離。封裝測試墊PTP可具有：第一側表面PTPa，具有第一寬度W2a；及第二側表面PTPb，具有第二寬度W2b，其中第一寬度W2a可以是約65微米至約100微米，且第二寬度W2b可以是約100微米至約150微米。相鄰的封裝測試墊PTP之間的距離D2可以是約30微米至約50微米。在此，相鄰的封裝測試墊PTP之間的距離D2可指的是相鄰的封裝測試墊PTP的相對側之間的距離。3 , the bump pad BP, the wafer test pad WTP, and the package test pad PTP are disposed on the front surface FS of the base wafer 100. When viewed in a plan view, the bump pad BP may have a circular shape, and the wafer test pad WTP and the package test pad PTP may have a square or rectangular shape. However, exemplary embodiments thereof are not limited thereto, and in some exemplary embodiments, the wafer test pad WTP and the package test pad PTP may have shapes such as a triangle, a rhombus, a circle, or the like, or similar shapes. As described above, the wafer test pad WTP and the package test pad PTP may be larger than the bump pad BP, and the wafer test pad WTP may be smaller than the package test pad PTP. For example, the area of the wafer test pad WTP may be smaller than the area of the package test pad PTP. For example, the wafer test pad WTP may have: a first side surface WTPa having a first width W1a; and a second side surface WTPb having a second width W1b, wherein the first width W1a may be about 40 microns to about 60 microns, and the second width W1b may be about 100 microns to about 150 microns. The distance D1 between adjacent wafer test pads WTP may be about 10 microns to about 30 microns. Here, the distance D1 between adjacent wafer test pads WTP may refer to the distance between opposite sides of adjacent wafer test pads WTP. The package test pad PTP may have: a first side surface PTPa having a first width W2a; and a second side surface PTPb having a second width W2b, wherein the first width W2a may be about 65 microns to about 100 microns, and the second width W2b may be about 100 microns to about 150 microns. The distance D2 between adjacent package test pads PTP may be about 30 microns to about 50 microns. Here, the distance D2 between adjacent package test pads PTP may refer to the distance between opposite sides of the adjacent package test pads PTP.

在實例性實施例中，晶圓測試墊WTP及封裝測試墊PTP可沿著基底晶片100的邊緣設置。舉例而言，基底晶片100可具有第一側表面101a、第二側表面101b、第三側表面101c及第四側表面101d，且晶圓測試墊WTP及封裝測試墊PTP可分別沿著第一側表面101a設置成一列。舉例而言，封裝測試墊PTP可與第一側表面101a相鄰地設置成一列，且晶圓測試墊WTP可在所述一列封裝測試墊PTP與第一側表面101a之間與第一側表面101a相鄰地設置成另一列。另外，封裝測試墊PTP可沿著第二側表面101b設置成一列且沿著第三側表面101c設置成一列。在實例性實施例中，晶圓測試墊WTP可被設置成距基底晶片100的前表面FS的中心部分較封裝測試墊PTP更遠。舉例而言，沿著第一側表面101a（或與第一側表面101a相鄰）的晶圓測試墊WTP中的每一者可被設置成較沿著第一側表面101a（或與第一側表面101a相鄰）的封裝測試墊PTP更靠近第一側表面101a。In an exemplary embodiment, the wafer test pad WTP and the package test pad PTP may be arranged along the edge of the base wafer 100. For example, the base wafer 100 may have a first side surface 101a, a second side surface 101b, a third side surface 101c, and a fourth side surface 101d, and the wafer test pad WTP and the package test pad PTP may be arranged in a row along the first side surface 101a, respectively. For example, the package test pad PTP may be arranged in a row adjacent to the first side surface 101a, and the wafer test pad WTP may be arranged in another row adjacent to the first side surface 101a between the row of package test pads PTP and the first side surface 101a. In addition, the package test pads PTP may be arranged in a row along the second side surface 101b and in a row along the third side surface 101c. In an exemplary embodiment, the wafer test pads WTP may be arranged farther from the center portion of the front surface FS of the substrate wafer 100 than the package test pads PTP. For example, each of the wafer test pads WTP along the first side surface 101a (or adjacent to the first side surface 101a) may be arranged closer to the first side surface 101a than the package test pads PTP along the first side surface 101a (or adjacent to the first side surface 101a).

根據本揭露的實例性實施例的晶圓測試墊WTP可被形成為小於封裝測試墊PTP，且如圖3中所說明，具有較小尺寸的晶圓測試墊WTP可被設置成較封裝測試墊PTP更靠近基底晶片100的側表面。因此，與晶圓測試墊WTP與封裝測試墊PTP被形成為具有相同尺寸的情形相比，基底晶片100的尺寸可減小，且半導體封裝10的尺寸可減小。另外，由於晶圓測試墊WTP的尺寸減小，因此設置測試墊WTP及PTP的空間效率得以增大，且可以各種方式設置測試墊WTP及PTP。圖3是說明晶圓測試墊WTP及封裝測試墊PTP的例示性佈局圖，但其實例性實施例並不僅限於此。在一些實例性實施例中，可具有各種設置結構。The wafer test pad WTP according to the exemplary embodiment of the present disclosure may be formed to be smaller than the package test pad PTP, and as illustrated in FIG3 , the wafer test pad WTP having a smaller size may be disposed closer to the side surface of the base wafer 100 than the package test pad PTP. Therefore, compared with a case where the wafer test pad WTP and the package test pad PTP are formed to have the same size, the size of the base wafer 100 may be reduced, and the size of the semiconductor package 10 may be reduced. In addition, since the size of the wafer test pad WTP is reduced, the space efficiency of disposing the test pad WTP and PTP is increased, and the test pad WTP and PTP may be disposed in various ways. Fig. 3 is an exemplary layout diagram illustrating a wafer test pad WTP and a package test pad PTP, but the exemplary embodiments are not limited thereto. In some exemplary embodiments, various configuration structures may be provided.

圖4A至圖4D是根據實例性實施例的基底晶片的自下方觀察的部分平面圖。圖4A至圖4D說明圖3的部分區。4A to 4D are partial plan views of a base wafer according to an exemplary embodiment as viewed from below. FIG. 4A to 4D illustrate a partial area of FIG.

參考圖4A，根據實例性實施例的基底晶片100a可包括交替設置的晶圓測試墊WTP與封裝測試墊PTP。舉例而言，晶圓測試墊WTP與封裝測試墊PTP可沿著基底晶片100的第二側表面101b交替地設置，且晶圓測試墊WTP與封裝測試墊PTP可沿著基底晶片100的第三側表面101c交替地設置。交替設置的晶圓測試墊WTP與封裝測試墊PTP之中的相鄰的晶圓測試墊WTP與封裝測試墊PTP之間的距離D3可等於距離D2。舉例而言，相鄰的晶圓測試墊WTP與封裝測試墊PTP之間的距離D3可以是30微米至50微米。4A , a substrate wafer 100a according to an exemplary embodiment may include wafer test pads WTP and package test pads PTP that are alternately disposed. For example, the wafer test pads WTP and package test pads PTP may be alternately disposed along the second side surface 101b of the substrate wafer 100, and the wafer test pads WTP and package test pads PTP may be alternately disposed along the third side surface 101c of the substrate wafer 100. A distance D3 between adjacent wafer test pads WTP and package test pads PTP among the alternately disposed wafer test pads WTP and package test pads PTP may be equal to the distance D2. For example, the distance D3 between adjacent wafer test pads WTP and package test pads PTP may be 30 μm to 50 μm.

如圖4A中所說明，與晶圓測試墊WTP與封裝測試墊PTP被形成為具有相同尺寸的情形相比，當晶圓測試墊WTP與封裝測試墊PTP交替地設置時，相同的空間中可設置有更多的測試墊WTP及PTP，且因此半導體封裝10的尺寸可減小。As illustrated in FIG. 4A , compared to a case where the wafer test pad WTP and the package test pad PTP are formed to have the same size, when the wafer test pad WTP and the package test pad PTP are alternately arranged, more test pads WTP and PTP can be arranged in the same space, and thus the size of the semiconductor package 10 can be reduced.

參考圖4B，根據實例性實施例的基底晶片100b可包括沿著基底晶片100的第二側表面101b及第三側表面101c設置的晶圓測試墊WTP。由於晶圓測試墊WTP的尺寸小於封裝測試墊PTP的尺寸，因此與封裝測試墊PTP沿著第二側表面101b及第三側表面101c設置的情形相比，半導體封裝10的尺寸可減小。4B , the base wafer 100b according to the exemplary embodiment may include a wafer test pad WTP disposed along the second side surface 101b and the third side surface 101c of the base wafer 100. Since the size of the wafer test pad WTP is smaller than the size of the package test pad PTP, the size of the semiconductor package 10 may be reduced compared to the case where the package test pad PTP is disposed along the second side surface 101b and the third side surface 101c.

參考圖4C，根據實例性實施例的基底晶片100c可包括設置於凸塊墊BP之間的封裝測試墊PTP。舉例而言，第二列封裝測試墊PTP可被設置成平行於第一側表面101a且設置於凸塊墊BP之間。4C, the substrate wafer 100c according to the exemplary embodiment may include a package test pad PTP disposed between the bump pads BP. For example, the second row of package test pads PTP may be disposed parallel to the first side surface 101a and disposed between the bump pads BP.

參考圖4D，根據實例性實施例的基底晶片100d可包括設置於凸塊墊BP之間的晶圓測試墊WTP及封裝測試墊PTP。晶圓測試墊WTP及封裝測試墊PTP可分別設置成一列。如圖4C及圖4D中所說明，可藉由將晶圓測試墊WTP或封裝測試墊PTP設置於凸塊墊BP之間來減小半導體封裝10的尺寸。Referring to FIG. 4D , the base wafer 100 d according to the exemplary embodiment may include a wafer test pad WTP and a package test pad PTP disposed between the bump pads BP. The wafer test pad WTP and the package test pad PTP may be disposed in a row, respectively. As illustrated in FIG. 4C and FIG. 4D , the size of the semiconductor package 10 may be reduced by disposing the wafer test pad WTP or the package test pad PTP between the bump pads BP.

圖5A及圖5B是說明根據實例性實施例的測試墊的示意性平面圖。5A and 5B are schematic plan views illustrating a test pad according to an exemplary embodiment.

圖5A及圖5B說明設置於基底晶片100的前表面FS上的晶圓測試墊WTP及封裝測試墊PTP及設置於第一半導體晶片200的下表面、第二半導體晶片300的下表面、第三半導體晶片400的下表面及第四半導體晶片500的下表面上的測試墊TP。5A and 5B illustrate a wafer test pad WTP and a package test pad PTP disposed on the front surface FS of the base chip 100 and a test pad TP disposed on the lower surface of the first semiconductor chip 200 , the lower surface of the second semiconductor chip 300 , the lower surface of the third semiconductor chip 400 , and the lower surface of the fourth semiconductor chip 500 .

參考圖5A，在實例性實施例中，晶圓測試墊WTP與測試墊TP可具有相同的尺寸。另外，如上文所述，本揭露的晶圓測試墊WTP可小於封裝測試墊PTP。舉例而言，晶圓測試墊WTP的第一寬度W1a可小於封裝測試墊PTP的第一寬度W2a及/或晶圓測試墊WTP的第二寬度W1b可小於封裝測試墊PTP的第二寬度W2b。5A , in an exemplary embodiment, the wafer test pad WTP and the test pad TP may have the same size. In addition, as described above, the wafer test pad WTP of the present disclosure may be smaller than the package test pad PTP. For example, the first width W1a of the wafer test pad WTP may be smaller than the first width W2a of the package test pad PTP and/or the second width W1b of the wafer test pad WTP may be smaller than the second width W2b of the package test pad PTP.

參考圖5B，在實例性實施例中，晶圓測試墊WTP可大於測試墊TP且小於封裝測試墊PTP。舉例而言，晶圓測試墊WTP的第一寬度W1a可大於測試墊TP的第一寬度Wa及/或晶圓測試墊WTP的第二寬度W1b可大於測試墊TP的第二寬度Wb。5B , in an exemplary embodiment, the wafer test pad WTP may be larger than the test pad TP and smaller than the package test pad PTP. For example, the first width W1a of the wafer test pad WTP may be larger than the first width Wa of the test pad TP and/or the second width W1b of the wafer test pad WTP may be larger than the second width Wb of the test pad TP.

圖6是說明製造根據實例性實施例的半導體封裝的方法的流程圖。FIG. 6 is a flow chart illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment.

圖7至圖14是說明根據實例性實施例的根據製程順序製造半導體封裝的方法的剖視圖。7 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to a process sequence according to an exemplary embodiment.

參考圖6至圖14，一種製造根據本揭露的實施例的半導體封裝10的方法可包括在基底晶圓104中形成貫穿電極110（步驟S100）；形成內部電路結構120（步驟S200）；形成連接結構20（步驟S400）；形成基底背部結構130（步驟S500）；堆疊半導體晶片（步驟S600）；形成模塑層M（步驟S700）；以及切割基底晶圓104（步驟S900）。另外，所述方法可更包括：形成內部電路結構120（步驟S200）；及然後對晶圓測試墊WTP執行測試（步驟S300）；以及形成模塑層M（步驟S700）；以及然後對封裝測試墊PTP執行測試（步驟S800）。6 to 14 , a method for manufacturing a semiconductor package 10 according to an embodiment of the present disclosure may include forming a through electrode 110 in a base wafer 104 (step S100); forming an internal circuit structure 120 (step S200); forming a connection structure 20 (step S400); forming a base back structure 130 (step S500); stacking semiconductor chips (step S600); forming a molding layer M (step S700); and cutting the base wafer 104 (step S900). In addition, the method may further include: forming the internal circuit structure 120 (step S200); and then performing a test on the wafer test pad WTP (step S300); and forming a molding layer M (step S700); and then performing a test on the package test pad PTP (step S800).

參考圖7，可提供基底晶圓104。基底晶圓104可包含半導體材料，例如第IV族半導體、第III-V族化合物半導體或第II-VI族化合物半導體。舉例而言，第IV族半導體可包括矽、鍺或矽鍺。此後，可在基底晶圓104中形成貫穿電極110（步驟S100）。形成貫穿電極110可包括：藉由蝕刻基底晶圓104的一個表面形成孔；形成覆蓋所述孔的內壁的絕緣材料；以及形成填充所述孔的導電材料。貫穿電極110可不完全穿透過基底晶圓104。7 , a base wafer 104 may be provided. The base wafer 104 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. Thereafter, a through electrode 110 may be formed in the base wafer 104 (step S100). Forming the through electrode 110 may include: forming a hole by etching a surface of the base wafer 104; forming an insulating material covering an inner wall of the hole; and forming a conductive material filling the hole. The through electrode 110 may not completely penetrate the base wafer 104.

參考圖8，可在圖7的所得結構上形成內部電路結構120（步驟S200）。舉例而言，可在基底晶圓104的所述一個表面上的多個層中形成電性連接至貫穿電極110的內部互連件122，且可形成下部絕緣層124以覆蓋貫穿電極110及內部互連件122。圖8說明基底晶圓104的上表面部分地凹陷，但其實例性實施例並不僅限於此。儘管未說明，但內部電路結構120可更包括電性連接至內部互連件122的電路元件，且所述電路元件包括例如電晶體等主動元件以及例如電阻器及電容器等被動元件。8 , an internal circuit structure 120 may be formed on the resulting structure of FIG. 7 (step S200). For example, an internal interconnect 122 electrically connected to the through electrode 110 may be formed in a plurality of layers on the one surface of the base wafer 104, and a lower insulating layer 124 may be formed to cover the through electrode 110 and the internal interconnect 122. FIG. 8 illustrates that the upper surface of the base wafer 104 is partially recessed, but exemplary embodiments thereof are not limited thereto. Although not illustrated, the internal circuit structure 120 may further include circuit elements electrically connected to the internal interconnect 122, and the circuit elements include active elements such as transistors and passive elements such as resistors and capacitors.

另外，可形成電性連接至內部互連件122的凸塊墊BP、晶圓測試墊WTP及封裝測試墊PTP。晶圓測試墊WTP可被形成為大於凸塊墊BP，且封裝測試墊PTP可被形成為大於晶圓測試墊WTP。下部絕緣層124可不會完全覆蓋凸塊墊BP、晶圓測試墊WTP及封裝測試墊PTP中的每一者，且至少可暴露出凸塊墊BP、晶圓測試墊WTP及封裝測試墊PTP中的每一者的上表面。凸塊墊BP可定位於與晶圓測試墊WTP及封裝測試墊PTP相同的水平高度處。In addition, a bump pad BP, a wafer test pad WTP, and a package test pad PTP electrically connected to the internal interconnect 122 may be formed. The wafer test pad WTP may be formed to be larger than the bump pad BP, and the package test pad PTP may be formed to be larger than the wafer test pad WTP. The lower insulating layer 124 may not completely cover each of the bump pad BP, the wafer test pad WTP, and the package test pad PTP, and may at least expose the upper surface of each of the bump pad BP, the wafer test pad WTP, and the package test pad PTP. The bump pad BP may be positioned at the same level as the wafer test pad WTP and the package test pad PTP.

凸塊墊BP中的至少一者可經由內部互連件122電性連接至貫穿電極110中的一者。晶圓測試墊WTP可電性連接至內部互連件122。封裝測試墊PTP中的每一者可經由內部互連件122電性連接至貫穿電極110中的一者。內部互連件122、凸塊墊BP、晶圓測試墊WTP及封裝測試墊PTP可包含導電材料，例如銅（Cu）、鋁（Al）或銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。下部絕緣層124可包含氧化矽、氮化矽、氮氧化矽或其組合。At least one of the bump pads BP may be electrically connected to one of the through electrodes 110 via the internal interconnect 122. The wafer test pad WTP may be electrically connected to the internal interconnect 122. Each of the package test pads PTP may be electrically connected to one of the through electrodes 110 via the internal interconnect 122. The internal interconnect 122, the bump pad BP, the wafer test pad WTP, and the package test pad PTP may include a conductive material such as copper (Cu), aluminum (Al) or silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The lower insulating layer 124 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

參考圖9，可對晶圓測試墊WTP執行測試（步驟S300）。可使用探針卡P1執行測試。由於晶圓測試墊WTP電性連接至內部電路結構120的內部互連件122，因此可藉由測試判斷內部電路結構120是否有缺陷。舉例而言，可藉由使探針卡P1的探針接腳PP與晶圓測試墊WTP接觸以量測內部互連件122的電性短路及洩漏電流來測試內部電路結構120。在實例性實施例中，可藉由使探針卡P1的多個探針接腳PP與多個晶圓測試墊WTP接觸以量測內部互連件122的電性短路及洩漏電流來測試內部電路結構120。Referring to FIG. 9 , the wafer test pad WTP may be tested (step S300). The test may be performed using a probe card P1. Since the wafer test pad WTP is electrically connected to the internal interconnect 122 of the internal circuit structure 120, it is possible to determine whether the internal circuit structure 120 is defective by testing. For example, the internal circuit structure 120 may be tested by contacting the probe pin PP of the probe card P1 with the wafer test pad WTP to measure the electrical short circuit and leakage current of the internal interconnect 122. In an exemplary embodiment, the internal circuit structure 120 may be tested by contacting the plurality of probe pins PP of the probe card P1 with the plurality of wafer test pads WTP to measure the electrical short circuit and leakage current of the internal interconnect 122 .

參考圖10，可在內部電路結構120上形成連接結構20（步驟S400）。連接結構20可被形成為接觸凸塊墊BP，且經由凸塊墊BP可電性連接至內部電路結構120或貫穿電極110。連接結構20可包含錫（Sn）或含有錫（Sn）的合金（Sn-Ag-Cu）。在一些實例性實施例中，在形成連接結構20之後，可進一步對晶圓測試墊WTP執行測試。所述測試可判斷在形成連接結構20的製程中內部電路結構120中是否出現缺陷。Referring to FIG. 10 , a connection structure 20 may be formed on the internal circuit structure 120 (step S400). The connection structure 20 may be formed to contact the bump pad BP, and may be electrically connected to the internal circuit structure 120 or the through-electrode 110 via the bump pad BP. The connection structure 20 may include tin (Sn) or an alloy (Sn-Ag-Cu) containing tin (Sn). In some exemplary embodiments, after the connection structure 20 is formed, a test may be further performed on the wafer test pad WTP. The test may determine whether a defect occurs in the internal circuit structure 120 during the process of forming the connection structure 20.

參考圖11，可藉由將圖10的所得結構倒置來形成基底背部結構130（步驟S500）。基底背部結構130可位於基底晶圓104的與內部電路結構120相對的一側上。形成基底背部結構130可包括研磨基底晶圓104以暴露出貫穿電極110。可形成連接至暴露的貫穿電極110的內部互連件132及覆蓋內部互連件132的上部絕緣層134，且可在上部絕緣層134上形成接合墊136及鈍化層138以形成基底後表面結構130。儘管圖11中說明基底晶圓104的一部分是凹陷的，但其實例性實施例並不僅限於此。Referring to FIG. 11 , a substrate back structure 130 may be formed by inverting the resulting structure of FIG. 10 (step S500). The substrate back structure 130 may be located on a side of the substrate wafer 104 opposite to the internal circuit structure 120. Forming the substrate back structure 130 may include grinding the substrate wafer 104 to expose the through-electrodes 110. An internal interconnect 132 connected to the exposed through-electrodes 110 and an upper insulating layer 134 covering the internal interconnect 132 may be formed, and a bonding pad 136 and a passivation layer 138 may be formed on the upper insulating layer 134 to form the substrate rear surface structure 130. Although FIG. 11 illustrates that a portion of the base wafer 104 is recessed, exemplary embodiments are not limited thereto.

內部互連件132可電性連接至貫穿電極110。上部絕緣層134可覆蓋基底晶圓104、貫穿電極110及內部互連件132。可在上部絕緣層134上形成接合墊136且所述接合墊136可電性連接至內部互連件132。可在上部絕緣層134上形成鈍化層138，且鈍化層138可保護上部絕緣層134。鈍化層138可不覆蓋接合墊136。The internal interconnect 132 may be electrically connected to the through electrode 110. The upper insulating layer 134 may cover the base wafer 104, the through electrode 110, and the internal interconnect 132. A bonding pad 136 may be formed on the upper insulating layer 134 and may be electrically connected to the internal interconnect 132. A passivation layer 138 may be formed on the upper insulating layer 134 and may protect the upper insulating layer 134. The passivation layer 138 may not cover the bonding pad 136.

內部互連件132及接合墊136可包含導電材料，例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。在實例性實施例中，接合墊136可包含銅（Cu）。上部絕緣層134可包含氧化矽、氮化矽、氮氧化矽或其組合，且鈍化層138可包含熱固性樹脂。The internal interconnect 132 and the bonding pad 136 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. In an exemplary embodiment, the bonding pad 136 may include copper (Cu). The upper insulating layer 134 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the passivation layer 138 may include a thermosetting resin.

參考圖12，可在基底後表面結構130上堆疊半導體晶片（步驟S600）。舉例而言，可在基底後表面結構130上堆疊第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500。基底背部結構130可接觸且耦合至第一半導體晶片200的內部電路結構220。舉例而言，基底後表面結構130的接合墊136中的每一者可接觸且耦合至第一半導體晶片200的接合墊226，且基底後表面結構130的鈍化層138可接觸且耦合至第一半導體晶片200的鈍化層228。基底背部結構130的接合墊136可經由第一半導體晶片200的接合墊226電性連接至貫穿電極210。12 , semiconductor chips may be stacked on the substrate rear surface structure 130 (step S600). For example, a first semiconductor chip 200, a second semiconductor chip 300, a third semiconductor chip 400, and a fourth semiconductor chip 500 may be stacked on the substrate rear surface structure 130. The substrate back structure 130 may contact and couple to the internal circuit structure 220 of the first semiconductor chip 200. For example, each of the bonding pads 136 of the substrate rear surface structure 130 may contact and couple to the bonding pad 226 of the first semiconductor chip 200, and the passivation layer 138 of the substrate rear surface structure 130 may contact and couple to the passivation layer 228 of the first semiconductor chip 200. The bonding pad 136 of the substrate back structure 130 may be electrically connected to the through electrode 210 via the bonding pad 226 of the first semiconductor chip 200 .

可在第一半導體晶片200上堆疊第二半導體晶片300。設置於第一半導體晶片200上方的每一接合墊232可接觸且耦合至設置於第二半導體晶片300下方的接合墊326。此後，可以相同的方式依序堆疊第三半導體晶片400及第四半導體晶片500。在本揭露的實例性實施例中，接合墊中的每一者被說明為彼此直接接觸，但其實例性實施例並不僅限於此。在一些實例性實施例中，可在接合墊中的每一者之間設置凸塊，且可使用覆蓋凸塊的側表面的黏合材料（例如，非導電膜（non-conductive film，NCF）或非導電膏（non-conductive paste，NCP））來堆疊第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500。The second semiconductor chip 300 may be stacked on the first semiconductor chip 200. Each bonding pad 232 disposed above the first semiconductor chip 200 may contact and be coupled to the bonding pad 326 disposed below the second semiconductor chip 300. Thereafter, the third semiconductor chip 400 and the fourth semiconductor chip 500 may be sequentially stacked in the same manner. In the exemplary embodiment of the present disclosure, each of the bonding pads is described as being in direct contact with each other, but the exemplary embodiment thereof is not limited thereto. In some exemplary embodiments, a bump may be provided between each of the bonding pads, and the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 may be stacked using an adhesive material (e.g., a non-conductive film (NCF) or a non-conductive paste (NCP)) covering the side surfaces of the bumps.

參考圖13，可形成模塑層M（步驟S700）。模塑層M可覆蓋基底後表面結構130的上表面及第一半導體晶片200的側表面、第二半導體晶片300的側表面、第三半導體晶片400的側表面及第四半導體晶片500的側表面。在實例性實施例中，在形成模塑層M以覆蓋第四半導體晶片500的上表面之後，可研磨模塑層M的上部部分，使得暴露出第四半導體晶片500的上表面。13 , a mold layer M may be formed (step S700). The mold layer M may cover the upper surface of the substrate rear surface structure 130 and the side surfaces of the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500. In an exemplary embodiment, after the mold layer M is formed to cover the upper surface of the fourth semiconductor chip 500, the upper portion of the mold layer M may be ground so that the upper surface of the fourth semiconductor chip 500 is exposed.

模塑層M可以是包括環氧樹脂或聚醯亞胺在內的樹脂。舉例而言，所述樹脂可以是雙酚基環氧樹脂、多環芳香族環氧樹脂、鄰甲酚酚醛清漆環氧樹脂、聯苯環氧樹脂或萘基族環氧樹脂。The molding layer M may be a resin including epoxy resin or polyimide. For example, the resin may be a bisphenol-based epoxy resin, a polycyclic aromatic epoxy resin, an o-cresol novolac epoxy resin, a biphenyl epoxy resin or a naphthyl epoxy resin.

參考圖14，可對封裝測試墊PTP執行測試（步驟S800）。可藉由使探針卡P2的探針接腳PP與封裝測試墊PTP接觸來執行所述測試。封裝測試墊PTP可經由內部電路結構120的貫穿電極110電性連接至第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500中的至少一者。因此，可藉由所述測試判斷第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500中的至少一者是否有缺陷。在實例性實施例中，可藉由使多個探針接腳PP接觸多個封裝測試墊PTP以藉由測試判斷第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500中的至少一者是否有缺陷來測試第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500。由於封裝測試墊PTP被形成為相對大於晶圓測試墊WTP，因此即使基底晶圓104在形成模塑層M的操作（步驟S700）中因熱量而在水平方向上收縮，封裝測試墊PTP仍可接觸探針接腳PP。因此，根據本揭露的實例性實施例，可防止探針接腳PP與封裝測試墊PTP之間出現接觸缺陷。Referring to FIG. 14 , a test may be performed on the package test pad PTP (step S800). The test may be performed by contacting the probe pin PP of the probe card P2 with the package test pad PTP. The package test pad PTP may be electrically connected to at least one of the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 via the through electrode 110 of the internal circuit structure 120. Therefore, it may be determined by the test whether at least one of the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 is defective. In an exemplary embodiment, the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 can be tested by making the plurality of probe pins PP contact the plurality of package test pads PTP to determine whether at least one of the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 is defective. Since the package test pad PTP is formed to be relatively larger than the wafer test pad WTP, even if the base wafer 104 shrinks in the horizontal direction due to heat in the operation of forming the mold layer M (step S700), the package test pad PTP can still contact the probe pins PP. Therefore, according to the exemplary embodiment of the present disclosure, the contact defect between the probe pin PP and the package test pad PTP can be prevented.

返回參考圖1，可繼續進行切割基底晶圓104的鋸切製程（步驟S900）。舉例而言，可切割基底晶圓104以及模塑層M，且可形成圖1中所說明的半導體封裝10。被切割並單體化的基底晶圓104可被稱為基底主體105，且基底主體105、貫穿電極110、內部電路結構120及基底背部結構130可形成基底晶片100。在一些實例性實施例中，在切割基底晶圓104之後，可進一步對封裝測試墊PTP執行測試。所述測試可判斷在鋸切製程中第一半導體晶片200、第二半導體晶片300、第三半導體晶片400及第四半導體晶片500中是否出現缺陷。可經由連接結構20將半導體封裝10安裝於封裝基板12上。Referring back to FIG. 1 , the sawing process of cutting the base wafer 104 may continue (step S900). For example, the base wafer 104 and the mold layer M may be cut, and the semiconductor package 10 illustrated in FIG. 1 may be formed. The cut and singulated base wafer 104 may be referred to as a base body 105, and the base body 105, the through-electrode 110, the internal circuit structure 120, and the base back structure 130 may form a base chip 100. In some exemplary embodiments, after cutting the base wafer 104, the package test pad PTP may be further tested. The test may determine whether defects occur in the first semiconductor chip 200, the second semiconductor chip 300, the third semiconductor chip 400, and the fourth semiconductor chip 500 during the sawing process. The semiconductor package 10 can be mounted on the package substrate 12 via the connection structure 20 .

如上文所陳述，根據本發明概念的實例性實施例，晶圓測試墊可被形成為小於封裝測試墊。As described above, according to exemplary embodiments of the inventive concept, a wafer test pad may be formed smaller than a package test pad.

因此，可防止測試墊與探針接腳之間出現接觸缺陷，且可提供微型化的半導體封裝。Therefore, contact defects between the test pad and the probe pin can be prevented, and a miniaturized semiconductor package can be provided.

雖然上文已示出且闡述實例性實施例，但對於熟習此項技術者而言將顯而易見的是，可做出修改及變化，而此並不背離隨附申請專利範圍所界定的本發明概念的範疇。While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

10:半導體封裝 12:封裝基板 20:連接結構 100、100a、100b、100c、100d:基底晶片 101a、PTPa、WTPa:第一側表面 101b、PTPb、WTPb:第二側表面 101c:第三側表面 101d:第四側表面 104:基底晶圓 105:基底主體 110、210、310、410:貫穿電極 120、220、520:內部電路結構 122、132、222:內部互連件 124、224、524:下部絕緣層 130:基底後表面結構/基底背部結構 134、230:上部絕緣層 136、226、232、526:接合墊 138、228、234、528:鈍化層 200:第一半導體晶片 205、305、405、505:半導體主體 300:第二半導體晶片 400:第三半導體晶片 500:第四半導體晶片 522:內部互連件 BP:凸塊墊 BS:後表面 D1、D2、D3:距離 FS:前表面 M:模塑層 P1、P2:探針卡 PP:探針接腳 PTP:封裝測試墊/測試墊 S100、S200、S300、S400、S500、S600、S700、S800、S900:步驟 TP:測試墊 W1a、W2a、Wa:第一寬度 W1b、W2b、Wb:第二寬度 WTP:晶圓測試墊/測試墊 10: semiconductor package 12: package substrate 20: connection structure 100, 100a, 100b, 100c, 100d: base wafer 101a, PTPa, WTPa: first side surface 101b, PTPb, WTPb: second side surface 101c: third side surface 101d: fourth side surface 104: base wafer 105: base body 110, 210, 310, 410: through electrode 120, 220, 520: internal circuit structure 122, 132, 222: internal interconnects 124, 224, 524: lower insulation layer 130: base rear surface structure/base back structure 134, 230: upper insulating layer 136, 226, 232, 526: bonding pad 138, 228, 234, 528: passivation layer 200: first semiconductor chip 205, 305, 405, 505: semiconductor body 300: second semiconductor chip 400: third semiconductor chip 500: fourth semiconductor chip 522: internal interconnect BP: bump pad BS: back surface D1, D2, D3: distance FS: front surface M: molding layer P1, P2: probe card PP: probe pin PTP: package test pad/test pad S100, S200, S300, S400, S500, S600, S700, S800, S900: Steps TP: Test pad W1a, W2a, Wa: First width W1b, W2b, Wb: Second width WTP: Wafer test pad/test pad

結合附圖閱讀以下詳細說明，將更清楚地理解本發明概念的以上及其他態樣、特徵及優點，在附圖中： 圖1是根據實例性實施例的半導體封裝的剖視圖。 圖2是以分解方式說明圖1中所說明的一些組件的剖視圖。 圖3是圖1中所示的基底晶片的自下方觀察的平面圖。 圖4A至圖4D是根據實例性實施例的基底晶片的部分放大圖。 圖5A及圖5B是說明根據實例性實施例的測試墊的示意性平面圖。 圖6是說明製造根據實例性實施例的半導體封裝的方法的流程圖。 圖7至圖14是說明根據實例性實施例的根據製程順序製造半導體封裝的方法的剖視圖。 The above and other aspects, features and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 2 is a cross-sectional view of some components illustrated in FIG. 1 in a decomposed manner. FIG. 3 is a plan view of the substrate wafer shown in FIG. 1 as viewed from below. FIGS. 4A to 4D are partially enlarged views of the substrate wafer according to an exemplary embodiment. FIGS. 5A and 5B are schematic plan views of a test pad according to an exemplary embodiment. FIG. 6 is a flow chart illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment. FIGS. 7 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to a process sequence according to an exemplary embodiment.

10:半導體封裝 10:Semiconductor packaging

12:封裝基板 12: Packaging substrate

20:連接結構 20: Connection structure

100:基底晶片 100: substrate wafer

105:基底主體 105: Base body

110:貫穿電極 110:Through-electrode

120:內部電路結構 120: Internal circuit structure

122:內部互連件 122: Internal interconnects

124:下部絕緣層 124: Lower insulating layer

130:基底後表面結構/基底背部結構 130: Back surface structure of substrate/back structure of substrate

132:內部互連件 132:Internal interconnects

134:上部絕緣層 134: Upper insulating layer

136:接合墊 136:Joint pad

138:鈍化層 138: Passivation layer

200:第一半導體晶片 200: First semiconductor chip

205:半導體主體 205:Semiconductor body

210:貫穿電極 210:Through-electrode

300:第二半導體晶片 300: Second semiconductor chip

305:半導體主體 305:Semiconductor body

310:貫穿電極 310:Through the electrode

400:第三半導體晶片 400: The third semiconductor chip

405:半導體主體 405:Semiconductor body

410:貫穿電極 410:Through-electrode

500:第四半導體晶片 500: Fourth semiconductor chip

505:半導體主體 505:Semiconductor body

BP:凸塊墊 BP: Bump pad

BS:後表面 BS: Back surface

FS:前表面 FS: front surface

M:模塑層 M: Molding layer

PTP:封裝測試墊/測試墊 PTP: Package test pad/test pad

TP:測試墊 TP: Test pad

WTP:晶圓測試墊/測試墊 WTP: Wafer test pad/test pad

Claims (20)

一種半導體封裝，包括： 基底晶片，具有前表面及與所述前表面相對的後表面，所述基底晶片包括設置於所述基底晶片的所述前表面上的凸塊墊、晶圓測試墊及封裝測試墊； 連接結構，設置於所述基底晶片的所述前表面上且連接至所述凸塊墊；以及 半導體晶片，堆疊於所述基底晶片的所述後表面上， 其中所述晶圓測試墊中的每一者的尺寸小於所述封裝測試墊。 A semiconductor package comprises: a base chip having a front surface and a rear surface opposite to the front surface, the base chip comprising a bump pad, a wafer test pad and a package test pad arranged on the front surface of the base chip; a connection structure arranged on the front surface of the base chip and connected to the bump pad; and a semiconductor chip stacked on the rear surface of the base chip, wherein the size of each of the wafer test pads is smaller than that of the package test pad. 如請求項1所述的半導體封裝，其中所述基底晶片包括： 基底主體； 貫穿電極，穿透過所述基底主體； 內部電路結構，設置於所述基底主體下方且包括內部互連件；以及 基底背部結構，設置於所述基底主體上。 A semiconductor package as described in claim 1, wherein the base chip includes: a base body; a through electrode penetrating the base body; an internal circuit structure disposed below the base body and including internal interconnects; and a base back structure disposed on the base body. 如請求項2所述的半導體封裝，其中所述晶圓測試墊電性連接至所述內部互連件中的至少一者，且所述封裝測試墊經由所述貫穿電極電性連接至所述半導體晶片中的至少一者。A semiconductor package as described in claim 2, wherein the wafer test pad is electrically connected to at least one of the internal interconnects, and the package test pad is electrically connected to at least one of the semiconductor chips via the through electrode. 如請求項1所述的半導體封裝，其中相對於所述基底晶片的所述前表面的中心部分而言，所述晶圓測試墊被設置得較所述封裝測試墊更遠。A semiconductor package as described in claim 1, wherein the wafer test pad is arranged farther than the package test pad relative to a central portion of the front surface of the base wafer. 如請求項1所述的半導體封裝，其中所述晶圓測試墊之中與所述基底晶片的第一側表面相鄰的一者與所述第一側表面之間的距離小於所述封裝測試墊中與所述基底晶片的第二側表面相鄰的一者與所述第二側表面之間的距離。A semiconductor package as described in claim 1, wherein the distance between one of the wafer test pads adjacent to the first side surface of the base chip and the first side surface is smaller than the distance between one of the package test pads adjacent to the second side surface of the base chip and the second side surface. 如請求項1所述的半導體封裝， 其中所述晶圓測試墊中的每一者包括具有第一寬度的第一側表面及具有第二寬度的第二側表面， 其中所述第一寬度是約40微米至約60微米且所述第二寬度是約100微米至約150微米。 A semiconductor package as described in claim 1, wherein each of the wafer test pads includes a first side surface having a first width and a second side surface having a second width, wherein the first width is about 40 microns to about 60 microns and the second width is about 100 microns to about 150 microns. 如請求項1所述的半導體封裝，其中所述晶圓測試墊之中彼此相鄰的晶圓測試墊之間的距離是約10微米至約30微米。A semiconductor package as described in claim 1, wherein the distance between adjacent wafer test pads among the wafer test pads is about 10 microns to about 30 microns. 如請求項1所述的半導體封裝， 其中所述封裝測試墊中的每一者包括具有第一寬度的第一側表面及具有第二寬度的第二側表面， 其中所述第一寬度是約65微米至約100微米且所述第二寬度是約100微米至約150微米。 A semiconductor package as described in claim 1, wherein each of the package test pads includes a first side surface having a first width and a second side surface having a second width, wherein the first width is about 65 microns to about 100 microns and the second width is about 100 microns to about 150 microns. 如請求項1所述的半導體封裝，其中所述封裝測試墊之中相鄰的封裝測試墊之間的距離是約30微米至約50微米。A semiconductor package as described in claim 1, wherein the distance between adjacent package test pads among the package test pads is about 30 microns to about 50 microns. 如請求項1所述的半導體封裝， 其中所述晶圓測試墊包括與所述基底晶片的第一側表面相鄰的第一晶圓測試墊， 其中所述封裝測試墊包括與所述第一側表面相鄰的第一封裝測試墊，且 其中所述第一晶圓測試墊中的每一者被設置成較所述第一封裝測試墊更靠近所述第一側表面。 A semiconductor package as described in claim 1, wherein the wafer test pad includes a first wafer test pad adjacent to a first side surface of the base wafer, wherein the package test pad includes a first package test pad adjacent to the first side surface, and wherein each of the first wafer test pads is disposed closer to the first side surface than the first package test pad. 如請求項10所述的半導體封裝，其中所述第一晶圓測試墊沿著所述第一側表面被設置成一列，且所述第一封裝測試墊沿著所述第一側表面被設置成一列。A semiconductor package as described in claim 10, wherein the first wafer test pads are arranged in a row along the first side surface, and the first package test pads are arranged in a row along the first side surface. 如請求項1所述的半導體封裝， 其中所述晶圓測試墊包括與所述基底晶片的第二側表面相鄰的第二晶圓測試墊，且 其中所述封裝測試墊包括與所述第二側表面相鄰的第二封裝測試墊， 其中所述第二晶圓測試墊與所述第二封裝測試墊交替地設置。 A semiconductor package as described in claim 1, wherein the wafer test pad includes a second wafer test pad adjacent to the second side surface of the base wafer, and wherein the package test pad includes a second package test pad adjacent to the second side surface, wherein the second wafer test pad and the second package test pad are arranged alternately. 如請求項12所述的半導體封裝，其中所述第二晶圓測試墊及所述第二封裝測試墊之中的相鄰者之間的距離是約30微米至約50微米。A semiconductor package as described in claim 12, wherein a distance between adjacent ones of the second wafer test pad and the second package test pad is approximately 30 microns to approximately 50 microns. 如請求項1所述的半導體封裝，其中所述封裝測試墊包括設置於所述凸塊墊之間的第三封裝測試墊。A semiconductor package as described in claim 1, wherein the package test pad includes a third package test pad arranged between the bump pads. 一種半導體封裝，包括： 基底晶片，具有前表面及與所述前表面相對的後表面，所述基底晶片包括設置於所述基底晶片的所述前表面上的凸塊墊、晶圓測試墊及封裝測試墊； 連接結構，設置於所述基底晶片的所述前表面上且連接至所述凸塊墊；以及 半導體晶片，堆疊於所述基底晶片的所述後表面上且包括測試墊， 其中所述晶圓測試墊中的每一者的尺寸小於所述封裝測試墊且大於或等於所述測試墊。 A semiconductor package comprises: a base chip having a front surface and a rear surface opposite to the front surface, the base chip comprising a bump pad, a wafer test pad and a package test pad arranged on the front surface of the base chip; a connection structure arranged on the front surface of the base chip and connected to the bump pad; and a semiconductor chip stacked on the rear surface of the base chip and comprising a test pad, wherein the size of each of the wafer test pads is smaller than that of the package test pad and larger than or equal to that of the test pad. 如請求項15所述的半導體封裝，其中所述基底晶片包括 基底主體； 貫穿電極，穿透過所述基底主體； 內部電路結構，設置於所述基底主體下方且包括內部互連件；以及 基底背部結構，設置於所述基底主體上。 A semiconductor package as described in claim 15, wherein the base chip includes a base body; a through electrode penetrating the base body; an internal circuit structure disposed below the base body and including internal interconnects; and a base back structure disposed on the base body. 如請求項16所述的半導體封裝，其中所述晶圓測試墊電性連接至所述內部互連件中的至少一者，且所述封裝測試墊經由所述貫穿電極電性連接至所述半導體晶片中的至少一者。A semiconductor package as described in claim 16, wherein the wafer test pad is electrically connected to at least one of the internal interconnects, and the package test pad is electrically connected to at least one of the semiconductor chips via the through electrode. 如請求項16所述的半導體封裝， 其中所述半導體晶片包括與所述基底晶片接觸的第一半導體晶片，且 其中所述第一半導體晶片的所述測試墊設置於所述第一半導體晶片的下表面上且與所述基底背部結構的鈍化層接觸。 A semiconductor package as described in claim 16, wherein the semiconductor chip includes a first semiconductor chip in contact with the substrate chip, and wherein the test pad of the first semiconductor chip is disposed on the lower surface of the first semiconductor chip and in contact with the passivation layer of the substrate back structure. 一種半導體封裝，包括： 基底晶片，具有前表面及與所述前表面相對的後表面，所述基底晶片包括：基底主體；貫穿電極，穿透過所述基底主體；內部電路結構，設置於所述基底主體下方且包括內部互連件；以及基底背部結構，設置於所述基底主體上； 半導體晶片，堆疊於所述基底晶片的所述後表面上； 連接結構，設置於所述基底晶片的所述前表面上；以及 模塑層，覆蓋所述基底晶片及所述半導體晶片， 其中所述內部電路結構包括設置於所述前表面上的凸塊墊、電性連接至所述內部互連件中的至少一者的晶圓測試墊及電性連接至所述半導體晶片中的至少一者的封裝測試墊， 其中所述晶圓測試墊中的每一者小於所述封裝測試墊。 A semiconductor package comprises: a substrate chip having a front surface and a rear surface opposite to the front surface, the substrate chip comprising: a substrate body; a through electrode penetrating the substrate body; an internal circuit structure disposed below the substrate body and comprising an internal interconnect; and a substrate back structure disposed on the substrate body; a semiconductor chip stacked on the rear surface of the substrate chip; a connection structure disposed on the front surface of the substrate chip; and a molding layer covering the substrate chip and the semiconductor chip, wherein the internal circuit structure comprises a bump pad disposed on the front surface, a wafer test pad electrically connected to at least one of the internal interconnects, and a package test pad electrically connected to at least one of the semiconductor chips, wherein each of the wafer test pads is smaller than the package test pad. 如請求項19所述的半導體封裝，其中所述晶圓測試墊之間的距離小於所述封裝測試墊之間的距離。A semiconductor package as described in claim 19, wherein the distance between the wafer test pads is smaller than the distance between the package test pads.