TW202418817A - Decoder circuits for the transmission of video media using spread spectrum direct sequence modulation - Google Patents
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Abstract
Description
相關申請案的交叉引用Cross-references to related applications
本申請要求於2020年11月25日提交的美國臨時申請 No. 63/118,320 的優先權，兩者名稱均為“Encoder and Decoder Circuits for the Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation（用於使用展頻直接序列調製傳輸視訊媒體的編碼器和解碼器電路）”，並且兩者出於所有目的整體併入本文。 This application claims priority to U.S. Provisional Application No. 63/118,320 filed on November 25, 2020, both entitled "Encoder and Decoder Circuits for the Transmission of Video Media Using Spread Spectrum Direct Sequence Modulation," and both are incorporated herein in their entirety for all purposes.
本發明一般涉及視訊和/或其他媒體傳送，更特別地，涉及用於使用分碼多重存取（CDMA）和展頻直接序列（SSDS）調製在視訊源和視訊接收端（video sink）之間的傳輸的視訊媒體的編碼和解碼。The present invention relates generally to video and/or other media transmission and, more particularly, to encoding and decoding of video media for transmission between a video source and a video sink using code division multiple access (CDMA) and spread spectrum direct sequence (SSDS) modulation.
高解析度視訊通常以多種不同格式產生，包括“720p”、“1080i”、“1080p”和最近的“4K”。對於這些格式，“i”指的是隔行掃描，“p”指的是逐行掃描。High-resolution video is commonly produced in a number of different formats, including "720p", "1080i", "1080p", and most recently, "4K". For these formats, the "i" refers to interlaced scanning and the "p" refers to progressive scanning.
使用上面列出的任何格式傳輸的視訊資料量是巨大的。對於“720p”，傳輸速率為 1280 水平線乘 720 垂直線或每訊框大約 921,600 個像素，典型刷新速率為每秒 50 或 60 訊框。1080i 的傳輸需要傳輸 1920 水平線乘 540 垂直線，或每場 1,036,800 個像素，每訊框由兩個隔行掃描場組成，刷新速率範圍為每秒 12.5 到 60 場。1080p 的傳輸涉及 1920 水平線乘 1080 垂直線，或每訊框 2,073,600 個像素，並且通常刷新速率範圍為每秒 30 到 60 訊框。4K 視訊傳輸涉及每訊框 3840 水平線乘 2160 垂直線，通常刷新速率為每秒 30 或 60 訊框。The amount of video data transmitted using any of the formats listed above is enormous. For "720p", the transmission rate is 1280 horizontal lines by 720 vertical lines, or approximately 921,600 pixels per frame, with a typical refresh rate of 50 or 60 frames per second. Transmission of 1080i requires transmission of 1920 horizontal lines by 540 vertical lines, or 1,036,800 pixels per field, with each frame consisting of two interlaced fields, and refresh rates ranging from 12.5 to 60 fields per second. Transmission of 1080p involves 1920 horizontal lines by 1080 vertical lines, or 2,073,600 pixels per frame, and typically has a refresh rate ranging from 30 to 60 frames per second. 4K video transmission involves 3840 horizontal lines by 2160 vertical lines per frame, typically at a refresh rate of 30 or 60 frames per second.
鑒於傳輸視訊所需的大量頻寬，通常使用各種類型的視訊壓縮，諸如MPEG、AVC和HEVC。視訊壓縮的問題包括有限的互通性、增加的實施成本、增加的時延和降低的影像保真度。因此，與未壓縮或視覺無損視訊相比，在顯示壓縮視訊時，圖片品質一定程度會下降。Given the large amounts of bandwidth required to transmit video, various types of video compression are commonly used, such as MPEG, AVC, and HEVC. Issues with video compression include limited interoperability, increased implementation costs, increased latency, and reduced image fidelity. As a result, there is some degradation in picture quality when displaying compressed video compared to uncompressed or visually lossless video.
上述問題的嚴重性在不久的將來只會變得更加嚴重。消費者電子公司現在正在向市場推出8K相機和顯示器。8K設備的訊框大小為 7,680 條水平線和 4,320 條垂直線，或每訊框 33,177,600 像素，並且刷新速率通常為每秒 120 或 240 訊框。因此，8K 視訊的傳輸將使已經存在的一系列挑戰變得更加糟糕。The severity of the above problems will only get worse in the near future. Consumer electronics companies are now bringing 8K cameras and displays to the market. 8K devices have a frame size of 7,680 horizontal lines and 4,320 vertical lines, or 33,177,600 pixels per frame, and refresh rates are typically 120 or 240 frames per second. Therefore, the transmission of 8K video will make an already existing set of challenges even worse.
因此需要一種能夠傳輸未經壓縮的高品質、高解析度視訊的視訊傳輸器。Therefore, a video transmitter capable of transmitting uncompressed high-quality, high-resolution video is needed.
本發明針對使用基於展頻直接序列（SSDS）調製的分碼多重存取（CDMA）通道共用在視訊源和視訊接收端之間傳輸的視訊媒體的編碼和解碼電路。The present invention is directed to encoding and decoding circuits for video media transmitted between a video source and a video sink using code division multiple access (CDMA) channel sharing based on spread spectrum direct sequence (SSDS) modulation.
在一個非排他性實施例中，描述了用於將一組相互正交的SSDS碼應用於視訊資料的編碼器電路和方法，其中 （“L”） 是限定為在 CDMA 碼本中使用的碼的長度的參數。該方法和編碼器電路涉及（a）建構包括第一電壓值和第二電壓值的N個樣本的視訊向量，N個樣本分別從表示多個像素的多組樣本得出，（b）使用每個來自其對應代碼的L 個SSDS碼片調製用於視訊向量中的N 個樣本的第一電壓值和第二電壓值中的每一個，調製中的每一個涉及分別取決於L個對應SSDS碼片的狀態而條件性地反轉或不反轉N個樣本的第一電壓值和第二電壓值，（c）產生L個差分電位準輸出訊號的序列，每個來自於條件性地被反轉或不被反轉的N個樣本的經調製的第一電壓值和第二電壓值的累加。In one non-exclusive embodiment, encoder circuits and methods for applying a set of mutually orthogonal SSDS codes to video data are described, where (“L”) is a parameter defined as the length of the code used in a CDMA codebook. The method and encoder circuit involve (a) constructing a video vector including N samples of a first voltage value and a second voltage value, the N samples being respectively derived from a plurality of groups of samples representing a plurality of pixels, (b) modulating each of the first voltage value and the second voltage value for the N samples in the video vector using L SSDS code chips each from its corresponding code, each of the modulations involving conditionally inverting or not inverting the first voltage value and the second voltage value of the N samples depending on the state of the L corresponding SSDS code chips, and (c) generating a sequence of L differential level output signals, each derived from the accumulation of the modulated first voltage value and the second voltage value of the N samples that are conditionally inverted or not inverted.
在另一個非排他性實施例中，描述了用於應用同一組相互正交的SSDS碼來將L個差分電位準訊號解碼為N個樣本的解碼電路和方法。該方法和電路包括（a）接收一系列L個差分電位準訊號，（b）將每個接收到的差分電位準訊號提供至N個解碼器電路，（c）將來自對應代碼的N個展頻直接序列（SSDS）碼片分別提供至N個解碼器電路，N個SSDS碼片中的每一個具有第一狀態或第二狀態，（d）對於N個解碼器電路中的每一個，取決於提供至N個解碼器電路的每一個的SSDS碼片分別是否具有第一狀態或第二狀態，藉由條件性地反轉或不反轉差分電位準訊號來解調，（e）對於N個解碼器電路中的每一個，在第一儲存位置和第二儲存位置處累積反轉或不反轉差分電位準訊號；（f）在L個解調步驟（d）和（e）之後，提供N個重建樣本，分別從儲存在N個解碼器電路中的每一個的第一儲存位置和第二儲存位置處的經反轉或未經反轉的差分電位準訊號中得出的N個樣本。In another non-exclusive embodiment, a decoding circuit and method for applying the same set of mutually orthogonal SSDS codes to decode L differential electrical level signals into N samples is described. The method and circuit include (a) receiving a series of L differential electrical level signals, (b) providing each received differential electrical level signal to N decoder circuits, (c) providing N spread spectrum direct sequence (SSDS) code chips from the corresponding code to the N decoder circuits, each of the N SSDS code chips having a first state or a second state, and (d) for each of the N decoder circuits, depending on whether the SSDS code chips provided to each of the N decoder circuits have a first state or a second state, respectively. (e) for each of the N decoder circuits, accumulating the inverted or non-inverted differential electric level signal at a first storage location and a second storage location; and (f) after L demodulation steps (d) and (e), providing N reconstructed samples, N samples derived from the inverted or non-inverted differential electric level signal stored at the first storage location and the second storage location of each of the N decoder circuits, respectively.
在又一非排他性實施例中，描述了一種解碼器電路和方法，用於藉由產生藉由對儲存在佈置於第一組中的（L）個存放裝置上的平均電壓值進行平均得出的平均電壓值，對使用SSDS編碼進行編碼的視訊媒體的（L）個訊號進行解碼以產生樣本視訊訊號，其中該（L）個電壓值是該（L）個訊號分別與（L）個SSDS碼片值進行相乘而得出的。In another non-exclusive embodiment, a decoder circuit and method are described for decoding (L) signals of a video media encoded using SSDS encoding to generate sample video signals by generating an average voltage value obtained by averaging average voltage values stored in (L) storage devices arranged in a first group, wherein the (L) voltage values are obtained by multiplying the (L) signals by (L) SSDS code chip values, respectively.
以下描述列舉了本文揭露的本發明的各個方面和實施例。沒有特定實施例旨在限定本發明的範圍。相反，實施例提供了包括在要求保護的發明範圍內的各種裝置和方法的非限制性示例。該描述將從本領域普通技術人員的角度來閱讀。因此，不一定包括普通技術人員熟知的資訊。 分碼多重存取（ CDMA ） The following description lists various aspects and embodiments of the present invention disclosed herein. No particular embodiment is intended to limit the scope of the present invention. Instead, the embodiments provide non-limiting examples of various devices and methods included within the scope of the claimed invention. The description is to be read from the perspective of a person of ordinary skill in the art. Therefore, it does not necessarily include information that is well known to a person of ordinary skill. Code Division Multiple Access ( CDMA )
分碼多重存取（CDMA）是眾所周知的通道存取協定，通常用於包括蜂巢在內的無線電通訊技術。CDMA是多址存取的示例，其中幾個發射器可以經由單個通訊通道同時發送資訊。在電信應用中，CDMA 允許多個使用者共用給定的頻帶，而不受其他使用者的干擾。 CDMA 採用展頻直接序列 （SSDS），這種編碼依賴於唯一的正交碼來編碼每個使用者的資料。藉由使用唯一代碼，可以將多個使用者的傳輸合併發送，而不會在使用者之間產生干擾。在接收側，每個使用者使用相同的唯一碼或正交碼來解調傳輸，分別恢復每個使用者的資料。 展頻直接序列（ SSDS ）調製 Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communications technologies including cellular. CDMA is an example of multiple access, in which several transmitters can send information simultaneously over a single communications channel. In telecommunications applications, CDMA allows multiple users to share a given frequency band without interference from other users. CDMA employs spread spectrum direct sequence (SSDS), a type of coding that relies on a unique orthogonal code to encode each user's data. By using a unique code, the transmissions of multiple users can be combined and sent without interference between the users. On the receiving side, each user uses the same unique code, or orthogonal code, to demodulate the transmission, recovering each user's data separately. Spread Spectrum Direct Sequence ( SSDS ) modulation
SSDS是一種調製技術，藉由該技術，特定頻寬中的訊號（例如，一系列電或電磁值）使用正交碼被有意地擴展，從而產生具有更寬頻寬的訊號。然後經由傳輸介質傳輸更寬頻寬的訊號。在接收側，使用與發送側調製相同的正交碼來解調寬頻寬訊號。結果，恢復了原始的電或電磁訊號。SSDS is a modulation technique whereby a signal in a specific bandwidth (e.g., a series of electric or electromagnetic values) is intentionally spread using an orthogonal code, thereby producing a signal with a wider bandwidth. The wider bandwidth signal is then transmitted via a transmission medium. On the receiving side, the wideband signal is demodulated using the same orthogonal code as that modulated on the transmitting side. As a result, the original electric or electromagnetic signal is restored.
本發明涉及用於使用基於展頻直接序列（SSDS）調製的分碼多重存取（CDMA）通道共用來編碼和解碼在視訊源和視訊接收端之間傳輸的視訊媒體的電路。在操作期間，從視訊源接收包含顏色值和像素相關資訊的按時間排序的視訊樣本串流，並為視訊接收端重建。如下文更詳細描述的，從視訊源接收的輸入視訊樣本的數量和內容取決於在源處操作的顏色空間。無論使用哪種顏色空間，每個視訊樣本都表示指定顏色空間中的感測或測量的光量。當接收到輸入視訊樣本串流時，輸入視訊樣本被重複（1）藉由根據預定排列將輸入視訊樣本分配到編碼器輸入向量中來“分佈”，以及（2）藉由應用基於SSDS的 CDMA 調製到多個編碼器輸入向量中的每一個，應用正交碼，進行編碼，以產生具有類雜訊特性的多個複合EM訊號。（3）然後，EM 訊號經由傳輸介質傳輸，諸如 HDMI 電纜。在接收側，（4）傳入的 EM 訊號藉由應用基於SSDS的 CMDA 解調進行解碼，應用相同的正交碼，將樣本重建為輸出向量，然後（5）使用預定排列的逆，藉由將重建的視訊樣本從輸出向量分配到輸出串流“收集”輸出向量。結果，包含顏色和像素相關資訊的按時間排序的原始視訊樣本串流從視訊源傳遞到視訊接收端。The present invention relates to circuits for encoding and decoding video media transmitted between a video source and a video sink using code division multiple access (CDMA) channel sharing based on spread spectrum direct sequence (SSDS) modulation. During operation, a time-ordered stream of video samples containing color values and pixel-related information is received from the video source and reconstructed for the video sink. As described in more detail below, the number and content of input video samples received from the video source depends on the color space operating at the source. Regardless of which color space is used, each video sample represents a sensed or measured amount of light in the specified color space. When an input video sample stream is received, the input video samples are repeatedly (1) "distributed" by assigning the input video samples to encoder input vectors according to a predetermined arrangement, and (2) encoded by applying SSDS-based CDMA modulation to each of the multiple encoder input vectors, applying an orthogonal code, to produce multiple composite EM signals with noise-like characteristics. (3) The EM signals are then transmitted via a transmission medium, such as an HDMI cable. On the receiving side, (4) the incoming EM signal is decoded by applying SSDS-based CDMA demodulation, applying the same orthogonal code, reconstructing the samples into output vectors, and then (5) the output vectors are "collected" by assigning the reconstructed video samples from the output vectors to the output stream using the inverse of the predetermined arrangement. As a result, a time-ordered stream of raw video samples containing color and pixel-related information is delivered from the video source to the video sink.
參考圖1，示出了根據本發明的非排他性實施例的示出使用基於展頻直接序列（SSDS）的 CDMA 調製將電磁（EM）視訊訊號從數位視訊源傳輸到數位視訊接收端的系統 10。1, a system 10 is shown for transmitting electromagnetic (EM) video signals from a digital video source to a digital video sink using spread spectrum direct sequence (SSDS) based CDMA modulation according to a non-exclusive embodiment of the present invention.
在下面的討論中，描述了通常如何捕獲數位視訊資料的過程。捕獲後，數位視訊資料可以傳輸到視訊顯示器以進行近乎即時的消耗。另一方面，可以將捕獲的視訊資料儲存起來以供以後以時移模式消耗。在任一情況下，本文建議使用基於SSDS的CDMA調製將數位視訊資料從視訊源（或存放裝置）傳輸到視訊接收端以供顯示（或儲存）。 視訊捕獲 In the following discussion, a process is described for how digital video data is typically captured. Once captured, the digital video data can be transmitted to a video display for near-instantaneous consumption. Alternatively, the captured video data can be stored for later consumption in a time-shifted mode. In either case, this article proposes the use of SSDS-based CDMA modulation to transmit the digital video data from a video source (or storage device) to a video sink for display (or storage). Video Capture
視訊源12包括影像感測器陣列16、一或更多類比數位轉換器18、影像訊號處理器（ISP 20）和負責產生視訊樣本串流22的視訊流化器21。視訊源12也可以可選地連接到視訊媒體存放裝置24。存放裝置可以接近影像感測器陣列16的位置，也可以是遠端的。The video source 12 includes an image sensor array 16, one or more analog-to-digital converters 18, an image signal processor (ISP 20), and a video streamer 21 responsible for generating a video sample stream 22. The video source 12 may also be optionally connected to a video media storage device 24. The storage device may be located close to the image sensor array 16 or remotely.
在各種實施例中，視訊源12可以是能夠捕獲成像資訊的任何設備，諸如但不限於攝影機、紅外線成像設備、超音波成像設備、核磁共振影像（MRI）設備、電腦斷層掃描，或幾乎任何其他類型的能夠產生視訊資訊的成像設備。In various embodiments, video source 12 may be any device capable of capturing imaging information, such as, but not limited to, a camera, an infrared imaging device, an ultrasound imaging device, an MRI device, a computer tomography scan, or virtually any other type of imaging device capable of producing video information.
影像感測器16是能夠產生與測量的光量成比例的電子訊號的任何設備。例如，在非排他性實施例中，影像感測器是光電二極體的平面陣列。每個光電二極體表示平面陣列中的像素樣本位置。平面陣列中的光電二極體的數量可以有很大的變化，並且取決於影像感測器 16 的尺寸。例如，“4K”成像感測器包括 3840 條水平線乘以 1080 條垂直線的光電二極體陣列，或者總共4,147,200 個光電二極體。8K成像感測器將有 7,680 條水平線和 4,320 條垂直線，或每訊框 3,317,7600 個像素。應當理解，4K和8K僅僅是解析度的示例，並且影像感測器16可以是任何尺寸，包括小於480、480、720、1080、4K、8K。陣列中光電二極體的數量當然會相應變化。Image sensor 16 is any device capable of producing an electronic signal that is proportional to the amount of light measured. For example, in a non-exclusive embodiment, the image sensor is a planar array of photodiodes. Each photodiode represents a pixel sample location in the planar array. The number of photodiodes in the planar array can vary greatly and depends on the size of image sensor 16. For example, a "4K" imaging sensor includes a photodiode array of 3840 horizontal lines by 1080 vertical lines, or a total of 4,147,200 photodiodes. An 8K imaging sensor would have 7,680 horizontal lines and 4,320 vertical lines, or 3,317,7600 pixels per frame. It should be understood that 4K and 8K are merely examples of resolutions, and that the image sensor 16 may be any size, including less than 480, 480, 720, 1080, 4K, 8K. The number of photodiodes in the array will of course vary accordingly.
在操作期間，影像感測器16以給定的刷新速率連續地重複感測間隔。在每個感測間隔期間，陣列中的每個光電二極體為每個像素位置產生電壓，該電壓與光電二極體產生的光子數量成反比。結果，光電二極體陣列產生一組電壓，這些電壓共同表示訊框。由於影像感測器以給定的畫面播放速率不斷刷新，因此連續不斷地產生多組電壓，每組電壓表示訊框。During operation, the image sensor 16 continuously repeats sensing intervals at a given refresh rate. During each sensing interval, each photodiode in the array generates a voltage for each pixel location that is inversely proportional to the number of photons generated by the photodiode. As a result, the photodiode array generates a set of voltages that collectively represent a frame. Because the image sensor is continuously refreshed at a given frame playback rate, multiple sets of voltages are continuously generated, each set of voltages representing a frame.
對於每個像素位置，光電二極體設置在電容器和地之間。就在感測間隔之前，電容器被預充電。感測時，光電二極體會產生與接收到的光量成正比的電流。當感測到幾乎沒有光時，幾乎沒有電容器藉由光電二極體對地放電。相反，如果感測到大量光，則電容器上的大部分電壓都會放電。因此，曝光間隔後電容器上剩餘的電壓與感測的光的量成反比。For each pixel location, a photodiode is placed between a capacitor and ground. Just before the sensing interval, the capacitor is pre-charged. When sensing, the photodiode produces a current proportional to the amount of light received. When almost no light is sensed, almost no capacitor is discharged to ground through the photodiode. Conversely, if a lot of light is sensed, most of the voltage on the capacitor is discharged. Therefore, the voltage remaining on the capacitor after the exposure interval is inversely proportional to the amount of light sensed.
對於許多數位影像感測器陣列16，通常存在一行類比數位轉換器（“ADC”）18，每列具有一個ADC。在給定的訊框間隔期間，對陣列16的所有行進行取樣，通常從上到下一個接一個，在本文中有時稱為“行優先”順序。對於每個樣本，ADC 18將感測到的電壓轉換為陣列中每一列的像素位置的數位值。當陣列16的所有行都已被取樣時，訊框就完成了。上述過程在逐訊框的基礎上以行優先順序重複。最終結果是一串數位值，每個數位值表示訊框中的像素位置。同樣，影像感測器的尺寸和刷新速率是每訊框數位值數量的決定性因素。例如，4K 或8K數位影像感測器每訊框將分別測量 8,294,400 或 33,177,600 個數位樣本。For many digital image sensor arrays 16, there is typically a row of analog-to-digital converters ("ADCs") 18, with one ADC per column. During a given frame interval, all rows of the array 16 are sampled, typically one after the other from top to bottom, sometimes referred to herein as a "row-first" order. For each sample, the ADC 18 converts the sensed voltage into a digital value for the pixel location in each column of the array. When all rows of the array 16 have been sampled, the frame is complete. The above process is repeated on a frame-by-frame basis in row-first order. The end result is a string of digital values, each representing a pixel location in the frame. Again, the size of the image sensor and the refresh rate are determining factors in the number of digital values per frame. For example, a 4K or 8K digital image sensor will measure 8,294,400 or 33,177,600 digital samples per frame, respectively.
用於表示每個樣本的位數可以廣泛地變化。例如，每個電壓可以由類比數位轉換器18轉換成8位或10位的值。應當理解，此處列出的這些位值僅是說明性的，用於表示像素電壓值的位元的數量可以多於或少於8或10。The number of bits used to represent each sample can vary widely. For example, each voltage can be converted to an 8-bit or 10-bit value by the analog-to-digital converter 18. It should be understood that the bit values listed here are illustrative only, and the number of bits used to represent the pixel voltage value can be more or less than 8 or 10.
影像感測器陣列16可以是單色的或彩色的。在單色的情況下，由ADC 18產生的數位值僅表示一種顏色。對於彩色的，通常應用眾所周知的顏色技術，諸如拜耳濾波。利用拜耳濾波，單個光電二極體16選擇性地覆蓋有預定顏色（例如，紅色（R）或藍色（B）或綠色（G））的濾波器。在替代實施例中，可以使用CYGM（青色、黃色、綠色和品紅色）或CMY（青色、品紅色和黃色）濾波。無論使用哪種類型的濾波器，都會在每個樣本位置測量濾波的光的量。The image sensor array 16 can be monochrome or color. In the case of monochrome, the digital value produced by the ADC 18 represents only one color. For color, well-known color techniques are generally applied, such as Bayer filtering. With Bayer filtering, a single photodiode 16 is selectively covered with a filter of a predetermined color, such as red (R) or blue (B) or green (G). In alternative embodiments, CYGM (cyan, yellow, green and magenta) or CMY (cyan, magenta and yellow) filtering may be used. Regardless of which type of filter is used, the amount of filtered light is measured at each sample location.
ISP 20被佈置為對從ADC 18接收的數位值串進行內插。藉由內插，ISP 20獲取包含在用於每個像素測量及其幾何鄰域的數位值中的資訊，並定義對應的像素的顏色的估計。為了在特定顏色空間（有很多）中輸出全彩影像，ISP 20 在每個位置會***“缺失”顏色值。也就是說，給定每個像素的單色測量值，ISP 會藉由演算法估計“缺失”的顏色值，以創建例如像素的 RGB 或 YCbCr 表示。ISP 20因此為給定訊框的給定像素產生一組樣本22，每組樣本22表示訊框內給定像素位置的顏色值（如測量的和/或內插的）。The ISP 20 is arranged to interpolate the string of digital values received from the ADC 18. By interpolation, the ISP 20 obtains the information contained in the digital values used for each pixel measurement and its geometric neighbors and defines an estimate of the color of the corresponding pixel. In order to output a full-color image in a specific color space (there are many), the ISP 20 interpolates the "missing" color value at each location. That is, given the monochrome measurement value of each pixel, the ISP estimates the "missing" color value by algorithm to create, for example, an RGB or YCbCr representation of the pixel. The ISP 20 thus generates a set of samples 22 for a given pixel of a given frame, each set of samples 22 representing the color value (as measured and/or interpolated) of a given pixel position within the frame.
給定的一組樣本22的內容可以變化，因為有許多方式來表示顏色。在不同的實施例中，包含在每組樣本22中的資訊因此可以變化。通常，RGB 被認為是全彩色，而其他空間，諸如 YCbCr是全彩色的近似值，更小而難以傳輸。RGB 提供三種顏色值。對於 YCbCr，Y 是亮度分量，Cb 和 Cr 分別是藍差和紅差色度值。YCbCr 顏色空間由關聯的 RGB 顏色空間的數學座標變換定義。在另一種表示顏色的方式中，可以使用“交替”方法。例如，每隔一個像素由其量度（Y）值表示，而交替像素由 Cb（藍色）或 Cr（紅色）值表示。因此，在各種實施例中，每組樣本22包括平行傳輸的一些數位“S”個樣本值。對於 RGB，每組樣本 22 的樣本數為 S = 3，而對於 YCbCr，S = 2。The contents of a given set of samples 22 can vary, as there are many ways to represent color. In different embodiments, the information contained in each set of samples 22 can therefore vary. Typically, RGB is considered full color, while other spaces, such as YCbCr, are approximations of full color that are smaller and difficult to transmit. RGB provides three color values. For YCbCr, Y is the brightness component, and Cb and Cr are the blue difference and red difference chrominance values, respectively. The YCbCr color space is defined by a mathematical coordinate transformation of the associated RGB color space. In another way of representing color, an "alternating" method can be used. For example, every other pixel is represented by its metric (Y) value, while alternate pixels are represented by Cb (blue) or Cr (red) values. Therefore, in various embodiments, each set of samples 22 includes a number of digital "S" sample values that are transmitted in parallel. For RGB, the number of samples per set of 22 is S = 3, and for YCbCr, S = 2.
作為回應，視訊流化器 21 產生一系列按時間排序的樣本集22。通常，每個樣本集 22 輸出整體表示陣列 16 上的一個像素位置的光測量值。樣本的值和/或數量由每個像素位置的ISP 產生，這取決於 ISP 的實現，尤其是應用的顏色空間。In response, the video streamer 21 generates a series of time-ordered sample sets 22. Typically, each sample set 22 outputs a light measurement value representing the entirety of a pixel location on the array 16. The value and/or number of samples generated by the ISP for each pixel location depends on the implementation of the ISP, and in particular the color space of the application.
視訊流化器21的輸出是按時間排序的樣本集22的連續串流，每個樣本從左到右，以行優先順序，訊框接訊框表示行中的像素，只要陣列16正在感應。然後，在傳輸之後，由視訊接收端14處理樣本集串流22，以重建由影像陣列感測器16逐訊框感測的影像。The output of the video streamer 21 is a continuous stream of time-ordered sample sets 22, with each sample from left to right, in row-first order, frame by frame representing pixels in a row, as long as the array 16 is sensing. Then, after transmission, the sample set stream 22 is processed by the video sink 14 to reconstruct the image sensed by the image array sensor 16 on a frame-by-frame basis.
在另一個可選實施例中，樣本集22的串流可以儲存在存放裝置24中。以這種方式，樣本集22的串流可以在視訊串流最初被影像感測器16捕獲之後的任何時間被傳輸。例如，可以在一個時間間隔期間捕獲樣本集22的串流，然後逐訊框傳輸到視訊接收端14以供在稍後的某個時間點顯示和/或儲存在儲存單元24中以傳輸到視訊接收端14。按照這種方式，視訊源12捕獲的視訊可在視訊接收端14上進行時移顯示。In another alternative embodiment, the stream of sample set 22 may be stored in storage unit 24. In this manner, the stream of sample set 22 may be transmitted at any time after the video stream is initially captured by image sensor 16. For example, the stream of sample set 22 may be captured during a time interval and then transmitted frame by frame to video receiving end 14 for display at a later point in time and/or stored in storage unit 24 for transmission to video receiving end 14. In this manner, the video captured by video source 12 may be displayed on video receiving end 14 in a time-shifted manner.
在影像捕獲和顯示的上下文中使用 SSVT 的一個優勢在於，影像在本質上容易出錯的感測器上測量，並顯示在本質上嘈雜的 LED 陣列上，並由極其複雜和穩健的人類視覺系統查看。因此，視訊的通訊要求與諸如試算表和電子郵件等傳統數位工件的通訊要求有很大不同，後者需要位元完美的傳輸。然而，傳統的視訊傳輸將視訊訊號視為另一種（數位）文檔。然而，使用 SSVT，視訊訊號以電氣穩健的方式傳輸。 SSVT 的優點之一是在接收器的 EM 訊號測量中出現的任何未補償誤差在重建影像中表現為廣譜時間和空間雜訊。這種白色雜訊比傳統位元序列傳輸產生的空白螢幕、重複影像和塊狀壓縮偽影更適合人類認知。 傳輸 One advantage of using SSVT in the context of image capture and display is that images are measured on inherently error-prone sensors, displayed on inherently noisy LED arrays, and viewed by an extremely complex and robust human visual system. The communication requirements of video are therefore very different from those of traditional digital artifacts such as spreadsheets and email, which require bit-perfect transmission. However, traditional video transmission treats the video signal as just another (digital) document. With SSVT, however, the video signal is transmitted in an electrically robust manner. One of the advantages of SSVT is that any uncompensated errors that appear in the measurement of the EM signal at the receiver appear as spectral temporal and spatial noise in the reconstructed image. This white noise is more perceptible to humans than the blank screens, repeated images , and blocky compression artifacts produced by traditional bit-sequence transmission.
圖1進一步包括發送側的發送重計時器26和展頻視訊傳輸（SSVT）發射器（TX）28。如以下更詳細解釋的，重計時器26負責解碼或暴露來自由視訊流化器21產生的串流中的每個樣本集22的顏色分量資訊（例如，RGB值）。SSVT 28然後負責用於（a）使用預定排列將樣本集 22 分佈到多個編碼器輸入向量中的一個，以及（b）對多個編碼器輸入向量中的每一個應用SSDS調製，以及（c）使用基於SSDS的多個輸入向量編碼CDMA編碼以產生EM電位準訊號序列，以及（d）然後藉由多個EM路徑或傳輸介質，諸如HDMI電纜向視訊接收端14傳輸EM電位準訊號序列。1 further includes a transmit side transmit retimer 26 and a spread spectrum video transmission (SSVT) transmitter (TX) 28. As explained in more detail below, the retimer 26 is responsible for decoding or exposing color component information (eg, RGB values) from each sample set 22 in the stream generated by the video streamer 21. SSVT 28 is then responsible for (a) distributing sample set 22 to one of a plurality of encoder input vectors using a predetermined arrangement, and (b) applying SSDS modulation to each of the plurality of encoder input vectors, and (c) encoding the plurality of input vectors using SSDS-based CDMA coding to generate an EM electric level signal sequence, and (d) then transmitting the EM electric level signal sequence to the video receiving end 14 via a plurality of EM paths or transmission media, such as an HDMI cable.
在接收側，提供SSVT接收器（RX） 30、重計時器32和視訊接收端14。 SSVT接收器（RX）30和重計時器32的功能是重計時器26和SSVT發射器28在發送側的互補。也就是說，SSVT接收器RX 30 （a）從傳輸介質的多個EM路徑接收EM電位準訊號序列，（b）藉由應用基於SSDS的CDMA解調來解碼每個序列以在多個輸出向量中重建視訊樣本（c）使用用於將輸入樣本分佈到發送側的輸入向量中的相同排列，將來自多個輸出向量的樣本收集到樣本集22的原始串流的重建中。重計時器32然後將重建的輸出樣本變換成適合由視訊接收端14顯示或儲存在接收側以在時移模式下顯示的格式。每個樣本集22中的輸出樣本值S的數量由視訊源應用的顏色空間確定。對於 RGB，S=3，並且對於 YCbCr，S=2。在其他情況下，每個樣本集 22 中的樣本值 S 可以小於二（即，僅一（1）或多於三（3）。On the receiving side, an SSVT receiver (RX) 30, a retimer 32 and a video receiver 14 are provided. The functions of the SSVT receiver (RX) 30 and the retimer 32 are the complement of the retimer 26 and the SSVT transmitter 28 on the transmitting side. That is, the SSVT receiver RX 30 (a) receives EM electrical level signal sequences from multiple EM paths of the transmission medium, (b) decodes each sequence to reconstruct video samples in multiple output vectors by applying SSDS-based CDMA demodulation, and (c) collects the samples from the multiple output vectors into a reconstruction of the original stream of sample sets 22 using the same arrangement used to distribute the input samples into the input vectors on the transmitting side. The retimer 32 then transforms the reconstructed output samples into a format suitable for display by the video receiver 14 or storage on the receiving side for display in a time-shifted mode. The number of output sample values S in each sample set 22 is determined by the color space used by the video source. For RGB, S=3, and for YCbCr, S=2. In other cases, the number of sample values S in each sample set 22 may be less than two (i.e., only one (1) or more than three (3).
如本文所述，SSDS調製和解調在類比或電磁（“EM”）域中執行。如以下更詳細解釋的，輸入樣本集22的串流以第一時脈速率（pix-clk）分佈以根據預定排列創建編碼器輸入向量。然後將基於SSDS的 CDMA 調製應用於每個編碼器輸入向量，從而為每個編碼器輸入向量產生編碼的“EM”訊號。然後，EM 訊號藉由以第二時脈速率（SSVT_clk） 平行傳輸進行傳輸。對編碼器輸入向量中的每個樣本應用擴展（SSDS）可提供電氣彈性，但會犧牲每個樣本的頻寬。然而，藉由調製一組相互正交的代碼並同時傳輸所有得到的 EM 訊號 （CDMA），可以恢復部分或全部丟失的頻寬。As described herein, SSDS modulation and demodulation are performed in the analog or electromagnetic ("EM") domain. As explained in more detail below, a stream of input sample sets 22 are distributed at a first clock rate (pix-clk) to create encoder input vectors according to a predetermined arrangement. SSDS-based CDMA modulation is then applied to each encoder input vector, thereby producing an encoded "EM" signal for each encoder input vector. The EM signal is then transmitted by transmitting in parallel at a second clock rate (SSVT_clk). Applying spreading (SSDS) to each sample in the encoder input vector provides electrical flexibility, but sacrifices the bandwidth of each sample. However, by modulating a set of mutually orthogonal codes and transmitting all resulting EM signals simultaneously (CDMA), some or all of the lost bandwidth can be recovered.
圖2A是藉由傳輸介質34連接的SSVT發射器28和SSVT接收器30的邏輯框圖。SSVT發射器28包括分配器40和多個編碼器42。SSVT接收器30包括多個解碼器44和收集器46。2A is a logical block diagram of a SSVT transmitter 28 and a SSVT receiver 30 connected via a transmission medium 34. The SSVT transmitter 28 includes a distributor 40 and a plurality of encoders 42. The SSVT receiver 30 includes a plurality of decoders 44 and a collector 46.
在發送側，SSVT接收器30的分配器40被佈置為接收在樣本22的輸入集合中暴露的顏色資訊（例如，R、G和B值）。作為回應，分配器40獲取一組輸入樣本22的暴露的顏色資訊，並根據預定義的排列建構多個編碼器輸入向量。在圖2A中所示的非排他性實施例中，有四個編碼器輸入向量（V 0、V 1、V 2和V 3），一個分別用於傳輸介質34上的四個EM路徑中的每一個。在多個實施例中，傳輸介質34可以是諸如HDMI、光纖或無線的電纜。多個編碼器42之一被分別分配給四個向量V 0、V 1、V 2和V 3之一。每個編碼器42負責對包含在相應編碼器輸入向量中的樣本值進行編碼，並產生經由傳輸介質34上的並行路徑之一發送的EM訊號。 On the transmit side, the distributor 40 of the SSVT receiver 30 is arranged to receive the color information (e.g., R, G, and B values) exposed in the input set of samples 22. In response, the distributor 40 obtains the exposed color information of a set of input samples 22 and constructs multiple encoder input vectors according to a predefined arrangement. In the non-exclusive embodiment shown in Figure 2A, there are four encoder input vectors ( V0 , V1 , V2 , and V3 ), one for each of the four EM paths on the transmission medium 34. In multiple embodiments, the transmission medium 34 can be a cable such as HDMI, optical fiber, or wireless. One of the multiple encoders 42 is respectively assigned to one of the four vectors V0 , V1 , V2 , and V3 . Each encoder 42 is responsible for encoding the sample values contained in the corresponding encoder input vector and generating an EM signal that is transmitted via one of the parallel paths on the transmission medium 34.
在所示的此特定實施例中，有四個EM路徑，並且四個編碼器42每個分別為四個路徑中的每一個產生EM訊號。然而，應當理解，本發明決不應當限於四種途徑。相反，傳輸介質34上的路徑的數量可以廣泛地從一到多於一的任何數量，包括多於四。 排列示例 In the particular embodiment shown, there are four EM paths, and four encoders 42 each generate an EM signal for each of the four paths. However, it should be understood that the present invention should in no way be limited to four paths. Rather, the number of paths on the transmission medium 34 can be widely any number from one to more than one, including more than four.
參考圖2B，示出了由分配器40實施的用於建構四個向量V 0、V 1、V 2和V 3的一種可能排列的圖。每個向量包括N個顏色資訊樣本。 2B, there is shown a diagram of one possible arrangement implemented by the distributor 40 for constructing four vectors V0 , V1 , V2 and V3 . Each vector includes N samples of color information.
在此非排他性實施例中，樣本集22的暴露顏色資訊分別是“RGB”。在此示例中，樣本集22的暴露的RGB樣本從左到右被分配給向量V 0、V 1、V 2和V 3。換言之，最左邊樣本的“R”、“G”和“B”值以及下一個樣本集22的“R”訊號被分配給向量V 0，而下一個樣本 22 的下一個（從左到右）“G”、“B”、“R”和“G”值被分配給向量 V 1，下一個（從左到右）“B”、“R”、“G”和“B”值分配給向量 V 2，下一個（從左到右）“R”、“G”、“R”和“R”值分配給向量 V 3。一旦第四向量V 3被分配了它的訊號，就重複上述過程，直到四個向量V 0、V 1、V 2和V 3中的每一個都具有N個樣本。在多個實施例中，N個樣本的數量可以廣泛地變化。 In this non-exclusive embodiment, the exposed color information of the sample set 22 is "RGB", respectively. In this example, the exposed RGB samples of the sample set 22 are assigned to vectors V 0 , V 1 , V 2 , and V 3 from left to right. In other words, the "R", "G", and "B" values of the leftmost sample and the "R" signal of the next sample set 22 are assigned to vector V 0 , while the next (from left to right) "G", "B", "R", and "G" values of the next sample 22 are assigned to vector V 1 , the next (from left to right) "B", "R", "G", and "B" values are assigned to vector V 2 , and the next (from left to right) "R", "G", "R", and "R" values are assigned to vector V 3 . Once the fourth vector V3 has been assigned its signal, the above process is repeated until each of the four vectors V0 , V1 , V2 , and V3 has N samples. In various embodiments, the number of N samples can vary widely.
作為示例，考慮非排他性實施例N= 60。在這種情況下，四個向量 V 0、V 1、V 2和 V 3中包括的N個樣本的總數為 240 （60 x 4 = 240）。四個編碼器輸入向量 V 0、V 1、V 2和 V 3在完全建立時包括 80 個不同樣本集 22 （240/3 = 80） 的樣本（其中 S = 3）。換句話說： ● 向量 V 0包括樣本 P 0、N 0到 P 0、N N-1； ● 向量 V 1包括樣本 P 1、N 0到 P 1、N N-1； ● 向量 V 2包括樣本 P 2、N 0到 P 2、N N-1；以及 ● 向量 V 3包括樣本 P 3、N 0到 P 3、N N-1。 As an example, consider the non-exclusive embodiment N = 60. In this case, the total number of N samples included in the four vectors V 0 , V 1 , V 2 and V 3 is 240 (60 x 4 = 240). The four encoder input vectors V 0 , V 1 , V 2 and V 3 include samples from 80 different sample sets 22 (240/3 = 80) when fully established (where S = 3). In other words: ● vector V0 includes samples P0 , N0 to P0 , NN-1 ; ● vector V1 includes samples P1 , N0 to P1 , NN-1 ; ● vector V2 includes samples P2 , N0 to P2 , NN-1 ; and ● vector V3 includes samples P3 , N0 to P3 , NN-1 .
應當理解，以上示例僅僅是說明性的並且在任何方面都不應被解釋為限制性的。樣本的數量N可以多於或少於60個。此外，應當理解，（a）每個樣本集22的暴露的顏色資訊可以是任何顏色資訊（例如，Y、C、Cr、Cb等）並且不限於 RGB。It should be understood that the above examples are merely illustrative and should not be construed as limiting in any respect. The number N of samples may be more or less than 60. In addition, it should be understood that (a) the exposed color information of each sample set 22 may be any color information (e.g., Y, C, Cr, Cb, etc.) and is not limited to RGB.
傳輸介質34上的EM路徑的數量也可以廣泛地變化。因此，向量V的數量和編碼器42的數量也可以從僅一個或大於一的任何數量廣泛變化。The number of EM paths on transmission medium 34 may also vary widely. Thus, the number of vectors V and the number of encoders 42 may also vary widely from just one to any number greater than one.
還應該理解，用於建構向量的排列方案，無論數量如何，都是任意的。可以使用任何排列方案，僅限於在發送側使用的任何排列方案也用於接收側的任何排列方案。It should also be understood that the permutation scheme used to construct the vectors, regardless of the number, is arbitrary. Any permutation scheme can be used, as long as any permutation scheme used on the sending side is also used on the receiving side.
參考圖3，示出了SSVT發射器28的邏輯框圖。分配器-編碼器 40 包括組裝組 50、分級組 52、呈現組 54 和訊框控制器 56。編碼器塊 60 包括類比數位轉換器（DAC） 62和四個編碼器 42的組，一個對於傳輸介質 34 上的每個 EM 路徑。3, there is shown a logical block diagram of the SSVT transmitter 28. The distributor-encoder 40 includes an assembly group 50, a classification group 52, a presentation group 54, and a frame controller 56. The encoder block 60 includes an analog-to-digital converter (DAC) 62 and a group of four encoders 42, one for each EM path on the transmission medium 34.
分配器40被佈置成一個接一個地接收集合樣本22的串流的暴露的顏色資訊（例如，RGB）。作為回應，組裝組50根據樣本集22的輸入串流的暴露的顏色資訊（例如RGB）建構四個向量V 0、V 1、V 2和V 3。當接收到樣本集22時，根據預定排列它們被儲存在組裝組50。同樣，當建構每個包含N個樣本的向量時，分配器40可以使用任何數量的不同排列。 The distributor 40 is arranged to receive, one by one, the exposed color information (e.g., RGB) of the stream of the set samples 22. In response, the assembly unit 50 constructs four vectors V 0 , V 1 , V 2 , and V 3 from the exposed color information (e.g., RGB) of the input stream of the sample set 22. When the sample set 22 is received, they are stored in the assembly unit 50 according to a predetermined arrangement. Likewise, the distributor 40 may use any number of different arrangements when constructing each vector containing N samples.
分級組52促進四個向量V 0、V 1、V 2和V 3中的每一個的N個樣本從重計時器26使用的第一時鐘頻率或域到用於編碼的第二時鐘頻率或域的交叉以及在傳輸介質34上傳輸所產生的EM電位準訊號。如先前在上面的示例中討論的N＝60和S＝3，恰好表示80組RGB樣本的樣本包含在四個編碼器輸入向量V 0、V 1、V 2和 V 3中。 The staging group 52 facilitates the crossing of the N samples of each of the four vectors V 0 , V 1 , V 2 and V 3 from the first clock frequency or domain used by the retimer 26 to the second clock frequency or domain used for encoding and the transmission of the resulting EM electric level signals over the transmission medium 34. As previously discussed in the example above with N=60 and S=3, samples representing exactly 80 sets of RGB samples are contained in the four encoder input vectors V 0 , V 1 , V 2 and V 3 .
在多個實施例中，第一時鐘頻率可以更快、更慢或與第二時鐘頻率相同。第一時鐘頻率 f_pix 由視訊源 12 選擇的視訊格式確定。第二時鐘頻率 f_ssvt 是 f_pix、傳輸介質 34 中 EM 路徑的數量 P、每個輸入/輸出樣本集中的樣本數量 S以及 SSVT 變換參數 N（輸入/輸出向量位置的數量）和 L（每個SSDS代碼的長度）的函數，其中f_ssvt = (f_pix * S * L) / (P * N)。藉由這種安排，輸入時鐘 （pix_clk） 以一種速率振盪，SSVT 時鐘 （ssvt_clk） 以不同的速率振盪。它們可以相同或不同。擴散的出現是因為N個輸入樣本（單個顏色分量）被分配給輸入向量；然後編碼器在準備下一個輸入向量的同時執行前向變換（基於SSDS的 CDMA）。In various embodiments, the first clock frequency can be faster, slower, or the same as the second clock frequency. The first clock frequency f_pix is determined by the video format selected by the video source 12. The second clock frequency f_ssvt is a function of f_pix, the number P of EM paths in the transmission medium 34, the number S of samples in each input/output sample set, and the SSVT transform parameters N (the number of input/output vector positions) and L (the length of each SSDS code), where f_ssvt = (f_pix * S * L) / (P * N). With this arrangement, the input clock (pix_clk) oscillates at one rate and the SSVT clock (ssvt_clk) oscillates at a different rate. They can be the same or different. Diffusion occurs because the N input samples (of a single color component) are distributed into an input vector; the encoder then performs a forward transform (SSDS-based CDMA) while preparing the next input vector.
呈現組54將四個編碼器輸入向量V 0、V 1、V 2和V 3中的每一個的N個樣本（N 0到N -1）提供給編碼器塊60。 The presentation group 54 provides N samples (N 0 to N −1 ) of each of the four encoder input vectors V 0 , V 1 , V 2 , and V 3 to the encoder block 60 .
控制器56控制組裝組50、分級組52和呈現組54的操作和定時。具體地，控制器負責在建構四個編碼器輸入向量 V 0、V 1、V 2和 V 3時定義所使用的排列和樣本的數量N。控制器56還負責協調從第一時鐘頻率到第二時鐘頻率的時鐘域交叉，如分級組52所執行的那樣。控制器56進一步負責協調呈現組54向編碼器塊60提供四個編碼器輸入向量V 0、V 1、V 2和V 3的每一個的N（N 0到N -1）個樣本的時機。 The controller 56 controls the operation and timing of the assembly group 50, the staging group 52, and the presentation group 54. Specifically, the controller is responsible for defining the arrangement and number of samples N used when constructing the four encoder input vectors V 0 , V 1 , V 2 , and V 3 . The controller 56 is also responsible for coordinating the clock domain crossing from the first clock frequency to the second clock frequency, as performed by the staging group 52 . The controller 56 is further responsible for coordinating the timing of the presentation group 54 providing the N (N 0 to N -1 ) samples of each of the four encoder input vectors V 0 , V 1 , V 2 , and V 3 to the encoder block 60 .
在編碼器塊 60 內，提供了多個類比數位轉換器（DAC） 62，每個數模轉換器被佈置為接收共同分配給四個編碼器輸入向量 V 0、V 1、V 2和 V 3的P*N樣本（P0, N 0到P 3, N N-1）之一。每個 DAC 62 從數位域轉換其接收到的樣本成電壓訊號的差分對，其量與其輸入的數位值成正比。在非排他性實施例中，DAC 62的輸出範圍從最大電壓到最小電壓。 Within the encoder block 60, a plurality of analog-to-digital converters (DACs) 62 are provided, each of which is arranged to receive one of the P*N samples (P0, N0 to P3 , N N-1 ) commonly assigned to the four encoder input vectors V0 , V1 , V2 , and V3 . Each DAC 62 converts the samples it receives from the digital domain into a differential pair of voltage signals whose magnitude is proportional to the digital value of its input. In a non-exclusive embodiment, the output range of the DAC 62 is from a maximum voltage to a minimum voltage.
分別為四個編碼器輸入向量V 0、V 1、V 2和V 3提供四個編碼器42。每個編碼器42接收其編碼器輸入向量的N個樣本（N 0到N -1）中的每一個的差分訊號對，使用正交SSVT“碼片”調製N個差分電壓訊號對中的每一個，累積調製值然後產生差分EM電位準輸出訊號。由於在此示例中存在四個編碼器42，因此存在經由傳輸介質34同時傳輸的EM電位準訊號（Level 0到Level 1）。 Four encoders 42 are provided for four encoder input vectors V 0 , V 1 , V 2 and V 3 respectively. Each encoder 42 receives a differential signal pair for each of the N samples (N 0 to N -1 ) of its encoder input vector, modulates each of the N differential voltage signal pairs using an orthogonal SSVT "chip", accumulates the modulated values and then generates a differential EM electrical level output signal. Since there are four encoders 42 in this example, there are EM electrical level signals (Level 0 to Level 1 ) transmitted simultaneously via the transmission medium 34.
定序器電路65協調DAC 62和編碼器42的操作時機。定序器電路65負責控制DAC 62和編碼器42的時鐘。如下文詳細描述的，定序器電路65還負責產生兩個時鐘相位訊號“clk 1”和“clk 2”，它們負責控制編碼器42的操作。The sequencer circuit 65 coordinates the timing of the operation of the DAC 62 and the encoder 42. The sequencer circuit 65 is responsible for controlling the clocks of the DAC 62 and the encoder 42. As described in detail below, the sequencer circuit 65 is also responsible for generating two clock phase signals "clk 1" and "clk 2" that are responsible for controlling the operation of the encoder 42.
參考圖4，示出了用於輸入向量V之一的編碼器42的電路圖。編碼器電路42包括多個乘法器級70和包括差分放大器74的累加器級72。4, there is shown a circuit diagram of an encoder 42 for one of the input vectors V. The encoder circuit 42 includes a plurality of multiplier stages 70 and an accumulator stage 72 including a differential amplifier 74.
每個乘法器級70被佈置為在第一（+）和第二（-）終端處分別接收來自DAC66之一的差分樣本訊號對（+Sample N-1/-Sample N-1到+Sample 0/-Sample 0）。每個乘法器級70還包括用於接收展頻直接序列（SSDS）“碼片”的終端、逆變器72、開關組S1-S1、S2-S2和S3-S3、由clk 1和clk驅動的開關組、第一電壓軌上的第一存放裝置C1和第二電壓軌上的第二存放裝置C2。 Each multiplier stage 70 is arranged to receive a differential sample signal pair (+Sample N-1 /-Sample N-1 to +Sample 0 /-Sample 0 ) from one of the DACs 66 at first (+) and second (-) terminals, respectively. Each multiplier stage 70 also includes terminals for receiving spread spectrum direct sequence (SSDS) "chips", an inverter 72, switch groups S1-S1, S2-S2 and S3-S3, switch groups driven by clk 1 and clk, a first storage device C1 on a first voltage rail and a second storage device C2 on a second voltage rail.
在操作期間，每個乘法器級70根據接收的SSDS碼片的值，藉由條件性地乘以（+1）或（-1）來調製其接收的類比訊號差分對。如果SSDS碼片為 （+1），則當 clk 1 具有有效狀態時，開關對 S1-S1 和 S3-S3 閉合，而開關對 S2-S2 保持打開狀態。結果，+/-樣本的差分對都被分別儲存在存放裝置C1和C2上而沒有任何反轉（即，乘以+1）。另一方面，如果SSDS碼片為（-1），則發生上述的補數。換言之，開關對 S1-S1 打開，而開關對 S2-S2 和 S3-S3 在 clk 1 具有有效狀態時閉合。結果，差分樣本對被反轉（乘以 -1）並分別儲存在 C1 和 C2 上。During operation, each multiplier stage 70 modulates its received analog signal differential pair by conditionally multiplying by (+1) or (-1) depending on the value of the received SSDS code chip. If the SSDS code chip is (+1), then when clk 1 has a valid state, switch pairs S1-S1 and S3-S3 are closed, while switch pair S2-S2 remains open. As a result, the differential pairs of +/- samples are stored in storage devices C1 and C2, respectively, without any inversion (i.e., multiplication by +1). On the other hand, if the SSDS code chip is (-1), the above-mentioned complement occurs. In other words, switch pair S1-S1 is open, while switch pairs S2-S2 and S3-S3 are closed when clk 1 has a valid state. As a result, the difference sample pairs are inverted (multiplied by -1) and stored on C1 and C2 respectively.
累加器級 72 操作以在所有乘法器級 70 的存放裝置 C1 和 C2 上累加電荷。當 clk 1 過渡為非有效狀態且 clk 2 過渡為有效狀態時，所有 clk 1 控制開關（S4-S4）閉合並且 clk 2 控制開關 （S5-S5, S6-S6） 打開。結果，所有乘法器級70的第一存放裝置C1上的所有電荷被放大器78放大並累積在差分放大器74的第一輸入上，而所有乘法器級70的第二存放裝置C2上的所有電荷由放大器78放大並累積在差分放大器74的第二輸入上。作為回應，差分放大器74產生一對差分電磁（EM）電位準訊號。The accumulator stage 72 operates to accumulate charge on the storage devices C1 and C2 of all multiplier stages 70. When clk 1 transitions to an inactive state and clk 2 transitions to an active state, all clk 1 control switches (S4-S4) are closed and clk 2 control switches (S5-S5, S6-S6) are opened. As a result, all the charge on the first storage device C1 of all multiplier stages 70 is amplified by the amplifier 78 and accumulated on the first input of the differential amplifier 74, and all the charge on the second storage device C2 of all multiplier stages 70 is amplified by the amplifier 78 and accumulated on the second input of the differential amplifier 74. In response, the differential amplifier 74 generates a pair of differential electromagnetic (EM) potential level signals.
對所有四個向量V 0、V 1、V 2和V 3執行上述過程。此外，只要 SSVT 發射器 28 接收到樣本集 22 的串流，就不斷重複上述過程。作為回應，四個差分 EM 輸出電位準訊號串流經由傳輸介質34被發送到 SSVT 接收器 30。 接收器 The above process is performed for all four vectors V 0 , V 1 , V 2 and V 3 . Furthermore, the above process is repeated as long as the SSVT transmitter 28 receives the stream of sample sets 22 . In response, four differential EM output level signal streams are sent to the SSVT receiver 30 via the transmission medium 34 .
在接收側，SSVT RX 30負責將經由傳輸介質34接收的四個差分EM電位準輸出訊號串流解碼回適合顯示的格式。一旦採用合適的格式，包含在樣本22中的視訊內容（例如，訊號S）可以逐訊框呈現在視訊顯示器上。結果，視訊源12的視訊捕獲可以由視訊接收端14重新創建。可替代地，可以儲存解碼的視訊資訊以供稍後以時移模式顯示。On the receiving side, SSVT RX 30 is responsible for decoding the four differential EM electrical level output signal streams received via transmission medium 34 back into a format suitable for display. Once in the appropriate format, the video content (e.g., signal S) contained in samples 22 can be presented on a video display frame by frame. As a result, the video capture of video source 12 can be recreated by video sink 14. Alternatively, the decoded video information can be stored for later display in a time-shifted mode.
SSVT RX 30在發送側執行SSVT TX 28的逆操作。 SSVT RX 30使用四個解碼器80和收集器46。解碼器80將四個差分EM電位準輸出訊號重建為四個解碼器輸出向量。然後，收集器 46 將解碼器輸出向量的樣本分配給樣本集22的原始串流，每個包括與串流中該位置處的原始S個樣本相對應的S個重建樣本。SSVT RX 30 performs the inverse operation of SSVT TX 28 on the transmit side. SSVT RX 30 uses four decoders 80 and collectors 46. Decoders 80 reconstruct the four differential EM electrical level output signals into four decoder output vectors. Collectors 46 then assign samples of the decoder output vectors to the original stream of sample sets 22, each including S reconstructed samples corresponding to the original S samples at that position in the stream.
參考圖5A，示出了視訊接收端14的SSVT RX 30、重計時器32和視訊顯示器85的詳細框圖。 P解碼器80（標記為0到P-1）被佈置為分別接收差分EM電位準訊號Level 0到Level P-1。作為回應，每個解碼器80產生N個差分對重建樣本（Sample 0到Sample N-1）。在有四個解碼器80（P＝4）的情況下，分別建構四個向量V 0、V 1、V 2和V 3。 5A, a detailed block diagram of the SSVT RX 30, the retimer 32, and the video display 85 of the video receiver 14 is shown. The P decoders 80 (labeled 0 to P-1) are arranged to receive the differential EM level signals Level 0 to Level P-1, respectively. In response, each decoder 80 generates N differential pair reconstruction samples (Sample 0 to Sample N-1 ). In the case of four decoders 80 (P=4), four vectors V 0 , V 1 , V 2 , and V 3 are constructed respectively.
重建組82分別在每個解碼間隔結束時對四個解碼器輸出向量V 0、V 1、V 2和V 3中的每一個進行取樣並保持N個重建樣本（Sample 0到Sample N-1）的差分對中的每一個。分別為四個向量V 0、V 1、V 2和V 3中的每一個的N個樣本（Sample 0到Sample N-1）中的每一個提供類比數位轉換器（ADC）84。每個 ADC 將其接收到的差分電壓訊號對轉換為相應的數位值，從而分別為四個向量 V 0、V 1、V 2和 V 3中的每一個產生數位樣本（Sample N-1到 Sample 0）。 ADC 以時脈速率 = f_ssvt /L運行。 The reconstruction group 82 samples each of the four decoder output vectors V 0 , V 1 , V 2 and V 3 at the end of each decoding interval and holds each of the differential pairs of N reconstructed samples (Sample 0 to Sample N-1 ). An analog-to-digital converter (ADC) 84 is provided for each of the N samples (Sample 0 to Sample N-1 ) of each of the four vectors V 0 , V 1 , V 2 and V 3 . Each ADC converts the differential voltage signal pair it receives into a corresponding digital value, thereby generating a digital sample (Sample N-1 to Sample 0 ) for each of the four vectors V 0 , V 1 , V 2 and V 3 . The ADC operates at a clock rate = f_ssvt /L.
收集器46包括分級組86和拆分組88。分級組86接收四個解碼器輸出向量V 0、V 1、V 2和V 3中的每一個的所有重建樣本（N n-1到N 0）。拆分組88（a）使用與在發送側使用的相同排列方案，將四個解碼器輸出向量V 0、V 1、V 2和V 3中的每一個的樣本（Sample N-1到Sample 0）拆分為樣本集22的串流（例如，在此示例中，“對於RGB像素S=3”）的暴露的顏色資訊（例如，S訊號），並且（b）將重建樣本從第二時鐘域交叉回到第一時鐘域。然後將重建樣本集22的串流提供至重計時器32，重計時器32重新格式化視訊訊號。重計時器32的輸出因此是按時間排序的樣本集22的序列的再創造。視訊接收端14包括DAC 103組和視訊顯示器85。DAC 103組負責將在數位域中的樣本22轉換回到類比域。在一個實施例中，為顯示器85中的每一行提供DAC 103。一旦樣本22被轉換為模擬域，它們就以眾所周知的方式顯示在視訊顯示器85上。 The collector 46 includes a staging group 86 and a splitting group 88. The staging group 86 receives all reconstructed samples ( Nn-1 to N0 ) of each of the four decoder output vectors V0 , V1 , V2 , and V3 . The splitting group 88 (a) splits the samples (Sample N-1 to Sample 0 ) of each of the four decoder output vectors V0 , V1 , V2 , and V3 into a stream of sample sets 22 (e.g., exposed color information (e.g., S signal) in this example, "for RGB pixel S=3") using the same arrangement scheme as used on the transmitting side, and (b) crosses the reconstructed samples from the second clock domain back to the first clock domain. The stream of reconstructed sample sets 22 is then provided to the retimer 32, which reformats the video signal. The output of the retimer 32 is therefore a recreation of the sequence of sample sets 22 ordered in time. The video receiving end 14 includes a set of DACs 103 and a video display 85. The set of DACs 103 is responsible for converting the samples 22 in the digital domain back to the analog domain. In one embodiment, a DAC 103 is provided for each row in the display 85. Once the samples 22 are converted to the analog domain, they are displayed on the video display 85 in a well-known manner.
SSVT RX 30還包括通道對準器87和收集器控制器89，其從每個解碼器80接收定框資訊和孔徑資訊。作為回應，收集器控制器89協調分級組86和/或拆分組 88 的時機以確保提供至拆分組的所有樣本都來自 SSVT TX 28 發送電位準訊號的公共時間間隔。結果，（a） 組 88 的拆分可能延遲到所有樣本被接收並且（b）傳輸介質34的單個通道不必都具有相同的長度，因為拆分組88補償了任何時機差。SSVT RX 30 also includes a channel aligner 87 and a collector controller 89 that receives framing information and aperture information from each decoder 80. In response, collector controller 89 coordinates the timing of the grading groups 86 and/or the split groups 88 to ensure that all samples provided to the split groups are from a common time interval during which the electrical level signal is transmitted by SSVT TX 28. As a result, (a) the splitting of group 88 may be delayed until all samples are received and (b) the individual channels of transmission medium 34 need not all be of the same length because the split groups 88 compensate for any timing differences.
圖6是四個編碼器80之一的邏輯圖。編碼器80包括差分放大器92和取樣及保持電路94，其被佈置為接收、取樣及保持經由傳輸介質34接收的四個差分EM電位準訊號之一。然後將樣本的EM電位準訊號提供至N個解碼器軌道電路96（N n-1到N 0）中的每一個。定序器控制器98向分別應用於發送側的N個解碼器軌道電路96中的每一個提供相同的SSDS碼片。結果，樣本輸出（N n-1到N 0）被提供至重建組82。同樣，在發送側使用的相同SSDS碼片被每個解碼器軌道電路96使用。結果，解調的樣本N n-1到 N 0與發送側調製之前相同。 FIG6 is a logic diagram of one of the four encoders 80. The encoder 80 includes a differential amplifier 92 and a sample and hold circuit 94, which is arranged to receive, sample and hold one of four differential EM electrical level signals received via the transmission medium 34. The sampled EM electrical level signal is then provided to each of the N decoder track circuits 96 (Nn -1 to N0 ). The sequencer controller 98 provides the same SSDS code chip to each of the N decoder track circuits 96 respectively applied to the transmit side. As a result, the sample output ( Nn-1 to N0 ) is provided to the reconstruction group 82. Likewise, the same SSDS code chip used on the transmit side is used by each decoder track circuit 96. As a result, the demodulated samples Nn-1 to N0 are the same as before modulation on the transmit side.
收集器控制器89負責跟蹤任何排列並確保拆分組88應用與在發送側建構向量V 0、V 1、V 2和V 3時使用的相同排列。 The collector controller 89 is responsible for keeping track of any permutations and ensuring that the split group 88 applies the same permutation as was used when constructing vectors V 0 , V 1 , V 2 , and V 3 on the sending side.
每個解碼器80的收集器控制器89還產生多個控制訊號，包括選通訊訊號、組的末端（eob）訊號、孔徑訊號和定框訊號。選通訊訊號被提供至ADC 84並且指示給定重建組內容的模數轉換過程何時可以開始的時機。eob訊號被提供至重建組82並且表示分級組86完全充滿樣本的時機。當這種情況發生時，eob 訊號起效，預期下一組重建樣本（N n-1到N 0），清除解碼器軌道96和分級組86。孔徑控制訊號被提供至取樣及保持電路94，定框訊號被提供至通道對準器87和收集器控制器89。 替代實施例 The collector controller 89 of each decoder 80 also generates a plurality of control signals, including a gate communication signal, an end of group (eob) signal, an aperture signal, and a framing signal. The gate communication signal is provided to the ADC 84 and indicates when the analog-to-digital conversion process of the contents of a given reconstruction group can begin. The eob signal is provided to the reconstruction group 82 and indicates when the classification group 86 is completely filled with samples. When this occurs, the eob signal becomes active, anticipating the next set of reconstructed samples ( Nn-1 to N0 ), clearing the decoder track 96 and the classification group 86. The aperture control signal is provided to the sample and hold circuit 94, and the framing signal is provided to the channel aligner 87 and the collector controller 89. Alternative Embodiments
在上述實施例中，ADC 84將解碼的樣本轉換至數位域中，並且視訊接收端14中的ADC 103將有序的樣本集22在顯示之前轉換回類比域。In the above embodiment, ADC 84 converts the decoded samples into the digital domain, and ADC 103 in the video receiver 14 converts the ordered set of samples 22 back into the analog domain before display.
如圖5B中所示，示出了替代實施例，其中來自重建組82的樣本輸出保持在模擬域中，因此消除了對ADC 103和其他元件的需要。藉由此實施例，可選地消除ADC 84、拆分組88和重計時器32。相反，類比樣本輸出被提供至分級儲存組86，分級儲存組86對在發送側建構向量V 0到V 3時使用的樣本執行相同的排列。分級組86的樣本輸出然後用於藉由可選的電位準轉換器（未示出）直接驅動視訊接收端的顯示器85。由於不同類型的顯示器需要不同的電壓來驅動它們的顯示面板，因此可以根據需要使用電位準轉換器來縮放分級組的視訊樣本輸出的電壓。如本領域已知的，可以使用任何合適的電位準轉換器，諸如鎖存器類型或逆變器類型。 As shown in FIG. 5B , an alternative embodiment is shown in which the sample output from the reconstruction group 82 is maintained in the analog domain, thereby eliminating the need for the ADC 103 and other components. With this embodiment, the ADC 84, the split group 88, and the re-timer 32 are optionally eliminated. Instead, the analog sample output is provided to the graded storage group 86, which performs the same arrangement on the samples used when constructing the vectors V 0 to V 3 on the transmitting side. The sample output of the graded group 86 is then used to directly drive the display 85 at the video receiving end by means of an optional level converter (not shown). Since different types of displays require different voltages to drive their display panels, the level converter can be used to scale the voltage of the video sample output of the graded group as needed. As is known in the art, any suitable level converter may be used, such as a latch type or an inverter type.
對於此實施例，收集器控制器89執行若干功能。收集器控制器98負責保持續跟蹤並向分級組86提供要使用的正確排列選擇。收集器控制器89還可以向顯示器85提供增益和伽馬值。增益確定應用了多少放大並且伽馬曲線將光通量與感知亮度相關聯，這使人類對光通量的光學感知線性化。定框訊號表示在顯示器85上建構視訊訊框的時機。反轉訊號可以可選地用於控制電位準轉換器以反轉或不反轉視訊樣本輸出，這可能是某些類型的顯示面板，諸如OLED所需要的。如果使用電位準轉換器，則電位準轉換器的輸出通常被鎖存。在這樣的實施例中，可以使用鎖存訊號來控制任何移位元視訊樣本輸出訊號的電位準的鎖存和釋放的時機。最後，閘極驅動器控制訊號用於通常用於驅動許多顯示器的水平行的閘極驅動器電路。For this embodiment, the collector controller 89 performs several functions. The collector controller 98 is responsible for keeping track and providing the grading group 86 with the correct arrangement selection to be used. The collector controller 89 can also provide gain and gamma values to the display 85. The gain determines how much amplification is applied and the gamma curve relates light flux to perceived brightness, which linearizes the human optical perception of light flux. The frame signal indicates when to construct a video frame on the display 85. The inversion signal can optionally be used to control an electric level converter to invert or not invert the video sample output, which may be required for certain types of display panels, such as OLED. If an electric level converter is used, the output of the electric level converter is typically latched. In such an embodiment, a latch signal may be used to control the timing of latching and releasing the electrical level of any of the bit-shifted video sample output signals. Finally, a gate driver control signal is used for a gate driver circuit commonly used to drive the horizontal lines of many displays.
參考圖7，示出了表示性解碼器軌道電路96的示意圖。解碼器軌道電路96包括乘法器部分100和累加器部分102。乘法器部分100包括第一對開關S1-S1、第二對開關S2-S2、第三對開關S3-S3和分別位於第一（正）和第二（負）電源軌線上的一對電容器 C1-C1。累加器部分102包括附加的電晶體對S4-S4、S5-S5、S6-S6和S7-S7、運算放大器104以及分別在第一（正）和第二（負）電源軌線上的一對電容器C F和C F。 7, a schematic diagram of a representative decoder track circuit 96 is shown. The decoder track circuit 96 includes a multiplier portion 100 and an accumulator portion 102. The multiplier portion 100 includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1-C1 located on a first (positive) and second (negative) power rail, respectively. The accumulator portion 102 includes additional transistor pairs S4-S4, S5-S5, S6-S6, and S7-S7, an operational amplifier 104, and a pair of capacitors CF and CF located on a first (positive) and second (negative) power rail, respectively.
對於每個解調週期，在第一電位準輸入（電位準+）端和第二電位準輸入（電位準-）端處接收差分EM電位準訊號對。根據接收到的SSDS碼片的值，差分EM電位準訊號對在乘法器部分100中藉由乘以（1）或負（-1）條件性地反轉來解調。For each demodulation cycle, a differential EM level signal pair is received at a first level input (level +) terminal and a second level input (level -) terminal. The differential EM level signal pair is demodulated in the multiplier section 100 by multiplying by (1) or conditionally inverting by (-1) depending on the value of the received SSDS chip.
如果SSDS碼片具有（+1）的值，則當 clk 1 啟動時，電晶體對 S1-S1 和 S3-S3 閉合，而 S2-S2 保持打開。結果，第一電位準輸入（電位準+）端和第二電位準輸入（電位準-）的電壓值分別傳遞到正負軌上的兩個電容器C1和C1上並由其儲存。換句話說，輸入值乘以（+1）並且不會發生反轉。If the SSDS chip has a value of (+1), when clk 1 is activated, the transistor pairs S1-S1 and S3-S3 are closed, while S2-S2 remains open. As a result, the voltage values of the first potential input (potential +) terminal and the second potential input (potential -) terminal are respectively transferred to and stored by the two capacitors C1 and C1 on the positive and negative rails. In other words, the input value is multiplied by (+1) and is not inverted.
如果SSDS碼片的值為-1，則當clk 1啟動時，S1-S1開關都關閉，而開關S2-S2和S3-S3都打開。結果，在正或第一（+）端和負或第二（-）端處接收的電壓值被交換。換句話說，在第一或正端提供的輸入電壓值被引導並儲存在下負軌上的電容器 C1 上，而在第二或（-）端上提供的電壓值被切換至並儲存在正上軌上的電容器 C1 上。在輸入端接收到的電壓值由此被反轉或乘以（-1）。If the value of the SSDS chip is -1, then when clk 1 is activated, the S1-S1 switches are both closed, while switches S2-S2 and S3-S3 are both opened. As a result, the voltage values received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided at the first or positive terminal is directed and stored on capacitor C1 on the lower negative rail, while the voltage value provided at the second or (-) terminal is switched to and stored on capacitor C1 on the positive upper rail. The voltage value received at the input terminal is thereby inverted or multiplied by (-1).
當 clk 1 過渡為不啟動時，C1 和 C1 上的累積電荷保持不變。當 clk 2 過渡為啟動，然後電晶體對 S4-S4 打開，而電晶體對 S5-S5 和 S6-S6 閉合。然後將上軌或正軌上的電容器C1和下軌或負軌上的C1上的累積電荷提供至運算放大器104的差分輸入。運算放大器104的輸出是在發送側進行編碼之前的原始+/-樣本對。When clk 1 transitions to inactive, the accumulated charge on C1 and C1 remains unchanged. When clk 2 transitions to active, then transistor pair S4-S4 is turned on, while transistor pairs S5-S5 and S6-S6 are closed. The accumulated charge on capacitor C1 on the upper or positive rail and C1 on the lower or negative rail is then provided to the differential input of op amp 104. The output of op amp 104 is the raw +/- sample pair before encoding on the transmit side.
當 Clk 2 啟動時，兩個電容器 C1 和 C1 上的累積電荷也被傳遞到上軌或正軌和下軌或負軌上的電容器 CF 和 CF。在每個解調週期中，上軌和下軌上的電容器 C1 和 C1 上的電荷分別累積到上軌和下軌上的兩個電容器 CF 和 CF 上。當 clk 1 和 eob 訊號都有效時，電晶體對 S7-S7 都閉合，使電容器 CF 和 CF 中的每一個的極板短路。結果，積累的電荷被去除，兩個電容器CF和CF被復位並為下一個解調週期做好準備。When Clk 2 is enabled, the accumulated charge on the two capacitors C1 and C1 is also transferred to the capacitors CF and CF on the upper or positive rail and the lower or negative rail. In each demodulation cycle, the charge on the capacitors C1 and C1 on the upper and lower rails is accumulated on the two capacitors CF and CF on the upper and lower rails, respectively. When both clk 1 and eob signals are valid, the transistor pair S7-S7 is closed, shorting the plates of each of the capacitors CF and CF. As a result, the accumulated charge is removed and the two capacitors CF and CF are reset and ready for the next demodulation cycle.
由於每個解碼器80具有N個解碼器軌道電路96，N個解碼或原始+/-樣本對在每個解調週期被重新創建。然後將這些N+/- 樣本對提供至重建組 82、ADC 84，然後是收集器 46，包括分級組 86 和拆分組 88，最後是重計時器 32。結果，原始樣本集22用其原始顏色內容資訊（例如，對於RGB，S＝3）重新創建，並準備好在視訊接收端14的顯示器85上顯示。Since each decoder 80 has N decoder track circuits 96, N decoded or original +/- sample pairs are recreated at each demodulation cycle. These N +/- sample pairs are then provided to the reconstruction group 82, the ADC 84, then the collector 46, including the classification group 86 and the decomposition group 88, and finally the re-timer 32. As a result, the original sample set 22 is recreated with its original color content information (e.g., for RGB, S=3) and is ready to be displayed on the display 85 of the video receiving end 14.
解碼器軌道96在連續L個週期上重建輸入電位準樣本，用該軌道代碼的連續SSDS碼片解調每個連續輸入電位準。每個L次解調的結果在回饋電容器 CF 上累加。當 eob 在 clk1 對應於解碼週期的第一個解調週期期間生效時，CF 在 eob 之後被清除，以便它可以從零伏或其他一些復位電壓開始再次累積。在多個非排他性實施例中，L的值是預定參數。通常，參數L越高，SSDS過程增益越大，並且SSVT訊號在傳輸介質34上傳輸的電彈性越好。另一方面，參數L越高，SSVT調製的應用所需的頻率就越高，由於傳輸介質34引起的***損耗，這可能會損害訊號品質。The decoder track 96 reconstructs input potential samples over L consecutive cycles, demodulating each consecutive input potential level with the consecutive SSDS code chips encoded by the track. The results of each L demodulation are accumulated on the feedback capacitor CF. When eob takes effect during the first demodulation cycle corresponding to the decoding cycle in clk1, CF is cleared after eob so that it can accumulate again starting from zero volts or some other reset voltage. In multiple non-exclusive embodiments, the value of L is a predetermined parameter. Generally, the higher the parameter L, the greater the SSDS process gain and the better the electroelasticity of the SSVT signal transmitted on the transmission medium 34. On the other hand, the higher the parameter L is, the higher the frequency required for the application of SSVT modulation, which may deteriorate the signal quality due to the insertion loss caused by the transmission medium 34.
用四個解碼器80中的每一個反復重複上述解調迴圈。最終結果是恢復按時間排序的樣本集22的原始串，每個樣本具有它們的原始顏色內容資訊（即，樣本集 S ）。如本領域已知的，樣本集22隨後被處理並顯示在視訊接收端14的顯示器85上。可替代地，可以將恢復的樣本集22儲存在接收側，以便以時移模式顯示。 無源乘法累加器解碼器 The above demodulation loop is repeated repeatedly with each of the four decoders 80. The end result is the recovery of the original string of time-ordered sample sets 22, each with their original color content information (i.e., sample set S). The sample set 22 is then processed and displayed on a display 85 at the video receiving end 14, as is known in the art. Alternatively, the recovered sample set 22 may be stored on the receiving side for display in a time-shifted mode. Passive Multiplier Accumulator Decoder
在替代實施例中，無源乘法累加器解碼器可以可選地用於解碼器塊80中，如關於圖5A所描述的。如下文詳細描述的，無源乘法累加器處理經由傳輸介質34接收的視訊媒體樣本的（L）差分對組，其中（L）是用於對傳輸前的媒體進行編碼的SSDS碼的長度。此解碼器是無源的，因為在解碼過程中不使用有源元件，諸如放大器。此解碼器還具有乘法累加器的特徵，因為在解碼過程中，（L）個差分樣本對的乘積結果及其對應的 SSDS碼片值被累加或儲存在多個存放裝置（例如電容器）上。In an alternative embodiment, a passive multiplier-accumulator decoder may optionally be used in the decoder block 80, as described with respect to FIG. 5A. As described in detail below, the passive multiplier-accumulator processes (L) differential pairs of video media samples received via the transmission medium 34, where (L) is the length of the SSDS code used to encode the media before transmission. This decoder is passive because no active components, such as amplifiers, are used in the decoding process. This decoder also has the characteristics of a multiplier-accumulator because during the decoding process, the product results of the (L) differential sample pairs and their corresponding SSDS code chip values are accumulated or stored in multiple storage devices (e.g., capacitors).
參考圖8，示出了無源乘法累加器編碼器120。根據一個實施例，無源乘法累加器編碼器120包括碼片乘法器級122、第一儲存組A，包括（+）組（L）電容器和（-）組（L）電容器，以及第一對電容器129。8, a passive multiplier accumulator encoder 120 is shown. According to one embodiment, the passive multiplier accumulator encoder 120 includes a chip multiplier stage 122, a first storage group A, including a (+) group (L) capacitors and a (-) group (L) capacitors, and a first pair of capacitors 129.
在可選實施例中，還提供了具有正（+）輸入端和負輸入端（-）的差分放大器124。在此實施例中，負（-）輸入端藉由第一電容器129選擇性地耦接到（+）組電容器（L），而正（+）輸入端藉由第二個電容器129選擇性地耦接到（-）組（L）電容器。In an alternative embodiment, a differential amplifier 124 having a positive (+) input and a negative input (-) is also provided. In this embodiment, the negative (-) input is selectively coupled to the (+) set of capacitors (L) via a first capacitor 129, and the positive (+) input is selectively coupled to the (-) set of capacitors (L) via a second capacitor 129.
還分別提供了位於耦接在差分放大器124的（+/-）輸出和（-/+）輸入之間的回饋路徑上的一對復位元件128。藉由在 （+/-） 輸出和 （-/+）輸入之間提供負反饋，可以設置差分放大器124的增益。在非排他性實施例中，每個復位元件128包括電容器和開關（未示出）。A pair of reset elements 128 are also provided on the feedback path coupled between the (+/-) output and the (-/+) input of the differential amplifier 124. By providing negative feedback between the (+/-) output and the (-/+) input, the gain of the differential amplifier 124 can be set. In a non-exclusive embodiment, each reset element 128 includes a capacitor and a switch (not shown).
碼片乘法器級122被配置為經由傳輸介質34順序地接收已經由編碼器28使用如前所述的展頻直接序列（SSDS）編碼編碼的視訊媒體樣本的差分對。碼片乘法器級122還被配置為接收由用於分別由編碼器28對樣本的差分對進行編碼的相互正交的SSDS碼指定的SSDS碼片值。在非排他性實施例中，通道對準器87負責將正確的SSDS碼片值分別應用於每個接收到的差分對樣本。The chip multiplier stage 122 is configured to sequentially receive differential pairs of video media samples that have been encoded by the encoder 28 using spread spectrum direct sequence (SSDS) encoding as previously described via the transmission medium 34. The chip multiplier stage 122 is also configured to receive SSDS chip values specified by the mutually orthogonal SSDS codes used to encode the differential pairs of samples, respectively, by the encoder 28. In a non-exclusive embodiment, the channel aligner 87 is responsible for applying the correct SSDS chip value to each received differential pair of samples, respectively.
在操作期間，利用樣本時鐘Fssvt的每個時鐘週期接收一個差分對樣本。回應於每個接收到的差分對樣本，碼片乘法器級 122 執行以下操作： （1）將與編碼時使用的相互正交的SSDS碼相同的SSDS碼片值應用於接收到的差分對樣本； （2）將差分對樣本與應用的碼片值相乘。根據給定差分對樣本的應用碼片值的狀態，乘數為（+1）或（-1）。如果碼片值是第一狀態（例如，“1”），則乘數是（+1）。如果碼片值為第二狀態（例如，“0”），則乘數為（-1）；以及 （3）在儲存塊A中分別儲存與（+）和（-）對電容器相乘的乘積結果相稱的電壓電荷。當碼片值為（+1）時，則儲存電荷而不進行任何反轉。如果碼片值為（-1），則電荷在儲存前首先反轉。 During operation, a differential pair sample is received using each clock cycle of the sample clock Fssvt. In response to each received differential pair sample, the chip multiplier stage 122 performs the following operations: (1) Applying the same SSDS chip value as the mutually orthogonal SSDS code used in encoding to the received differential pair sample; (2) Multiplying the differential pair sample with the applied chip value. Depending on the state of the applied chip value for a given differential pair sample, the multiplier is (+1) or (-1). If the chip value is a first state (e.g., "1"), the multiplier is (+1). If the chip value is a second state (e.g., "0"), the multiplier is (-1); and (3) Store voltage charges corresponding to the product results of multiplying the (+) and (-) pair capacitors in storage block A, respectively. When the chip value is (+1), the charge is stored without any inversion. If the chip value is (-1), the charge is first inverted before being stored.
隨著視訊媒體的（L）個差分訊號對被順序接收，對每個樣本重複上述過程。結果，（+）和（-）組中的（L）電容器被順序寫入並儲存分別與接收到的（L）差分樣本的乘積相稱的電荷。As the (L) differential signal pairs of the video media are received sequentially, the above process is repeated for each sample. As a result, the (L) capacitors in the (+) and (-) groups are sequentially written and store charges proportional to the product of the received (L) differential samples, respectively.
一旦已經接收到（L）個差分樣本並且儲存組A的（+）和（-）電容器組的所有（L）個電容器已經儲存了乘積結果，無源乘法累加器編碼器120操作以產生解碼的差分視訊媒體樣本輸出（即Sample P-1, N-1+, Sample P-1, N-1-）。這是藉由生效“平均”控制訊號來實現的，這會導致： （1）中斷電容器組 A 中乘積電荷的儲存； （2）儲存組A中的所有（L）個（+）電容器上的電荷一起短路，導致累積的電荷被“轉儲”到耦接到差分放大器124的負（-）輸入端的第一電容器129上。藉由轉儲所有（+）電容器上的累積電荷，在第一電容器129上實現“平均”電壓；以及 （3） 儲存組 A 中所有（L）個 （-） 電容器上的電荷一起短路，導致累積的電荷“轉儲”到耦接到差分放大器124的正 （+） 端的第二電容器 129 上。藉由轉儲所有（-）電容器上的累積電荷，在第二電容器129上實現“平均”電壓。 Once (L) differential samples have been received and all (L) capacitors of the (+) and (-) capacitor banks of storage bank A have stored the product results, the passive multiplier accumulator encoder 120 operates to produce decoded differential video media sample outputs (i.e., Sample P-1 , N-1 +, Sample P-1 , N-1- ). This is accomplished by asserting the "average" control signal, which causes: (1) the storage of product charge in capacitor bank A to be interrupted; (2) the charges on all (L) (+) capacitors in storage bank A to be shorted together, causing the accumulated charge to be "dumped" onto the first capacitor 129 coupled to the negative (-) input of the differential amplifier 124. An “average” voltage is achieved on the first capacitor 129 by dumping the accumulated charge on all (+) capacitors; and (3) shorting the charge on all (L) (-) capacitors in storage group A together, causing the accumulated charge to be “dumped” to the second capacitor 129 coupled to the positive (+) terminal of the differential amplifier 124. An “average” voltage is achieved on the second capacitor 129 by dumping the accumulated charge on all (-) capacitors.
藉由簡單地將儲存組A中的所有（+）電容器和所有（-）電容器短路在一起，在電容器對129上分別提供了（L）個輸入差分樣本的累積電荷的平均值。因此，平均基本上是“免費”執行的，這意味著相關過程是在沒有任何有源元件（例如，沒有放大器）的情況下被動完成的。By simply shorting together all (+) capacitors and all (-) capacitors in storage bank A, an average value of the accumulated charge of the (L) input differential samples is provided on capacitor pairs 129, respectively. Thus, the averaging is essentially performed "for free," meaning that the associated process is accomplished passively without any active components (e.g., no amplifiers).
解碼的差分視訊媒體樣本因此由分別耦接到差分放大器124的正端和負端的第一電容器129和第二電容器129上累積的平均電壓之間的差來表示。差分放大器124用於放大正負端之間的電壓差，同時抑制兩者之間的任何公共電壓。如圖5A或圖5B所示，利用附加電流增益，解碼的差分視訊媒體樣本更適合驅動重建組82。The decoded differential video media sample is thus represented by the difference between the average voltage accumulated on the first capacitor 129 and the second capacitor 129, which are respectively coupled to the positive and negative terminals of the differential amplifier 124. The differential amplifier 124 is used to amplify the voltage difference between the positive and negative terminals while suppressing any common voltage between the two. As shown in FIG. 5A or FIG. 5B, with the additional current gain, the decoded differential video media sample is more suitable for driving the reconstruction group 82.
差分放大器124的頻率不需要以用於對輸入的（L）個差分樣本進行取樣的相同頻率Fssvt操作。由於對每（L）個輸入樣本執行平均操作，差分放大器124的頻率只需Fssvt/L。藉由降低差分放大器124的速度/穩定時間要求，降低了執行該功能所需的功率。The frequency of the differential amplifier 124 does not need to operate at the same frequency Fssvt used to sample the (L) differential samples of the input. Since the averaging operation is performed on each (L) input samples, the frequency of the differential amplifier 124 only needs to be Fssvt/L. By reducing the speed/settling time requirements of the differential amplifier 124, the power required to perform this function is reduced.
提供用於差分放大器124的復位電路128以在每個Fssvt/L週期將差分放大器的（+/-）輸入處的電容器129上的電壓初始化或復位為零伏或某個其他復位電壓值。在每次平均操作之前沒有復位的情況下，差分放大器124將充當積分器並且隨著時間累積它接收到的差分電壓輸入，而不是簡單地放大它接收到的用於單個平均操作的差分輸入。A reset circuit 128 for the differential amplifier 124 is provided to initialize or reset the voltage on the capacitor 129 at the (+/-) input of the differential amplifier to zero volts or some other reset voltage value at each Fssvt/L cycle. Without a reset prior to each averaging operation, the differential amplifier 124 would act as an integrator and accumulate the differential voltage input it receives over time, rather than simply amplifying the differential input it receives for a single averaging operation.
對於上述實施例，儲存組A不能用於在平均操作期間儲存用於輸入差分樣本的乘積電荷。因此，可能會導致處理延遲。For the above embodiment, the storage group A cannot be used to store the product charge for inputting the differential samples during the averaging operation. Therefore, processing delay may be caused.
在替代實施例中，無源乘法累加器編碼器120還可以可選地包括第二儲存組B，其包括（L）組（+）和（-）電容器、第二差分放大器126、第二組電容器129，一對復位電路128和多工器130。第二儲存組B、差分放大器126、第二組電容器129和復位電路128都與如上所述的它們的對應物基本上相同地操作。因此，為簡潔起見，此處不提供這些元件的詳細說明。In an alternative embodiment, the passive multiplier accumulator encoder 120 may also optionally include a second storage group B, which includes a (L) group of (+) and (-) capacitors, a second differential amplifier 126, a second group of capacitors 129, a pair of reset circuits 128, and a multiplexer 130. The second storage group B, the differential amplifier 126, the second group of capacitors 129, and the reset circuit 128 all operate substantially the same as their counterparts as described above. Therefore, for the sake of brevity, a detailed description of these components is not provided here.
在操作期間，交替使用兩個儲存組A和B。一個是樣本，另一個是平均，反之亦然。藉由在另一組進行平均時使用一個組進行取樣，處理延遲至少以兩種方式減少。首先，可以不間斷地接收、相乘和儲存多組輸入（L）差分訊號對。其次，平均操作之後差分放大器的任何速度/穩定時間要求都被有效地否定了，因為一個組總是在樣本，而另一組在平均，反之亦然。During operation, the two storage groups A and B are used alternately. One is sampling and the other is averaging, and vice versa. By using one group to sample while the other is averaging, processing delays are reduced in at least two ways. First, multiple input (L) differential signal pairs can be received, multiplied, and stored without interruption. Second, any speed/settling time requirements of the differential amplifier after the averaging operation are effectively negated because one group is always sampling while the other is averaging, and vice versa.
為了實現具有兩個儲存組A和B的無源乘法累加器編碼器120的實施例，需要幾個控制訊號。這些控制訊號包括： （1） 提供至儲存組 A 的樣本/平均控制訊號，同時提供至儲存組 B 的互補平均/樣本訊號。由於這兩個控制訊號是互補的，所以一個儲存組將總是對當前輸入的（L）差分訊號集合進行取樣，而與另一個儲存組相關的差分放大器正在平均，反之亦然；以及 （2）將組選擇控制訊號提供至多工器130。因此，當一個儲存組正在樣本和儲存時，多工器130選擇正在平均的另一儲存組的差分放大器輸出（124或126）。藉由使組選擇控制訊號過渡為與樣本/平均控制訊號的過渡一致，多工器130的輸出總是被選擇以挑選正在平均的電容器組。結果，只要碼片乘法器級122正在接收輸入的差分輸入訊號，就連續產生解碼的差分視訊媒體樣本。 To implement an embodiment of a passive multiplier accumulator encoder 120 having two storage groups A and B, several control signals are required. These control signals include: (1) a sample/average control signal provided to storage group A and a complementary average/sample signal provided to storage group B. Since these two control signals are complementary, one storage group will always sample the current input (L) differential signal set while the differential amplifier associated with the other storage group is averaging, and vice versa; and (2) a group select control signal provided to multiplexer 130. Thus, when one storage group is sampling and storing, multiplexer 130 selects the differential amplifier output (124 or 126) of the other storage group being averaged. By aligning the transitions of the group select control signal with the transitions of the sample/average control signal, the output of multiplexer 130 is always selected to pick the capacitor group being averaged. As a result, decoded differential video media samples are continuously generated as long as the chip multiplier stage 122 is receiving the input differential input signal.
參考圖9，示出了說明無源乘法累加器編碼器120的兩組實施例的操作的交替性質的時機圖。9, a timing diagram illustrating the alternating nature of the operation of two sets of embodiments of the passive multiplier-accumulator encoder 120 is shown.
如圖所示，兩個電容器組A和B在樣本和平均之間交替。從左到右，電容器組A最初取樣，然後平均並將結果輸出到差分放大器124的電容器129，然後再次取樣。同時，電容器組 B 執行補充，這意味著它最初對結果進行平均並將結果輸出到差分放大器 126，然後進行取樣，然後對結果進行平均並將結果輸出到差分放大器 126。藉由過渡Fssvt 的每（L）個時鐘週期的平均/控制訊號的狀態來不斷重複這種交替模式。結果，連續產生多個輸出、解碼、差分、視訊媒體樣本。As shown, two capacitor sets, A and B, alternate between sampling and averaging. From left to right, capacitor set A initially samples, then averages and outputs the result to capacitor 129 of differential amplifier 124, then samples again. At the same time, capacitor set B performs replenishment, meaning it initially averages and outputs the result to differential amplifier 126, then samples, then averages and outputs the result to differential amplifier 126. This alternating pattern is repeated continuously by transitioning the state of the average/control signal every (L) clock cycles of Fssvt. As a result, multiple output, decoded, differential, video media samples are continuously generated.
參考圖10，示出了示例性儲存組140（例如，A或B）和控制邏輯。使用L＝128的上述示例，儲存組140將包括128個級，在圖1至（L）中標記。每個級包括第一對開關（S1-S1）、第二對開關（S2-S2）以及互補電容器C（+）和C（-）。Referring to FIG. 10 , an exemplary storage group 140 (e.g., A or B) and control logic are shown. Using the above example of L=128, the storage group 140 will include 128 stages, labeled in FIG. 1 to (L). Each stage includes a first pair of switches (S1-S1), a second pair of switches (S2-S2), and complementary capacitors C(+) and C(-).
每個級還被配置為接收來自控制邏輯單元148的輸出，其用於控制第一對開關S1-S1的打開/閉合。在非排他性實施例中，控制邏輯單元148包括長度為（L）位的迴圈移位暫存器，其將單個“1”位分別迴圈到（L）級周圍。“1”位在任何時間點的位置選擇（L）級中的一個用於對給定的差分對輸入的乘積進行取樣。藉由迴圈“1”位以與（L）個Fssvt時鐘週期基本一致，（L）個樣本分別在（L）個級上收集。在多個替代實施例中，單個“1”位的脈衝寬度可以與Fssvt時鐘的脈衝寬度相同或稍小。藉由使用較小的脈衝寬度，可以避免或減輕部分導通的相鄰級（L）的樣本電容器之間的任何重疊。Each stage is also configured to receive an output from a control logic unit 148, which is used to control the opening/closing of the first pair of switches S1-S1. In a non-exclusive embodiment, the control logic unit 148 includes a loop shift register of length (L) bits, which loops a single "1" bit around the (L) stages respectively. The position of the "1" bit at any point in time selects one of the (L) stages for sampling the product of a given differential pair input. By looping the "1" bit to substantially coincide with (L) Fssvt clock cycles, (L) samples are collected at the (L) stages respectively. In multiple alternative embodiments, the pulse width of the single "1" bit can be the same as or slightly smaller than the pulse width of the Fssvt clock. By using a smaller pulse width, any overlap between partially turned-on sample capacitors of neighboring stages (L) can be avoided or mitigated.
每個級還具有輸入端，該輸入端子被配置為接收電容器組 A 的樣本/平均控制訊號，或電容器組 B 的互補平均/樣本控制訊號。對於兩個組，此控制訊號用於控制第二組開關S2-S2的打開/閉合。Each stage also has an input terminal configured to receive a sample/average control signal for capacitor bank A, or a complementary average/sample control signal for capacitor bank B. For both banks, this control signal is used to control the opening/closing of the second bank of switches S2-S2.
在樣本期間，電容器組A的樣本/平均值（或電容器組B的平均值/樣本）訊號保持在樣本狀態。結果，開關S2-S2保持打開。During the sample period, the sample/average value of capacitor bank A (or the average value/sample value of capacitor bank B) signal remains in the sample state. As a result, switch S2-S2 remains open.
在樣本期間，控制邏輯單元148順序地迴圈分別用於級（L）至（1）的單個“1”位。結果，每個 Fssvt 時鐘週期只選擇一個級。對於選定的級，開關 S1-S1 閉合，允許接收與當前接收到的差分對樣本的乘積結果相稱的電荷值，並將其分別儲存在選定的級的 C（+） 和 C（-） 電容器上。During the sample period, the control logic unit 148 loops sequentially for a single "1" bit for level (L) to (1), respectively. As a result, only one level is selected per Fssvt clock cycle. For the selected level, the switch S1-S1 is closed, allowing a charge value corresponding to the product result of the currently received differential pair sample to be received and stored on the C (+) and C (-) capacitors of the selected level, respectively.
藉由迴圈藉由所有（L）級，與接收的（L）個輸入差分訊號對樣本的乘積相稱的電荷分別在（L）個Fssvt時鐘週期上儲存在（L）級上。一旦所有（L）級都累積了它們的電荷，就可以準備好執行平均操作了。By looping through all (L) stages, a charge proportional to the product of the received (L) input differential signal pair samples is stored on the (L) stages over (L) Fssvt clock cycles respectively. Once all (L) stages have accumulated their charges, they are ready to perform an averaging operation.
為了啟動平均操作，儲存組A的樣本/平均訊號（或儲存組B的平均/樣本訊號）過渡到平均狀態並且控制邏輯單元148停止“1”位的迴圈。結果，所有（L）級的開關S1-S1打開，所有（L）級的開關S2-S2閉合。因此，所有（L）級的互補電容器C（+）和C（-）上的電荷分別被“轉儲”（即平均）到對應差分放大器的（-）和（+）端處的電容器129上。To start the averaging operation, the sample/average signal of storage group A (or the average/sample signal of storage group B) transitions to the averaging state and controls the logic unit 148 to stop the loop of the "1" bit. As a result, the switches S1-S1 of all (L) stages are turned on, and the switches S2-S2 of all (L) stages are closed. Therefore, the charges on the complementary capacitors C(+) and C(-) of all (L) stages are "dumped" (i.e., averaged) to the capacitors 129 at the (-) and (+) terminals of the corresponding differential amplifiers, respectively.
注意，在“轉儲”/平均過程中，可以將另一個電容器（之前初始化為沒有電荷）連接到L個電容器的集合以傳送一部分結果（該比例取決於額外電容器的大小與L電容器的總和）到額外電容器。這種技術提供了將結果傳遞到相應差分放大器輸入的手段，124 用於組A或 126 用於組B。Note that during the "dumping"/averaging process, another capacitor (previously initialized to have no charge) can be connected to the set of L capacitors to transfer a portion of the result (the proportion depends on the size of the additional capacitor and the sum of the L capacitors) to the additional capacitor. This technique provides a means of delivering the result to the input of the corresponding differential amplifier, 124 for group A or 126 for group B.
儘管如上所述的儲存組A和B是對稱的並且都包括（L）級，但是應該理解這絕不是必需的。相反，A 和 B 儲存組不需要是完整的副本。只需要有足夠的重複來滿足可以處理連續的差分輸入樣本串流的要求。例如，一個或兩個儲存組的級數可以少於（L）個。在替代實施例中，僅需要複製多個儲存組中的少量級。潛在複製級的數量只需要足以確保完成對輸出放大器的輸入電容器129的平均操作。即使它們共用記憶元件，一個儲存組的結果（由放大器）的輸出也可以在下一個儲存組的樣本期間完成，因為輸出放大器在評估完成後“獨立”。Although storage groups A and B are symmetric and both include (L) stages as described above, it should be understood that this is by no means required. Instead, the A and B storage groups do not need to be complete copies. There only need to be enough repetitions to meet the requirement that a continuous stream of differential input samples can be processed. For example, the number of stages in one or both storage groups may be less than (L). In alternative embodiments, only a small number of stages in multiple storage groups need to be replicated. The number of potential replicated stages only needs to be sufficient to ensure that the averaging operation on the input capacitor 129 of the output amplifier is completed. Even though they share memory elements, the output of the results of one storage group (by the amplifier) can be completed during the sample period of the next storage group because the output amplifier is "independent" after the evaluation is completed.
此外，每個儲存組不一定需要相應的差分放大器。在替代實施例中，可以多工從多個儲存組到給定差分放大器的輸入，從而減少所需的差分放大器的數量。Furthermore, each storage group does not necessarily require a corresponding differential amplifier. In an alternative embodiment, the inputs to a given differential amplifier from multiple storage groups can be multiplexed, thereby reducing the number of differential amplifiers required.
無源乘法累加器解碼器120的各種上述實施例本質上是用於如圖5A和圖5B所示的解碼器塊80中的N個解碼器的“***式”替代。如前所述，每個解碼器塊80提供有N個解碼器電路（N 0到N -1）。N個解碼器電路中的每一個被配置為順序地接收差分電位準樣本（+/-電位準訊號）。當接收到差分電位準訊號時，N個無源乘法累加器解碼器電路120中的每一個應用與用於對發送端的電位準位置（P）和樣本位置（N）進行編碼的相互正交的SSDS碼相同的唯一SSDS碼。結果，每個無源乘法累加器解碼器電路120為其給定的 P 和N位置產生樣本的差分對。換言之，對於（P）個解碼器80中的每一個的所有N個解碼器電路，產生從（樣本0 +，樣本0 -到樣本 P-1, N-1+，樣本 P-1, N-1-）的差分樣本的完整集合並提供至重建組82，如圖5A和圖5B所示。在關於圖5A和圖5B以及本文關於圖8描述的非排他性實施例中，N是64個通道並且SSDS碼的長度是L＝128。 The various above-described embodiments of the passive multiplier accumulator decoder 120 are essentially "plug-in" replacements for the N decoders in the decoder block 80 shown in Figures 5A and 5B. As previously described, each decoder block 80 is provided with N decoder circuits ( N0 to N -1 ). Each of the N decoder circuits is configured to sequentially receive differential electrical level samples (+/- electrical level signals). When receiving the differential electrical level signals, each of the N passive multiplier accumulator decoder circuits 120 applies a unique SSDS code that is the same as the mutually orthogonal SSDS code used to encode the electrical level position (P) and sample position (N) of the transmitting end. As a result, each passive multiplier accumulator decoder circuit 120 generates a differential pair of samples for its given P and N positions. In other words, for all N decoder circuits of each of the (P) decoders 80, a complete set of differential samples from (sample 0 + , sample 0 - to sample P-1 , N-1 +, sample P-1 , N-1 -) is generated and provided to the reconstruction group 82, as shown in Figures 5A and 5B. In the non-exclusive embodiment described with respect to Figures 5A and 5B and herein with respect to Figure 8, N is 64 channels and the length of the SSDS code is L = 128.
多種編碼器和解碼器的上述討論是關於差分訊號來描述的。然而，應該注意的是，這絕不是要求。在多種替代實施例中，編碼器和解碼器也可以被配置為操作和處理非差分訊號（即，單個訊號）。 結論 The above discussion of various encoders and decoders is described with respect to differential signals. However, it should be noted that this is by no means a requirement. In various alternative embodiments, the encoders and decoders may also be configured to operate and process non-differential signals (i.e., a single signal). Conclusion
本實施例應該被認為是說明性的而不是限制性的，並且本發明不限於本文給出的細節，而是可以在所附申請專利範圍的範圍和等同物內進行修正。The present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
12:視訊源 14:視訊接收端 16:影像感測器陣列 18:類比數位轉換器（“ADC”） 20:影像訊號處理器（ISP） 21:視訊流化器 22:視訊樣本串流、樣本集 24:存放裝置、儲存單元 26、32:重計時器 28:展頻視訊傳輸（SSVT）發射器（TX） 30:SSVT接收器（RX） 34:傳輸介質 40:分配器、分配器-編碼器 42:編碼器 44:解碼器 46:收集器 50:組裝組 52、86:分級組 54:呈現組 56:訊框控制器 60:編碼器塊 62、103:類比數位轉換器（DAC） 65:定序器電路 70:乘法器級 72:累加器級、逆變器 74、92、124、126:差分放大器 78:放大器 80:解碼器塊 82:重建組 84:類比數位轉換器（ADC） 85:顯示器 87:通道對準器 88:拆分組 89:收集器控制器 94:取樣及保持電路 96:解碼器軌道電路 98:控制器 100:乘法器部分 102:累加器部分 104:運算放大器 120:無源乘法累加器解碼器 122:碼片乘法器級 128:復位元件 130:多工器 148:控制邏輯單元 C1:存放裝置 C1-C1、C F:電容器 clk 1、clk 2:時鐘相位訊號 S1-S1、S2-S2、S3-S3、S4-S4、S5-S5、S6-S6、S7-S7:開關組 SSDS:展頻直接序列 12: Video source 14: Video receiver 16: Image sensor array 18: Analog-to-digital converter ("ADC") 20: Image signal processor (ISP) 21: Video streamer 22: Video sample stream, sample set 24: Storage device, storage unit 26, 32: Retimer 28: Spread spectrum video transmission (SSVT) transmitter (TX) 30: SSVT receiver (RX) 34: Transmission medium 40: Distributor, distributor-encoder 42: Encoder 44: Decoder 46: Collector 50: Assembly group 52, 86: Classification group 54: Presentation group 56: Frame controller 60: Encoder block 62, 103: Analog-to-digital converter (DAC) 65: Sequencer circuit 70: Multiplier stage 72: Accumulator stage, inverter 74, 92, 124, 126: Differential amplifier 78: Amplifier 80: Decoder block 82: Reconstruction group 84: Analog-to-digital converter (ADC) 85: Display 87: Channel aligner 88: Splitting group 89: Collector controller 94: Sample and hold circuit 96: Decoder track circuit 98: Controller 100: Multiplier section 102: Accumulator section 104: Operational amplifier 120: Passive multiplier accumulator decoder 122: Chip multiplier stage 128: Reset element 130: Multiplexer 148: Control logic unit C1: Storage device C1-C1, CF : Capacitor clk 1, clk 2: Clock phase signal S1-S1, S2-S2, S3-S3, S4-S4, S5-S5, S6-S6, S7-S7: Switch group SSDS: Spread spectrum direct sequence
本發明及其優點可以藉由參考以下結合附圖進行的描述得到最好的理解，其中： 圖1是示出根據本發明的非排他性實施例的使用基於展頻直接序列（SSDS）的CDMA調製（展頻視訊傳輸（SSVT））將電磁（EM）視訊訊號從數位視訊源傳輸到數位視訊接收端的系統圖。 圖2A是根據本發明的非排他性實施例的經由傳輸電纜連線的展頻視訊傳輸（SSVT）發射器和SSVT接收器的邏輯框圖。 圖2B是根據本發明的非排他性實施例的視訊訊號排列成向量的一種可能的示意圖，這些向量在傳輸前進行調製。 圖3是根據本發明的非排他性實施例的SSVT發射器中使用的編碼器-分配器的邏輯框圖。 圖4是根據本發明非排他性實施例的SSVT編碼器的電路圖。 圖5A是說明根據本發明的非排他性實施例的用於將P個接收到的EM電位準訊號的差分對解調回HDMI訊號的接收器元件的邏輯框圖。 圖5B是說明根據本發明的另一個非排他性實施例的用於將P個接收到的EM電位準訊號的差分對解調回HDMI訊號的另一個接收器元件的邏輯框圖。 圖6是根據本發明的非排他性實施例的用於解調EM電位準訊號的一對差分對的N個解碼器軌道的邏輯圖。 圖7是根據本發明的非排他性實施例的表示性解碼器軌道電路的電路圖。 圖8是根據本發明的另一個非排他性實施例的用於解碼SSDS編碼的媒體訊號的另一個解碼器電路的電路圖。 圖9是根據本發明的非排他性實施例的示出圖8的解碼器電路的操作的時機圖。 圖10示出了根據本發明的非排他性實施例的在圖8的解碼器電路中使用的儲存組和控制邏輯。 在附圖中，有時使用相同的附圖標記來表示相同的結構元件。 還應該理解，圖中的描述是圖解的而不是按比例的。 The present invention and its advantages can be best understood by referring to the following description in conjunction with the accompanying drawings, wherein: FIG. 1 is a system diagram showing the transmission of electromagnetic (EM) video signals from a digital video source to a digital video receiving end using CDMA modulation (spread spectrum video transmission (SSVT)) based on spread spectrum direct sequence (SSDS) according to a non-exclusive embodiment of the present invention. FIG. 2A is a logical block diagram of a spread spectrum video transmission (SSVT) transmitter and an SSVT receiver connected via a transmission cable according to a non-exclusive embodiment of the present invention. FIG. 2B is a possible schematic diagram of a video signal arranged into vectors according to a non-exclusive embodiment of the present invention, which are modulated before transmission. FIG. 3 is a logical block diagram of an encoder-distributor used in an SSVT transmitter according to a non-exclusive embodiment of the present invention. FIG. 4 is a circuit diagram of an SSVT encoder according to a non-exclusive embodiment of the present invention. FIG. 5A is a logic block diagram of a receiver element for demodulating P received differential pairs of EM electrical level signals back to HDMI signals according to a non-exclusive embodiment of the present invention. FIG. 5B is a logic block diagram of another receiver element for demodulating P received differential pairs of EM electrical level signals back to HDMI signals according to another non-exclusive embodiment of the present invention. FIG. 6 is a logic diagram of N decoder tracks for demodulating a differential pair of EM electrical level signals according to a non-exclusive embodiment of the present invention. FIG. 7 is a circuit diagram of a representative decoder track circuit according to a non-exclusive embodiment of the present invention. FIG. 8 is a circuit diagram of another decoder circuit for decoding SSDS-encoded media signals according to another non-exclusive embodiment of the present invention. FIG. 9 is a timing diagram showing the operation of the decoder circuit of FIG. 8 according to a non-exclusive embodiment of the present invention. FIG. 10 shows a storage group and control logic used in the decoder circuit of FIG. 8 according to a non-exclusive embodiment of the present invention. In the accompanying drawings, the same figure labels are sometimes used to represent the same structural elements. It should also be understood that the descriptions in the figures are diagrammatic and not to scale.
28:展頻視訊傳輸(SSVT)發射器(TX) 28: Spread Spectrum Video Transmission (SSVT) Transmitter (TX)
40:分配器、分配器-編碼器 40: Distributor, distributor-encoder
42:編碼器 42: Encoder
50:組裝組 50:Assembly group
52:分級組 52: Classification Group
54:呈現組 54: Presentation Group
56:訊框控制器 56: Frame controller
60:編碼器塊 60: Encoder block
62:類比數位轉換器(DAC) 62: Analog-to-digital converter (DAC)
65:定序器電路 65: Sequencer circuit
Claims (59)
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| US63/118,320 | 2020-11-25 |
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| TW202418817A true TW202418817A (en) | 2024-05-01 |
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| TW112124061A TW202418817A (en) | 2020-11-25 | 2021-11-22 | Decoder circuits for the transmission of video media using spread spectrum direct sequence modulation |
| TW110143382A TWI810720B (en) | 2020-11-25 | 2021-11-22 | Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation |
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| TW110143382A TWI810720B (en) | 2020-11-25 | 2021-11-22 | Encoder and decoder circuits for the transmission of video media using spread spectrum direct sequence modulation |
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| EP (1) | EP4186239A1 (en) |
| TW (2) | TW202418817A (en) |
| WO (1) | WO2022115312A1 (en) |
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| US5793759A (en) * | 1995-08-25 | 1998-08-11 | Terayon Corporation | Apparatus and method for digital data transmission over video cable using orthogonal cyclic codes |
| US6456607B2 (en) * | 1996-10-16 | 2002-09-24 | Canon Kabushiki Kaisha | Apparatus and method for transmitting an image signal modulated with a spreading code |
| US6018547A (en) * | 1998-01-09 | 2000-01-25 | Bsd Broadband, N.V. | Method and apparatus for increasing spectral efficiency of CDMA systems using direct sequence spread spectrum signals |
| JP2001144653A (en) * | 1999-08-27 | 2001-05-25 | Ibiden Sangyo Kk | Wired spread spectrum communication unit and communication method |
| US10230956B2 (en) * | 2012-09-26 | 2019-03-12 | Integrated Device Technology, Inc. | Apparatuses and methods for optimizing rate-distortion of syntax elements |
| CN113708882B (en) * | 2017-03-20 | 2024-03-29 | Hyphy美国有限公司 | Transmitting sampled signals through multiple electromagnetic paths |
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- 2021-11-18 WO PCT/US2021/059966 patent/WO2022115312A1/en unknown
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| TW202226821A (en) | 2022-07-01 |
| TWI810720B (en) | 2023-08-01 |
| WO2022115312A1 (en) | 2022-06-02 |
| EP4186239A1 (en) | 2023-05-31 |
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