TW202412007A - Track and hold circuit - Google Patents

Track and hold circuit Download PDF

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Publication number
TW202412007A
TW202412007A TW112131342A TW112131342A TW202412007A TW 202412007 A TW202412007 A TW 202412007A TW 112131342 A TW112131342 A TW 112131342A TW 112131342 A TW112131342 A TW 112131342A TW 202412007 A TW202412007 A TW 202412007A
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sampling
tracking
voltage
branch
node
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TW112131342A
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Chinese (zh)
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歐根 安卓斯 米歇爾森
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挪威商諾凡爾達艾斯公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

A track and hold circuit (100) for sampling an input signal, the track and hold circuit (100) comprising a first stage (200) and a second stage (300) and being arranged to operate alternately in a track mode and a hold mode. The first stage (200) is arranged to generate a constant output voltage at a first node in the hold mode and to generate the constant output voltage modulated by the input signal at the first node in the track mode. The second stage (300) comprises a sampling capacitor having a first side connected to the first node and a second side connected to a bias voltage through a sampling switch. A sampling output is provided at a sampling node between the sampling capacitor and the sampling switch. In the track mode, the sampling switch is closed and the voltage across the sampling capacitor varies as the input signal varies. In the hold mode, the sampling switch is open, the voltage across the sampling capacitor becomes fixed, and the sampling output becomes set based on the voltage at the node and the fixed voltage across the sampling capacitor.

Description

追蹤與保持電路Track and hold circuit

本發明是有關一種用於高速信號取樣的追蹤與保持電路The present invention relates to a tracking and holding circuit for high-speed signal sampling

時變信號的取樣的執行通常使用帶電容的時脈開關在開關關閉時保持信號。 換言之，當開關閉合時，時脈開關的輸出追蹤輸入，當開關打開時，輸入的最後一個值保持在電容器上。在某些無線電架構中，對有限頻寬信號進行子取樣比對於下混頻信號進行曲樣更可取。這需要一個能夠處理可能處於高頻的帶通信號的取樣電路。因此，需要高速取樣電路。Sampling of time varying signals is usually performed using a clock switch with a capacitor to hold the signal when the switch is closed. In other words, when the switch is closed, the output of the clock switch tracks the input, and when the switch is open, the last value of the input is held on the capacitor. In some radio architectures, it is preferable to subsample a limited bandwidth signal rather than downsample a downmixed signal. This requires a sampling circuit capable of handling band-pass signals that may be at high frequencies. Therefore, high speed sampling circuits are required.

為了實現足夠快速的取樣，可以使用追蹤與保持電路來追蹤時間變化的輸入信號，然後在特定時間點保持或取樣輸入信號。這個“保持”的值可以被儲存，例如在一個電容器中，它在處理保持的數值時可以充當緩衝器，例如使用外部元件，如類比數位轉換器（ADC）。換句話說，在“保持”期間，ADC可以將取樣的類比信號值轉換為數位領域。追蹤與保持通常使用一個取樣開關來執行，這個開關以特定的頻率開啟和關閉。當開關開啟時，輸入信號通過開關傳遞到電容器，而輸出（從電容器取出）追蹤輸入。當開關關閉時，自電容器阻擋（斷開）輸入信號，然後當進行處理時，電容器保持著輸入信號的最後值。To achieve fast enough sampling, a track-and-hold circuit can be used to track a time-varying input signal and then hold or sample the input signal at a specific point in time. This "held" value can be stored, such as in a capacitor, which can act as a buffer while the held value is processed, such as using external components such as an analog-to-digital converter (ADC). In other words, during the "hold" period, the ADC can convert the sampled analog signal value into the digital domain. Track-and-hold is usually implemented using a sampling switch that is turned on and off at a specific frequency. When the switch is open, the input signal is passed through the switch to the capacitor, and the output (taken from the capacitor) tracks the input. When the switch is closed, the capacitor blocks (disconnects) the input signal, and then when processing occurs, the capacitor holds the last value of the input signal.

本發明提供了一種替代方法。The present invention provides an alternative approach.

從第一個方面來看，本發明提供了一種用於取樣輸入信號的追蹤與保持電路，該追蹤與保持電路包括第一級和第二級； 其中，該追蹤與保持電路被安排成能夠在追蹤模式和保持模式之間交替操作； 在保持模式中，第一級被配置為在第一節點生成恆定的輸出電壓； 在追蹤模式中，第一級被配置為在第一節點生成由輸入信號調製的恆定輸出電壓； 第二級包括： 一個第一取樣電容器，其第一側連接到第一節點，第二側通過第一取樣開關連接到第一偏壓電壓； 其中，第一取樣輸出設置在第一取樣電容器和第一取樣開關之間的第一取樣節點； 其中，在追蹤模式下，第一取樣開關閉合，第一取樣電容器兩端的電壓隨輸入信號的變化而變化；以及 其中，在保持模式下，第一取樣開關斷開，第一取樣電容器兩端的電壓變為固定，並且第一取樣輸出基於第一節點處的電壓和第一取樣電容器兩端的固定電壓進行設定。 From a first aspect, the present invention provides a tracking and holding circuit for sampling an input signal, the tracking and holding circuit comprising a first stage and a second stage; wherein the tracking and holding circuit is arranged to be able to operate alternately between a tracking mode and a holding mode; in the holding mode, the first stage is configured to generate a constant output voltage at a first node; in the tracking mode, the first stage is configured to generate a constant output voltage modulated by the input signal at the first node; the second stage comprises: a first sampling capacitor, a first side of which is connected to the first node and a second side of which is connected to a first bias voltage via a first sampling switch; wherein a first sampling output is provided at a first sampling node between the first sampling capacitor and the first sampling switch; Wherein, in the tracking mode, the first sampling switch is closed, and the voltage across the first sampling capacitor changes with the change of the input signal; and Wherein, in the holding mode, the first sampling switch is disconnected, the voltage across the first sampling capacitor becomes fixed, and the first sampling output is set based on the voltage at the first node and the fixed voltage across the first sampling capacitor.

因此，如本發明提供了一種兩級追蹤與保持電路，被配置成在第一模式（當第一取樣開關閉合時）中追蹤輸入信號，並在第二模式（當第一取樣開關斷開時）中提供一個保持的輸出信號。本發明的追蹤與保持電路巧妙地避免了在輸入信號上串聯使用取樣開關。這樣，通常會發生的穿越開關的損失可以減少，而無需增加開關的寬度，這樣就不會引入額外的不需要的電容和電荷注入，也就無需在追蹤與保持電路中使用更大的電容器。Therefore, the present invention provides a two-stage track and hold circuit configured to track an input signal in a first mode (when the first sampling switch is closed) and provide a held output signal in a second mode (when the first sampling switch is open). The track and hold circuit of the present invention cleverly avoids the use of a sampling switch in series with the input signal. In this way, the loss that usually occurs through the switch can be reduced without increasing the width of the switch, thus not introducing additional unnecessary capacitance and charge injection, and eliminating the need to use a larger capacitor in the track and hold circuit.

在某些實施例中，第二級可能包括一個第二取樣電容器，其第一側連接到第一節點，第二側通過第二取樣開關連接到第二偏置電壓。第二取樣開關與第二取樣電容器和第二取樣開關之間的第二取樣節點之間可以提供第二取樣輸出。在追蹤模式下，第二取樣開關關閉，第二取樣電容器上的電壓隨著輸入信號的變化而變化；而在保持模式下，第二取樣開關打開，第二取樣電容器上的電壓固定，第二取樣輸出基於第一節點的電壓和第二取樣電容器上的固定電壓被設置。In some embodiments, the second stage may include a second sampling capacitor having a first side connected to the first node and a second side connected to a second bias voltage through a second sampling switch. A second sampling output may be provided between the second sampling switch and a second sampling node between the second sampling capacitor and the second sampling switch. In a tracking mode, the second sampling switch is closed, and the voltage on the second sampling capacitor changes with changes in the input signal; while in a holding mode, the second sampling switch is opened, the voltage on the second sampling capacitor is fixed, and the second sampling output is set based on the voltage of the first node and the fixed voltage on the second sampling capacitor.

在這種實施例中，追蹤輸入信號因此可以存儲在兩個分開的取樣電容器上，這兩個取樣電容器可以在各自的第二側連接到第一和第二偏置電壓。第一和第二偏置電壓可以由電壓軌或電壓節點提供。較佳地，第一和第二偏置電壓為固定電壓或恆定電壓。例如，第一取樣開關可以被配置成開關的第一側連接到第一取樣電容器的第二側，並且開關的第二側連接到第一偏置電壓節點或第一偏置電壓軌（即能夠提供或吸收電流以將其偏置電壓保持在穩定和一致的水準的穩定電壓節點）。In this embodiment, the tracking input signal can therefore be stored on two separate sampling capacitors, which can be connected to the first and second bias voltages at their respective second sides. The first and second bias voltages can be provided by voltage rails or voltage nodes. Preferably, the first and second bias voltages are fixed voltages or constant voltages. For example, the first sampling switch can be configured such that the first side of the switch is connected to the second side of the first sampling capacitor, and the second side of the switch is connected to the first bias voltage node or the first bias voltage rail (i.e., a stable voltage node that can source or sink current to maintain its bias voltage at a stable and consistent level).

第二取樣開關可以配置成這樣的開關，即開關的第一側連接到第二取樣電容器的第二側，並且開關的第二側連接到第二偏置電壓節點或第二偏置電壓軌（即能夠提供或吸收電流以將其偏置電壓保持在穩定和一致的水準的穩定電壓節點）。因此，當第一取樣開關閉合時，第一取樣電容器的第二側可以連接到第一偏壓電壓，而當第二取樣開關閉合時，第二取樣電容器的第二側可以連接到第二偏壓電壓。這些偏壓電壓可以根據其他電路元件的需要進行選擇。The second sampling switch can be configured as a switch where a first side of the switch is connected to a second side of a second sampling capacitor, and a second side of the switch is connected to a second bias voltage node or a second bias voltage rail (i.e., a stable voltage node capable of sourcing or sinking current to maintain its bias voltage at a stable and consistent level). Thus, when the first sampling switch is closed, the second side of the first sampling capacitor can be connected to a first bias voltage, and when the second sampling switch is closed, the second side of the second sampling capacitor can be connected to a second bias voltage. These bias voltages can be selected as needed by other circuit components.

在某些實施方式中，第一取樣輸出可以連接到第一放大器，使得第一放大器的輸出取決於第一取樣輸出。第一放大器可以被連接，以便它在第三節點提供輸出信號。在某些這樣的實施方式中，第一放大器可以是第一電晶體，被配置成在其閘極處接收第一取樣輸出。因此，在某些實施方式中，第一取樣輸出被連接到第一個電晶體的閘極。第一電晶體可以是一個PMOS電晶體，其正電源軌連接到源極，第三節點連接到汲極。或者，第一電晶體也可以是一個NMOS電晶體，其負電源連接到源極，第三節點連接到汲極。In some embodiments, the first sampled output may be connected to the first amplifier so that the output of the first amplifier depends on the first sampled output. The first amplifier may be connected so that it provides an output signal at the third node. In some such embodiments, the first amplifier may be a first transistor configured to receive the first sampled output at its gate. Therefore, in some embodiments, the first sampled output is connected to the gate of the first transistor. The first transistor may be a PMOS transistor with its positive power rail connected to the source and the third node connected to the drain. Alternatively, the first transistor may also be an NMOS transistor with its negative power rail connected to the source and the third node connected to the drain.

在某些實施方式中，第二取樣輸出可以連接到第二放大器，使得第二放大器的輸出取決於第二取樣輸出。第二放大器可以被連接，以便它在第三節點提供輸出信號。將第一放大器和第二放大器的輸出信號都提供到同一第三節點可能會提供比使用單個放大器在第一或第二取樣輸出中的任何一個所能實現的幅度更大的輸出信號。在某些這樣的實施方式中，第二放大器可以是第二電晶體，被配置成在其閘極處接收第二取樣輸出。因此，在某些實施方式中，第二取樣輸出被連接到第二電晶體的閘極。第二電晶體可以是一個PMOS電晶體，其正電源軌連接到源極，第三節點連接到汲極。或者，第二電晶體也可以是一個NMOS電晶體，其負電源軌連接到源極，第三節點連接到汲極。In some embodiments, the second sampled output may be connected to a second amplifier so that the output of the second amplifier depends on the second sampled output. The second amplifier may be connected so that it provides an output signal at a third node. Providing both the output signals of the first amplifier and the second amplifier to the same third node may provide an output signal with a greater amplitude than can be achieved using a single amplifier in either the first or second sampled output. In some such embodiments, the second amplifier may be a second transistor configured to receive the second sampled output at its gate. Therefore, in some embodiments, the second sampled output is connected to the gate of the second transistor. The second transistor may be a PMOS transistor having a positive power rail connected to the source and a third node connected to the drain. Alternatively, the second transistor may also be an NMOS transistor having a negative power rail connected to the source and a third node connected to the drain.

在某些實施方式中，第一取樣輸出可以連接到一個PMOS電晶體的閘極，而第二取樣輸出可以連接到一個NMOS電晶體的閘極。PMOS電晶體可以被連接，使得在第三節點的PMOS電晶體的輸出取決於第一取樣輸出，而NMOS電晶體可以被連接，使得在第三節點的NMOS電晶體的輸出取決於第二取樣輸出。NMOS電晶體可以被連接，使得其源極連接到負電源軌，而第三節點連接到其汲極。PMOS電晶體可以被連接，使得其源極連接到正電源軌，而第三節點連接到其汲極。將NMOS電晶體和PMOS電晶體的輸出信號都提供到相同的第三節點可能會允許在第三節點生成比使用單個NMOS或PMOS電晶體放大第一和/或第二取樣輸出所能實現的更大幅度的輸出信號。這兩個電晶體有效地協同工作。當NMOS電晶體被更多地關閉時，PMOS電晶體將被更多地打開，反之亦然，從而以相反的方式調整兩個電晶體的電流吸取，並且因此將第三節點的輸出電壓移位了兩倍，相較於使用單個電晶體。In some embodiments, the first sampling output may be connected to the gate of a PMOS transistor, and the second sampling output may be connected to the gate of an NMOS transistor. The PMOS transistor may be connected so that the output of the PMOS transistor at the third node depends on the first sampling output, and the NMOS transistor may be connected so that the output of the NMOS transistor at the third node depends on the second sampling output. The NMOS transistor may be connected so that its source is connected to the negative power rail and the third node is connected to its drain. The PMOS transistor may be connected so that its source is connected to the positive power rail and the third node is connected to its drain. Providing the output signals of both the NMOS transistor and the PMOS transistor to the same third node may allow a larger magnitude output signal to be generated at the third node than can be achieved by amplifying the first and/or second sampled output using a single NMOS or PMOS transistor. The two transistors effectively work in tandem. When the NMOS transistor is turned off more, the PMOS transistor will be turned on more, and vice versa, thereby adjusting the current draw of the two transistors in opposite ways and thus shifting the output voltage of the third node by a factor of two compared to using a single transistor.

在某些實施方式中，第一級可以包括第一分支和第二分支，第一分支和第二分支是第二節點和第一節點之間的電流路徑，並且交替運作。第一分支可以被配置成在第一節點生成恆定的輸出電壓。第二分支可以被配置成在第一節點生成由輸入信號調變的恆定輸出電壓。這種安排提供了在第一節點產生所需電壓的方便方法。這兩個分支交替運作，所以當第二分支運作時，即電路處於追蹤模式且取樣開關（或開關）閉合時，第一節點的電壓只有在輸入電壓的影響下才會被調變。當取樣開關處於開啟狀態時，第一分支運作，電路處於保持模式，第一節點的電壓只是恆定的輸出電壓，並且不受輸入信號的影響。In some embodiments, the first stage may include a first branch and a second branch, the first branch and the second branch being current paths between the second node and the first node, and operating alternately. The first branch may be configured to generate a constant output voltage at the first node. The second branch may be configured to generate a constant output voltage modulated by an input signal at the first node. This arrangement provides a convenient method for generating a desired voltage at the first node. The two branches operate alternately, so when the second branch operates, that is, when the circuit is in tracking mode and the sampling switch (or switches) is closed, the voltage at the first node is modulated only under the influence of the input voltage. When the sampling switch is in the open state, the first branch operates, the circuit is in holding mode, and the voltage at the first node is only a constant output voltage and is not affected by the input signal.

在某些實施方式中，追蹤與保持電路的第一分支和第二分支可以根據來自外部時脈源的時脈信號交替運作。例如，在來自外部時脈源的時脈信號的作用下，第一分支和第二分支可以交替連接到追蹤與保持電路的第一節點。這裡的“連接”是指電氣上的連接，例如，表示電流可以在兩個連接的元件之間流動。因此，如果第一分支在運作，它實際上是與第一節點連接的，電流可以通過追蹤與保持電路的第一分支流向第一節點。同樣地，如果第一分支沒有運作，它實際上是與第一節點斷開的，電流不會通過追蹤與保持電路的第一分支流向第一節點。以同樣的方式，如果第二分支在運作，它實際上是與第一節點連接的，電流可以通過追蹤與保持電路的第二分支流向第一節點。同樣地，如果第二分支沒有運作，它實際上是與第一節點斷開的，電流不會通過追蹤與保持電路的第二分支流向第一節點。In some embodiments, the first branch and the second branch of the tracking and holding circuit can operate alternately according to a clock signal from an external clock source. For example, under the action of the clock signal from the external clock source, the first branch and the second branch can be alternately connected to the first node of the tracking and holding circuit. The "connection" here refers to an electrical connection, for example, indicating that current can flow between two connected elements. Therefore, if the first branch is operating, it is actually connected to the first node, and current can flow to the first node through the first branch of the tracking and holding circuit. Similarly, if the first branch is not operating, it is actually disconnected from the first node, and current will not flow to the first node through the first branch of the tracking and holding circuit. In the same way, if the second branch is operating, it is actually connected to the first node, and current can flow to the first node through the second branch of the tracking and holding circuit. Similarly, if the second branch is not operating, it is actually disconnected from the first node, and current will not flow to the first node through the second branch of the tracking and holding circuit.

時脈信號可能具有至少兩個狀態，例如，時脈信號可能為高或低。在某些這樣的實施方式中，當時脈信號為高時，第二分支可能在運作，例如，它可能被連接到第一節點，而第一分支則不在運作。當時脈信號為低時，第一分支可能在運作，例如，它可能被連接到第一節點，而第二分支可能不連接到第一節點。The clock signal may have at least two states, for example, the clock signal may be high or low. In some such implementations, when the clock signal is high, the second branch may be in operation, for example, it may be connected to the first node, and the first branch may not be in operation. When the clock signal is low, the first branch may be in operation, for example, it may be connected to the first node, and the second branch may not be connected to the first node.

在某些實施方式中，時脈信號可能是一個方波信號。這個方波信號可能有一個預定的頻率和工作週期，被選擇來允許以所需的取樣率取樣輸入信號，例如，在樣本之間具有預定的取樣間隔。例如，在只需要偶爾在第一取樣輸出（如果存在，也包括第二取樣輸出）處進行取樣的情況下，方波信號可能具有較低的頻率。在需要更頻繁進行取樣的情況下，方波信號可能具有較高的頻率。In some implementations, the clock signal may be a square wave signal. The square wave signal may have a predetermined frequency and duty cycle selected to allow sampling of the input signal at a desired sampling rate, e.g., with a predetermined sampling interval between samples. For example, in the case where sampling is only required occasionally at the first sampled output (and the second sampled output if present), the square wave signal may have a lower frequency. In the case where more frequent sampling is required, the square wave signal may have a higher frequency.

時脈的工作週期可以調整以平衡電路每個級的操作時間。每個級可能對時間有不同的要求。例如，如果在第二級使用放大器來放大輸出，該放大器可能需要時間將輸出信號提高到更高的水準。因此，調整時脈的工作週期以在保持模式中花費更多時間而不是在追蹤模式中可能是有利的。在切換到追蹤模式後，第一級也可能需要一些時間來穩定，因此工作週期還需要為追蹤模式提供一定的最小時間。因此，在某些實施方式中，時脈的工作週期可能是50:50，以使追蹤模式和保持模式的時間相等。在其他實施方式中，可以設置工作週期，使保持模式的持續時間比追蹤模式長。在某些實施方式中，工作週期可能被設置為保持模式的持續時間不超過追蹤模式的兩倍。The duty cycle of the clock can be adjusted to balance the operating time of each stage of the circuit. Each stage may have different requirements for time. For example, if an amplifier is used in the second stage to amplify the output, the amplifier may need time to increase the output signal to a higher level. Therefore, it may be advantageous to adjust the duty cycle of the clock to spend more time in hold mode rather than in tracking mode. The first stage may also need some time to stabilize after switching to tracking mode, so the duty cycle also needs to provide a certain minimum time for tracking mode. Therefore, in some embodiments, the duty cycle of the clock may be 50:50 to make the time in tracking mode and holding mode equal. In other embodiments, the duty cycle can be set so that the hold mode lasts longer than the tracking mode. In some implementations, the duty cycle may be set so that the duration of the hold mode does not exceed twice that of the tracking mode.

在某些實施方式中，第一分支和第二分支可能分別包括各自的“時脈”電晶體，安排在它們各自的閘極接收基於時脈信號的訊號。第一時脈電晶體可能連接在第一分支上，例如，可能被安排成第一分支同時連接到第一時脈電晶體的源極和汲極。第二時脈電晶體可能連接在第二分支上，例如，可能被安排成第二分支同時連接到第二時脈電晶體的源極和汲極。第一時脈電晶體可能被安排成在其閘極處接收時脈信號，而第二時脈電晶體可能被安排成在其閘極處接收反相的時脈信號。透過使用單一時脈來控制第一分支和第二分支的運作，可以以這種方式進行操作。此外，通過使用相反的時脈信號對第一分支和第二分支進行時脈控制，這種安排有利於確保在任何時刻只有第一分支和第二分支中的一個在運作，因此在任何給定時刻只有一個分支在第一節點產生電壓。在某些實施方式中，時脈電晶體可以是PMOS電晶體。In some embodiments, the first branch and the second branch may each include a respective "clock" transistor, arranged at their respective gates to receive a signal based on the clock signal. The first clock transistor may be connected to the first branch, for example, it may be arranged so that the first branch is simultaneously connected to the source and drain of the first clock transistor. The second clock transistor may be connected to the second branch, for example, it may be arranged so that the second branch is simultaneously connected to the source and drain of the second clock transistor. The first clock transistor may be arranged to receive the clock signal at its gate, and the second clock transistor may be arranged to receive an inverted clock signal at its gate. Operation can be performed in this manner by using a single clock to control the operation of the first branch and the second branch. In addition, by using opposite clock signals to clock the first branch and the second branch, this arrangement is conducive to ensuring that only one of the first branch and the second branch is in operation at any time, so that only one branch generates a voltage at the first node at any given time. In some embodiments, the clock transistor can be a PMOS transistor.

在某些實施方式中，第一取樣開關（如果存在，還包括第二取樣開關）可能使用與第一分支和第二分支相同的時脈信號進行時脈控制，即當時脈信號為高電位時，第一取樣開關（如果存在，還包括第二取樣開關）處於開啟狀態，而當時脈信號為低時，則處於關閉狀態。這確保了只有在第二分支運作時，才會在第一取樣電容器（如果存在，還包括第二取樣電容器）之間變化電壓。在某些具有第一和第二取樣開關的實施方式中，第一和第二取樣開關可能使用相同的時脈信號進行時脈控制，即當時脈信號為低時，兩個取樣開關都處於開啟狀態，而當時脈信號為高時，兩個取樣開關都處於關閉狀態。這確保了第一取樣輸出和第二取樣輸出在基於第一節點的電壓和第一和第二取樣電容器上的固定電壓的情況下，同時被設置。這在第一和第二取樣輸出被提供到共同的第三節點（例如在被提供到各自的放大器後）的實施方式中可能尤為重要，因為兩個取樣電容器將完全反映相同的取樣時間。In some embodiments, the first sampling switch (and the second sampling switch if present) may be clocked using the same clock signal as the first branch and the second branch, i.e., when the clock signal is high, the first sampling switch (and the second sampling switch if present) is in an open state, and when the clock signal is low, it is in a closed state. This ensures that the voltage between the first sampling capacitor (and the second sampling capacitor if present) changes only when the second branch is in operation. In some embodiments having the first and second sampling switches, the first and second sampling switches may be clocked using the same clock signal, i.e., when the clock signal is low, both sampling switches are in an open state, and when the clock signal is high, both sampling switches are in a closed state. This ensures that the first sampled output and the second sampled output are set at the same time based on the voltage of the first node and the fixed voltage on the first and second sampling capacitors. This may be particularly important in an implementation where the first and second sampled outputs are provided to a common third node (e.g., after being provided to respective amplifiers), because the two sampling capacitors will reflect exactly the same sampling time.

在某些實施方式中，取樣電路的第一級可能包括一個反饋元件。這個反饋元件可以被設計成補償由於輸入信號變化而引起的電流抽取變化。換句話說，這個反饋元件可以被設計成提高第一級的線性度。In some implementations, the first stage of the sampling circuit may include a feedback element. The feedback element may be designed to compensate for current extraction changes due to input signal changes. In other words, the feedback element may be designed to improve the linearity of the first stage.

第二節點可以是一個正供電軌（或其他電流供應），例如，一個高電位軌，被設計成作為取樣電路的電壓源。第二節點可以通過一個第一電流控制電晶體連接到第一和第二分支。在某些實施方式中，這個電流控制電晶體可能是一個PMOS電晶體，連接在取樣電路的第一級的第一和第二分支之間，例如，其源極端被連接到第二節點，並且其汲極端被連接到第一和第二分支。這個第一電流控制電晶體可以允許在第一電流控制電晶體的閘極處接收到的電壓的存在下開啟或關閉取樣電路，並且也可以通過在第一電流控制電晶體的閘極處施加的第一偏壓電壓的變化來控制第一和第二分支中的電流。The second node can be a positive supply rail (or other current supply), for example, a high potential rail, designed to serve as a voltage source for the sampling circuit. The second node can be connected to the first and second branches via a first current control transistor. In some embodiments, the current control transistor may be a PMOS transistor connected between the first and second branches of the first stage of the sampling circuit, for example, with its source terminal connected to the second node and its drain terminal connected to the first and second branches. The first current control transistor can allow the sampling circuit to be turned on or off in the presence of a voltage received at the gate of the first current control transistor, and can also control the current in the first and second branches by changing the first bias voltage applied at the gate of the first current control transistor.

在某些實施方式中，第一分支、第二分支和第一節點可能通過第二電流控制電晶體連接到地或一個負供電軌（或其他電流汲取），例如，一個低電位軌。這個第二電流控制電晶體可能是一個NMOS電晶體，連接在電流汲取和取樣電路的第一級的第一和第二分支之間。通過這種方式，第一和第二分支可以連接在一個“上游”第二節點（可能是電流供應）和一個“下游”電流汲取（例如，地）。這裡的“上游”和“下游”這些詞語指的是直流電流從正供電軌（或其他電流供應）流向地或低電位軌（或其他電流汲取）的方向。在某些這樣的實施方式中，NMOS電晶體的源極端可能被連接到電流汲取，其汲極端可能被連接到取樣電路的第一級的第一和第二分支。NMOS電晶體的閘極可能被連接到一個第二偏壓電壓，可以變化以設定第一和第二分支中的電流。In some embodiments, the first branch, the second branch and the first node may be connected to ground or a negative supply rail (or other current draw), for example, a low potential rail, via a second current control transistor. This second current control transistor may be an NMOS transistor connected between the first and second branches of the first stage of the current draw and sampling circuit. In this way, the first and second branches can be connected to an "upstream" second node (which may be a current supply) and a "downstream" current draw (for example, ground). The terms "upstream" and "downstream" here refer to the direction in which the DC current flows from the positive supply rail (or other current supply) to the ground or low potential rail (or other current draw). In some such embodiments, the source terminal of the NMOS transistor may be connected to the current draw and its drain terminal may be connected to the first and second branches of the first stage of the sampling circuit. The gate of the NMOS transistor may be connected to a second bias voltage that can be varied to set the current in the first and second branches.

在某些實施方式中，第一級的第一分支可能包括用於接收共模電壓的裝置，例如，來自一個共模電壓源。用於接收共模電壓的裝置可能是一個連接在追蹤與保持電路的第一級的第一分支上的第一偏壓部分。第一偏壓部分可能是一個連接在追蹤與保持電路的第一級的第一分支上的第一偏壓電晶體。第一偏壓電晶體可能被配置成在其閘極處接收共模電壓，例如，使得第一分支可以基於共模電壓進行控制。在某些這樣的實施方式中，第一偏壓電晶體可能被連接，使得第一分支同時連接到第一偏壓電晶體的源極和汲極，並且電晶體的閘極被安排為接收共模電壓。在某些實施方式中，第一偏壓電晶體可能是一個NMOS電晶體。In some embodiments, the first branch of the first stage may include means for receiving a common-mode voltage, for example, from a common-mode voltage source. The means for receiving the common-mode voltage may be a first bias portion connected to the first branch of the first stage of the tracking and holding circuit. The first bias portion may be a first bias transistor connected to the first branch of the first stage of the tracking and holding circuit. The first bias transistor may be configured to receive the common-mode voltage at its gate, for example, so that the first branch can be controlled based on the common-mode voltage. In some such embodiments, the first bias transistor may be connected so that the first branch is simultaneously connected to the source and drain of the first bias transistor, and the gate of the transistor is arranged to receive the common-mode voltage. In some implementations, the first bias transistor may be an NMOS transistor.

追蹤與保持電路的第一級可能包括接收外部信號的裝置。在某些情況下，用於接收輸入信號的裝置可能是連接在追蹤與保持電路的第一級的第二分支和輸入信號源之間的偏置部分。該偏置部分可能是連接在追蹤與保持電路的第一級的第一分支上的第二偏置電晶體。第二偏置電晶體可能被配置為在其閘極處接收共模電壓，使得第二分支可以根據輸入信號進行控制。在某些這樣的情況下，第二偏置電晶體可能被連接，使得第二分支同時連接到第二偏置電晶體的源極和汲極，並且第二偏置電晶體的閘極被安排為接收輸入信號。該電晶體可能是一個NMOS電晶體。The first stage of the tracking and holding circuit may include a device for receiving an external signal. In some cases, the device for receiving the input signal may be a biasing portion connected between the second branch of the first stage of the tracking and holding circuit and the input signal source. The biasing portion may be a second biasing transistor connected to the first branch of the first stage of the tracking and holding circuit. The second biasing transistor may be configured to receive a common mode voltage at its gate so that the second branch can be controlled according to the input signal. In some such cases, the second biasing transistor may be connected so that the second branch is simultaneously connected to the source and drain of the second biasing transistor, and the gate of the second biasing transistor is arranged to receive the input signal. The transistor may be an NMOS transistor.

在某些實施方式中，如果第一分支被設計為接收共模電壓，第二偏置部分可能被設計為同時接收共模電壓和輸入信號。例如，在第二偏置部分為第二偏置電晶體的情況下，第二偏置電晶體可能被設計為在其閘極接收共模電壓和輸入信號的總和。In some embodiments, if the first branch is designed to receive a common mode voltage, the second bias portion may be designed to receive both the common mode voltage and the input signal. For example, in the case where the second bias portion is a second bias transistor, the second bias transistor may be designed to receive the sum of the common mode voltage and the input signal at its gate.

在某些實施方式中，輸入信號可以是類比電壓，例如一個隨時間變化的類比電壓。In some implementations, the input signal can be an analog voltage, such as a time-varying analog voltage.

根據另一方面，本發明提供了一種用於取樣輸入信號的取樣電路，該取樣電路包括第一級和第二級； 其中，第一級包括第一分支和第二分支，第一分支和第二分支是第一節點和第二節點之間的電流路徑，並且交替操作； 其中，第一分支被設置為在第二節點產生恒定的輸出電壓； 其中，第二分支被設置為在第二節點上產生由輸入信號調變的恒定輸出電壓； 其中，第二級包括： 第一個取樣電容器，第一個側連接到第二節點，第二個側通過第一個取樣開關連接到第一個偏置電壓； 其中，第一個取樣電容器和第一個取樣開關之間提供第一個取樣節點的第一個取樣輸出； 其中，第一個取樣開關閉合時，第二分支工作，第一個取樣電容器的電壓隨輸入信號的變化而變化；以及 其中，第一個取樣開關打開時，第一分支工作，第一個取樣電容器兩端的電壓變成固定，第一個取樣輸出基於第二節點上的電壓和第一個取樣電容器上的固定電壓而確定。 According to another aspect, the present invention provides a sampling circuit for sampling an input signal, the sampling circuit comprising a first stage and a second stage; wherein the first stage comprises a first branch and a second branch, the first branch and the second branch are current paths between a first node and a second node, and operate alternately; wherein the first branch is configured to generate a constant output voltage at the second node; wherein the second branch is configured to generate a constant output voltage modulated by an input signal at the second node; wherein the second stage comprises: a first sampling capacitor, a first side of which is connected to the second node, and a second side of which is connected to a first bias voltage via a first sampling switch; wherein a first sampling output of a first sampling node is provided between the first sampling capacitor and the first sampling switch; Wherein, when the first sampling switch is closed, the second branch works, and the voltage of the first sampling capacitor changes with the change of the input signal; and Wherein, when the first sampling switch is opened, the first branch works, the voltage at both ends of the first sampling capacitor becomes fixed, and the first sampling output is determined based on the voltage on the second node and the fixed voltage on the first sampling capacitor.

需要注意的是，與第一方面相關的所有首選和可選特徵也同樣適用於這個替代方面。Note that all preferred and optional features associated with the first aspect also apply to this alternative aspect.

本文所描述的任何方面或實施方式的特徵，在適當的情況下，都可以應用於本文所描述的任何其他方面或實施方式。在提及不同實施方式或一組實施方式時，應理解這些並不一定是相互獨立的，可能會有重疊。The features of any aspect or implementation described herein may, where appropriate, be applied to any other aspect or implementation described herein. When referring to different implementations or a group of implementations, it should be understood that these are not necessarily independent of each other and may overlap.

圖1顯示了如本發明一種實施例的追蹤保持電路100。追蹤保持電路100包括第一級200和第二級300。FIG1 shows a tracking and holding circuit 100 according to an embodiment of the present invention. The tracking and holding circuit 100 includes a first stage 200 and a second stage 300.

第一級200包括一個第一部分210，用於取樣輸入信號V IN，例如，一個時間變化的類比信號，並且在某些實施例中，還包括一個回饋部分250，用於在第一級200中提供額外的增益。 The first stage 200 includes a first section 210 for sampling an input signal V IN , for example, a time-varying analog signal, and, in some embodiments, a feedback section 250 for providing additional gain in the first stage 200 .

第一級200可以處於兩種狀態或模式中的一種。在第一種狀態（追蹤模式）中，第一級200被配置為追蹤輸入信號V IN，即提供一個帶有附加共模電壓V CM的輸出信號V OUT1，該輸出信號V OUT1與輸入信號V IN同步。因此，在第一種狀態下，第一級200基於由輸入信號V IN調製的共模電壓輸出位於第一節點的電壓（V OUT1）。在第二種狀態（保持模式）中，第一級200被配置為輸出信號V OUT1不追蹤輸入信號，而是僅基於共模電壓V CM。第二級300被配置為接收第一級200的輸出信號（V OUT1），並且要麼允許取樣電容器C S兩端的電壓變化（在第一種狀態或追蹤模式中），要麼固定取樣電容器C S兩端的電壓（在第二種狀態或保持模式中）。在第二種模式（保持模式）中，第二級300基於取樣開關打開時輸入電壓V IN的大小提供放大信號V OUT2。 The first stage 200 can be in one of two states or modes. In the first state (tracking mode), the first stage 200 is configured to track the input signal V IN , that is, to provide an output signal V OUT1 with an additional common-mode voltage V CM , which is synchronized with the input signal V IN . Therefore, in the first state, the first stage 200 outputs a voltage (V OUT1 ) at the first node based on the common-mode voltage modulated by the input signal V IN . In the second state (holding mode), the first stage 200 is configured so that the output signal V OUT1 does not track the input signal, but is only based on the common-mode voltage V CM . The second stage 300 is configured to receive the output signal (V OUT1 ) of the first stage 200 and either allow the voltage across the sampling capacitor CS to vary (in the first state or tracking mode) or fix the voltage across the sampling capacitor CS (in the second state or holding mode). In the second mode (holding mode), the second stage 300 provides an amplified signal V OUT2 based on the magnitude of the input voltage V IN when the sampling switch is opened.

圖2更詳細地展示了追蹤保持電路100的第一級200。第一級200的第一部分210可以看到包括兩個平行分支，連接到與正供電軌201相連的PMOS電晶體211，以及連接到與負供電軌203相連的NMOS電晶體213。PMOS電晶體211和NMOS電晶體213用於設置第一級200的兩個平行分支中的偏置電流，但在追蹤保持電路100的追蹤保持功能方面沒有其他積極貢獻。可以看到，追蹤保持電路100的第一級200還包括一個輸出端子220，位元於兩個平行分支的下游（即離正供電軌201更遠的地方），並與兩個平行分支相連接。FIG2 shows the first stage 200 of the track-and-hold circuit 100 in more detail. The first portion 210 of the first stage 200 can be seen to include two parallel branches connected to a PMOS transistor 211 connected to the positive supply rail 201, and to an NMOS transistor 213 connected to the negative supply rail 203. The PMOS transistor 211 and the NMOS transistor 213 are used to set the bias current in the two parallel branches of the first stage 200, but have no other active contribution to the track-and-hold function of the track-and-hold circuit 100. It can be seen that the first stage 200 of the track-and-hold circuit 100 also includes an output terminal 220 located downstream of the two parallel branches (i.e., further from the positive supply rail 201) and connected to the two parallel branches.

第一級200的每個分支包括兩個電晶體：第一個電晶體（以下簡稱為時脈部分），其閘極連接到接收來自時脈源的信號，和第二個電晶體（以下簡稱為偏置部分），其閘極連接到接收兩個偏置電壓中的一個。正如下面將更詳細地描述的，這兩個分支充當交替的電流路徑，因此電流可以通過第一級200的兩個分支中的任意一個依次從正供電軌201流向負供電軌203，具體取決於來自時脈源的信號。Each branch of the first stage 200 includes two transistors: a first transistor (hereinafter referred to as the clock portion) whose gate is connected to receive a signal from a clock source, and a second transistor (hereinafter referred to as the bias portion) whose gate is connected to receive one of two bias voltages. As will be described in more detail below, the two branches act as alternating current paths, so that current can flow from the positive supply rail 201 to the negative supply rail 203 through either of the two branches of the first stage 200 in sequence, depending on the signal from the clock source.

第一個分支包括一個第一個時脈部分，即一個PMOS電晶體212，其閘極連接到接收來自時脈源的時脈信號 （在圖2中未顯示），和一個第一個偏置部分，即一個NMOS電晶體214，其閘極連接到一個偏置電壓，在圖2中表示為共模電壓V CM。在圖2中顯示的示例中，時脈信號 採用50%工作週期的方波形式，但應當理解，本公開內容並不限於此，任何具有至少兩種狀態的時脈信號都可以使用。第一個分支將第一節點230（也是第一級輸出V OUT1）與第二節點232連接起來。 The first branch includes a first clock portion, namely a PMOS transistor 212, whose gate is connected to receive a clock signal from a clock source. (not shown in FIG. 2 ), and a first biasing section, namely an NMOS transistor 214, whose gate is connected to a bias voltage, denoted as a common mode voltage V CM in FIG. 2 . In the example shown in FIG. 2 , the clock signal A square wave with a 50% duty cycle is used, but it should be understood that the present disclosure is not limited thereto, and any clock signal with at least two states can be used. The first branch connects the first node 230 (also the first stage output V OUT1 ) with the second node 232 .

第二個分支包括一個第二個時脈部分，即一個PMOS電晶體216，其閘極連接到時脈源的反相輸出，即接收時脈信號的反相 ，和一個第二個偏置部分，即一個NMOS電晶體218，其閘極連接，以便接收共模電壓V CM和待取樣的時間變化輸入信號V IN的總和。第二個分支還將第一節點230與第二節點232連接起來。 The second branch includes a second clock section, namely a PMOS transistor 216, whose gate is connected to the inverting output of the clock source, namely the inverting output of the receiving clock signal. , and a second biasing section, namely an NMOS transistor 218, whose gate is connected to receive the sum of the common mode voltage V CM and the time-varying input signal V IN to be sampled. The second branch also connects the first node 230 with the second node 232.

通過控制施加在時脈電晶體212、216的閘極上的時脈信號 ，可以使電流從正電源201流過第一分支或第二分支，即從第一偏置部分214或第二偏置部分218中的任何一個流過。這導致了在輸出端220（和第一節點230）提供的輸出V OUT1會隨著時脈信號 是邏輯高還是邏輯低而變化。 By controlling the clock signal applied to the gate of the clock transistors 212 and 216 , current can flow from the positive power supply 201 through the first branch or the second branch, that is, through any one of the first bias section 214 or the second bias section 218. This results in the output V OUT1 provided at the output terminal 220 (and the first node 230) to follow the clock signal It varies depending on whether the logic is high or low.

當時脈信號 為邏輯低時，電流通過電路的第一分支，其取決於第一偏置部分214處的偏置電壓V CM。這實際上導致了V CM的追蹤，儘管由於V CM是恒定的，在這種模式下第一節點230上的輸出電壓也是恒定的，因此V OUT1∝V CM。然而，當時脈信號為邏輯高時，電流通過電路的第二分支，使得第一級的輸出（在第一節點230處）的信號受到輸入信號V IN與公共模式電壓V CM的和形式）在第二偏置部分218處的調變。這導致輸入信號V IN被追蹤，因此在第一級的輸出（在第一節點230處）提供了一個取決於V IN的信號，即V OUT1∝(V CM+V IN)。 Current pulse signal When the pulse signal is logically low, the current flows through the first branch of the circuit, which depends on the bias voltage V CM at the first bias section 214. This actually results in tracking of V CM , although since V CM is constant, the output voltage at the first node 230 is also constant in this mode, so V OUT1 ∝ V CM . However, when the pulse signal is logically high, the current flows through the second branch of the circuit, so that the signal at the output of the first stage (at the first node 230) is modulated by the input signal V IN and the common mode voltage V CM in the form of a sum at the second bias section 218. This results in the input signal V IN being tracked, and thus provides a signal at the output of the first stage (at the first node 230) that depends on V IN , i.e., V OUT1 ∝ (V CM + V IN ).

因此，追蹤保持電路100的第一級200的輸出V OUT1在時脈信號 為邏輯高時（追蹤模式）追蹤時間變化的輸入信號V IN，並在時脈信號 為邏輯低時（保持模式）輸出基於V CM的固定電壓。 Therefore, the output V OUT1 of the first stage 200 of the tracking and holding circuit 100 is at the clock signal When the logic is high (tracking mode), it tracks the time variation of the input signal V IN and the clock signal When in logic low (hold mode), the output is a fixed voltage based on V CM .

在某些實施例中，追蹤保持電路100的第一級200還可以包括第二部分250，即一個反饋回路。反饋回路包括兩個放大器，即一個PMOS電晶體222（M CAS）和一個NMOS電晶體224（M MIR）。這兩個電晶體222、224被配置成使第二部分250能夠補償由輸入信號變化引起的電流波動。這提高了第一級200的線性度。 In some embodiments, the first stage 200 of the tracking and holding circuit 100 may further include a second portion 250, i.e., a feedback loop. The feedback loop includes two amplifiers, i.e., a PMOS transistor 222 (M CAS ) and an NMOS transistor 224 (M MIR ). The two transistors 222, 224 are configured to enable the second portion 250 to compensate for current fluctuations caused by changes in the input signal. This improves the linearity of the first stage 200.

第一級200的輸出V OUT1被提供到追蹤保持電路100的第二級300，如圖3中更詳細地顯示。 The output V OUT1 of the first stage 200 is provided to the second stage 300 of the track-and-hold circuit 100 , as shown in more detail in FIG. 3 .

追蹤保持電路100的第二級300包括一個輸入端301，用於接收追蹤保持電路100的第一級200的輸出V OUT1。因此，輸入端301接收到一個信號，在時脈信號 來自時脈源時（在追蹤模式下）追蹤時間變化的輸入信號V IN，並且在時脈信號 為邏輯低時（在保持模式下）輸出基於公共模式電壓V CM的固定電壓。 The second stage 300 of the tracking and holding circuit 100 includes an input terminal 301 for receiving the output V OUT1 of the first stage 200 of the tracking and holding circuit 100. Therefore, the input terminal 301 receives a signal, in the clock signal Tracks the time variation of the input signal V IN when it is from a clock source (in tracking mode) and When the logic is low (in hold mode), it outputs a fixed voltage based on the common mode voltage V CM .

輸入端301位於第一和第二取樣電容器302a、302b之間，每個取樣電容器通過相應的取樣開關303a、303b連接到各自的供電軌。第一取樣電容器302a通過第一取樣開關303a連接到第一偏壓電壓節點V BP304，並且還連接到PMOS電晶體306的閘極。第二取樣電容器302b通過第二取樣開關303b連接到第二偏壓電壓節點V BN305，並且還連接到NMOS電晶體307的閘極。PMOS電晶體306和NMOS電晶體307的汲極分別連接到一個輸出端310，該輸出端用於輸出基於PMOS電晶體306和NMOS電晶體307的漏源電壓的信號V OUT2。這兩個電晶體共同工作，推拉輸出電壓V OUT2使其升高或降低。當NMOS電晶體被更多地“關斷”時，PMOS電晶體將被更多地“導通”，反之亦然，從而以相反的方式調整兩個電晶體的電流流向，因此將V OUT的輸出電壓移位元了兩倍，相較於使用單個電晶體的情況。例如，當NMOS電晶體“關斷”時，它的電流較小。與此同時，PMOS電晶體“導通”，它的電流較大。兩個電晶體的電壓降會相應改變，輸出電壓V OUT2會被兩個電晶體推拉到一個新的輸出電平。 The input terminal 301 is located between first and second sampling capacitors 302a, 302b, each of which is connected to a respective supply rail via a corresponding sampling switch 303a, 303b. The first sampling capacitor 302a is connected to a first bias voltage node V BP 304 via a first sampling switch 303a, and is also connected to the gate of a PMOS transistor 306. The second sampling capacitor 302b is connected to a second bias voltage node VBN 305 via a second sampling switch 303b, and is also connected to the gate of an NMOS transistor 307. The drains of the PMOS transistor 306 and the NMOS transistor 307 are connected to an output terminal 310, respectively, which is used to output a signal V OUT2 based on the drain-source voltage of the PMOS transistor 306 and the NMOS transistor 307. The two transistors work together to push and pull the output voltage V OUT2 to increase or decrease. When the NMOS transistor is more "off", the PMOS transistor will be more "on", and vice versa, thereby adjusting the current flow direction of the two transistors in an opposite way, thus shifting the output voltage of V OUT by two times, compared to the case of using a single transistor. For example, when the NMOS transistor is "off", its current is small. At the same time, the PMOS transistor is "on" and its current is large. The voltage drops of the two transistors will change accordingly, and the output voltage V OUT2 will be pushed or pulled to a new output level by the two transistors.

第一個取樣開關303a和第二個取樣開關303b被配置為可以由時脈信號 控制。這兩個開關303a和303b被配置為在回應時脈信號 時以相同的方式行為，以便在任何給定時刻，兩個開關303a和303b同時處於開啟（不導通）或關閉（導通）的狀態。具體來說，第一個和第二個開關303a、303b被配置為當時脈信號 為邏輯高電平時，第一個開關303a和第二個開關303b都閉合（導通），當時脈信號 為邏輯低電平時，第一個開關303a和第二個開關303b都打開（不導通）。 The first sampling switch 303a and the second sampling switch 303b are configured to be able to be The two switches 303a and 303b are configured to respond to the clock signal 303a and 303b behave in the same manner at any given moment, so that at any given moment, the two switches 303a and 303b are simultaneously in the open (non-conducting) or closed (conducting) state. Specifically, the first and second switches 303a, 303b are configured to be When the voltage is at a logical high level, the first switch 303a and the second switch 303b are both closed (conducting). When the voltage is at a logical low level, both the first switch 303a and the second switch 303b are open (non-conducting).

當時脈信號 為邏輯高電平時，開關303a、303b閉合，將輸入端301接收到的信號，即第一級200的輸出V OUT1，該信號追蹤著時間變化的輸入信號V IN，提供給第一和第二取樣電容器302a、302b。這會導致第一和第二電容器302a、302b兩端的電壓隨著追蹤保持電路100的第一級輸出變化而變化，即追蹤輸入信號V IN。因此，當開關303a、303b閉合時，電容器302a、302b兩端的電壓取決於輸入信號V IN（具體來說，取決於V CM+ V IN）。通過這種方式，電容器302a、302b追蹤與輸入信號V IN對應的電壓，也就是說，它們充當一個緩衝器，在追蹤模式下，它們有效地儲存（並在追蹤模式期間持續更新）代表任何給定時刻輸入信號V IN的“值”（以電壓形式）。 Current pulse signal When the voltage is at a logical high level, switches 303a and 303b are closed, and the signal received at the input terminal 301, i.e., the output V OUT1 of the first stage 200, which tracks the time-varying input signal V IN , is provided to the first and second sampling capacitors 302a and 302b. This causes the voltage across the first and second capacitors 302a and 302b to change as the first-stage output of the tracking and holding circuit 100 changes, i.e., tracks the input signal V IN . Therefore, when switches 303a and 303b are closed, the voltage across the capacitors 302a and 302b depends on the input signal V IN (specifically, depends on V CM + V IN ). In this manner, capacitors 302a, 302b track the voltage corresponding to input signal V IN , that is, they act as a buffer and, in tracking mode, they effectively store (and continuously update during tracking mode) a “value” (in voltage form) representing the input signal V IN at any given moment.

當時脈信號 為邏輯低電平（保持模式）時，輸入端301接收到的信號V OUT1僅僅是一個固定的電壓，該電壓僅僅依賴於公共模式電壓V CM。在這個時候，由於時脈信號 過渡到邏輯低電平狀態，開關303a、303b被配置為打開。在回應開關303a、303b打開時，電容器302a、302b兩端的電壓變得固定，導致PMOS電晶體306和NMOS電晶體307的閘極上提供的電壓是基於開關303a、303b打開時電容器302a、302b兩端的電壓和第一級200的第一分支提供的新參考電壓V OUT1設置的。這有效地在電晶體306、307的閘極上提供了一個包含關於輸入信號V IN的資訊的輸入，該輸入是在開關303a、303b打開時的輸入信號V IN的資訊。PMOS電晶體306和NMOS電晶體307放大了在其各自閘極上接收到的保持信號，並在輸出端310提供一個電壓。因此，基於PMOS電晶體306和NMOS電晶體307的偏置狀態（因此基於開關303a、303b打開時電容器302a、302b兩端的電壓），在輸出端310提供了一個放大的信號V OUT2。 Current pulse signal When the voltage is at a logical low level (hold mode), the signal V OUT1 received by the input terminal 301 is only a fixed voltage, which depends only on the common mode voltage V CM . At this time, due to the clock signal Transitioning to a logical low state, switches 303a, 303b are configured to be open. In response to switches 303a, 303b being opened, the voltage across capacitors 302a, 302b becomes fixed, resulting in the voltage provided at the gates of PMOS transistor 306 and NMOS transistor 307 being set based on the voltage across capacitors 302a, 302b when switches 303a, 303b are opened and the new reference voltage V OUT1 provided by the first branch of first stage 200. This effectively provides an input at the gates of transistors 306, 307 containing information about the input signal V IN , which is the information of the input signal V IN when switches 303a, 303b are opened. PMOS transistor 306 and NMOS transistor 307 amplify the hold signal received at their respective gates and provide a voltage at output 310. Thus, based on the bias states of PMOS transistor 306 and NMOS transistor 307 (and therefore based on the voltage across capacitors 302a, 302b when switches 303a, 303b are open), an amplified signal V OUT2 is provided at output 310.

在追蹤模式期間，V OUT1上的電壓與V CM+ V IN成正比，取樣開關303a、303b關閉，NMOS電晶體307由電壓VBN偏置，PMOS電晶體306由電壓V BN偏置，因此取樣電容器器302a、302b上的電壓為： 其中，k是取決於偏置電晶體214、218的比例常數。 During tracking mode, the voltage on V OUT1 is proportional to V CM + V IN , sampling switches 303 a, 303 b are closed, NMOS transistor 307 is biased by voltage VBN, and PMOS transistor 306 is biased by voltage VBN , so the voltage on sampling capacitors 302 a, 302 b is: Wherein, k is a proportional constant that depends on the bias transistors 214, 218.

然後，當追蹤模式切換到保持模式時，V OUT1的變化只與V CM成正比，NMOS電晶體307和PMOS電晶體306的閘極電壓基於V OUT1上的電壓和它們各自取樣電容器兩端的現在固定的電壓，如下所示： 同時使用PMOS和NMOS電晶體306、307具有優勢，因為輸入電壓引起了一個電晶體的柵極-源極電壓增加，同時另一個電晶體的柵源電壓減小，反之亦然。相應地，當另一個電晶體兩端的汲極-源極電壓減小時，則一個電晶體兩端的汲極-源極電壓增加，反之亦然，從而使得兩個取樣電容器302a、302b同時對輸出電壓V OUT2產生推拉作用，增加了效果。 Then, when the tracking mode switches to the hold mode, the change in V OUT1 is proportional only to V CM , and the gate voltages of NMOS transistor 307 and PMOS transistor 306 are based on the voltage on V OUT1 and the now fixed voltages across their respective sampling capacitors as follows: Using both PMOS and NMOS transistors 306, 307 has an advantage because the input voltage causes the gate-source voltage of one transistor to increase while the gate-source voltage of the other transistor decreases, and vice versa. Accordingly, when the drain-source voltage across the other transistor decreases, the drain-source voltage across one transistor increases, and vice versa, so that the two sampling capacitors 302a, 302b simultaneously push and pull the output voltage V OUT2 , increasing the effect.

因此，當時脈信號 為邏輯高時，該追蹤保持電路100的第二級300輸出一個基於偏壓電壓VBP和VBN的恒定信號V OUT2。而當時脈信號 為邏輯低時，輸出信號V OUT2基於在取樣開關打開時保持的輸入信號V IN（保持在時脈信號 變為邏輯低時的時間點）。如圖3所示，在高取樣速率和因此較短的時間尺度下，輸出信號V OUT2呈現為一個曲線，該曲線從開關303a、303b打開時開始，即時脈信號 轉換為邏輯低時開始，並且隨著時間的推移，基於電容器302a、302b兩端的保持電壓（這又基於輸入電壓V IN）逐漸增長，並且最終趨於一個穩定的最終狀態值。該曲線是由於電晶體306、307響應改變的閘極電壓和在新平衡點上穩定的時間而產生的。 Therefore, the clock signal When the clock signal is high, the second stage 300 of the track-and-hold circuit 100 outputs a constant signal V OUT2 based on the bias voltages VBP and VBN. When the sampling switch is open, the output signal V OUT2 is based on the input signal V IN (maintained at the clock signal As shown in FIG3 , at a high sampling rate and thus a short time scale, the output signal V OUT2 appears as a curve starting from when switches 303a, 303b are turned on, i.e., the clock signal The transition begins at a logical low and, over time, gradually increases based on the holding voltage across capacitors 302a, 302b (which in turn is based on the input voltage V IN ), and eventually approaches a stable final state value. This curve is due to the time it takes for transistors 306, 307 to respond to the changing gate voltage and settle at the new equilibrium point.

輸出V OUT2310無需達到穩定狀態，即可被後續處理電路可靠使用，因為對於所有輸入電壓，該曲線將採取相同的形式。因此，只要後續處理電路的定時是始終考慮V OUT2輸出信號的相同時間點（或時間段的一部分），它們將始終以相同的程度依賴於保持的輸入電壓。因此，可以相對容易地比較追蹤與保持輸出信號的這些輸出，即使在較短的時間尺度上也可以。 The output V OUT2 310 does not need to reach a stable state in order to be reliably used by subsequent processing circuitry, because the curve will take the same form for all input voltages. Therefore, as long as the timing of subsequent processing circuitry is such that the same points in time (or portions of time periods) of the V OUT2 output signal are always considered, they will always depend to the same degree on the maintained input voltage. Therefore, it is relatively easy to compare these outputs that track with the maintained output signal, even on shorter time scales.

儘管圖中顯示了兩個電容器302a、302b連接到各自的開關和電晶體，但應該注意，追蹤與保持電路100的第二級300的功能也可以通過僅使用每個元件中的一個來實現。這方面的示例顯示在圖4A和4B中。Although two capacitors 302a, 302b are shown connected to respective switches and transistors, it should be noted that the functionality of the second stage 300 of the tracking and holding circuit 100 can also be achieved by using only one of each component. Examples of this are shown in Figures 4A and 4B.

圖4A顯示了根據本發明的第二實施例的追蹤與保持電路的第二級400a。第二級400a包括一個輸入端401a，用於接收圖2所示的追蹤與保持電路100的第一級200的輸出V OUT1。如上所述，當時脈源的信號 為邏輯高時，輸入信號V OUT1追蹤時間變化的輸入信號V IN，並且在時脈信號為邏輯低時基於共模電壓V CM輸出一個固定電壓。 FIG4A shows a second stage 400a of a tracking and holding circuit according to a second embodiment of the present invention. The second stage 400a includes an input terminal 401a for receiving the output V OUT1 of the first stage 200 of the tracking and holding circuit 100 shown in FIG2 . As described above, when the signal of the pulse source The input signal V OUT1 tracks the time-varying input signal V IN when the clock signal is logically high, and outputs a fixed voltage based on the common-mode voltage V CM when the clock signal is logically low.

輸入端401a連接到一個單一的取樣電容器402a，該電容器通過取樣開關403a連接到一個偏壓電源V p供電，同時還連接到一個PMOS電晶體406的閘極。 PMOS電晶體406的汲極連接到一個輸出端410a，該輸出端用於輸出基於PMOS電晶體306的汲極輸出的信號V OUT2。 The input terminal 401a is connected to a single sampling capacitor 402a, which is connected to a bias power supply Vp through a sampling switch 403a and is also connected to the gate of a PMOS transistor 406. The drain of the PMOS transistor 406 is connected to an output terminal 410a, which is used to output a signal VOUT2 based on the drain output of the PMOS transistor 306.

開關403a配置為可以回應時脈信號 的控制，因此當時脈信號 邏輯高時，第一個開關403a是閉合的，而當時脈信號 為邏輯低時，開關403a是斷開的。當時脈信號 為邏輯高時，開關403a是閉合的，基於在輸入端401a接收到的信號和偏壓電壓V P，跨電容402a產生一個電壓。因此，當開關403a閉合時，跨電容402a產生的電壓依賴於（並隨著）輸入信號V IN而變化。因此，電容402a充當一個緩衝器，實際上儲存代表輸入信號的“值”，在開關403a閉合時持續更新。 Switch 403a is configured to respond to a clock signal Therefore, the pulse signal When the logic is high, the first switch 403a is closed, and the clock signal When the clock signal is logic low, switch 403a is open. When logically high, switch 403a is closed, and a voltage is developed across capacitor 402a based on the signal received at input 401a and the bias voltage V P . Thus, when switch 403a is closed, the voltage developed across capacitor 402a is dependent on (and varies with) the input signal V IN . Thus, capacitor 402a acts as a buffer, effectively storing a “value” representing the input signal that is continuously updated while switch 403a is closed.

當時脈信號 為邏輯低時，輸入端401a接收到的信號變化，僅基於固定的共模電壓V CM。當時脈信號 變為低電平時，開關403a打開，電容402a上的電壓變為固定值，導致PMOS電晶體406的閘極電壓根據開關403a打開時輸入信號V IN的幅度而改變（即對應於開關打開之前的追蹤信號）。PMOS電晶體406在其汲極輸出一個基於其閘極接收到的改變信號的信號，並將其提供到輸出端410a，其中它作為V OUT2輸出。 Current pulse signal When the common mode voltage V CM is logically low, the signal received by the input terminal 401a changes only based on the fixed common mode voltage V CM . When V IN becomes low, switch 403a is turned on, and the voltage on capacitor 402a becomes a fixed value, causing the gate voltage of PMOS transistor 406 to change according to the amplitude of input signal V IN when switch 403a is turned on (i.e., corresponding to the tracking signal before the switch is turned on). PMOS transistor 406 outputs a signal at its drain based on the changing signal received at its gate, and provides it to output terminal 410a, where it is output as V OUT2 .

與圖3描述的類似，圖4a中所示的第二級400a在時脈信號為邏輯高時輸出一個基於偏壓電壓V P的信號V OUT2，並且在時脈信號為邏輯低時基於取樣輸入信號V IN而改變。 Similar to the description of FIG. 3 , the second stage 400 a shown in FIG. 4 a outputs a signal V OUT2 based on the bias voltage VP when the clock signal is logically high, and changes based on the sampled input signal V IN when the clock signal is logically low.

因此，第二級400b在功能上等同於圖4A中顯示的第二級400a，唯一的區別是PMOS電晶體406被NMOS電晶體407替代。第二級400b的功能方式與上述相對於圖4A描述的方式等效，並且在時脈信號 為邏輯高時，它在輸出410b處生成一個基於偏壓電壓 V N信號V OUT2，在時脈信號 為邏輯低時，它基於取樣的輸入信號V IN發生變化。 Thus, the second stage 400b is functionally equivalent to the second stage 400a shown in FIG. 4A, with the only difference being that the PMOS transistor 406 is replaced by the NMOS transistor 407. The second stage 400b functions in an equivalent manner to that described above with respect to FIG. 4A, and in the case of a clock signal When it is logically high, it generates a signal V OUT2 based on the bias voltage V N at the output 410b, and the clock signal When it is logically low, it changes based on the sampled input signal V IN .

熟悉本領域的技術人員將會明白，本發明已經通過描述一個或多個具體實施方式進行了說明，但不限於這些實施方式；在所附請求項的範圍內，有很多變化和修改是可能的。It will be apparent to those skilled in the art that the present invention has been described by way of one or more specific embodiments but is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.

100:追蹤保持電路 200:第一級 201:正供電軌 203:負供電軌 210:第一部分 211:PMOS電晶體 212:PMOS電晶體 213:NMOS電晶體 214:NMOS電晶體 216:PMOS電晶體 218:NMOS電晶體 220:輸出端 222:PMOS電晶體（M CAS） 224:NMOS電晶體（M MIR） 230:第一節點 232:第二節點 250:回饋部分 300:第二級 301:輸入端 302a:第一取樣電容器 302b:第二取樣電容器 303a:開關 303b:開關 304:第一偏壓電壓節點V BP306:PMOS電晶體 307:NMOS電晶體 310:輸出端 400a:第二級 400b:第二級 401a:輸入端 402a:電容器 403a:開關 406:開關 407:NMOS電晶體 410a:輸出端 100: Tracking and holding circuit 200: First stage 201: Positive supply rail 203: Negative supply rail 210: First section 211: PMOS transistor 212: PMOS transistor 213: NMOS transistor 214: NMOS transistor 216: PMOS transistor 218: NMOS transistor 220: Output terminal 222: PMOS transistor (M CAS ) 224: NMOS transistor (M MIR ) 230: First node 232: Second node 250: Feedback section 300: Second stage 301: Input terminal 302a: First sampling capacitor 302b: Second sampling capacitor 303a: Switch 303b: Switch 304: First bias voltage node V BP 306: PMOS transistor 307: NMOS transistor 310: output terminal 400a: second stage 400b: second stage 401a: input terminal 402a: capacitor 403a: switch 406: switch 407: NMOS transistor 410a: output terminal

以下將參考附圖，對發明的某些首選實施方式進行例示描述。圖示如下： 圖1是根據本發明的追蹤保持電路的示意圖； 圖2是根據本發明的追蹤保持電路的第一部分的示意圖； 圖3是根據本發明的追蹤保持電路的第二部分的示意圖； 圖4是根據本發明的追蹤保持電路的第二部分的另一種實現示意圖。 The following will refer to the attached figures to illustrate some preferred embodiments of the invention. The figures are as follows: Figure 1 is a schematic diagram of a tracking and holding circuit according to the present invention; Figure 2 is a schematic diagram of the first part of the tracking and holding circuit according to the present invention; Figure 3 is a schematic diagram of the second part of the tracking and holding circuit according to the present invention; Figure 4 is another implementation schematic diagram of the second part of the tracking and holding circuit according to the present invention.

100:追蹤與保持電路 100: Tracking and holding circuit

200:第一級 200: Level 1

210:第一部分 210: Part 1

250:回饋部分 250: Feedback part

300:第二級 300: Second level

Claims (24)

一種追蹤與保持電路，用於取樣一輸入訊號，該追蹤與保持電路包括一第一級和一第二級； 其中，該追蹤與保持電路被設置為交替地操作在一追蹤模式和一保持模式下； 其中，在該保持模式下，該第一級被設置為在一第一節點處產生一恆定輸出電壓； 其中，在該追蹤模式下，該第一級被設置為產生由該第一節點處的輸入訊號所調變的該恆定輸出電壓； 其中，該第二級包括： 一第一取樣電容器，具有一第一側連接至該第一節點，及一第二側透過一第一取樣開關連接至一第一偏壓； 其中，在該第一取樣電容器和該第一取樣開關之間的一第一取樣節點處提供一第一取樣輸出； 其中，在該追蹤模式下，該第一取樣開關閉合，且該第一取樣電容器兩端的電壓隨著該輸入訊號的變化而改變；以及 其中，在該保持模式下，該第一取樣開關打開，該第一取樣電容器兩端的電壓變為固定，並且該第一取樣輸出變成根據該第一節點處的該電壓和該第一取樣電容器兩端的該固定電壓來設定。 A tracking and holding circuit for sampling an input signal, the tracking and holding circuit comprising a first stage and a second stage; wherein the tracking and holding circuit is configured to operate alternately in a tracking mode and a holding mode; wherein, in the holding mode, the first stage is configured to generate a constant output voltage at a first node; wherein, in the tracking mode, the first stage is configured to generate the constant output voltage modulated by the input signal at the first node; wherein the second stage comprises: a first sampling capacitor having a first side connected to the first node and a second side connected to a first bias voltage via a first sampling switch; wherein a first sampling output is provided at a first sampling node between the first sampling capacitor and the first sampling switch; Wherein, in the tracking mode, the first sampling switch is closed, and the voltage across the first sampling capacitor changes with the change of the input signal; and Wherein, in the holding mode, the first sampling switch is opened, the voltage across the first sampling capacitor becomes fixed, and the first sampling output becomes set according to the voltage at the first node and the fixed voltage across the first sampling capacitor. 如請求項1所述的追蹤與保持電路，其中第二級包括一個第二取樣電容器，其第一側連接到第一節點，第二側通過第二取樣開關連接到第二偏壓電壓； 其中，在第二取樣電容器和第二取樣開關之間的第二取樣節點處提供第二取樣輸出； 其中，在追蹤模式下，第二取樣開關關閉，第二取樣電容器兩端的電壓隨著輸入信號的變化而變化；以及 其中，在保持模式下，第二取樣開關打開，第二取樣電容器兩端的電壓固定，第二取樣輸出基於第一節點的電壓和第二取樣電容器兩端的固定電壓被設置。 A tracking and holding circuit as described in claim 1, wherein the second stage includes a second sampling capacitor having a first side connected to the first node and a second side connected to a second bias voltage via a second sampling switch; wherein a second sampling output is provided at a second sampling node between the second sampling capacitor and the second sampling switch; wherein, in a tracking mode, the second sampling switch is closed, and the voltage across the second sampling capacitor changes as the input signal changes; and wherein, in a holding mode, the second sampling switch is opened, the voltage across the second sampling capacitor is fixed, and the second sampling output is set based on the voltage of the first node and the fixed voltage across the second sampling capacitor. 如請求項1或2所述的追蹤與保持電路，其中第一取樣輸出連接到第一放大器，使第一放大器的輸出依賴於第一取樣輸出；該放大器在第三節點提供一個輸出信號。A tracking and holding circuit as described in claim 1 or 2, wherein the first sampled output is connected to a first amplifier so that the output of the first amplifier depends on the first sampled output; the amplifier provides an output signal at a third node. 如請求項3所述的追蹤與保持電路，其中第一放大器是第一電晶體，第一取樣輸出連接到第一電晶體的閘極。A tracking and holding circuit as described in claim 3, wherein the first amplifier is a first transistor and the first sampling output is connected to the gate of the first transistor. 如請求項3或4所述的追蹤與保持電路，其中第二取樣輸出連接到第二放大器，使第二放大器的輸出依賴於第二取樣輸出；該第二放大器在第三節點提供一個輸出信號。A track and hold circuit as described in claim 3 or 4, wherein the second sampled output is connected to a second amplifier so that the output of the second amplifier depends on the second sampled output; the second amplifier provides an output signal at a third node. 如請求項5所述的追蹤與保持電路，其中第二放大器是第二電晶體，第二取樣輸出連接到第二電晶體的閘極。A tracking and holding circuit as described in claim 5, wherein the second amplifier is a second transistor and the second sampling output is connected to the gate of the second transistor. 如請求項2所述的追蹤與保持電路，其中第一取樣輸出連接到PMOS電晶體的閘極，使得在第三節點處的PMOS電晶體的輸出依賴於第一取樣輸出；並且第二取樣輸出連接到NMOS電晶體的閘極，使得在第三節點處的NMOS電晶體的輸出依賴於第二取樣輸出。A tracking and holding circuit as described in claim 2, wherein the first sampling output is connected to the gate of the PMOS transistor so that the output of the PMOS transistor at the third node depends on the first sampling output; and the second sampling output is connected to the gate of the NMOS transistor so that the output of the NMOS transistor at the third node depends on the second sampling output. 如前述任一請求項所述的追蹤與保持電路，其中第一級包括第一分支和第二分支，第一分支和第二分支在第二節點和第一節點之間交替形成電流通路； 其中，第一分支被設計為在第一節點處生成恒定的輸出電壓；以及 其中，第二分支被設計為在第一節點處生成受輸入信號調變的恒定輸出電壓。 A tracking and holding circuit as described in any of the preceding claims, wherein the first stage includes a first branch and a second branch, the first branch and the second branch alternately forming a current path between the second node and the first node; wherein the first branch is designed to generate a constant output voltage at the first node; and wherein the second branch is designed to generate a constant output voltage modulated by an input signal at the first node. 如請求項8所述的追蹤保持電路，其中第一分支和第二分支是在回應來自外部時脈源的時脈信號的情況下交替操作的。A tracking and holding circuit as described in claim 8, wherein the first branch and the second branch operate alternately in response to a clock signal from an external clock source. 如請求項9所述的追蹤保持電路，其中第一分支包括第一時脈電晶體，設置為在其閘極接收時脈信號，而第二分支包括第二時脈電晶體，設置為在其閘極接收反相時脈信號。A tracking and holding circuit as described in claim 9, wherein the first branch includes a first clock transistor configured to receive a clock signal at its gate, and the second branch includes a second clock transistor configured to receive an inverted clock signal at its gate. 如請求項9或10所述的追蹤與保持電路，當時脈訊號為高時，第二分支開始運作；而當時脈訊號為低時，第一分支開始運作。In the tracking and holding circuit as described in claim 9 or 10, when the clock signal is high, the second branch starts to operate; and when the clock signal is low, the first branch starts to operate. 如請求項9至11任一項所述的追蹤與保持電路，當時脈訊號為高時，第一取樣開關閉合；而當時脈訊號為低時，第一取樣開關斷開。In the tracking and holding circuit as described in any one of claim items 9 to 11, when the clock signal is high, the first sampling switch is closed; and when the clock signal is low, the first sampling switch is opened. 如請求項8至12任一項所述的追蹤與保持電路，第二節點是一個電壓軌或其他電流供應。A tracking and holding circuit as described in any one of claims 8 to 12, wherein the second node is a voltage rail or other current supply. 如請求項8至13任一項所述的追蹤與保持電路，其中第二節點通過第一電流控制電晶體連接至第一分支和第二分支。A tracking and holding circuit as described in any one of claims 8 to 13, wherein the second node is connected to the first branch and the second branch through a first current control transistor. 如請求項14項所述的追蹤與保持電路，其中第一電流控制電晶體是一個PMOS電晶體，並且第一電流控制電晶體的閘極被配置成連接到選定以設定第一分支和第二分支通過的電流的第一偏壓電壓。A tracking and holding circuit as described in claim 14, wherein the first current control transistor is a PMOS transistor, and the gate of the first current control transistor is configured to be connected to a first bias voltage selected to set the current passing through the first branch and the second branch. 如請求項8至15任一項所述的追蹤與保持電路，其中通過第二電流控制電晶體，電流源連接到第一分支、第二分支和第一節點。A tracking and holding circuit as described in any one of claims 8 to 15, wherein a current source is connected to the first branch, the second branch and the first node through a second current control transistor. 如請求項16所述的追蹤與保持電路，其中第二電流控制電晶體是一個NMOS電晶體，並且第二電流控制電晶體的閘極被配置成連接到選定以設定第一分支和第二分支通過的電流的第二偏壓電壓。A tracking and holding circuit as described in claim 16, wherein the second current control transistor is an NMOS transistor, and the gate of the second current control transistor is configured to be connected to a second bias voltage selected to set the current passing through the first branch and the second branch. 如請求項8至17任一項所述的追蹤與保持電路，其中第一分支包括用於接收共模電壓的第一偏壓部分。A tracking and holding circuit as described in any of claims 8 to 17, wherein the first branch includes a first bias portion for receiving a common mode voltage. 如請求項18所述的追蹤與保持電路，其中第一偏壓部分是連接在追蹤與保持電路的第一分支上的第一偏壓電晶體，並且被配置成在其閘極處接收共模電壓。A tracking and holding circuit as described in claim 18, wherein the first bias portion is a first bias transistor connected to a first branch of the tracking and holding circuit and is configured to receive a common mode voltage at its gate. 如請求項8至19任一項所述的追蹤與保持電路，其中第二分支包括一個第二偏壓部分，用於接收來自外部源的輸入信號。A tracking and holding circuit as described in any one of claims 8 to 19, wherein the second branch includes a second bias section for receiving an input signal from an external source. 如請求項20所述的追蹤與保持電路，其中第二偏壓部分是連接在追蹤和保持電路的第二分支上的第二偏壓電晶體，並被配置成在其閘極處接收輸入信號。A tracking and holding circuit as described in claim 20, wherein the second bias portion is a second bias transistor connected to the second branch of the tracking and holding circuit and is configured to receive an input signal at its gate. 如請求項21所述的追蹤與保持電路，其中第二偏壓電晶體被安排成在其閘極處接收共模電壓和輸入信號的總和。A tracking and holding circuit as described in claim 21, wherein the second bias transistor is arranged to receive the sum of the common mode voltage and the input signal at its gate. 如前述任一項所述的追蹤與保持電路，電路包括一個用於提高第一級線性度的反饋元件。A track and hold circuit as described in any of the preceding items, the circuit including a feedback element for improving the linearity of the first stage. 如前述任一項所述的追蹤和保持電路，輸入信號是一個時變的類比電壓。In a track and hold circuit as described in any of the preceding items, the input signal is a time-varying analog voltage.
TW112131342A 2022-09-07 2023-08-21 Track and hold circuit TW202412007A (en)

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