TW202405493A - On-chip optical interconnect structure and method of manufacturing the same - Google Patents
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- 235000012431 wafers Nutrition 0.000 claims description 377
- 230000008878 coupling Effects 0.000 claims description 78
- 238000010168 coupling process Methods 0.000 claims description 78
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- 229910052751 metal Inorganic materials 0.000 claims description 26
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- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
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- 240000000233 Melia azedarach Species 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000708 deep reactive-ion etching Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/26—Optical coupling means
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
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Abstract
Description
本發明涉及光互連技術領域，特別涉及一種片上光互連結構及其製作方法。The present invention relates to the technical field of optical interconnection, and in particular to an on-chip optical interconnection structure and a manufacturing method thereof.
隨著頻寬的資料處理和通信，資料中心和高性能電腦的不斷增長的需求必須不斷提高自己的能力和表現。該增強資料處理性能應該伴隨著功耗的減少以及較低的製造成本。矽光子可能是最有前途的技術，例如，可以在通過波長分波多工(WDM)使得多個通道並行，從而實現高頻寬鏈路。With the growing demand for bandwidth for data processing and communications, data centers and high-performance computers must continually improve their capabilities and performance. This enhanced data processing performance should be accompanied by reduced power consumption and lower manufacturing costs. Silicon photonics may be the most promising technology, for example, enabling high-bandwidth links by parallelizing multiple channels through wavelength division multiplexing (WDM).
目前現有的光互連技術，通常指的是晶片上的互連，即基於單顆晶片內的光互連；對於光互連技術而言，晶片的尺寸越大，其優勢越明顯。但是，由於受晶圓代工工廠的限制，晶片尺寸（包括矽光子晶片）設有上限，暫無成熟製程或者成熟代工廠提供單顆晶片尺寸不受限制的矽光子晶片，故導致該光互連的技術應用受到限制，無法充分發揮該技術的潛能。The current existing optical interconnection technology usually refers to the interconnection on the chip, that is, based on the optical interconnection within a single chip. For optical interconnection technology, the larger the size of the chip, the more obvious its advantages. However, due to restrictions on wafer foundries, there is an upper limit on chip size (including silicon photonic wafers). There is currently no mature process or mature foundry that can provide silicon photonic wafers with unlimited single wafer size. Lian's technology applications are limited and unable to realize the technology's full potential.
為了克服現有技術的不足，本發明的目的在於提供一種片上光互連結構及其製作方法，以解決現有片上光互連技術受限於單顆光子積體電路晶片的尺寸限制的問題。In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide an on-chip optical interconnection structure and a manufacturing method thereof to solve the problem that the existing on-chip optical interconnection technology is limited by the size limitation of a single photonic integrated circuit chip.
本發明的目的採用以下技術方案實現：The purpose of the present invention is achieved by adopting the following technical solutions:
根據本發明的一方面，提供一種片上光互連結構，包括： 半導體晶片，所述半導體晶片包括多個第一光子積體電路晶片，每個所述第一光子積體電路晶片具有相對的第一表面和第二表面，其中，每個所述第一光子積體電路晶片包括多個第一光波導； 多個第二光子積體電路晶片，每個所述第二光子積體電路晶片包括多個第二光波導，每個所述第二光子積體電路晶片固定於相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上並覆蓋相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界； 其中，相鄰的兩個所述第一光子積體電路晶片通過固定於該相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上的所述第二光子積體電路晶片進行光互連。 According to one aspect of the present invention, an on-chip optical interconnect structure is provided, including: A semiconductor wafer, the semiconductor wafer includes a plurality of first photonic integrated circuit wafers, each of the first photonic integrated circuit wafers having opposite first and second surfaces, wherein each of the first photonic integrated circuit wafers The bulk circuit chip includes a plurality of first optical waveguides; A plurality of second photonic integrated circuit wafers, each of the second photonic integrated circuit wafers includes a plurality of second optical waveguides, and each of the second photonic integrated circuit wafers is fixed to two adjacent second photonic integrated circuit wafers. A portion of the first surface of a photonic integrated circuit chip and covering the corresponding area boundaries of two adjacent first photonic integrated circuit chips on the semiconductor wafer; Wherein, two adjacent first photonic integrated circuit wafers pass through the second photonic integrated body fixed on part of the first surface of the two adjacent first photonic integrated circuit wafers. Circuit wafers are optically interconnected.
進一步地，所述多個第二光子積體電路晶片是無源光子積體電路晶片。Further, the plurality of second photonic integrated circuit wafers are passive photonic integrated circuit wafers.
進一步地，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片，該相鄰的兩個所述第一光子積體電路晶片的所述多個第一光波導與固定於該相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上的所述第二光子積體電路晶片的所述多個第二光波導一一對應，以將該相鄰的兩個所述第一光子積體電路晶片進行光互連。Further, for two adjacent first photonic integrated circuit wafers that are optically interconnected, the plurality of first optical waveguides of the two adjacent first photonic integrated circuit wafers are connected to fixed The plurality of second optical waveguides of the second photonic integrated circuit chip on the part of the first surface of the two adjacent first photonic integrated circuit chips are in one-to-one correspondence, so as to connect the Two adjacent first photonic integrated circuit wafers are optically interconnected.
可選地，在所述半導體晶片的厚度方向上，該相鄰的兩個所述第一光子積體電路晶片的所述多個第一光波導的端部的投影與固定於該相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上的每個所述第二光子積體電路晶片的所述多個第二光波導的端部的投影以一一對應的方式交疊。Optionally, in the thickness direction of the semiconductor wafer, the projections of the ends of the plurality of first optical waveguides of the two adjacent first photonic integrated circuit wafers are fixed to the adjacent ones. The projections of the ends of the plurality of second optical waveguides of each of the second photonic integrated circuit wafers on the portions of the first surfaces of the two first photonic integrated circuit wafers are in one-to-one correspondence. ways overlap.
可選地，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片，在該相鄰的兩個所述第一光子積體電路晶片的所述第一表面上靠近該相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界各設置有至少一個光束重定向元件，其中，每個所述光束重定向元件用於改變光束的方向以進入每個所述第一光波導和/或每個所述第二光波導中；針對固定於該相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上的所述第二光子積體電路晶片，在平行該第二光子積體電路晶片所在平面的方向上，在該第二光子積體電路晶片的所述多個第二光波導的兩側均設置有一組光柵耦合器，每組所述光柵耦合器分別與該相鄰的兩個所述第一光子積體電路晶片的所述多個第一光波導一一對應並且用於光耦合，其中，每組所述光柵耦合器包括至少一個光柵耦合器元件；其中，相鄰的兩個所述第一光子積體電路晶片通過所述光束重定向元件、兩組光柵耦合器以及所述多個第二光波導進行光互連。Optionally, for the two adjacent first photonic integrated circuit wafers for optical interconnection, the first surface of the adjacent two first photonic integrated circuit wafers is close to the The two adjacent first photonic integrated circuit wafers are each provided with at least one beam redirection element at the corresponding area boundary on the semiconductor wafer, wherein each of the beam redirection elements is used to change the direction of the light beam. to enter each of the first optical waveguides and/or each of the second optical waveguides; for the components fixed on the first surfaces of the two adjacent first photonic integrated circuit wafers The second photonic integrated circuit chip is provided with a plurality of second optical waveguides on both sides of the second photonic integrated circuit chip in a direction parallel to the plane of the second photonic integrated circuit chip. A group of grating couplers, each group of the grating couplers corresponds one-to-one to the plurality of first optical waveguides of the two adjacent first photonic integrated circuit wafers and is used for optical coupling, wherein each The group of grating couplers includes at least one grating coupler element; wherein two adjacent first photonic integrated circuit wafers pass through the beam redirection element, two groups of grating couplers and the plurality of second Optical waveguides perform optical interconnections.
進一步地，每個所述第一光子積體電路晶片包括多個金屬連接柱，並且所述金屬連接柱的一側表面從每個所述第一光子積體電路晶片的所述第一表面露出。Further, each of the first photonic integrated circuit wafers includes a plurality of metal connection posts, and one side surface of the metal connection posts is exposed from the first surface of each of the first photonic integrated circuit wafers. .
進一步地，所述片上光互連結構還包括固定於至少一個所述第一光子積體電路晶片的所述第一表面上的至少一個電子積體電路晶片。Further, the on-chip optical interconnect structure further includes at least one electronic integrated circuit chip fixed on the first surface of at least one first photonic integrated circuit chip.
進一步地，在所述半導體晶片的所述第一表面上設置有多個光耦合區，每個所述光耦合區內設置有光耦合介面。Further, a plurality of optical coupling regions are provided on the first surface of the semiconductor wafer, and an optical coupling interface is provided in each of the optical coupling regions.
進一步地，所述片上光互連結構還包括多個偽晶片，所述多個偽晶片一一對應固定於所述半導體晶片的所述第一表面上的所述多個光耦合區上，其中，每個所述偽晶片具有上下開口的空腔，所述空腔的開口面對所述光耦合介面並覆蓋所述光耦合介面。Further, the on-chip optical interconnect structure further includes a plurality of dummy wafers, the plurality of dummy wafers are fixed on the plurality of optical coupling areas on the first surface of the semiconductor wafer in one-to-one correspondence, wherein , Each of the dummy wafers has a cavity with upper and lower openings, and the opening of the cavity faces the optical coupling interface and covers the optical coupling interface.
進一步地，所述片上光互連結構還包括封裝層，所述封裝層覆蓋在所述半導體晶片的所述第一表面上，並且包覆所述多個偽晶片的側面、至少一個電子積體電路晶片的側面以及所述多個第二光子積體電路晶片。Further, the on-chip optical interconnect structure further includes an encapsulation layer covering the first surface of the semiconductor wafer and covering the sides of the plurality of dummy wafers and at least one electronic integrated body. A side surface of the circuit chip and the plurality of second photonic integrated circuit chips.
進一步地，所述片上光互連結構還包括多個導光結構，所述多個導光結構與所述多個偽晶片一一對應，其中，每個所述導光結構穿過每個所述偽晶片的所述空腔，以將光信號耦合至對應的所述光耦合介面。Further, the on-chip optical interconnection structure further includes a plurality of light guide structures, the plurality of light guide structures correspond to the plurality of dummy wafers, wherein each of the light guide structures passes through each of the dummy wafers. The cavity of the dummy chip is used to couple optical signals to the corresponding optical coupling interface.
根據本發明的另一方面，還提供了一種片上光互連結構的製作方法，所述方法包括： 提供半導體晶片，所述半導體晶片包括多個第一光子積體電路晶片，每個所述第一光子積體電路晶片具有相對的第一表面和第二表面，其中，每個所述第一光子積體電路晶片包括多個第一光波導； 提供多個第二光子積體電路晶片，每個所述第二光子積體電路晶片包括多個第二光波導，將每個所述第二光子積體電路晶片固定在相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上並覆蓋相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界； 其中，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片，將每個所述第二光子積體電路晶片的所述多個第二光波導與該相鄰的兩個所述第一光子積體電路晶片的所述多個第一光波導進行一一對準，以將該相鄰的兩個所述光子積體電路晶片進行光互連。 According to another aspect of the present invention, a method for manufacturing an on-chip optical interconnection structure is also provided. The method includes: A semiconductor wafer is provided, the semiconductor wafer including a plurality of first photonic integrated circuit wafers, each of the first photonic integrated circuit wafers having opposing first and second surfaces, wherein each of the first photonic integrated circuit wafers The integrated circuit chip includes a plurality of first optical waveguides; A plurality of second photonic integrated circuit wafers are provided, each of the second photonic integrated circuit wafers includes a plurality of second optical waveguides, and each of the second photonic integrated circuit wafers is fixed to two adjacent ones. Part of the first surface of the first photonic integrated circuit chip covers the corresponding area boundaries of the two adjacent first photonic integrated circuit chips on the semiconductor wafer; Wherein, for two adjacent first photonic integrated circuit wafers that are optically interconnected, the plurality of second optical waveguides of each second photonic integrated circuit wafer are connected to the two adjacent first photonic integrated circuit wafers. The plurality of first optical waveguides of each of the first photonic integrated circuit chips are aligned one by one to optically interconnect the two adjacent photonic integrated circuit chips.
進一步地，所述方法還包括：將每個所述第二光子積體電路晶片以背面貼裝的方式固定在相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上並覆蓋相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界；或者 去除每個所述第二光子積體電路晶片的底部半導體層，將已去除底部半導體層的每個所述第二光子積體電路晶片以正面貼裝的方式固定在相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上並覆蓋相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界。 Further, the method further includes: fixing each of the second photonic integrated circuit wafers on part of the first surfaces of the two adjacent first photonic integrated circuit wafers in a back-mounted manner. on and covering the corresponding area boundaries of the two adjacent first photonic integrated circuit wafers on the semiconductor wafer; or Remove the bottom semiconductor layer of each of the second photonic integrated circuit wafers, and fix each of the second photonic integrated circuit wafers with the bottom semiconductor layer removed to two adjacent ones in a front-mounted manner. A portion of the first surface of the first photonic integrated circuit wafer covers the corresponding area boundaries of the two adjacent first photonic integrated circuit wafers on the semiconductor wafer.
可選地，所述方法還包括：在所述半導體晶片的厚度方向上，將該相鄰的兩個所述第一光子積體電路晶片的所述多個第一光波導的端部的投影與固定於該相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上的每個所述第二光子積體電路晶片的所述多個第二光波導的端部的投影以一一對應的方式交疊，以通過絕熱耦合的方式將相鄰的兩個所述第一光子積體電路晶片進行光互連。Optionally, the method further includes: projecting the ends of the plurality of first optical waveguides of the two adjacent first photonic integrated circuit wafers in the thickness direction of the semiconductor wafer. and the end portions of the plurality of second optical waveguides of each of the second photonic integrated circuit wafers fixed on the portions of the first surfaces of the two adjacent first photonic integrated circuit wafers. The projections overlap in a one-to-one correspondence manner to optically interconnect the two adjacent first photonic integrated circuit wafers through adiabatic coupling.
可選地，所述方法還包括：在該相鄰的兩個所述第一光子積體電路晶片的所述第一表面上靠近該相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界各放置有至少一個光束重定向元件；其中，每個所述光束重定向元件用於改變光束的方向以進入每個所述第一光波導和/或每個所述第二光波導中；以及針對固定於該相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上的所述第二光子積體電路晶片，在平行於該第二光子積體電路晶片所在平面的方向上，在該第二光子積體電路晶片的所述多個第二光波導的兩側均形成有一組光柵耦合器，每組所述光柵耦合器分別與該相鄰的兩個所述光子積體電路晶片的所述多個第一光波導一一對應並且用於光耦合，其中，每組所述光柵耦合器包括至少一個光柵耦合器元件；其中，相鄰的兩個所述第一光子積體電路晶片通過所述光束重定向元件、兩組光柵耦合器以及所述多個第二光波導進行光互連。Optionally, the method further includes: placing the first photonic integrated circuit wafer close to the two adjacent first photonic integrated circuit wafers on the first surface of the adjacent two first photonic integrated circuit wafers. At least one beam redirecting element is placed at each corresponding area boundary on the semiconductor wafer; wherein each beam redirecting element is used to change the direction of the beam to enter each of the first optical waveguides and/or each in the second optical waveguide; and for the second photonic integrated circuit chip fixed on the first surface of part of the two adjacent first photonic integrated circuit chips, in parallel with the In the direction of the plane of the second photonic integrated circuit chip, a group of grating couplers is formed on both sides of the plurality of second optical waveguides of the second photonic integrated circuit chip, and each group of the grating couplers is respectively The plurality of first optical waveguides of the two adjacent photonic integrated circuit wafers correspond one to one and are used for optical coupling, wherein each group of the grating couplers includes at least one grating coupler element; wherein , two adjacent first photonic integrated circuit wafers are optically interconnected through the beam redirection element, two sets of grating couplers and the plurality of second optical waveguides.
進一步地，所述方法還包括：在每個所述第一光子積體電路晶片內製作多個金屬連接柱，並將所述金屬連接柱的一側表面從每個所述第一光子積體電路晶片的所述第一表面露出。Further, the method further includes: making a plurality of metal connection posts in each of the first photonic integrated circuit wafers, and removing one side surface of the metal connection posts from each of the first photonic integrated circuit wafers. The first surface of the circuit chip is exposed.
進一步地，所述方法還包括：在將每個所述第二光子積體電路晶片固定在相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上並覆蓋相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界之後，針對至少一個所述第一光子積體電路晶片，提供與該第一光子積體電路晶片對應的至少一個電子積體電路晶片，並將所述至少一個電子積體電路晶片固定在該第一光子積體電路晶片的所述第一表面的對應區域。Further, the method further includes: fixing each second photonic integrated circuit wafer on part of the first surface of two adjacent first photonic integrated circuit wafers and covering the adjacent ones. After the corresponding area boundaries of the two first photonic integrated circuit wafers on the semiconductor wafer, for at least one of the first photonic integrated circuit wafers, at least one of the first photonic integrated circuit wafers corresponding to the first photonic integrated circuit wafer is provided. An electronic integrated circuit wafer, and fixing the at least one electronic integrated circuit wafer on the corresponding area of the first surface of the first photonic integrated circuit wafer.
進一步地，所述方法還包括：在所述半導體晶片的所述第一表面上設置多個光耦合區，在每個所述光耦合區內設置光耦合介面；提供多個偽晶片，每個所述偽晶片具有單面開口的空腔，將所述多個偽晶片一一對應固定在所述多個光耦合區上，以使每個所述偽晶片的所述空腔的開口面對所述光耦合介面並覆蓋所述光耦合介面。Further, the method further includes: arranging a plurality of optical coupling regions on the first surface of the semiconductor wafer, and arranging an optical coupling interface in each of the optical coupling regions; and providing a plurality of dummy wafers, each The dummy wafer has a cavity with a single-sided opening, and the plurality of dummy wafers are fixed on the plurality of light coupling areas one by one, so that the opening of the cavity of each dummy wafer faces The optical coupling interface covers the optical coupling interface.
進一步地，所述方法還包括：在將所述多個偽晶片一一對應固定在所述多個光耦合區上之後，在所述半導體晶片的所述第一表面上製作封裝層，所述封裝層包覆所述多個偽晶片的側面、所述至少一個電子積體電路晶片的側面以及所述多個第二光子積體電路晶片。Further, the method further includes: after fixing the plurality of dummy wafers on the plurality of light coupling areas one by one, forming an encapsulation layer on the first surface of the semiconductor wafer, said The encapsulation layer covers the side surfaces of the plurality of dummy wafers, the side surfaces of the at least one electronic integrated circuit wafer, and the plurality of second photonic integrated circuit wafers.
進一步地，所述方法還包括：在所述封裝層製作完成之後，在所述半導體晶片遠離所述多個第二光子積體電路晶片的一側對所述半導體晶片的本體進行減薄處理，以露出所述金屬連接柱遠離所述多個第二光子積體電路晶片一側的表面。Further, the method further includes: after the encapsulation layer is produced, thinning the body of the semiconductor wafer on a side of the semiconductor wafer away from the plurality of second photonic integrated circuit wafers, To expose the surface of the metal connecting post on the side away from the plurality of second photonic integrated circuit chips.
進一步地，所述方法還包括：在露出所述金屬連接柱遠離所述多個第二光子積體電路晶片一側的表面之後，在所述半導體晶片的所述第二表面形成與每個所述金屬連接柱一一對應電連接的佈線層以及導電凸塊。Further, the method further includes: after exposing the surface of the metal connecting post on a side away from the plurality of second photonic integrated circuit wafers, forming a connection with each of the second photonic integrated circuit wafers on the second surface of the semiconductor wafer. The metal connection pillars correspond to the electrically connected wiring layers and conductive bumps one by one.
進一步地，所述方法還包括：減薄所述封裝層、所述多個偽晶片，使得所述多個偽晶片的空腔上下貫通以及所述多個電子積體電路晶片的遠離所述半導體晶片的一側表面露出。Further, the method further includes: thinning the packaging layer and the plurality of dummy wafers, so that the cavities of the plurality of dummy wafers penetrate up and down and the cavities of the plurality of electronic integrated circuit wafers are away from the semiconductor. One side of the wafer surface is exposed.
進一步地，所述方法還包括：將導光結構或者雷射器晶片通過每個所述偽晶片的開口安裝至對應的所述光耦合介面上。Further, the method further includes: installing a light guide structure or a laser chip onto the corresponding optical coupling interface through the opening of each dummy chip.
本發明實施例提供的片上光互連結構及其製作方法，旨在通過在具有多個第一光子積體電路晶片的所述半導體晶片上設置有覆蓋在相鄰兩個第一光子積體電路晶片的部分所述第一表面的第二光子積體電路晶片，利用第二光子積體電路晶片的多個第二光波導，將相鄰的兩個所述第一光子積體電路晶片之間進行光互連，從而實現晶圓級無間斷的片上光互連，以提高片上光網路的性能和應用價值。突破了單顆第一光子積體電路晶片尺寸的上限，並且可以根據需要選擇在同一光通信中的第一光子積體電路晶片的數量，設計靈活。The on-chip optical interconnection structure and the manufacturing method thereof provided by embodiments of the present invention are intended to cover two adjacent first photonic integrated circuits by providing a semiconductor wafer having a plurality of first photonic integrated circuit wafers. The second photonic integrated circuit chip on part of the first surface of the wafer uses a plurality of second optical waveguides of the second photonic integrated circuit chip to connect two adjacent first photonic integrated circuit chips. Perform optical interconnection to achieve uninterrupted on-chip optical interconnection at the wafer level to improve the performance and application value of on-chip optical networks. It breaks through the upper limit of the size of a single First Photonic Integrated Circuit chip, and the number of First Photonic Integrated Circuit chips in the same optical communication can be selected as needed, making the design flexible.
上述說明僅是本發明技術方案的概述，為了能夠更清楚瞭解本發明的技術手段，而可依照說明書的內容予以實施，並且為了讓本發明的上述和其他目的、特徵和優點能夠更明顯易懂，以下特舉較佳實施例，並配合圖式，詳細說明如下。The above description is only an overview of the technical solution of the present invention. In order to have a clearer understanding of the technical means of the present invention, it can be implemented according to the content of the description, and in order to make the above and other objects, features and advantages of the present invention more obvious and understandable. , the preferred embodiments are specifically cited below and described in detail with reference to the drawings.
在本發明的描述中，需要說明的是，除非另有明確的規定和限定，術語“安裝”、“相連”、“連接”應做廣義理解，例如，可以是固定連接，也可以是可拆卸連接，或一體地連接；可以是機械連接，也可以是電連接或可以相互通訊；可以是直接相連，也可以通過中間媒介間接相連，可以是兩個元件內部的連通或兩個元件的相互作用關係。本文中晶片的含義可以包括裸晶片。在涉及方法步驟時，本文圖示的先後順序代表了一種示例性的方案，但不表示對先後順序的限定。對於本發明所屬技術領域的通常知識者而言，可以根據具體情況理解上述術語在本發明中的具體含義。In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be internal connection of two elements or interaction of two elements relation. The meaning of wafer herein may include bare wafers. When it comes to method steps, the sequence illustrated in this article represents an exemplary solution, but does not represent a limitation on the sequence. For those of ordinary skill in the technical field to which the present invention belongs, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
針對現有片上光互連技術受限於單顆光子積體電路晶片的尺寸限制的問題，本發明實施例提出了一種片上光互連結構及其製作方法，旨在實現晶圓級範圍內無間斷的片上光互連。In view of the problem that existing on-chip optical interconnection technology is limited by the size of a single photonic integrated circuit chip, embodiments of the present invention propose an on-chip optical interconnection structure and a manufacturing method thereof, aiming to achieve uninterrupted operation within the wafer level. on-chip optical interconnect.
為使本發明的目的、特徵和優點能夠更加明顯易懂，下面結合圖式和具體實施方式對本發明作進一步詳細的說明。In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the present invention will be described in further detail below in conjunction with the drawings and specific embodiments.
圖 1A 是根據本發明實施例提供的一種片上光互連結構的俯視結構示意圖，圖 1B 是根據本發明實施例提供的一種片上光互連結構的側視結構示意圖。FIG. 1A is a schematic top view structural diagram of an on-chip optical interconnection structure provided according to an embodiment of the present invention. FIG. 1B is a schematic side view structural diagram of an on-chip optical interconnection structure provided according to an embodiment of the present invention.
如圖 1A-圖 1B 所示，所述片上光互連結構包括：半導體晶片 100，所述半導體晶片 100 包括多個第一光子積體電路晶片 102，每個所述第一光子積體電路晶片 102 具有相對的第一表面 102a 和第二表面 102b，其中，每個所述第一光子積體電路晶片 102 包括多個第一光波導 110；多個第二光子積體電路晶片 200，每個所述第二光子積體電路晶片 200 包括多個第二光波導 210，每個所述第二光子積體電路晶片 200 固定於相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上並覆蓋相鄰的兩個所述第一光子積體電路晶片 102 在所述半導體晶片 100 上對應的區域邊界；其中，相鄰的兩個所述第一光子積體電路晶片 102 通過固定於該相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上的所述第二光子積體電路晶片 200 進行光互連。As shown in FIGS. 1A and 1B , the on-chip optical interconnection structure includes: a semiconductor wafer 100 . The semiconductor wafer 100 includes a plurality of first photonic integrated circuit wafers 102 . Each of the first photonic integrated circuit wafers 102 has opposite first surfaces 102a and second surfaces 102b, wherein each first photonic integrated circuit chip 102 includes a plurality of first optical waveguides 110; a plurality of second photonic integrated circuit chips 200, each The second photonic integrated circuit chip 200 includes a plurality of second optical waveguides 210, and each second photonic integrated circuit chip 200 is fixed to two adjacent parts of the first photonic integrated circuit chip 102. The first surface 102a is on and covers the corresponding area boundaries of the two adjacent first photonic integrated circuit wafers 102 on the semiconductor wafer 100; wherein, the two adjacent first photonic integrated circuit wafers 102 are The circuit chips 102 are optically interconnected through the second photonic integrated circuit chips 200 fixed on part of the first surfaces 102a of the two adjacent first photonic integrated circuit chips 102.
需要說明的是，在本發明實施例中，所述半導體晶片100例如是一個主機板光子晶圓，在該主機板光子晶圓上製備有多個第一光子積體電路晶片102。其中，第一光子積體電路晶片102是用光子為資訊載體進行資訊的處理與傳送，其可以是基於矽的光子積體電路晶片。一般地，在該主機板光子晶圓的製造過程中，可在相鄰兩個第一光子積體電路晶片102之間設置有切割道，該切割道代表主機板光子晶圓上預留有用於切割的空間，以便於後續可以根據同一光通信中所需承載光通信容量大小進行晶片之間的分離以選擇用於光互連的合適數量的第一光子積體電路晶片102。示例性地，在本實施方式中，相鄰的兩個所述第一光子積體電路晶片102在所述半導體晶片100上對應的區域邊界可以為相鄰兩個第一光子積體電路晶片102之間設置的切割道，並且，上方固定有所述第二光子積體電路晶片200的相鄰兩個所述第一光子積體電路晶片102之間的切割道不進行晶片切割分離成單獨晶片的步驟，該相鄰兩個所述第一光子積體電路晶片102是連接在一起的晶片，以增強所述第一光子積體電路晶片102和所述第二光子積體電路晶片200的光路對準度，提高光耦合效率，同時節約了製程成本。It should be noted that in this embodiment of the present invention, the semiconductor wafer 100 is, for example, a motherboard photonic wafer, and a plurality of first photonic integrated circuit wafers 102 are prepared on the motherboard photonic wafer. Among them, the first photonic integrated circuit chip 102 uses photons as an information carrier to process and transmit information, and may be a silicon-based photonic integrated circuit chip. Generally, during the manufacturing process of the motherboard photonic wafer, a dicing lane can be provided between two adjacent first photonic integrated circuit wafers 102 , and the dicing lane represents the space reserved for the motherboard photonic wafer. The cutting space is so that the wafers can be subsequently separated according to the required optical communication capacity in the same optical communication to select an appropriate number of first photonic integrated circuit wafers 102 for optical interconnection. For example, in this embodiment, the corresponding area boundaries of two adjacent first photonic integrated circuit wafers 102 on the semiconductor wafer 100 may be the boundaries between the two adjacent first photonic integrated circuit wafers 102 There are dicing lanes provided between them, and the dicing lanes between the two adjacent first photonic integrated circuit wafers 102 with the second photonic integrated circuit wafer 200 fixed above are not separated into separate wafers by wafer cutting. The two adjacent first photonic integrated circuit chips 102 are connected together to enhance the optical path of the first photonic integrated circuit chip 102 and the second photonic integrated circuit chip 200 Alignment improves optical coupling efficiency and saves process costs.
本發明實施例提供的技術方案，旨在通過在具有多個第一光子積體電路晶片的所述半導體晶片上設置有覆蓋在相鄰兩個第一光子積體電路晶片的部分所述第一表面的第二光子積體電路晶片，利用第二光子積體電路晶片的多個第二光波導，將相鄰的兩個所述第一光子積體電路晶片之間進行光互連，從而實現晶圓級無間斷的片上光互連，以提高片上光網路（Optical Network-on-Chip，ONOC）的性能和應用價值。突破了單顆第一光子積體電路晶片尺寸的上限，並且可以根據需要選擇在同一光通信中的第一光子積體電路晶片的數量，設計靈活。The technical solution provided by the embodiment of the present invention is to provide a semiconductor wafer having multiple first photonic integrated circuit wafers with a portion of the first photonic integrated circuit wafer covering two adjacent first photonic integrated circuit wafers. The second photonic integrated circuit chip on the surface uses a plurality of second optical waveguides of the second photonic integrated circuit chip to optically interconnect the two adjacent first photonic integrated circuit chips, thereby achieving Wafer-level uninterrupted on-chip optical interconnection to improve the performance and application value of Optical Network-on-Chip (ONOC). It breaks through the upper limit of the size of a single First Photonic Integrated Circuit chip, and the number of First Photonic Integrated Circuit chips in the same optical communication can be selected as needed, making the design flexible.
進一步地，所述多個第一光波導110和所述多個第二光波導210以並行的方式進行多通道傳輸，能夠顯著增加各個所述第一光子積體電路晶片102中傳輸的光通信容量。Furthermore, the plurality of first optical waveguides 110 and the plurality of second optical waveguides 210 perform multi-channel transmission in parallel, which can significantly increase the optical communication transmitted in each of the first photonic integrated circuit chips 102 capacity.
進一步地，所述多個第二光子積體電路晶片 200 是無源光子積體電路晶片。也即，每個所述第二光子積體電路晶片 200 在正常工作時不需要另外給它提供電源。使用每個所述第二光子積體電路晶片 200 內設置的多個第二光波導210 進行光信號傳輸，而且，每個所述第二光子積體電路晶片 200 在正常工作時也不會產生任何諧波。Further, the plurality of second photonic integrated circuit wafers 200 are passive photonic integrated circuit wafers. That is, each second photonic integrated circuit chip 200 does not need to be provided with additional power during normal operation. A plurality of second optical waveguides 210 provided in each second photonic integrated circuit chip 200 are used for optical signal transmission, and each second photonic integrated circuit chip 200 does not generate any harmonics.
示例性地，每個所述第二光子積體電路晶片 200 的多個第二光波導 210基於半導體層上的第一區域圖案化形成，在其中一實施例中，所述半導體層例如是 SOI（Silicon on Insulator，絕緣體上矽）結構的頂層矽，在頂層矽上通過濕法蝕刻或者鐳射燒蝕的方式形成多個第二光波導 210。當然，在其他實施例中，也可以採用其他方式在所述第二光子積體電路晶片 200 上形成多個第二光波導 210。本發明實施例在此不做限制。Exemplarily, the plurality of second optical waveguides 210 of each second photonic integrated circuit chip 200 are patterned and formed based on the first area on the semiconductor layer. In one embodiment, the semiconductor layer is, for example, SOI. A plurality of second optical waveguides 210 are formed on the top silicon of the (Silicon on Insulator) structure by wet etching or laser ablation. Of course, in other embodiments, other methods may also be used to form a plurality of second optical waveguides 210 on the second photonic integrated circuit chip 200. The embodiments of the present invention are not limited here.
圖 2 是根據圖 1A 實施例中相鄰的兩個所述第一光子積體電路晶片的多個第一光波導通過所述第二光子積體電路晶片的所述多個第二光波導進行光互連的第一種實施方式的側視結構示意圖。Figure 2 is a process in which the plurality of first optical waveguides of two adjacent first photonic integrated circuit wafers pass through the plurality of second optical waveguides of the second photonic integrated circuit wafer in the embodiment of Figure 1A Schematic side view of the first embodiment of optical interconnection.
可選地，如圖 2 所示，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片 102，該相鄰的兩個所述第一光子積體電路晶片 102 的所述多個第一光波導 110與固定於該相鄰的兩個所述第一光子積體電路晶片102的部分所述第一表面 102a 上的所述第二光子積體電路晶片 200 的所述多個第二光波導 210一一對應，以將該相鄰的兩個所述第一光子積體電路晶片 102 進行光互連。Optionally, as shown in FIG. 2 , for two adjacent first photonic integrated circuit wafers 102 that are optically interconnected, all of the two adjacent first photonic integrated circuit wafers 102 are The plurality of first optical waveguides 110 and the second photonic integrated circuit chip 200 fixed on the part of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 The plurality of second optical waveguides 210 are in one-to-one correspondence to optically interconnect the two adjacent first photonic integrated circuit chips 102 .
進一步地，在所述半導體晶片 100 的厚度方向上，該相鄰的兩個所述第一光子積體電路晶片102的所述多個第一光波導110的端部111的投影與固定於該相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上的每個所述第二光子積體電路晶片200的所述多個第一光波導110的端部與第二光波導 210 的端部211的投影以一一對應的方式交疊。該相鄰的兩個所述第一光子積體電路晶片102的所述多個第一光波導110的端部111通過絕熱耦合的方式實現相鄰的兩個所述第一光子積體電路晶片 102 之間的光互連。Further, in the thickness direction of the semiconductor wafer 100, the projections of the end portions 111 of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit wafers 102 are fixed to the The ends of the plurality of first optical waveguides 110 of each of the second photonic integrated circuit wafers 200 on the portions of the first surfaces 102a of the two adjacent first photonic integrated circuit wafers 102 The projections overlap with the end portion 211 of the second optical waveguide 210 in a one-to-one correspondence. The end portions 111 of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit wafers 102 realize the two adjacent first photonic integrated circuit wafers through adiabatic coupling. Optical interconnection between 102.
圖 3 是根據圖 1A 實施例中相鄰的兩個所述第一光子積體電路晶片的多個第一光波導通過所述第二光子積體電路晶片的所述多個第二光波導進行光互連的第二種實施方式的側視結構示意圖。Figure 3 is a process in which the plurality of first optical waveguides of two adjacent first photonic integrated circuit wafers pass through the plurality of second optical waveguides of the second photonic integrated circuit wafer in the embodiment of Figure 1A Schematic side view of a second embodiment of optical interconnection.
可選地，如圖 3 所示，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片 102，在該相鄰的兩個所述第一光子積體電路晶片 102 的所述第一表面102a 上靠近該相鄰的兩個所述第一光子積體電路晶片 102 在所述半導體晶片100 上對應的區域邊界各設置有至少一個光束重定向元件 810，其中，每個所述光束重定向元件810用於改變光束的方向以進入每個所述第一光波導 110和/或每個所述第二光波導 210 中；針對固定於該相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上的所述第二光子積體電路晶片 200，在平行該第二光子積體電路晶片 200 所在平面的方向上，在該第二光子積體電路晶片 200 的所述多個第二光波導 210 的兩側均設置有一組光柵耦合器 213，每組所述光柵耦合器 213 分別與該相鄰的兩個所述第一光子積體電路晶片 102的所述多個第一光波導 110 一一對應並且用於光耦合，其中，每組所述光柵耦合器 213 包括至少一個光柵耦合器元件；其中，相鄰的兩個所述第一光子積體電路晶片 102 通過所述光束重定向元件 810、兩組光柵耦合器 213 以及所述多個第二光波導 210 進行光互連。Optionally, as shown in FIG. 3 , for two adjacent first photonic integrated circuit wafers 102 that are optically interconnected, between the two adjacent first photonic integrated circuit wafers 102 On the first surface 102a, at least one beam redirecting element 810 is respectively provided at the corresponding area boundary of the two adjacent first photonic integrated circuit wafers 102 on the semiconductor wafer 100, wherein each The beam redirecting element 810 is used to change the direction of the beam to enter each of the first optical waveguides 110 and/or each of the second optical waveguides 210; The second photonic integrated circuit chip 200 on part of the first surface 102a of a photonic integrated circuit chip 102 is in a direction parallel to the plane where the second photonic integrated circuit chip 200 is located. A group of grating couplers 213 are disposed on both sides of the plurality of second optical waveguides 210 of the integrated circuit chip 200. Each group of the grating couplers 213 is connected to the two adjacent first photonic integrated devices. The plurality of first optical waveguides 110 of the circuit wafer 102 correspond one to one and are used for optical coupling, wherein each group of the grating couplers 213 includes at least one grating coupler element; wherein two adjacent grating coupler elements A photonic integrated circuit chip 102 is optically interconnected through the beam redirecting element 810 , two sets of grating couplers 213 and the plurality of second optical waveguides 210 .
示例性地，在本發明實施例中，所述光束重定向元件 810 可以是棱鏡元件，該棱鏡元件用於改變光束的傳輸方向以進入每個所述第一光波導 110 和/或每個所述第二光波導 210 中，具體地，該棱鏡元件為三棱鏡，該三棱鏡具有兩個直角邊和一個斜邊，該相鄰的兩個所述第一光子積體電路晶片 102 的所述多個第一光波導 110 的端部均正對棱鏡元件的斜邊，以將一個第一光子積體電路晶片 102 的所述多個第一光波導 110 傳輸的光束的傳播方向改變 90 度後經由一組所述光柵耦合器213傳輸到第二光子積體電路晶片200的所述多個第二光波導中 210 中，並由另一組所述光柵耦合器 213 傳輸到另一個第一光子積體電路晶片102 中，從而實現相鄰的兩個所述第一光子積體電路晶片 102 的光互連。Exemplarily, in the embodiment of the present invention, the beam redirecting element 810 may be a prism element, which is used to change the transmission direction of the light beam to enter each of the first optical waveguides 110 and/or each of the In the second optical waveguide 210, specifically, the prism element is a triangular prism having two right-angled sides and a hypotenuse. The plurality of adjacent first photonic integrated circuit chips 102 are The ends of the first optical waveguides 110 are all facing the hypotenuse of the prism element, so as to change the propagation direction of the light beam transmitted by the plurality of first optical waveguides 110 of a first photonic integrated circuit chip 102 by 90 degrees and then pass through a A group of the grating couplers 213 is transmitted to the plurality of second optical waveguides 210 of the second photonic integrated circuit chip 200, and is transmitted to another first photonic integrated circuit by another group of the grating couplers 213. in the circuit chip 102, thereby realizing optical interconnection between the two adjacent first photonic integrated circuit chips 102.
可選地，如圖 3 所示，可在每個所述第一光子積體電路晶片 102 的第一表面 102a 上開設有凹槽，並將所述光束重定向元件 810 容置於該凹槽中，一方面起到固定及限位的作用，另一方面也能夠調節該相鄰的兩個所述第一光子積體電路晶片 102 的所述多個第一光波導 110 的光束恰好入射/出射至該光束重定向元件 810 的中部，以避免發生不必要的光損耗。Optionally, as shown in Figure 3, a groove can be opened on the first surface 102a of each first photonic integrated circuit chip 102, and the beam redirecting element 810 can be accommodated in the groove. On the one hand, it plays the role of fixing and limiting, and on the other hand, it can also adjust the light beams of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit chips 102 to be incident/ It is emitted to the middle of the beam redirecting element 810 to avoid unnecessary light loss.
進一步地，如圖 1B 所示，每個所述第一光子積體電路晶片 102 包括多個金屬連接柱 1022，並且所述金屬連接柱 1022 的一側表面從每個所述第一光子積體電路晶片 102 的所述第一表面 102a 露出。Further, as shown in FIG. 1B , each of the first photonic integrated circuit chips 102 includes a plurality of metal connecting posts 1022 , and one side surface of the metal connecting posts 1022 extends from each of the first photonic integrated circuit chips. The first surface 102a of the circuit chip 102 is exposed.
圖 4A 是根據本發明實施例提供的又一種片上光互連結構的俯視結構示意圖，圖 4B 是根據本發明實施例提供的又一種片上光互連結構的側視結構示意圖。FIG. 4A is a schematic top view of another on-chip optical interconnect structure provided according to an embodiment of the present invention. FIG. 4B is a schematic side view of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
如圖 4A 和圖 4B 所示，所述片上光互連結構還包括固定於至少一個所述第一光子積體電路晶片 102 的所述第一表面 102a 上的至少一個電子積體電路晶片 300。其中，每個所述電子積體電路晶片 300 是用電子為資訊載體進行資訊的處理與資料的傳送，例如基於矽的電子積體電路晶片、基於鍺的電子積體電路晶片或者化合物半導體電子積體電路晶片，通過將至少一個所述第一光子積體電路晶片102和所述至少一個電子積體電路晶片300進行堆疊可實現光子積體電路晶片和電子積體電路晶片的集成。As shown in Figures 4A and 4B, the on-chip optical interconnect structure further includes at least one electronic integrated circuit die 300 fixed on the first surface 102a of at least one of the first photonic integrated circuit die 102. Each of the electronic integrated circuit chips 300 uses electrons as an information carrier to process information and transmit data, such as silicon-based electronic integrated circuit chips, germanium-based electronic integrated circuit chips, or compound semiconductor electronic chips. Integration of the photonic integrated circuit wafer and the electronic integrated circuit wafer can be achieved by stacking at least one of the first photonic integrated circuit wafer 102 and the at least one electronic integrated circuit wafer 300 .
示例性地，至少一個電子積體電路晶片 300 例如可以採用焊接或者其他方式進行固定於至少一個所述第一光子積體電路晶片 102 的所述第一表面 102a上的非光耦合區域及非所述第二光子積體電路晶片 200 所覆蓋的區域。本發明實施例中，所述至少一個電子積體電路晶片 300 採用倒裝焊接的方式焊接到所述至少一個第一光子積體電路晶片 102 的所述第一表面 102a 上。可選地，在每個所述電子積體電路晶片 300 與所述第一表面 102a 之間的縫隙處填充底膠（under fill）以進一步地加固每個所述電子積體電路晶片 300。Exemplarily, at least one electronic integrated circuit chip 300 may be fixed to the non-light coupling area and non-optical coupling area on the first surface 102a of at least one first photonic integrated circuit chip 102 by welding or other methods. The area covered by the second photonic integrated circuit chip 200. In the embodiment of the present invention, the at least one electronic integrated circuit chip 300 is soldered to the first surface 102a of the at least one first photonic integrated circuit chip 102 using flip-chip soldering. Optionally, an underfill is filled in the gap between each electronic integrated circuit chip 300 and the first surface 102a to further strengthen each electronic integrated circuit chip 300.
本發明實施例中示意了在所述第一光子積體電路晶片 102 的第一表面102a 的上方形成一個所述電子積體電路晶片 300，在實際使用中，可以是多於一個的所述電子積體電路晶片 300，例如 2 個、3 個、4 個或者更多，可以根據實際需要靈活選擇。In the embodiment of the present invention, one electronic integrated circuit chip 300 is formed above the first surface 102a of the first photonic integrated circuit chip 102. In actual use, there may be more than one electronic integrated circuit chip 300. The integrated circuit chips 300, such as 2, 3, 4 or more, can be flexibly selected according to actual needs.
進一步地，在所述半導體晶片 100 的所述第一表面 102a 上設置有多個光耦合區 1024，每個所述光耦合區 1024 內設置有光耦合介面 104。一部分的光耦合介面 104 使得外部光源提供的光可以通過光纖陣列（Fiber Array，FA）等導光結構 600 輸入到光耦合介面 104 中，進而使光信號在每個所述第一光子積體電路晶片 102 的多個第一光波導 110 中進行傳輸。例如通過與光耦合介面104 內的光柵耦合器耦合進第一光子積體電路晶片 102。另一部分光耦合介面104 使得經過多個所述第一光子積體電路晶片 102 傳輸/處理後的光信號通過光纖陣列等導光結構 600 傳輸到其基底上的積體電路晶片結構進行後續處理。在本實施方案中，光耦合介面 104 的位置可以根據實際需要設置，佈局更加靈活。需要說明的是，在其他實施例中，也可以在光耦合介面 104 內相應的設置其他用於傳輸光信號的光互連介面或者器件。Further, a plurality of optical coupling regions 1024 are provided on the first surface 102a of the semiconductor wafer 100, and an optical coupling interface 104 is provided in each of the optical coupling regions 1024. A part of the optical coupling interface 104 allows the light provided by the external light source to be input into the optical coupling interface 104 through a light guide structure 600 such as a fiber array (Fiber Array, FA), thereby allowing the optical signal to be transmitted in each of the first photonic integrated circuits. Transmission is performed in a plurality of first optical waveguides 110 of the wafer 102 . For example, it is coupled into the first photonic integrated circuit chip 102 through a grating coupler in the optical coupling interface 104 . Another part of the optical coupling interface 104 allows the optical signals transmitted/processed by the plurality of first photonic integrated circuit chips 102 to be transmitted to the integrated circuit chip structure on its substrate through a light guide structure 600 such as an optical fiber array for subsequent processing. In this implementation, the position of the optical coupling interface 104 can be set according to actual needs, making the layout more flexible. It should be noted that in other embodiments, other optical interconnection interfaces or devices for transmitting optical signals may also be provided in the optical coupling interface 104 accordingly.
圖 5 是根據本發明實施例提供的另一種片上光互連結構的側視結構示意圖。Figure 5 is a schematic side structural diagram of another on-chip optical interconnect structure provided according to an embodiment of the present invention.
如圖 5 所示，所述片上光互連結構還包括多個偽晶片 400，所述多個偽晶片 400 一一對應固定於所述半導體晶片 100 的所述第一表面 102a 上的所述多個光耦合區 1024 上，其中，每個所述偽晶片 400 具有上下開口的空腔，所述空腔的開口面對所述光耦合介面 104 並覆蓋所述光耦合介面 104。As shown in FIG. 5 , the on-chip optical interconnection structure further includes a plurality of dummy wafers 400 . The plurality of dummy wafers 400 correspond to the plurality of dummy wafers fixed on the first surface 102 a of the semiconductor wafer 100 in one-to-one correspondence. Each of the dummy wafers 400 has a cavity with upper and lower openings, and the opening of the cavity faces the optical coupling interface 104 and covers the optical coupling interface 104 .
繼續參考圖 5 所示，所述片上光互連結構還包括封裝層 106，所述封裝層106 覆蓋在所述半導體晶片 100 的所述第一表面 102a 上，並且包覆所述多個偽晶片 400 的側面、所述至少一個電子積體電路晶片 300 的側面以及所述多個第二光子積體電路晶片 200。Continuing to refer to FIG. 5 , the on-chip optical interconnect structure further includes an encapsulation layer 106 covering the first surface 102a of the semiconductor wafer 100 and covering the plurality of dummy wafers. 400 , the at least one electronic integrated circuit chip 300 and the plurality of second photonic integrated circuit chips 200 .
進一步地，所述片上光互連結構還包括多個導光結構 600，所述多個導光結構 600 與所述多個偽晶片 400 一一對應，其中，每個所述導光結構 600 穿過每個所述偽晶片 400 的所述空腔，以將光信號耦合至對應的所述光耦合介面104。Further, the on-chip optical interconnection structure further includes a plurality of light guide structures 600, which correspond to the plurality of dummy wafers 400 one-to-one, wherein each of the light guide structures 600 passes through The optical signal is coupled to the corresponding optical coupling interface 104 through the cavity of each dummy chip 400 .
根據本發明的又一方面，還提供了一種片上光互連結構的製作方法。According to another aspect of the present invention, a method for manufacturing an on-chip optical interconnection structure is also provided.
圖 6 是根據本發明實施例提供的片上光互連結構的製作方法的流程圖。所述片上光互連結構的製作方法包括： S101，提供半導體晶片，所述半導體晶片包括多個第一光子積體電路晶片，每個所述第一光子積體電路晶片具有相對的第一表面和第二表面，其中，每個所述第一光子積體電路晶片包括多個第一光波導； S102，提供多個第二光子積體電路晶片，每個所述第二光子積體電路晶片包括多個第二光波導，將每個所述第二光子積體電路晶片固定在相鄰的兩個所述第一光子積體電路晶片的部分所述第一表面上並覆蓋相鄰的兩個所述第一光子積體電路晶片在所述半導體晶片上對應的區域邊界； 其中，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片，將每個所述第二光子積體電路晶片的所述多個第二光波導與該相鄰的兩個所述第一光子積體電路晶片的所述多個第一光波導進行一一對準，以將該相鄰的兩個所述光子積體電路晶片進行光互連。 Figure 6 is a flow chart of a method for manufacturing an on-chip optical interconnect structure according to an embodiment of the present invention. The manufacturing method of the on-chip optical interconnect structure includes: S101, provide a semiconductor wafer, the semiconductor wafer includes a plurality of first photonic integrated circuit wafers, each of the first photonic integrated circuit wafers has an opposite first surface and a second surface, wherein each of the first photonic integrated circuit wafers A photonic integrated circuit chip includes a plurality of first optical waveguides; S102, provide a plurality of second photonic integrated circuit wafers, each of the second photonic integrated circuit wafers includes a plurality of second optical waveguides, and fix each of the second photonic integrated circuit wafers on two adjacent ones. A portion of the first surface of one of the first photonic integrated circuit wafers and covering the corresponding area boundaries of two adjacent first photonic integrated circuit wafers on the semiconductor wafer; Wherein, for two adjacent first photonic integrated circuit wafers that are optically interconnected, the plurality of second optical waveguides of each second photonic integrated circuit wafer are connected to the two adjacent first photonic integrated circuit wafers. The plurality of first optical waveguides of each of the first photonic integrated circuit chips are aligned one by one to optically interconnect the two adjacent photonic integrated circuit chips.
圖 7A-圖 7I 是根據本發明實施例提供的片上光互連結構的製作方法的製作工序示意圖。7A-7I are schematic diagrams of the manufacturing process of the method for manufacturing an on-chip optical interconnect structure provided according to an embodiment of the present invention.
以下將結合圖 7A-圖 7I 以及圖 1A、圖 1B、圖 2、圖 3 對本發明實施例進行詳細說明。The embodiments of the present invention will be described in detail below with reference to Figures 7A-7I and Figures 1A, 1B, 2, and 3.
示例性地，請參閱圖 7A 所示，首先提供半導體晶片 100，所述半導體晶片 100 包括多個第一光子積體電路晶片 102，每個所述第一光子積體電路晶片102 具有相對的第一表面 102a 和第二表面 102b，其中，每個所述第一光子積體電路晶片 102 包括多個第一光波導 110。Illustratively, as shown in FIG. 7A , a semiconductor wafer 100 is first provided. The semiconductor wafer 100 includes a plurality of first photonic integrated circuit wafers 102 , each of the first photonic integrated circuit wafers 102 having a corresponding first photonic integrated circuit wafer 102 . A surface 102a and a second surface 102b, wherein each of the first photonic integrated circuit wafers 102 includes a plurality of first optical waveguides 110.
需要說明的是，在本發明實施例中，所述半導體晶片100例如是一個主機板光子晶圓，該主機板光子晶圓上具有多個第一光子積體電路晶片102，在相鄰兩個第一光子積體電路晶片102之間可以具有切割道，該切割道代表主機板光子晶圓上預留有用於切割的空間，以便於後續可以根據同一光通信中所需承載光通信容量大小進行晶片之間的分離以選擇用於光互連的合適數量的第一光子積體電路晶片102。It should be noted that in the embodiment of the present invention, the semiconductor chip 100 is, for example, a motherboard photonic wafer. The motherboard photonic wafer has a plurality of first photonic integrated circuit chips 102 on two adjacent ones. There may be dicing lanes between the first photonic integrated circuit wafers 102. The dicing lanes represent the space reserved for cutting on the motherboard photonic wafer, so that subsequent operations can be carried out according to the required optical communication capacity in the same optical communication. Separation between wafers to select an appropriate number of first photonic integrated circuit wafers 102 for optical interconnection.
請參閱圖 7B 所示，提供多個第二光子積體電路晶片 200，每個所述第二光子積體電路晶片 200 包括多個第二光波導 210，將每個所述第二光子積體電路晶片200固定在相鄰的兩個所述第一光子積體電路晶片102的部分所述第一表面 102a 上並覆蓋相鄰的兩個所述第一光子積體電路晶片 102 在所述半導體晶片上 100 對應的區域邊界；其中，相鄰的兩個所述第一光子積體電路晶片102 在所述半導體晶片上 100 對應的區域邊界可以是相鄰兩個第一光子積體電路晶片 102 之間的切割道；其中，針對進行光互連的相鄰的兩個所述第一光子積體電路晶片 102，將每個所述第二光子積體電路晶片 200 的所述多個第二光波導210與該相鄰的兩個所述第一光子積體電路晶片102的所述多個第一光波導 110 進行一一對準，以將該相鄰的兩個所述光子積體電路晶片 102 進行光互連。Referring to FIG. 7B, a plurality of second photonic integrated circuit chips 200 are provided. Each of the second photonic integrated circuit chips 200 includes a plurality of second optical waveguides 210. Each of the second photonic integrated circuit chips is The circuit chip 200 is fixed on part of the first surface 102a of the two adjacent first photonic integrated circuit wafers 102 and covers the two adjacent first photonic integrated circuit wafers 102 on the semiconductor The area boundaries corresponding to 100 on the wafer; wherein, the area boundaries corresponding to the two adjacent first photonic integrated circuit wafers 102 on the semiconductor wafer may be the two adjacent first photonic integrated circuit wafers 102 between the dicing lanes; wherein, for the two adjacent first photonic integrated circuit wafers 102 that are optically interconnected, the plurality of second photonic integrated circuit wafers 200 of each second photonic integrated circuit wafer 200 are The optical waveguide 210 is aligned with the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit wafers 102 to align the two adjacent photonic integrated circuits. Wafer 102 is optically interconnected.
在本發明實施例中，所述多個第二光子積體電路晶片 200 是無源光子積體電路晶片。每個所述第二光子積體電路晶片 200 在正常工作時不需要另外給它提供電源。使用每個所述第二光子積體電路晶片 200 內設置的多個第二光波導210 進行光信號傳輸，而且，每個所述第二光子積體電路晶片 200 在正常工作時也不會產生任何諧波。In the embodiment of the present invention, the plurality of second photonic integrated circuit chips 200 are passive photonic integrated circuit chips. Each of the second photonic integrated circuit chips 200 does not need to be provided with additional power during normal operation. A plurality of second optical waveguides 210 provided in each second photonic integrated circuit chip 200 are used for optical signal transmission, and each second photonic integrated circuit chip 200 does not generate any harmonics.
示例性地，每個所述第二光子積體電路晶片 200 的多個第二光波導 210基於半導體層上的第一區域圖案化形成，在其中一實施例中，所述半導體層例如是 SOI（Silicon on Insulator，絕緣體上矽）結構的頂層矽，在頂層矽上通過濕法蝕刻或者鐳射燒蝕的方式形成多個第二光波導 210。當然，在其他實施例中，也可以採用其他方式在所述第二光子積體電路晶片 200 上形成多個第二光波導 210。本發明實施例在此不做限制。Exemplarily, the plurality of second optical waveguides 210 of each second photonic integrated circuit chip 200 are patterned and formed based on the first area on the semiconductor layer. In one embodiment, the semiconductor layer is, for example, SOI. A plurality of second optical waveguides 210 are formed on the top silicon of the (Silicon on Insulator) structure by wet etching or laser ablation. Of course, in other embodiments, other methods may also be used to form a plurality of second optical waveguides 210 on the second photonic integrated circuit chip 200. The embodiments of the present invention are not limited here.
為了盡可能地能夠減少每個所述第二光子積體電路晶片 200 的多個第二光波導210與位於其下方的相鄰兩個第一光子積體電路晶片102的多個第一光波導 110 的耦合距離，可選地，在本發明的一些實施方式中，將每個所述第二光子積體電路晶片 200 以背面貼裝的方式固定在相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上並覆蓋相鄰的兩個所述第一光子積體電路晶片 102 在所述半導體晶片 100 上對應的區域邊界。In order to reduce as much as possible the number of second optical waveguides 210 of each second photonic integrated circuit chip 200 and the multiple first optical waveguides of the two adjacent first photonic integrated circuit chips 102 located below it. 110 coupling distance. Optionally, in some embodiments of the present invention, each second photonic integrated circuit chip 200 is fixed to two adjacent first photonic integrated circuit chips 200 in a back-mounted manner. part of the first surface 102a of the integrated circuit chip 102 and covering the corresponding area boundaries of the two adjacent first photonic integrated circuit chips 102 on the semiconductor wafer 100.
可選地，在本發明的另一些實施方式中，也可以通過去除每個所述第二光子積體電路晶片 200 的底部半導體層，將已去除底部半導體層的每個所述第二光子積體電路晶片 200 以正面貼裝的方式固定在相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上並覆蓋相鄰的兩個所述第一光子積體電路晶片 102 在所述半導體晶片 100 上對應的區域邊界。Optionally, in other embodiments of the present invention, each second photonic integrated circuit chip 200 whose bottom semiconductor layer has been removed can also be removed by removing the bottom semiconductor layer of each second photonic integrated circuit chip 200 . The integrated circuit chip 200 is fixed on part of the first surface 102a of the two adjacent first photonic integrated circuit wafers 102 in a front-mounted manner and covers the adjacent two first photonic integrated circuit wafers 102. The circuit wafer 102 corresponds to the area boundary on the semiconductor wafer 100 .
進一步地，結合圖 2 所示，在所述半導體晶片 100 的厚度方向上，將該相鄰的兩個所述第一光子積體電路晶片102的所述多個第一光波導110的端部的投影與固定於該相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面102a上的每個所述第二光子積體電路晶片200的所述多個第二光波導210的端部的投影以一一對應的方式交疊，以通過絕熱耦合的方式實現相鄰的兩個所述第一光子積體電路晶片 102 之間的光互連。Further, as shown in FIG. 2 , in the thickness direction of the semiconductor wafer 100 , the ends of the plurality of first optical waveguides 110 of the two adjacent first photonic integrated circuit wafers 102 are The projection and the plurality of second photonic integrated circuit chips 200 of each second photonic integrated circuit chip 200 fixed on the part of the first surface 102a of the two adjacent first photonic integrated circuit chips 102 The projections of the end portions of the optical waveguides 210 overlap in a one-to-one correspondence to achieve optical interconnection between the two adjacent first photonic integrated circuit wafers 102 through adiabatic coupling.
進一步地，結合圖 3 所示，在該相鄰的兩個所述第一光子積體電路晶片102的所述第一表面 102a上靠近該相鄰的兩個所述第一光子積體電路晶片 102在所述半導體晶片 100 上對應的區域邊界各放置有至少一個光束重定向元件810；其中，每個所述光束重定向元件 810 用於改變光束的方向以進入每個所述第一光波導 110 和/或每個所述第二光波導 210 中；以及針對固定於該相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a 上的所述第二光子積體電路晶片 200，在平行於該第二光子積體電路晶片 200 所在平面的方向上，在該第二光子積體電路晶片 200 的所述多個第二光波導 210 的兩側均形成有一組光柵耦合器 213，每組所述光柵耦合器 213 分別與該相鄰的兩個所述光子積體電路晶片 102 的所述多個第一光波導 110 一一對應並且用於光耦合，其中，每組所述光柵耦合器 213 包括至少一個光柵耦合器元件；其中，相鄰的兩個所述第一光子積體電路晶片 102 通過所述光束重定向元件 810、兩組光柵耦合器 213 以及所述多個第二光波導 210 進行光互連。Further, as shown in FIG. 3 , on the first surface 102 a of the two adjacent first photonic integrated circuit wafers 102 , close to the two adjacent first photonic integrated circuit wafers 102 At least one beam redirecting element 810 is placed at each corresponding area boundary on the semiconductor wafer 100; wherein each beam redirecting element 810 is used to change the direction of the beam to enter each of the first optical waveguides. 110 and/or in each of the second optical waveguides 210; and for the second photons fixed on the portions of the first surfaces 102a of the two adjacent first photonic integrated circuit wafers 102 In the integrated circuit chip 200, in a direction parallel to the plane of the second photonic integrated circuit chip 200, a plurality of second optical waveguides 210 are formed on both sides of the second photonic integrated circuit chip 200. A group of grating couplers 213, each group of grating couplers 213 corresponds one-to-one to the plurality of first optical waveguides 110 of the two adjacent photonic integrated circuit wafers 102 and is used for optical coupling, where , each group of grating couplers 213 includes at least one grating coupler element; wherein, two adjacent first photonic integrated circuit wafers 102 pass through the beam redirection element 810, two groups of grating couplers 213 and The plurality of second optical waveguides 210 perform optical interconnection.
示例性地，所述光柵耦合器 213 例如可以是具有多個通道的環形光柵耦合器。For example, the grating coupler 213 may be, for example, a ring-shaped grating coupler with multiple channels.
進一步地，在每個所述第一光子積體電路晶片 102 內製作多個金屬連接柱1022，並將所述金屬連接柱 1022 的一側表面從每個所述第一光子積體電路晶片 102 的所述第一表面 102a 露出。Further, a plurality of metal connection posts 1022 are made in each of the first photonic integrated circuit wafers 102 , and one side surface of the metal connection posts 1022 is removed from each of the first photonic integrated circuit wafers 102 The first surface 102a is exposed.
具體地，當所述第一光子積體電路晶片102為基於矽的光子積體電路晶片時，在所述第一光子積體電路晶片102中的基底中製作多個導電通孔，導電通孔可以作為導電通道的一部分，該導電通孔在製造時可採用“矽通孔”（Through Silicon Via，TSV）技術，TSV是一項高密度封裝技術，正在逐漸取代目前製程比較成熟的引線鍵合技術，被認為是***封裝技術。TSV技術通過銅、鎢、多晶矽等導電物質的填充，實現矽通孔的垂直電氣互連。矽通孔技術可以通過垂直互連減小互聯長度，減小信號延遲，降低電容/電感，實現晶片間的低功耗、高速通信，增加寬頻和實現器件集成的小型化。TSV製程可以包括深矽蝕刻形成微孔或盲孔、絕緣層/阻擋層/種子層的沉積、深孔填充、化學機械拋光、減薄、以及再分佈引線製備等製程技術，在所述第一光子積體電路晶片102中形成導電通孔的製程方法包括但不限於鐳射蝕刻、深反應離子蝕刻等，在形成導電通孔後再採用例如深孔填充等製程進行導電材料(例如金屬)的填充。本發明在此不再贅述。Specifically, when the first photonic integrated circuit chip 102 is a silicon-based photonic integrated circuit chip, a plurality of conductive via holes are made in the base of the first photonic integrated circuit chip 102, and the conductive via holes are It can be used as part of the conductive channel. The conductive via can be manufactured using "Through Silicon Via" (TSV) technology. TSV is a high-density packaging technology that is gradually replacing the current wire bonding process, which is relatively mature. technology, considered to be the fourth generation packaging technology. TSV technology realizes vertical electrical interconnection of through-silicon holes by filling them with conductive substances such as copper, tungsten, and polycrystalline silicon. Through silicon via technology can reduce interconnect length, reduce signal delay, reduce capacitance/inductance through vertical interconnection, achieve low power consumption and high-speed communication between chips, increase bandwidth and achieve miniaturization of device integration. The TSV process may include process technologies such as deep silicon etching to form microvias or blind vias, deposition of insulating layers/barrier layers/seed layers, deep hole filling, chemical mechanical polishing, thinning, and redistribution lead preparation. In the first step, The process methods for forming conductive vias in the photonic integrated circuit chip 102 include but are not limited to laser etching, deep reactive ion etching, etc. After the conductive vias are formed, processes such as deep hole filling are used to fill the conductive material (such as metal). . The present invention will not be described in detail here.
進一步地，如圖 7B-圖 7C 所示，在將每個所述第二光子積體電路晶片 200固定在相鄰的兩個所述第一光子積體電路晶片 102 的部分所述第一表面 102a上並覆蓋相鄰的兩個所述第一光子積體電路晶片 102 在所述半導體晶片 100上對應的區域邊界之後，針對至少一個所述第一光子積體電路晶片 102，提供與該第一光子積體電路晶片 102 對應的至少一個電子積體電路晶片 300，並將所述至少一個電子積體電路晶片300固定在該第一光子積體電路晶片102的所述第一表面 102a 的對應區域。Further, as shown in FIGS. 7B to 7C , each second photonic integrated circuit chip 200 is fixed to the portion of the first surface of the two adjacent first photonic integrated circuit chips 102 102a and covering the two adjacent first photonic integrated circuit wafers 102. After the corresponding area boundary on the semiconductor wafer 100, for at least one of the first photonic integrated circuit wafers 102, provide a A photonic integrated circuit chip 102 corresponds to at least one electronic integrated circuit chip 300, and the at least one electronic integrated circuit chip 300 is fixed on the corresponding first surface 102a of the first photonic integrated circuit chip 102. area.
進一步地，如圖 7D 所示，在所述半導體晶片 100 上所述第一表面 102a上製作有多個光耦合區 1024，在每個所述光耦合區 1024 內設置光耦合介面104。為了形成對每個所述光耦合區 1024 內的光耦合介面 104 的保護，提供多個偽晶片 400，每個所述偽晶片 400 具有單面開口的空腔，將所述多個偽晶片400 一一對應固定在所述多個光耦合區 1024 上，以使每個所述偽晶片 400 的所述空腔的開口面對所述光耦合介面 104 並覆蓋所述光耦合介面 104。所述偽晶片 400 及其空腔可以對所述光耦合介面 104 形成封閉的保護空間，以避免後續在對所述片上光互連結構進行封裝的過程中，封裝層中的有機物材料接觸光耦合區後造成有機物殘留，從而嚴重影響到所述光耦合介面 104 的耦合效率，導致其光損耗嚴重，進而影響所述第一光子積體電路晶片 102 的正常運行。Further, as shown in FIG. 7D, a plurality of optical coupling regions 1024 are formed on the first surface 102a of the semiconductor wafer 100, and an optical coupling interface 104 is provided in each of the optical coupling regions 1024. In order to form protection for the optical coupling interface 104 in each of the optical coupling regions 1024, a plurality of dummy wafers 400 are provided, each of the dummy wafers 400 has a cavity with a single side opening, and the plurality of dummy wafers 400 are They are fixed on the plurality of optical coupling areas 1024 in one-to-one correspondence, so that the opening of the cavity of each dummy chip 400 faces the optical coupling interface 104 and covers the optical coupling interface 104 . The dummy chip 400 and its cavity can form a closed protective space for the optical coupling interface 104 to prevent the organic material in the packaging layer from contacting the optical coupling during the subsequent packaging of the on-chip optical interconnect structure. Organic matter remains after the optical coupling interface 104 has been removed, which seriously affects the coupling efficiency of the optical coupling interface 104 , resulting in serious light loss, thereby affecting the normal operation of the first photonic integrated circuit chip 102 .
需要說明的是，偽晶片 400 是指其上不集成或者不具有任何光子元件和電子元件的晶片，例如裸矽片。It should be noted that the dummy wafer 400 refers to a wafer that is not integrated with or does not have any photonic components and electronic components, such as a bare silicon wafer.
進一步地，如圖 7E 所示，在將所述多個偽晶片 400 一一對應固定在所述多個光耦合區 1024 上之後，在所述半導體晶片 100 的所述第一表面 102a 上製作封裝層 106，所述封裝層 106 包覆所述多個偽晶片 400 的側面、所述至少一個電子積體電路晶片 300 的側面以及所述多個第二光子積體電路晶片 200。具體地，所述封裝層 106 的注塑材料例如可以是環氧樹脂，其在熔融狀態下覆蓋所述半導體晶片 100 的所述第一表面 102a，並在固化後形成封裝層 106，使得所述多個偽晶片 400、所述至少一個電子積體電路晶片 300 以及所述多個第二光子積體電路晶片 200 均被牢固地固定在所述半導體晶片 100 的相應位置上，從而能夠形成穩定的封裝結構。Further, as shown in FIG. 7E , after the plurality of dummy wafers 400 are fixed on the plurality of light coupling regions 1024 in one-to-one correspondence, a package is produced on the first surface 102a of the semiconductor wafer 100 Layer 106 , the encapsulation layer 106 covers the side surfaces of the plurality of dummy wafers 400 , the side surfaces of the at least one electronic integrated circuit wafer 300 and the plurality of second photonic integrated circuit wafers 200 . Specifically, the injection molding material of the encapsulation layer 106 may be, for example, epoxy resin, which covers the first surface 102a of the semiconductor wafer 100 in a molten state, and forms the encapsulation layer 106 after solidification, so that the multi-layer The dummy wafer 400, the at least one electronic integrated circuit wafer 300 and the plurality of second photonic integrated circuit wafers 200 are all firmly fixed at corresponding positions of the semiconductor wafer 100, thereby forming a stable package. structure.
如圖 7F 所示，在所述封裝層 106 製作完成之後，在所述半導體晶片 100遠離所述多個第二光子積體電路晶片200的一側對所述半導體晶片100的本體進行減薄處理(101)，以露出所述金屬連接柱 1022 遠離所述多個第二光子積體電路晶片 200 一側的表面。As shown in FIG. 7F , after the encapsulation layer 106 is produced, the body of the semiconductor wafer 100 is thinned on the side of the semiconductor wafer 100 away from the plurality of second photonic integrated circuit wafers 200 . (101) to expose the surface of the metal connecting post 1022 on the side away from the plurality of second photonic integrated circuit chips 200.
隨後，在露出所述金屬連接柱 1022 遠離所述多個第二光子積體電路晶片200 一側的表面之後，在所述半導體晶片 100 的所述第二表面 102b 形成與每個所述金屬連接柱 1022 一一對應電連接的佈線層以及導電凸塊 1023，以實現所述金屬連接柱 1022 與外部電連接點進行電連接。Subsequently, after exposing the surface of the metal connection post 1022 away from the side of the plurality of second photonic integrated circuit wafers 200, a metal connection with each of the metal connections is formed on the second surface 102b of the semiconductor wafer 100. The pillars 1022 correspond to the electrically connected wiring layers and the conductive bumps 1023 one-to-one to achieve electrical connection between the metal connection pillars 1022 and external electrical connection points.
如圖 7G 所示，減薄所述封裝層 106、所述多個偽晶片 400，使得所述多個偽晶片400的空腔上下貫通以及所述多個電子積體電路晶片300的遠離所述半導體晶片 100 的一側表面露出。As shown in FIG. 7G , the encapsulation layer 106 and the plurality of dummy wafers 400 are thinned so that the cavities of the plurality of dummy wafers 400 penetrate up and down and the cavities of the plurality of electronic integrated circuit wafers 300 are away from the One surface of the semiconductor wafer 100 is exposed.
如圖 7H 所示，在將所述多個偽晶片 400 的空腔上下貫通以及所述多個電子積體電路晶片 300 的遠離所述半導體晶片 100 的一側表面露出之後，將所述半導體晶片 100 的第二表面 102b 固定到封裝基板 500 上。As shown in FIG. 7H , after the cavities of the plurality of dummy wafers 400 are penetrated up and down and the side surface of the plurality of electronic integrated circuit wafers 300 away from the semiconductor wafer 100 is exposed, the semiconductor wafer 100 is exposed. The second surface 102b of 100 is fixed to the package substrate 500.
最後，如圖 7I 所示，將導光結構 600 或者雷射器晶片通過每個所述偽晶片 400 的開口安裝至對應的所述光耦合介面 104 上。示例性地，所示導光結構600 為光纖陣列，光纖陣列穿過每個所述偽晶片 400 的空腔耦合至所述光耦合介面 104，根據一些實施例，可以使用光耦合膠將光纖陣列傾斜地耦合到光耦合介面 104。例如，可以相對於所述半導體晶片 100 的第一表面 102a 以 45°角的方式將光纖陣列耦合至光耦合器的光耦合介面，光纖陣列的另一端連接外部光源，以提供對所述第一光子積體電路晶片 102 的光信號輸入。Finally, as shown in FIG. 7I , the light guide structure 600 or the laser chip is installed on the corresponding optical coupling interface 104 through the opening of each dummy chip 400 . Illustratively, the light guide structure 600 shown is an optical fiber array. The optical fiber array passes through the cavity of each dummy wafer 400 and is coupled to the optical coupling interface 104. According to some embodiments, optical coupling glue can be used to couple the optical fiber array to the optical coupling interface 104. Obliquely coupled to the optical coupling interface 104. For example, the optical fiber array may be coupled to the optical coupling interface of the optical coupler at an angle of 45° relative to the first surface 102a of the semiconductor wafer 100, and the other end of the optical fiber array is connected to an external light source to provide light for the first Optical signal input to the photonic integrated circuit chip 102 .
由上述內容可知，本發明實施例提供的片上光互連結構及其製作方法，旨在通過在具有多個第一光子積體電路晶片的所述半導體晶片上設置有覆蓋在相鄰兩個第一光子積體電路晶片的部分所述第一表面的第二光子積體電路晶片，利用第二光子積體電路晶片的多個第二光波導，將相鄰的兩個所述第一光子積體電路晶片之間進行光互連，從而實現晶圓級無間斷的片上光互連，以提高片上光網路（Optical Network-on-Chip，ONOC）的性能和應用價值。不僅突破單顆第一光子積體電路晶片尺寸的上限，而且在該晶圓級的片上光互連結構中，光輸入端和輸出端的埠可以靈活設置在該晶圓級的片上光互連結構的任何位置，並且可以根據需要選擇在同一光通信中的第一光子積體電路晶片的數量，設計靈活。As can be seen from the above, the on-chip optical interconnection structure and the manufacturing method thereof provided by embodiments of the present invention are intended to cover two adjacent second photonic integrated circuit wafers by providing a semiconductor wafer having a plurality of first photonic integrated circuit wafers. A second photonic integrated circuit chip on part of the first surface of a photonic integrated circuit chip uses a plurality of second optical waveguides of the second photonic integrated circuit chip to connect two adjacent first photonic integrated circuit chips. Optical interconnection between bulk circuit chips is achieved to achieve uninterrupted on-chip optical interconnection at the wafer level to improve the performance and application value of the Optical Network-on-Chip (ONOC). Not only does it break through the upper limit of the size of a single first photonic integrated circuit chip, but also in this wafer-level on-chip optical interconnection structure, the optical input and output ports can be flexibly set in this wafer-level on-chip optical interconnection structure. Any position, and the number of first photonic integrated circuit wafers in the same optical communication can be selected as needed, with flexible design.
進一步地，所述多個第一光波導和所述多個第二光波導以並行的方式進行多通道傳輸，能夠顯著增加每個所述第一光子積體電路晶片中傳輸的光通信容量。Furthermore, the plurality of first optical waveguides and the plurality of second optical waveguides perform multi-channel transmission in parallel, which can significantly increase the optical communication capacity transmitted in each of the first photonic integrated circuit wafers.
上文僅為本發明的較佳實施例而已，並非用來限定本發明實施的範圍，凡依本發明申請專利範圍所述的形狀、構造、特徵及精神所為的均等變化與修飾，均應包括於本發明的申請專利範圍內。The above are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention. All equal changes and modifications in shape, structure, characteristics and spirit described in the patent application scope of the present invention shall include within the patentable scope of the present invention.
100:半導體晶片 101:減薄半導體晶片 102:第一光子積體電路晶片 102a:第一表面 102b:第二表面 1022:金屬連接柱 1023:導電凸塊 1024:光耦合區 104:光耦合介面 106:封裝層 110:第一光波導 111:第一光波導端部 200:第二光子積體電路晶片 210:第二光波導 211:第二光波導端部 213:光柵耦合器 300:電子積體電路晶片 400:偽晶片 500:封裝基板 600:導光結構 810:光束重定向元件 S101/S102:步驟 100:Semiconductor wafer 101:Thinning semiconductor wafers 102: The first photonic integrated circuit chip 102a: First surface 102b: Second surface 1022:Metal connecting post 1023: Conductive bumps 1024: Optical coupling area 104: Optical coupling interface 106: Encapsulation layer 110:First optical waveguide 111: First optical waveguide end 200: The second photonic integrated circuit chip 210: Second optical waveguide 211: Second optical waveguide end 213:Grating coupler 300: Electronic integrated circuit chips 400: Pseudo chip 500:Package substrate 600:Light guide structure 810: Beam redirection element S101/S102: Steps
為了更清楚地說明本申請實施例中的技術方案，下面將對實施例描述中所需要使用的圖式作簡單地介紹，顯而易見地，下面描述中的圖式僅僅是本申請的一些實施例，對於本發明所屬技術領域的通常知識者來講，在不付出創造性勞動的前提下，還可以根據這些圖式獲得其他的實施方式。 圖 1A 是根據本發明實施例提供的一種片上光互連結構的俯視結構示意圖。 圖 1B 是根據本發明實施例提供的一種片上光互連結構的側視結構示意圖。 圖 2 是根據圖 1A 實施例中相鄰的兩個所述第一光子積體電路晶片的多個第一光波導通過所述第二光子積體電路晶片的所述多個第二光波導進行光互連的第一種實施方式的側視結構示意圖。 圖 3 是根據圖 1A 實施例中相鄰的兩個所述第一光子積體電路晶片的多個第一光波導通過所述第二光子積體電路晶片的所述多個第二光波導進行光互連的第二種實施方式的側視結構示意圖。 圖 4A 是根據本發明實施例提供的又一種片上光互連結構的俯視結構示意圖。 圖 4B 是根據本發明實施例提供的又一種片上光互連結構的側視結構示意圖。 圖 5 是根據本發明實施例提供的另一種片上光互連結構的側視結構示意圖。 圖 6 是根據本發明實施例提供的片上光互連結構的製作方法的流程圖。 圖 7A-圖 7I 是根據本發明實施例提供的片上光互連結構的製作方法的製作工序示意圖。 In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those with ordinary knowledge in the technical field to which the present invention belongs, other implementation modes can be obtained based on these drawings without exerting creative efforts. FIG. 1A is a schematic top view of an on-chip optical interconnect structure provided according to an embodiment of the present invention. FIG. 1B is a schematic side structural diagram of an on-chip optical interconnect structure provided according to an embodiment of the present invention. Figure 2 is a process in which the plurality of first optical waveguides of two adjacent first photonic integrated circuit wafers pass through the plurality of second optical waveguides of the second photonic integrated circuit wafer in the embodiment of Figure 1A Schematic side view of the first embodiment of optical interconnection. Figure 3 is a process in which the plurality of first optical waveguides of two adjacent first photonic integrated circuit wafers pass through the plurality of second optical waveguides of the second photonic integrated circuit wafer in the embodiment of Figure 1A Schematic side view of a second embodiment of optical interconnection. FIG. 4A is a schematic top view of another on-chip optical interconnect structure provided according to an embodiment of the present invention. FIG. 4B is a schematic side view of another on-chip optical interconnect structure provided according to an embodiment of the present invention. Figure 5 is a schematic side structural diagram of another on-chip optical interconnect structure provided according to an embodiment of the present invention. Figure 6 is a flow chart of a method for manufacturing an on-chip optical interconnect structure according to an embodiment of the present invention. 7A-7I are schematic diagrams of the manufacturing process of the method for manufacturing an on-chip optical interconnect structure provided according to an embodiment of the present invention.
100:半導體晶片 100:Semiconductor wafer
102:第一光子積體電路晶片 102: The first photonic integrated circuit chip
102a:第一表面 102a: First surface
102b:第二表面 102b: Second surface
1022:金屬連接柱 1022:Metal connecting post
110:第一光波導 110:First optical waveguide
200:第二光子積體電路晶片 200: The second photonic integrated circuit chip
210:第二光波導 210: Second optical waveguide
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