TW202405253A - High density coil design and process - Google Patents
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- 238000000034 method Methods 0.000 title description 229
- 230000008569 process Effects 0.000 title description 123
- 238000013461 design Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 107
- 229910000679 solder Inorganic materials 0.000 claims description 64
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 238000003466 welding Methods 0.000 claims description 25
- 238000005476 soldering Methods 0.000 claims description 23
- 239000010410 layer Substances 0.000 description 190
- 238000007747 plating Methods 0.000 description 161
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 57
- 239000010949 copper Substances 0.000 description 57
- 229910052802 copper Inorganic materials 0.000 description 57
- 239000004020 conductor Substances 0.000 description 47
- 239000003990 capacitor Substances 0.000 description 32
- 238000004519 manufacturing process Methods 0.000 description 30
- 239000000853 adhesive Substances 0.000 description 21
- 230000001070 adhesive effect Effects 0.000 description 21
- 230000008878 coupling Effects 0.000 description 20
- 238000010168 coupling process Methods 0.000 description 20
- 238000005859 coupling reaction Methods 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 16
- 230000001939 inductive effect Effects 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 239000000725 suspension Substances 0.000 description 16
- 238000012546 transfer Methods 0.000 description 16
- 239000011800 void material Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 15
- 238000009713 electroplating Methods 0.000 description 15
- 239000000654 additive Substances 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 229920001721 polyimide Polymers 0.000 description 11
- 239000004642 Polyimide Substances 0.000 description 10
- 239000012530 fluid Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910000881 Cu alloy Inorganic materials 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000003795 chemical substances by application Substances 0.000 description 5
- 239000003112 inhibitor Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000000976 ink Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 229910000851 Alloy steel Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000008713 feedback mechanism Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000002595 magnetic resonance imaging Methods 0.000 description 2
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 2
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001223 polyethylene glycol Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000003351 stiffener Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
- LMPMFQXUJXPWSL-UHFFFAOYSA-N 3-(3-sulfopropyldisulfanyl)propane-1-sulfonic acid Chemical compound OS(=O)(=O)CCCSSCCCS(O)(=O)=O LMPMFQXUJXPWSL-UHFFFAOYSA-N 0.000 description 1
- OBDVFOBWBHMJDG-UHFFFAOYSA-N 3-mercapto-1-propanesulfonic acid Chemical compound OS(=O)(=O)CCCS OBDVFOBWBHMJDG-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- RVGRUAULSDPKGF-UHFFFAOYSA-N Poloxamer Chemical compound C1CO1.CC1CO1 RVGRUAULSDPKGF-UHFFFAOYSA-N 0.000 description 1
- 239000002202 Polyethylene glycol Substances 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000002156 adsorbate Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- DMFGNRRURHSENX-UHFFFAOYSA-N beryllium copper Chemical compound [Be].[Cu] DMFGNRRURHSENX-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008468 bone growth Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002052 colonoscopy Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 235000013305 food Nutrition 0.000 description 1
- 230000012010 growth Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001983 poloxamer Polymers 0.000 description 1
- 229960000502 poloxamer Drugs 0.000 description 1
- 229920001992 poloxamer 407 Polymers 0.000 description 1
- 229920001987 poloxamine Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001451 polypropylene glycol Polymers 0.000 description 1
- 229920000036 polyvinylpyrrolidone Polymers 0.000 description 1
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 description 1
- 239000001267 polyvinylpyrrolidone Substances 0.000 description 1
- 229920005604 random copolymer Polymers 0.000 description 1
- 238000007761 roller coating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007764 slot die coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F5/00—Coils
- H01F5/003—Printed circuit coils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10265—Metallic coils or springs, e.g. as part of a connection element
Abstract
Description
本發明大體上係關於線圈結構及其製造製程。The present invention generally relates to coil structures and processes for their manufacture.
用於製造諸如銅或銅合金電路結構(諸如引線、跡線及通孔互連件)之結構的電鍍製程通常已知且揭示於例如Castellani等人，美國專利4,315,985，名為Fine-Line Circuit Fabrication and Photoresist Application Therefor中。此等類型之製程例如與如以下專利中所揭示之磁碟機頭懸掛件之製造結合使用：Bennin等人，美國專利8,885,299，名為Low Resistance Ground Joints for Dual Stage Actuation Disk Drive Suspensions；Rice等人，美國專利8,169,746，名為Integrated Lead Suspension with Multiple Trace Configurations；Hentges等人，美國專利8,144,430，名為Multi-Layer Ground Plane Structures for Integrated Lead Suspensions；Hentges等人，美國專利7,929,252，名為Multi-Layer Ground Plane Structures for Integrated Lead Suspensions；Swanson等人，美國專利7,388,733，名為Method for Making Noble Metal Conductive Leads for Suspension Assemblies；及Peltoma等人美國專利7,384,531，名為Plated Ground Features for Integrated Lead Suspensions。此等類型之製程亦與如所以下揭示之相機鏡頭懸掛件之製造結合使用，例如在Miller美國專利9,366,879，名為Camera Lens Suspension with Polymer Bearings中。Electroplating processes for fabricating structures such as copper or copper alloy circuit structures such as leads, traces, and through-hole interconnects are generally known and disclosed, for example, by Castellani et al., U.S. Patent 4,315,985, entitled Fine-Line Circuit Fabrication and Photoresist Application Therefor. This type of process is used, for example, in conjunction with the fabrication of disk drive suspensions as disclosed in Bennin et al., U.S. Patent 8,885,299, Low Resistance Ground Joints for Dual Stage Actuation Disk Drive Suspensions; Rice et al. , US Patent 8,169,746, named Integrated Lead Suspension with Multiple Trace Configurations; Hentges et al., US Patent 8,144,430, named Multi-Layer Ground Plane Structures for Integrated Lead Suspensions; Hentges et al., US Patent 7,929,252, named Multi-Layer Ground Plane Structures for Integrated Lead Suspensions; Swanson et al., U.S. Patent 7,388,733, titled Method for Making Noble Metal Conductive Leads for Suspension Assemblies; and Peltoma et al., U.S. Patent 7,384,531, titled Plated Ground Features for Integrated Lead Suspensions. These types of processes are also used in conjunction with the manufacture of camera lens suspensions as disclosed below, for example in Miller US Patent 9,366,879, Camera Lens Suspension with Polymer Bearings.
超級填充及超保形鍍覆製程及組合物亦為已知的且揭示於例如以下文章中：Vereecken等人，「The chemistry of additives in damascene copper plating」,Res. & Dev.之IBM J.,第49卷,第1期,2005年1月；Andricacos等人，「Damascene copper electroplating for chip interconnections」,Res. & Dev.之IBM J.,第42卷,第5期,1998年9月；及Moffat等人,「Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing」,Electrochimica Acta 53, 第145-154頁, 2007。藉由此等製程，在溝槽(例如，界定待電鍍結構之空間的光阻遮遮罩溝槽)內之電鍍較佳地發生在底部中。可藉此避免沉積結構中之空隙。所有以上鑑別之專利及文章出於所有目的特此以全文引用之方式併入。Superfilled and superconformal plating processes and compositions are also known and disclosed in, for example, Vereecken et al., "The chemistry of additives in damascene copper plating," IBM J. Res. & Dev., Volume 49, Issue 1, January 2005; Andricacos et al., "Damascene copper electroplating for chip interconnections", IBM J. Res. & Dev., Volume 42, Issue 5, September 1998; and Moffat et al., "Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing," Electrochimica Acta 53, pp. 145-154, 2007. With these processes, plating within trenches (eg, photoresist mask trenches defining the space of the structure to be plated) preferably occurs in the bottom. This allows voids in the deposited structure to be avoided. All patents and articles identified above are hereby incorporated by reference in their entirety for all purposes.
仍存在對增強型電路結構的持續需求。亦持續需要用於製造電路及其他結構之高效及有效製程，包括電鍍製程。There remains a continuing need for enhanced circuit structures. There is also a continuing need for efficient and effective processes for manufacturing circuits and other structures, including electroplating processes.
描述包括高縱橫比電鍍結構之裝置及形成高縱橫比電鍍結構之方法。一種用於製造金屬結構之方法包括提供具有特徵為高與寬縱橫比之金屬基底的基板且在基底上電鍍金屬頂部，以形成高與寬縱橫比大於基底之縱橫比的金屬結構。Devices including high aspect ratio electroplated structures and methods of forming high aspect ratio electroplated structures are described. A method for fabricating a metal structure includes providing a substrate having a metal base characterized by a height to width aspect ratio and electroplating a metal top on the base to form a metal structure with a height to width aspect ratio greater than the aspect ratio of the base.
本發明之實施例的其他特徵及優勢將自隨附圖式及以下實施方式顯而易知。Other features and advantages of embodiments of the invention will be apparent from the accompanying drawings and the following description.
相關申請案之交叉參考Cross-references to related applications
本申請案主張2019年11月22日申請之美國專利申請案第16/693,125號之優先權，且進一步主張2018年11月30日申請之美國臨時申請案第62/774,027號之權益，該等申請案中之每一者以全文引用之方式併入本文中。This application claims the priority of U.S. Patent Application No. 16/693,125 filed on November 22, 2019, and further claims the rights of U.S. Provisional Application No. 62/774,027 filed on November 30, 2018, which Each of these applications is incorporated by reference in its entirety.
描述根據本發明之實施例的高縱橫比電鍍結構及製造方法。高縱橫比電鍍結構提供比當前技術更緊密的導體間距。舉例而言，根據各種實施例之高縱橫比之電鍍結構包括導體堆疊，其具有大於50%之導體堆疊之橫截面積。此外，根據實施例，高縱橫比電鍍結構實現多層導體。另外，根據各種實施例，高縱橫比電鍍結構實現層與層之間的精密對準。舉例而言，高縱橫比電鍍結構在層與層之間具有小於0.030 mm之對準。根據各種實施例，高縱橫比電鍍結構實現降低之總堆疊高度。High aspect ratio plating structures and fabrication methods according to embodiments of the present invention are described. High aspect ratio plated structures provide tighter conductor spacing than current technology. For example, a high aspect ratio electroplated structure according to various embodiments includes a conductor stack having greater than 50% of the cross-sectional area of the conductor stack. Furthermore, according to embodiments, the high aspect ratio plating structure enables multi-layer conductors. Additionally, according to various embodiments, high aspect ratio electroplated structures enable precise alignment between layers. For example, high aspect ratio electroplated structures have less than 0.030 mm alignment between layers. According to various embodiments, high aspect ratio plating structures enable reduced overall stack height.
根據各種實施例，高縱橫比電鍍結構實現使用高縱橫比電鍍結構形成之線圈與磁體之間的較薄介電材料。此使得線圈能夠產生比電流印刷電路線圈(諸如圖1中所說明之彼等線圈)更強的電磁場。因此，高縱橫比電鍍結構更具成本效益，產生更高性能裝置，且相對於當前技術減少裝置所需之佔據面積。According to various embodiments, the high aspect ratio plating structure enables thinner dielectric material between the coil and the magnet formed using the high aspect ratio plating structure. This enables the coil to generate stronger electromagnetic fields than current printed circuit coils such as those illustrated in Figure 1 . Therefore, high aspect ratio electroplated structures are more cost-effective, produce higher performance devices, and reduce the required device footprint relative to current technology.
圖2說明根據實施例之包括高縱橫比電鍍結構的高密度精密線圈。高縱橫比電鍍結構202形成於列中，其中在每一列與每個高縱橫比電鍍結構204之間具有介電材料。高密度精密線圈可形成為螺旋線圈或其他線圈類型。Figure 2 illustrates a high density precision coil including a high aspect ratio electroplated structure, according to an embodiment. High aspect ratio plated structures 202 are formed in columns with dielectric material between each column and each high aspect ratio plated structure 204 . High-density precision coils can be formed as spiral coils or other coil types.
圖3說明根據實施例用以表示由包括高縱橫比電鍍結構之高密度精密線圈產生之電磁力的圖。圖式包括接近磁體304之線圈橫截面302。最高電磁力306位於更接近磁體304之線圈層308中。其他來自磁體304之線圈層310施加較小力。影響力之主要因素來自勞倫茲方程式(Lorentz equation)： 。因為 之量值之強度隨著線圈與磁體之間的距離而減小，因此 為流過銅之電流。不為導體之橫截面302之任何區域不促成力( )。 3 illustrates a graph representing electromagnetic forces generated by a high-density precision coil including a high aspect ratio electroplated structure, according to an embodiment. The illustration includes a coil cross-section 302 proximal to the magnet 304. The highest electromagnetic force 306 is located in the coil layer 308 closer to the magnet 304. Other coil layers 310 from magnets 304 exert smaller forces. The main factor of influence comes from the Lorentz equation: . Because The magnitude of decreases with the distance between the coil and the magnet, so is the current flowing through copper. Any area of cross-section 302 that is not a conductor does not contribute to the force ( ).
影響線圈之施力能力(force capability)的主要因素包括磁場內之匝的數目(最接近磁體之極點的匝提供最大力)、線圈距磁體之距離(更接近磁體之層將施加更多力)及磁場內之銅橫截面積的總百分比。與使用電流線圈技術之線圈相比，使用根據各種實施例之高縱橫比電鍍結構改良此等態樣。The main factors that affect the force capability of a coil include the number of turns in the magnetic field (turns closest to the poles of the magnet provide the greatest force), and the distance of the coil from the magnet (layers closer to the magnet will exert more force). and the total percentage of copper cross-sectional area within the magnetic field. The use of high aspect ratio electroplated structures in accordance with various embodiments improves these aspects compared to coils using current coil technology.
舉例而言，使用現行技術具有兩層之線圈具有約210微米之總厚度、38微米之導體間距、約20%之銅之橫截面百分比、3.1歐姆之估算電阻、1.0之估算力比(1.0之估算B比率及1.0之估算J比率)及1.0之估算功率比。相比之下，根據各種實施例，包括高縱橫比電鍍結構之高密度精密線圈具有約116微米之總厚度、40微米之導體間距、約60%之銅之橫截面百分比、5.5歐姆之估算電阻、1.2之估算力比(1.5之估算B比率及0.8之估算J比率)及0.71之估算功率比。因此，根據各種實施例，包括高縱橫比電鍍結構之高密度精密線圈為更高性能裝置。因此，根據一些實施例，此高密度精密線圈以使用目前所屬領域技術之線圈厚度的一半提供多20%的力，功率小30%。For example, a coil with two layers using current technology has a total thickness of about 210 microns, a conductor spacing of 38 microns, a cross-section percentage of about 20% copper, an estimated resistance of 3.1 ohms, and an estimated force ratio of 1.0 (1.0 Estimated B ratio and estimated J ratio of 1.0) and estimated power ratio of 1.0. In comparison, according to various embodiments, a high-density precision coil including a high aspect ratio electroplated structure has a total thickness of approximately 116 microns, a conductor spacing of 40 microns, a cross-section percentage of approximately 60% copper, and an estimated resistance of 5.5 ohms. , an estimated force ratio of 1.2 (an estimated B ratio of 1.5 and an estimated J ratio of 0.8) and an estimated power ratio of 0.71. Therefore, according to various embodiments, high density precision coils including high aspect ratio electroplated structures are higher performance devices. Therefore, according to some embodiments, this high-density precision coil provides 20% more force and 30% less power at half the thickness of coils using current state-of-the-art technology.
圖 4說明經組態以用於線性馬達類型應用之包括多層根據一實施例的高縱橫比電鍍結構之裝置。由於優於當前技術之尺寸優勢，與諸如圖1中所說明之使用當前技術可能的情況相比，高縱橫比電鍍結構之各層402a-d更接近磁體404。另外，每一層402a-d更接近於磁體404藉由利用體積 場(磁通量密度)來改良線性馬達之施力能力。因此，多層高縱橫比電鍍結構用於線性馬達將需要比使用當前技術更少之層。另外，此結構在獲得如低電阻之電特性方面提供較大靈活性。 Figure 4 illustrates a device configured for linear motor type applications including multiple layers of a high aspect ratio electroplated structure according to an embodiment. Due to size advantages over current technology, the layers 402a-d of the high aspect ratio electroplated structure are closer to the magnet 404 than is possible using current technology such as illustrated in FIG. 1 . Additionally, each layer 402a-d is closer to the magnet 404 by utilizing the volume Field (magnetic flux density) to improve the force application capability of the linear motor. Therefore, multilayer high aspect ratio plating structures for linear motors will require fewer layers than using current technology. In addition, this structure provides greater flexibility in achieving electrical characteristics such as low resistance.
圖5說明根據一些實施例在製造製程期間之一階段的高縱橫比電鍍結構。在製造製程期間此階段之高縱橫比電鍍結構602之層係使用半加成技術形成，以產生具有約1比1之初始高度與寬度縱橫比(A/B)之精細間距、抗蝕劑界定之導體。舉例而言，高縱橫比電鍍結構可具有20微米高度及20微米寬度。根據一些實施例，鍍覆製程在此時停止以便使用包括此項技術中已知彼等的技術移除界定產品，諸如光阻遮罩及晶種層。Figure 5 illustrates a high aspect ratio electroplated structure at one stage during a manufacturing process in accordance with some embodiments. The layers of high aspect ratio plating structure 602 at this stage during the manufacturing process are formed using semi-additive techniques to produce fine pitch, resist definitions with an initial height to width aspect ratio (A/B) of approximately 1 to 1. of conductor. For example, a high aspect ratio plated structure may have a height of 20 microns and a width of 20 microns. According to some embodiments, the plating process is stopped at this point to remove defined products, such as the photoresist mask and seed layer, using techniques including those known in the art.
圖6說明根據一些實施例在製造製程期間之另一階段的高縱橫比電鍍結構。在製造製程期間此階段之高縱橫比電鍍結構702之層使用頂部鍍覆技術形成以將半加成導體轉化為高縱橫比、高百分比金屬導體電路。舉例而言，高縱橫比電鍍結構具有大於1比1之最終高度與寬度比(A/S)。根據各種實施例，最終高度與寬度比可在包括1.2至3.0的範圍內。其他實施例包括大於3.0之最終高度與寬度比。然而，熟習此項技術者應理解，可使用本文中所描述之技術獲得任何最終高度與寬度比以便符合設計及性能準則。在如圖6中所說明的由如圖5中所說明之前一階段形成的形成階段，不存在對如各種實施例中所揭示的高縱橫比電鍍結構之最終高度的特定限制。Figure 6 illustrates a high aspect ratio electroplated structure at another stage during the manufacturing process in accordance with some embodiments. The layers of high aspect ratio plating structure 702 at this stage during the manufacturing process are formed using top plating techniques to convert semi-additive conductors into high aspect ratio, high percentage metal conductor circuits. For example, high aspect ratio plated structures have a final height to width ratio (A/S) of greater than 1 to 1. According to various embodiments, the final height to width ratio may range from 1.2 to 3.0. Other embodiments include final height to width ratios greater than 3.0. However, those skilled in the art will understand that any final height to width ratio may be achieved using the techniques described herein so as to comply with design and performance guidelines. In the formation stage as illustrated in Figure 6 resulting from the previous stage as illustrated in Figure 5, there are no specific limitations on the final height of the high aspect ratio plated structures as disclosed in the various embodiments.
圖7說明根據一些實施例在製造製程期間另一階段的高縱橫比電鍍結構。在製造製程期間此階段之高縱橫比電鍍結構802a、802b之層係使用平坦化轉換技術形成，以允許使用半加成技術堆疊多層高縱橫比電鍍結構以形成後續層。圖8說明根據一些實施例之具有多層高縱橫比電鍍結構的裝置，該等高縱橫比電鍍結構具有高比例之導體橫截面積901。Figure 7 illustrates a high aspect ratio electroplated structure at another stage during the manufacturing process in accordance with some embodiments. The layers of high aspect ratio plating structures 802a, 802b at this stage during the manufacturing process are formed using planarization switching techniques to allow stacking of multiple layers of high aspect ratio plating structures using semi-additive techniques to form subsequent layers. Figure 8 illustrates a device with multiple layers of high aspect ratio plating structures having a high proportion of conductor cross-sectional area 901 in accordance with some embodiments.
用以自結構(諸如圖5中所說明之彼等結構)形成高縱橫比電鍍結構的方法包括使用低電流密度鍍覆技術。此鍍覆技術將側壁鍍覆直至在高縱橫比電鍍結構之間獲得所要間隔為止。對於各種實施例，若高縱橫比之電鍍結構之間的間隔不夠窄，則可發生頂部處之不合需要的捏合。在鄰近結構之頂部邊緣生長在一起且夾斷間隙的情況下發生捏合，此產生短路。對於各種實施例，藉由充分流體交換增強低電流密度鍍覆製程，使得新鮮鍍覆浴連續地可用於發生銅鍍覆之表面。另外，用以形成高縱橫比電鍍結構之方法包括使用高電流密度鍍覆技術。此高電流密度鍍覆技術在高百分比之質量轉移極限下執行。此主要或僅鍍覆於形成高縱橫比電鍍結構之導電材料之頂部上。藉由精密電流密度控制來增強高電流密度鍍覆製程。圖9說明具有上線1002及下線1004的圖表，上線1002指示根據一實施例在高電流密度鍍覆技術期間之高SPS覆蓋，且下線1004指示在根據一實施例在低電流密度鍍覆技術期間之低、極均勻加速劑覆蓋。Methods for forming high aspect ratio electroplated structures from structures such as those illustrated in Figure 5 include the use of low current density plating techniques. This plating technique plates the sidewalls until the desired spacing is achieved between high aspect ratio plated structures. For various embodiments, if the spacing between high aspect ratio plated structures is not narrow enough, undesirable pinching at the top can occur. The pinching occurs where the top edges of adjacent structures grow together and pinch off the gap, which creates a short circuit. For various embodiments, the low current density plating process is enhanced with sufficient fluid exchange such that fresh plating baths are continuously available to the surface where copper plating occurs. Additionally, methods for forming high aspect ratio electroplated structures include the use of high current density plating techniques. This high current density plating technology performs at high percentage mass transfer limits. This is primarily or only plated on top of the conductive material forming the high aspect ratio plated structure. Enhance high current density plating processes with precise current density control. Figure 9 illustrates a graph with an upper line 1002 indicating high SPS coverage during a high current density plating technique according to one embodiment, and a lower line 1004 indicating high SPS coverage during a low current density plating technique according to an embodiment. Low, extremely uniform accelerator coverage.
圖10a-f說明根據一實施例用於形成高縱橫比電鍍結構之製程。圖10a說明形成於製程之時間T1處之抗蝕劑能力之厚極限處的跡線1102。對於一些實施例，預鍍覆傳統跡線係使用諸如金屬鑲嵌法之製程，或使用包括此項技術中已知之彼等的蝕刻及沉積技術由銅形成。圖10b說明在低電流密度或保形鍍覆製程期間在時間T2處的高縱橫比電鍍結構之形成。根據一實施例，保形鍍覆製程以大致相同速率生長跡線之所有表面。另外，保形鍍覆製程抑制鍍覆動力(低加速劑覆蓋)。保形鍍覆製程亦提供相當均勻的金屬濃度，其具有高的均勻抑制劑覆蓋以抵消。此經抑制之鍍覆動力效應可藉由電鍍浴包括調平劑而增強。獲得均勻的金屬濃度且獲得高的均勻抑制劑覆蓋需要較低電流密度。根據一些實施例，將使用每平方公尺2安培之保形鍍覆製程用於鍍覆，諸如銅、增亮劑添加劑、壓板之溫度及流體機制。此保形鍍覆製程之實例包括但不限於低電流密度鍍覆製程。在低電流密度下，鍍覆浴維持均勻抑制狀態，提供保形鍍覆。對於另一實施例，可在電鍍浴中添加調平劑以提供更高電流密度及更快鍍覆。對於又一實施例，將銅含量增加至接近於鍍覆浴中之硫酸銅之溶解度極限可用於進一步提高電流密度。此提供使電流密度加倍或甚至更大的能力以達成相同保形鍍覆品質。舉例而言，在減少酸含量之情況下銅含量可高達40公克/公升以防止共離子效應。Figures 10a-f illustrate a process for forming high aspect ratio electroplated structures according to one embodiment. Figure 10a illustrates trace 1102 formed at the thick limit of resist capability at time T1 of the process. For some embodiments, pre-plated conventional traces are formed from copper using a process such as damascene, or using etching and deposition techniques including those known in the art. Figure 10b illustrates the formation of a high aspect ratio electroplated structure at time T2 during a low current density or conformal plating process. According to one embodiment, the conformal plating process grows traces at approximately the same rate on all surfaces. In addition, the conformal plating process inhibits plating dynamics (low accelerator coverage). The conformal plating process also provides a fairly uniform metal concentration, which is offset by high uniform inhibitor coverage. This suppressed plating kinetic effect can be enhanced by including a leveling agent in the electroplating bath. Lower current densities are required to obtain uniform metal concentration and to obtain high uniform inhibitor coverage. According to some embodiments, a conformal plating process using 2 amps per square meter will be used for plating, such as copper, brightener additives, temperature of the platen, and fluidic mechanisms. Examples of such conformal plating processes include, but are not limited to, low current density plating processes. At low current densities, the plating bath maintains a uniform suppression state, providing conformal plating. For another example, a leveling agent can be added to the plating bath to provide higher current density and faster plating. For yet another example, increasing the copper content close to the solubility limit of copper sulfate in the plating bath can be used to further increase the current density. This provides the ability to double the current density or even greater to achieve the same conformal plating quality. For example, the copper content can be as high as 40 g/L with reduced acid content to prevent common ion effects.
對於一些實施例，低電流密度鍍覆製程將諸如銅之導電材料沉積至跡線1102之頂部及側壁上，例如，T2為在低電流密度鍍覆製程期間進入製程中大致五分鐘(T1+5分鐘)。圖10c說明在低電流密度鍍覆製程期間在進入製程中時間T3處形成高縱橫比電鍍結構。對於一實施例，低電流密度鍍覆製程將諸如銅之導電材料沉積至跡線1102之頂部及側壁上，例如T3為在低電流密度鍍覆製程期間進入製程中大致五分鐘(T1+15分鐘)。For some embodiments, a low current density plating process deposits a conductive material, such as copper, onto the tops and sidewalls of traces 1102. For example, T2 is approximately five minutes into the process during the low current density plating process (T1+5 minute). Figure 10c illustrates the formation of a high aspect ratio plated structure at mid-process time T3 during a low current density plating process. For one embodiment, a low current density plating process deposits a conductive material, such as copper, onto the top and sidewalls of traces 1102, such that T3 is approximately five minutes into the process during the low current density plating process (T1 + 15 minutes ).
圖10d說明在頂部鍍覆製程(諸如，高電流各向異性超鍍覆製程)期間在進入製程中時間T4處形成高縱橫比電鍍結構。舉例而言，T4為進入製程大致15分鐘及10秒(T1+15分鐘10秒)。對於一些實施例，高電流各向異性超鍍覆製程為頂部鍍覆。頂部鍍覆基於平衡以下因素之間的相互作用：溶液中之金屬濃度、增亮劑添加劑、抑制劑添加劑、至表面之質量轉移-流體交換率、調平劑、及基板處之電流密度。溶液中之金屬濃度可包括但不限於銅。增亮劑添加劑可包括但不限於SPS(雙(3-磺丙基)-二硫)、DPS(3-N,N-二甲基胺基二硫代胺甲醯基-1-丙磺酸)及MPS(巰基丙基磺酸)。抑制劑添加劑可包括但不限於包括本領域中熟習此項技術者已知之彼等的各種分子量之直鏈PEG；泊洛沙胺(poloxamine)；聚乙二醇及聚丙二醇之共嵌段聚合物，諸如藉由各種商標名已知之水溶性泊洛沙姆(poloxamer)，諸如BASF pluronic f127；及同樣各種單體比率及各種分子量之無規共聚物，諸如高性能流體之DOW®UCON系列；各種分子量之聚乙烯吡咯啶酮。Figure 10d illustrates the formation of a high aspect ratio plated structure at time T4 into the process during a top plating process, such as a high current anisotropic super plating process. For example, T4 is approximately 15 minutes and 10 seconds into the process (T1+15 minutes and 10 seconds). For some embodiments, the high current anisotropic super plating process is top plating. Top plating is based on balancing the interplay between: metal concentration in solution, brightener additives, inhibitor additives, mass transfer-fluid exchange rate to the surface, leveling agents, and current density at the substrate. Metal concentrations in the solution may include, but are not limited to, copper. Brightener additives may include, but are not limited to, SPS (bis(3-sulfopropyl)-disulfide), DPS (3-N,N-dimethylaminodithiocarbamate-1-propanesulfonic acid ) and MPS (mercaptopropyl sulfonic acid). Inhibitor additives may include, but are not limited to, linear PEGs of various molecular weights including those known to those skilled in the art; poloxamine; co-block polymers of polyethylene glycol and polypropylene glycol. , such as water-soluble poloxamer known by various trade names, such as BASF pluronic f127; and also random copolymers of various monomer ratios and various molecular weights, such as the DOW® UCON series of high-performance fluids; various Molecular weight of polyvinylpyrrolidone.
根據一些實施例，高電流各向異性超鍍覆製程包括為1%的加速電流的經抑制交換電流。另外，所形成的高縱橫比電鍍結構之側壁具有幾乎零的加速劑覆蓋。藉由轉移銅沉積之能斯特電位(Nernst Potential)以促進抑制劑覆蓋來達成幾乎零的加速劑覆蓋。此外，高過電位及銅可用性(傳輸現象)在所形成之結構之頂部處產生較高加速劑覆蓋。銅整體濃度亦可經調節以支持在製程期間之接近零的加速劑覆蓋。舉例而言，用於高電流各向異性超鍍覆製程之銅整體濃度為14公克/公升或更低。對於一些實施例，銅整體濃度取決於特定流體機制。由於該製程的各種實施例在較高比例之質量轉移極限下運行，因此待鍍覆物品上的流體速度的微小差異將影響質量轉移極限，從而在無高度控制待鍍覆之物品的所有區域流體速度的情況下，難以實現對鍍覆線之間的間隙的充分控制。根據一些實施例，高電流各向異性超鍍覆製程包括調平劑添加劑，其用於阻止加速劑覆蓋以將所形成之結構側壁上的鍍覆降至最低或消除。對於其他實施例，使用無調平劑添加劑之電鍍浴。According to some embodiments, the high current anisotropic super plating process includes a suppressed exchange current of 1% of the acceleration current. Additionally, the high aspect ratio electroplated structures are formed with almost zero accelerator coverage on the sidewalls. Nearly zero accelerator coverage is achieved by shifting the Nernst potential of copper deposition to promote inhibitor coverage. Additionally, high overpotential and copper availability (transport phenomena) produce higher accelerator coverage at the top of the formed structure. The overall copper concentration can also be adjusted to support near-zero accelerator coverage during processing. For example, the overall copper concentration used in high current anisotropic super plating processes is 14 grams/liter or less. For some embodiments, the overall copper concentration depends on the specific fluid regime. Since various embodiments of the process operate at a higher proportion of the mass transfer limit, small differences in fluid velocity across the item to be plated will affect the mass transfer limit, thereby not having a high degree of control over the fluid in all areas of the item to be plated. At high speeds, it is difficult to achieve adequate control of the gap between the plated lines. According to some embodiments, the high current anisotropic super-plating process includes a leveling agent additive to prevent accelerator coverage to minimize or eliminate plating on the sidewalls of the formed structure. For other examples, a plating bath without leveler additive was used.
根據一些實施例，在高電流密度下，諸如在高電流各向異性超鍍覆製程期間使用之電流密度下，三倍回饋機制起作用。質量轉移效應在跡線之間的間隔中耗乏銅。此外，高電流密度支持加速劑(例如，SPS)主導之表面。為維持遏制側壁，質量轉移經調節以經由銅質量轉移效應降低能斯特電位。舉例而言，流體邊界層厚度及各跡線之間的間距經設計以降低能斯特電位。According to some embodiments, the triple feedback mechanism operates at high current densities, such as those used during high current anisotropic super plating processes. Mass transfer effects deplete copper in the spaces between traces. Furthermore, high current densities support surfaces dominated by accelerators (eg, SPS). To maintain containment sidewalls, mass transfer is adjusted to lower the Nernst potential via the copper mass transfer effect. For example, the thickness of the fluid boundary layer and the spacing between traces are designed to reduce the Nernst potential.
另外，根據一些實施例，高電流各向異性超電鍍製程包括在銅濃度下操作，其中此等差異可產生大於四倍的濃度差異。在此類條件期間，較低銅濃度及能斯特電位促使鍍覆速率降低。舉例而言，當能斯特電位大致在50毫伏(「mV」)至60 mV之範圍內改變時，此可促使鍍覆速率降低二十倍。此類條件誘導塔費爾動力學(Tafel kinetics)，其對於銅鍍覆而言為所施加電壓(非整流電壓)每120 mV之變化電流之變化的十倍。下部側壁電流回饋至形成之結構之頂面，其中擴散長度較短，其促進金屬自電鍍浴(溶液)更快地遞送至表面及更高加速劑覆蓋而非抑制，及較高能斯特電位。對於一些實施例，使用兩種添加劑系統(例如增亮劑及抑制劑)。調平劑藉由阻斷鍍覆特徵之頂側上之SPS作用而減輕反饋機制。Additionally, according to some embodiments, the high-current anisotropic superplating process includes operating at copper concentrations, where such differences can result in greater than a fourfold concentration difference. During such conditions, lower copper concentrations and Nernst potentials result in reduced plating rates. For example, when the Nernst potential changes approximately in the range of 50 millivolts ("mV") to 60 mV, this can result in a twenty-fold reduction in plating rate. Such conditions induce Tafel kinetics, which for copper plating are ten times the change in current per 120 mV change in applied voltage (non-rectified voltage). The lower sidewall current is fed back to the top surface of the resulting structure, where the diffusion length is shorter, which promotes faster delivery of metal from the electroplating bath (solution) to the surface and higher accelerator coverage rather than suppression, and higher Nernst potential. For some embodiments, two additive systems (eg, brightener and suppressor) are used. Leveling agents mitigate the feedback mechanism by blocking the action of the SPS on the top side of the plated feature.
隨著金屬導體或跡線之間的間距繼續縮小，金屬導體之間的間隔的高度與寬度的縱橫比實質上提高。根據一些實施例，本文提供的電鍍製程的方法在金屬導體之間的間距中以7:1及更大的縱橫比實現鍍覆。As the spacing between metal conductors or traces continues to shrink, the aspect ratio of the height to width of the spaces between the metal conductors increases substantially. According to some embodiments, the electroplating process methods provided herein achieve plating in the spacing between metal conductors at aspect ratios of 7:1 and greater.
根據一些實施例，形成高縱橫比電鍍結構之方法在選擇性位置或區域處選擇性形成金屬頂部鍍覆。在一個例示性實施例中，金屬頂部係藉由根據以下關係進行電鍍製程來選擇性形成： 其中C為鍍覆發生處之金屬(在此情況下為銅)之濃度，且C∞為電鍍浴中之整體濃度。此關係亦可表示為進行電鍍製程，其中 等於或大於質量轉移極限之67%(%)。根據其他實施例，金屬頂部係藉由根據以下關係進行電鍍製程來選擇性形成： 或其中 等於或大於質量轉移極限之80%。在另一態樣中，金屬頂部之選擇性形成藉由根據以下關係進行電鍍製程來達成： 此處 i為電流密度，且 i limit 為電流密度極限。 According to some embodiments, methods of forming high aspect ratio electroplated structures selectively form metal top plating at selective locations or regions. In an exemplary embodiment, the metal top is selectively formed by performing a plating process according to the following relationship: where C is the concentration of the metal (copper in this case) where plating occurs, and C∞ is the overall concentration in the plating bath. This relationship can also be expressed as performing an electroplating process, where Equal to or greater than 67% (%) of the mass transfer limit. According to other embodiments, the metal top is selectively formed by performing a plating process according to the following relationship: or among them Equal to or greater than 80% of the mass transfer limit. In another aspect, selective formation of the metal top is achieved by performing a plating process according to the following relationship: Here i is the current density, and i limit is the current density limit.
圖10e說明在高電流各向異性超鍍覆製程期間，在時間T5時形成高縱橫比電鍍結構。舉例而言，T5為進入製程中約15分鐘及30秒(T1+15分鐘30秒)。對於另一實施例，在時間T5=T1+5分鐘時形成如圖10e中所說明的高縱橫比電鍍結構。圖10f說明在高電流各向異性超鍍覆製程期間在時間T6處形成高縱橫比電鍍結構。此說明頂部鍍覆製程之結束，其結束根據一些實施例之高縱橫比電鍍結構之形成。舉例而言，T6為進入製程中大致20分鐘(T1+20分鐘)。對於另一實施例，在時間T6=T1+10分鐘時形成如圖10f中所說明的高縱橫比電鍍結構。Figure 10e illustrates the formation of a high aspect ratio electroplated structure at time T5 during the high current anisotropic super plating process. For example, T5 is about 15 minutes and 30 seconds into the process (T1 + 15 minutes and 30 seconds). For another example, a high aspect ratio electroplated structure is formed as illustrated in Figure 10e at time T5 = T1 + 5 minutes. Figure 10f illustrates the formation of a high aspect ratio plated structure at time T6 during a high current anisotropic super-plating process. This illustrates the end of the top plating process, which concludes the formation of high aspect ratio electroplated structures in accordance with some embodiments. For example, T6 is approximately 20 minutes into the process (T1+20 minutes). For another example, a high aspect ratio plating structure is formed as illustrated in Figure 10f at time T6 = T1 + 10 minutes.
對於一些實施例，用於形成高縱橫比電鍍結構之方法使用包括如本文所描述之保形鍍覆及各向異性鍍覆的製程。根據一些實施例，保形鍍覆製程使用總鍍覆時間之2/3。對於其他實施例，保形鍍覆製程使用總鍍覆時間之1/3。此外，保形鍍覆製程開始於2安培/平方公寸(「ASD」)低金屬電鍍浴或4 ASD高金屬電鍍浴。舉例而言，電鍍浴包括12公克/公升銅及1.85莫耳濃度(莫耳/公升)硫酸。或者，保形鍍覆製程為以0.4至1.2微米/分鐘之速率鍍覆的製程。根據一實施例，保形鍍覆製程繼續直至跡線之間的間隔在包括6至8微米之範圍內為止。電流密度將隨著所形成之結構表面積增加而緩慢降低。然而，該製程將達成所形成之所有表面之均一電流密度及生長率。對於一些實施例，隨著所形成之高縱橫比結構之表面積增加，可提高電流以維持電流密度。For some embodiments, methods for forming high aspect ratio plated structures use processes including conformal plating and anisotropic plating as described herein. According to some embodiments, the conformal plating process uses 2/3 of the total plating time. For other embodiments, the conformal plating process uses 1/3 of the total plating time. In addition, the conformal plating process starts with a 2 Amperes per square inch ("ASD") low metal plating bath or a 4 ASD high metal plating bath. For example, a plating bath includes 12 grams/liter copper and 1.85 molar (mol/liter) sulfuric acid. Alternatively, the conformal plating process is a process plating at a rate of 0.4 to 1.2 microns/minute. According to one embodiment, the conformal plating process continues until the spacing between traces is within a range including 6 to 8 microns. The current density will slowly decrease as the surface area of the formed structure increases. However, the process will achieve uniform current density and growth rate for all surfaces formed. For some embodiments, as the surface area of the formed high aspect ratio structure increases, the current can be increased to maintain the current density.
根據一些實施例，各向異性電鍍製程使用總鍍覆時間之1/3以形成高縱橫比電鍍結構。各向異性電鍍製程使ASD增加至7 ASD(保形電鍍製程之電流的3.5倍)，但平均而言，使在所形成之金屬結構之頂部處的ASD加倍。可維持與保形鍍覆製程中所使用之流體流動相同的流體流動。舉例而言，鍍覆速率為3微米/分鐘，結構之頂部在結構之側壁上以幾乎零之鍍覆速率形成。隨著結構生長，平均電流減半，但峰值電流密度在根據實施例之結構化頂部維持在大約14 ASD。舉例而言，峰值電流密度僅超過頂面處之質量轉移極限之50%，且即使側壁暴露於3公克/公升銅，側壁仍以低於10%之質量轉移極限或5:1鍍覆速率鍍覆。在質量轉移極限之更高比例下，吾人可得到更高之鍍覆速率比率。According to some embodiments, the anisotropic plating process uses 1/3 of the total plating time to form high aspect ratio plating structures. The anisotropic plating process increases the ASD to 7 ASD (3.5 times the current of the conformal plating process), but on average doubles the ASD at the top of the formed metal structure. The same fluid flow as that used in the conformal plating process is maintained. For example, the plating rate is 3 microns/minute, and the top of the structure is formed on the sidewalls of the structure at almost zero plating rate. As the structure grows, the average current is halved, but the peak current density remains at approximately 14 ASD on top of the structure according to embodiments. For example, the peak current density only exceeds 50% of the mass transfer limit at the top surface, and even though the sidewalls are exposed to 3 g/L copper, the sidewalls are still plated at less than 10% of the mass transfer limit or a 5:1 plating rate. cover. At higher ratios of the mass transfer limit, one can obtain higher plating rate ratios.
用於形成高縱橫比電鍍結構之方法之實施例包括對上文所描述之彼等的變化，以形成包括不同特徵的高縱橫比電鍍結構。舉例而言，經組態為各向異性浴之電鍍浴中之銅含量可與如上文所描述相差13.5公克/公升。在平坦跡線浴中改變銅含量但使用相同電流密度可用於控制高縱橫比電鍍結構之間的間距。本文所描述之方法之另一實施例包括使用具有12公克/公升銅含量之平坦跡線浴之平坦跡線浴，以形成相隔8微米之高縱橫比電鍍結構。本文所描述之方法之又一實施例包括使用具有15公克/公升銅含量之平坦跡線浴之平坦跡線浴，以形成相隔4微米之高縱橫比電鍍結構。因此，熟習此項技術者應理解，調節本文所描述之方法之其他參數可用以更改高縱橫比電鍍結構之特徵。本文中所描述之方法之一些實施例包括調節電流密度以匹配當前鍍覆條件，諸如質量轉移速率、電鍍浴中所含之金屬、流體速度、銅濃度、所用添加劑及溫度。Embodiments of methods for forming high aspect ratio electroplated structures include variations on those described above to form high aspect ratio electroplated structures that include different features. For example, the copper content in an electroplating bath configured as an anisotropic bath may vary by 13.5 grams/liter as described above. Varying the copper content in a flat trace bath but using the same current density can be used to control the spacing between high aspect ratio plated structures. Another embodiment of the method described herein includes using a flat trace bath with a flat trace bath having a copper content of 12 grams/liter to form high aspect ratio electroplated structures 8 microns apart. Yet another embodiment of the method described herein includes using a flat trace bath having a copper content of 15 grams/liter to form high aspect ratio electroplated structures 4 microns apart. Accordingly, those skilled in the art will appreciate that adjusting other parameters of the methods described herein can be used to modify the characteristics of high aspect ratio electroplated structures. Some embodiments of the methods described herein include adjusting the current density to match current plating conditions, such as mass transfer rate, metal contained in the electroplating bath, fluid velocity, copper concentration, additives used, and temperature.
形成高縱橫比電鍍結構之方法亦包括使用較薄介電製程。根據一些實施例，將感光聚醯亞胺用作每一高縱橫比電鍍結構之間的介電質。液體感光聚醯亞胺實現較小通孔能力、高縱橫比導體之間的良好覆蓋、良好對齊/容限能力，其為高可靠性材料且具有與銅緊密匹配之熱膨脹係數(「CTE」)。液體感光聚醯亞胺可容易填充高縱橫比電鍍結構之間的間隙。根據一些實施例，使用液體感光聚醯亞胺產生降至0.030毫米之通孔入口。可使用之其他介電質包括但不限於KMPR及SU-8。Methods of forming high aspect ratio electroplated structures also include using thinner dielectric processes. According to some embodiments, photosensitive polyimide is used as the dielectric between each high aspect ratio plated structure. Liquid photopolymer enables smaller via capabilities, good coverage between high aspect ratio conductors, good alignment/margin capabilities, is a high reliability material and has a Coefficient of Thermal Expansion (“CTE”) that closely matches copper . Liquid photopolymer can easily fill the gaps between high aspect ratio electroplated structures. According to some embodiments, liquid photopolymer is used to create via entrances down to 0.030 mm. Other dielectrics that may be used include, but are not limited to, KMPR and SU-8.
圖11說明根據一些實施例之使用本文所描述之方法形成的高縱橫比電鍍結構。每一高縱橫比電鍍結構1202包括展示電鍍製程如何發展以形成結構之多個紋理線1204。較薄介電質1206形成於高縱橫比電鍍結構1202之間且安置於高縱橫比電鍍結構1202上。圖12說明根據一些實施例之使用本文所描述之方法形成的高縱橫比電鍍結構1302之透視圖。Figure 11 illustrates a high aspect ratio electroplated structure formed using methods described herein, in accordance with some embodiments. Each high aspect ratio electroplated structure 1202 includes a plurality of texture lines 1204 that illustrate how the electroplating process develops to form the structure. A thinner dielectric 1206 is formed between and disposed on the high aspect ratio plating structures 1202 . Figure 12 illustrates a perspective view of a high aspect ratio electroplated structure 1302 formed using methods described herein, in accordance with some embodiments.
本文所描述之方法可用於形成高縱橫比電鍍結構，其形成高密度精密線圈。圖13a說明根據實施例之使用高縱橫比電鍍結構形成之高密度精密線圈。線圈1402由諸如本文所描述之彼等結構的高縱橫比電鍍結構形成。高密度精密線圈亦包括中心線圈通孔1404。中心線圈通孔1404在本文中所描述之製造步驟期間減小線圈上之電壓降。另外，中心線圈通孔1404使得能夠經由在本文中所描述之各向異性電鍍製程期間對電壓降及電流之較好控制而較好地控制線圈內間距之變化。中心線圈通孔1404亦使得能夠較佳地控制所形成之高密度精密線圈之電壓降。圖13b說明作為如本文中所描述之高密度精密線圈之部分的中心線圈通孔1404之橫截面。The methods described herein can be used to form high aspect ratio electroplated structures that form high density precision coils. Figure 13a illustrates a high density precision coil formed using a high aspect ratio electroplated structure according to an embodiment. Coil 1402 is formed from a high aspect ratio electroplated structure such as those described herein. The high-density precision coil also includes a center coil through hole 1404. Center coil via 1404 reduces voltage drop across the coil during the manufacturing steps described herein. Additionally, center coil via 1404 enables better control of changes in spacing within the coil through better control of voltage drop and current during the anisotropic plating process described herein. The center coil through hole 1404 also enables better control of the voltage drop of the high density precision coil formed. Figure 13b illustrates a cross-section of a center coil through hole 1404 that is part of a high density precision coil as described herein.
圖14說明根據一實施例包括高解析度堆疊導體層的高縱橫比電鍍結構。第一導體層1502a包括使用包括本文所描述之彼等技術之技術形成的高縱橫比電鍍結構1504。使用薄介電製程(使用包括本文所描述之彼等的技術)形成第一介電層1508。第一介電層1508填充在第一導體層1502a之高縱橫比電鍍結構之間的所有空間且在高縱橫比電鍍結構1504上方形成塗層。使用此項技術中已知之技術平面化第一介電層1508。第二導體層1502b包括形成於第一介電層1508之平面化表面上方的高縱橫比電鍍結構1506。使用薄介電製程(使用包括本文所描述之彼等的技術)來形成第二介電層1510，以填充第二導體層1502b之高縱橫比電鍍結構1506之間的所有間隔且用以在高縱橫比電鍍結構1506上方形成塗層。亦可平面化第二介電層1510。可使用本文所描述之技術形成包括高縱橫比電鍍結構之額外層。Figure 14 illustrates a high aspect ratio electroplated structure including high resolution stacked conductor layers according to one embodiment. First conductor layer 1502a includes a high aspect ratio electroplated structure 1504 formed using techniques including those described herein. First dielectric layer 1508 is formed using a thin dielectric process (using techniques including those described herein). The first dielectric layer 1508 fills all spaces between the high aspect ratio plating structures of the first conductor layer 1502a and forms a coating over the high aspect ratio plating structures 1504. The first dielectric layer 1508 is planarized using techniques known in the art. The second conductor layer 1502b includes a high aspect ratio plating structure 1506 formed over the planarized surface of the first dielectric layer 1508. The second dielectric layer 1510 is formed using a thin dielectric process (using techniques including those described herein) to fill all gaps between the high aspect ratio plating structures 1506 of the second conductor layer 1502b and to provide high-aspect ratio plating at high A coating is formed over the aspect ratio plating structure 1506 . The second dielectric layer 1510 may also be planarized. Additional layers including high aspect ratio plated structures can be formed using techniques described herein.
圖15說明根據一實施例之包括高縱橫比電鍍結構之高密度精密線圈，該高縱橫比電鍍結構包括高解析度堆疊導體層。第一導體層1602a包括使用包括本文所描述之彼等技術之技術形成的高縱橫比電鍍結構。使用薄介電製程(使用包括本文中所描述之彼等的技術)來形成第一介電層1608。第一介電層1608填充第一導體層1602a的高縱橫比電鍍結構之間的所有空間，且在高縱橫比電鍍結構上方形成塗層。使用此項技術中已知之技術平面化第一介電層1608。第二導體層1602b包括形成於第一介電層1608之平面化表面上方的高縱橫比電鍍結構。使用薄介電製程(使用包括本文中所描述之彼等的技術)來形成第二介電層1610，以填充第二導體層1602b的高縱橫比電鍍結構之間的所有空間且高縱橫比電鍍結構上方形成塗層。亦可平面化第二介電層1610。可使用本文所描述之技術形成包括高縱橫比電鍍結構之額外層。Figure 15 illustrates a high density precision coil including a high aspect ratio electroplated structure including high resolution stacked conductor layers, according to one embodiment. First conductor layer 1602a includes a high aspect ratio electroplated structure formed using techniques including those described herein. The first dielectric layer 1608 is formed using a thin dielectric process (using techniques including those described herein). The first dielectric layer 1608 fills all spaces between the high aspect ratio plating structures of the first conductor layer 1602a and forms a coating over the high aspect ratio plating structures. The first dielectric layer 1608 is planarized using techniques known in the art. The second conductor layer 1602b includes a high aspect ratio plating structure formed over the planarized surface of the first dielectric layer 1608. Second dielectric layer 1610 is formed using a thin dielectric process (using techniques including those described herein) to fill all spaces between the high aspect ratio plating structures of second conductor layer 1602b and the high aspect ratio plating. A coating forms over the structure. The second dielectric layer 1610 may also be planarized. Additional layers including high aspect ratio plated structures can be formed using techniques described herein.
形成高密度精密線圈以具有在第一導體層1602a之高縱橫比電鍍結構與第二導體層1602b之高縱橫比電鍍結構之間的第一距離1614。對於各種實施例，第一距離1614小於0.020毫米。對於另一實施例，第一距離1614為0.010毫米。形成高密度精密線圈以具有在第二介電層1610之表面1618與第一導體層1602a之高縱橫比電鍍結構之間的第二距離1616。對於各種實施例，第二距離1616小於0.010毫米。對於一些實施例，第二距離1616為0.005毫米。對於一些實施例，第二距離1616可為起始間隙減去最終所要間隙除以2。形成高密度精密線圈以具有第一導體層1602a之高縱橫比電鍍結構與第一介電層1622之表面之間的第三距離1620。對於各種實施例，第三距離1620小於0.020毫米。對於一些實施例，第三距離1620小於0.015毫米。對於另一實施例，第三距離1620為0.010毫米。對於各種實施例，使用包括本文中所描述之彼等的技術將第一介電層形成於基板1624上。對於一些實施例，基板1624為不鏽鋼層。熟習此項技術者應理解，基板1624可用其他材料形成，包括但不限於鋼合金、銅合金(諸如青銅、純銅、鎳合金、鈹銅合金)及包括此項技術中已知之彼等金屬的其他金屬。The high density precision coil is formed to have a first distance 1614 between the high aspect ratio plating structure of the first conductor layer 1602a and the high aspect ratio plating structure of the second conductor layer 1602b. For various embodiments, first distance 1614 is less than 0.020 millimeters. For another embodiment, first distance 1614 is 0.010 mm. The high density precision coil is formed to have a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high aspect ratio plating structure of the first conductor layer 1602a. For various embodiments, the second distance 1616 is less than 0.010 mm. For some embodiments, the second distance 1616 is 0.005 millimeters. For some embodiments, the second distance 1616 may be the starting gap minus the final desired gap divided by two. The high density precision coil is formed to have a third distance 1620 between the high aspect ratio plating structure of the first conductor layer 1602a and the surface of the first dielectric layer 1622. For various embodiments, the third distance 1620 is less than 0.020 millimeters. For some embodiments, third distance 1620 is less than 0.015 mm. For another embodiment, the third distance 1620 is 0.010 mm. For various embodiments, a first dielectric layer is formed on substrate 1624 using techniques including those described herein. For some embodiments, substrate 1624 is a layer of stainless steel. Those skilled in the art will appreciate that the substrate 1624 may be formed of other materials, including but not limited to steel alloys, copper alloys (such as bronze, pure copper, nickel alloys, beryllium copper alloys), and other metals including those known in the art. metal.
使用如本文所描述的高縱橫比電鍍結構形成裝置之其他優點包括具有高結構強度、高可靠性及高散熱量之裝置。經由在裝置之所有層上形成極密集濃度之金屬高縱橫比電鍍結構之能力提供高結構強度。另外，用於形成本文中所描述之金屬高縱橫比電鍍結構的製程提供層與層之間的結構橫向對準，從而增加高結構強度。使用用於形成本文所描述之金屬高縱橫比電鍍結構之製程形成的裝置之高結構強度亦為介電層材料(諸如感光聚醯亞胺層)對結構之良好黏著力的結果。對於一些實施例，用非磁性鎳層塗佈使用本文所描述之技術形成的高縱橫比電鍍結構以提高介電層之黏著力。此將進一步增加使用本文所描述之高縱橫比電鍍結構形成之最終裝置的高結構強度。Other advantages of using high aspect ratio electroplated structure forming devices as described herein include devices with high structural strength, high reliability, and high heat dissipation. High structural strength is provided through the ability to form extremely dense concentrations of metal high aspect ratio electroplated structures on all layers of the device. Additionally, the processes used to form the metallic high aspect ratio electroplated structures described herein provide structural lateral alignment between layers, thereby adding high structural strength. The high structural strength of devices formed using the processes used to form the metal high aspect ratio electroplated structures described herein is also a result of the good adhesion of the dielectric layer material, such as the photosensitive polyimide layer, to the structure. For some embodiments, high aspect ratio plated structures formed using techniques described herein are coated with a non-magnetic nickel layer to improve adhesion of the dielectric layer. This will further increase the high structural strength of the final device formed using the high aspect ratio electroplated structures described herein.
使用本文中所描述的高縱橫比電鍍結構形成的裝置之可靠性亦較高，此係由於使用提供穩固電氣性能的高可靠性材料，諸如用於介電層之感光聚醯亞胺。使用本文中所描述之技術提供以較少介電材料形成裝置且減少所形成裝置之總厚度的能力。因此，經由使用當前製程技術增加裝置上方之導熱性來增加散熱。Devices formed using the high aspect ratio electroplated structures described herein also have higher reliability due to the use of high reliability materials that provide robust electrical properties, such as photosensitive polyimide for the dielectric layer. Use of the techniques described herein provides the ability to form devices with less dielectric material and reduce the overall thickness of the formed devices. Therefore, heat dissipation is increased by using current process technology to increase thermal conductivity above the device.
圖16a-c說明根據另一實施例之用於形成高縱橫比電鍍結構的製程。圖16a說明使用消減蝕刻形成於基板1804上之跡線1802。根據一些實施例，金屬層形成於基板1804上方。使用包括此項技術中已知之彼等之技術在金屬層上方形成光阻層。對於一些實施例，光阻層為以液態形式沉積於金屬層上方的感光聚醯亞胺。使用包括此項技術中已知之彼等的技術來圖案化及顯影光阻。隨後使用包括此項技術中已知之的技術蝕刻金屬層。在蝕刻製程之後，形成跡線1802。Figures 16a-c illustrate a process for forming high aspect ratio electroplated structures according to another embodiment. Figure 16a illustrates traces 1802 formed on a substrate 1804 using subtractive etching. According to some embodiments, a metal layer is formed over substrate 1804. A photoresist layer is formed over the metal layer using techniques including those known in the art. For some embodiments, the photoresist layer is a photosensitive polyimide deposited in a liquid form over the metal layer. The photoresist is patterned and developed using techniques including those known in the art. The metal layer is then etched using techniques including those known in the art. After the etching process, traces 1802 are formed.
圖16b說明使用保形鍍覆製程(諸如本文中所描述之彼等製程)形成高縱橫比電鍍結構。圖16c說明使用頂部鍍覆製程(諸如本文中所描述之彼等製程) 形成高縱橫比電鍍結構。對於各種實施例，在不使用保形鍍覆製程(諸如參看圖16b所描述者)的情況下形成高縱橫比的電鍍結構。實情為，在形成如圖16a中所說明之跡線1802之後使用頂部鍍覆製程，諸如參看圖16c描述者。Figure 16b illustrates the use of a conformal plating process, such as those described herein, to form a high aspect ratio plated structure. Figure 16c illustrates the use of a top plating process, such as those described herein, to form a high aspect ratio plated structure. For various embodiments, high aspect ratio plated structures are formed without using a conformal plating process, such as that described with reference to Figure 16b. Instead, a top plating process, such as that described with reference to Figure 16c, is used after forming trace 1802 as illustrated in Figure 16a.
圖17說明根據一實施例選擇性形成高縱橫比電鍍結構。一旦使用包括本文中所描述之彼等的技術形成跡線1902，則光阻層1904形成於所形成跡線1902中之一或多者之區段上方。光阻層1904可為感光聚醯亞胺，且使用包括本文中所描述之彼等的技術來沉積及形成該光阻層1904。使用如本文中所描述之保形鍍覆製程及頂部鍍覆製程中之一者或兩者在跡線1902上形成金屬頂部1906。圖18說明根據一實施例以選擇性地形成於跡線上之金屬頂部部分形成之高縱橫比電鍍結構的透視圖。根據一些實施例，在跡線上選擇性形成金屬頂部部分用於改良高縱橫比電鍍結構之結構特性、改良高縱橫比電鍍結構之電氣性能、改良熱傳遞特性且符合使用高縱橫比電鍍結構形成之裝置的定製尺寸需求。電氣性能改良之實例包括但不限於高縱橫比電鍍結構之電容、電感及電阻特性。此外，在跡線上選擇性形成金屬頂部部分可用於調節使用高縱橫比電鍍結構形成之電路之機械或電學特性。Figure 17 illustrates the selective formation of high aspect ratio electroplated structures according to one embodiment. Once the traces 1902 are formed using techniques including those described herein, a photoresist layer 1904 is formed over a section of one or more of the formed traces 1902 . Photoresist layer 1904 may be photosensitive polyimide and is deposited and formed using techniques including those described herein. Metal top 1906 is formed on trace 1902 using one or both of a conformal plating process and a top plating process as described herein. Figure 18 illustrates a perspective view of a high aspect ratio electroplated structure formed with metal top portions selectively formed on traces, according to one embodiment. According to some embodiments, selectively forming metal top portions on traces is used to improve the structural properties of high aspect ratio electroplated structures, improve the electrical properties of high aspect ratio electroplated structures, improve heat transfer characteristics and is consistent with the use of high aspect ratio electroplated structures formed. Custom size requirements for the device. Examples of electrical performance improvements include, but are not limited to, capacitive, inductive and resistive characteristics of high aspect ratio electroplated structures. Additionally, the selective formation of metal top portions on traces can be used to tune the mechanical or electrical properties of circuits formed using high aspect ratio electroplated structures.
圖19說明包括根據一實施例之使用如本文所描述之選擇性形成所形成的高縱橫比電鍍結構之硬碟驅動機懸掛件撓曲件2102。圖20說明沿著線A-A截取的圖19中所說明之硬碟驅動機懸掛件撓曲件之橫截面圖。撓曲件2102之橫截面包括高縱橫比電鍍結構2104及跡線2106。使用如本文所描述之選擇性形成技術形成高縱橫比電鍍結構2104。形成高縱橫比電鍍結構2104以用作撓曲件之預定區域中之導體可達成DC電阻之減小。此允許撓曲件上所需之細線及間隔，同時滿足對DC電阻之設計需求且改良撓曲件之電氣性能。Figure 19 illustrates a hard drive suspension flexure 2102 including a high aspect ratio electroplated structure formed using selective formation as described herein, according to one embodiment. Figure 20 illustrates a cross-sectional view of the hard drive suspension flexure illustrated in Figure 19, taken along line A-A. The cross-section of flexure 2102 includes high aspect ratio plating structures 2104 and traces 2106. High aspect ratio plated structure 2104 is formed using selective formation techniques as described herein. Forming high aspect ratio plating structures 2104 to serve as conductors in predetermined areas of the flexure may achieve a reduction in DC resistance. This allows for the thinnest lines and spacing required on the flexure while meeting design requirements for DC resistance and improving the electrical performance of the flexure.
圖21a、圖21b說明一種用於在保形鍍覆製程期間使用光阻形成根據一實施例的高縱橫比電鍍結構之製程。圖21a說明使用包括本文中所描述之彼等之技術形成於基板2304上之跡線2302。圖21b說明使用如本文所描述之鍍覆製程形成高縱橫比電鍍結構。使用包括本文中所描述之彼等者的沉積及圖案化技術在基板2304上方形成光阻部分2306。一旦光阻部分2306形成於保形鍍覆製程中之一者或兩者，執行頂部鍍覆製程以在跡線2302上形成金屬部分2308。可使用光阻部分2306較佳地界定高縱橫比電鍍結構之間的間距。21a, 21b illustrate a process for using photoresist to form a high aspect ratio electroplated structure according to an embodiment during a conformal plating process. Figure 21a illustrates traces 2302 formed on a substrate 2304 using techniques including those described herein. Figure 21b illustrates the formation of a high aspect ratio plated structure using a plating process as described herein. Photoresist portion 2306 is formed over substrate 2304 using deposition and patterning techniques including those described herein. Once photoresist portion 2306 is formed in one or both of the conformal plating processes, a top plating process is performed to form metal portion 2308 on trace 2302 . Photoresist portions 2306 may be used to better define spacing between high aspect ratio plated structures.
圖22說明根據各種實施例之用於形成初始金屬層之製程、標準/保形鍍覆製程及頂部鍍覆製程之例示性化學物質。Figure 22 illustrates exemplary chemistries for processes used to form an initial metal layer, a standard/conformal plating process, and a top plating process, according to various embodiments.
圖23說明由具有積體調諧電容器之根據一實施例之高縱橫比電鍍結構2504形成的電感耦合線圈2502之頂面2501的透視圖。與使用電流技術形成線圈之電感耦合線圈相比較，使用高縱橫比電鍍結構形成電感耦合線圈減小電感耦合線圈之佔據面積。此使得電感耦合線圈2502能夠用於空間受到限制之應用中。另外，整合於電感耦合線圈中電容器之使用進一步減小電感耦合線圈之佔據面積，此係因為不需要額外空間要求來容納諸如表面安裝技術(「SMT」)電容器之離散電容器。Figure 23 illustrates a perspective view of the top surface 2501 of an inductively coupled coil 2502 formed from a high aspect ratio plated structure 2504 with integrated tuning capacitors according to one embodiment. Compared with inductive coupling coils that use galvanic technology to form coils, using high aspect ratio electroplating structures to form inductive coupling coils reduces the area occupied by the inductive coupling coils. This enables the inductively coupled coil 2502 to be used in applications where space is limited. Additionally, the use of capacitors integrated into the inductive coupling coil further reduces the area occupied by the inductive coupling coil because no additional space requirements are required to accommodate discrete capacitors such as surface mount technology ("SMT") capacitors.
圖24說明圖23中所說明之電感耦合線圈2502之實施例的背面2604的透視圖。圖25說明與射頻識別(「RFID」)晶片2704耦接根據一實施例之電感耦合線圈2502之頂面的透視圖。Figure 24 illustrates a perspective view of the backside 2604 of the embodiment of the inductively coupled coil 2502 illustrated in Figure 23. Figure 25 illustrates a perspective view of the top surface of an inductive coupling coil 2502 coupled to a radio frequency identification ("RFID") chip 2704 according to one embodiment.
圖26a-j說明形成電感耦合線圈2502之方法，該電感耦合線圈2502由根據一實施例之高縱橫比電鍍結構2504形成。根據各種實施例，電感耦合線圈包括積體調諧電容器。圖26a說明使用包含此項技術中已知之彼等之技術形成的基板2802。對於一些實施例，基板2802由不鏽鋼形成。可用於基板之其他材料包括但不限於鋼合金、銅、銅合金、鋁、可使用包括電漿氣相沉積、化學氣相沉積及無電極化學沉積之技術金屬化的非導體材料。將遮蔽罩2804形成於基板2802上方。根據一些實施例，遮蔽罩2804為高K介電質。可使用之高K介電質之實例包括但不限於二氧化鈦(TiO2)、氧化鈮(Nb2O5)、氧化鉭(TaO)、氧化鋁(Al2O3)、二氧化矽(SiO2)、聚醯亞胺、SU-8、KMPR及其他高電容率介電材料。根據一些實施例，使用濺鍍製程使用包括此項技術中已知之技術的技術來形成遮蔽罩2804。對於一些實施例，遮蔽罩2804經形成以具有介於500至1000埃之範圍內的厚度。對於其他實施例，使用高電容率墨水之網版印刷來形成遮蔽罩2804。高電容率油墨之實例包括油墨，該油墨包括負載有由二氧化鈦(TiO2)、氧化鈮(Nb2O5)、氧化鉭(TaO)、氧化鋁(Al2O3)、二氧化矽(SiO2)、聚醯亞胺及其他高電容率介電材料中之一或多者製成之粒子的環氧樹脂。對於其他實施例，使用摻雜有高K填充劑之可光成像介電質之槽模應用來形成遮蔽罩2804。高K填充劑之實例包括二氧化鋯(ZrO2)。26a-j illustrate a method of forming an inductive coupling coil 2502 formed from a high aspect ratio electroplated structure 2504 according to an embodiment. According to various embodiments, the inductive coupling coil includes an integral tuning capacitor. Figure 26a illustrates a substrate 2802 formed using techniques including those known in the art. For some embodiments, substrate 2802 is formed from stainless steel. Other materials that may be used for the substrate include, but are not limited to, steel alloys, copper, copper alloys, aluminum, non-conductive materials that may be metallized using techniques including plasma vapor deposition, chemical vapor deposition, and electrodeless chemical deposition. A shielding cover 2804 is formed above the substrate 2802. According to some embodiments, shield 2804 is a high-K dielectric. Examples of high-K dielectrics that can be used include, but are not limited to, titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU -8. KMPR and other high permittivity dielectric materials. According to some embodiments, mask 2804 is formed using a sputtering process using techniques including those known in the art. For some embodiments, mask 2804 is formed to have a thickness in the range of 500 to 1000 Angstroms. For other embodiments, mask 2804 is formed using screen printing of high permittivity ink. Examples of high permittivity inks include inks containing materials loaded with titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and Epoxy resin with particles made of one or more other high permittivity dielectric materials. For other embodiments, mask 2804 is formed using slot die application of a photoimageable dielectric doped with a high-K filler. Examples of high-K fillers include zirconium dioxide (ZrO2).
圖26b說明形成於遮蔽罩2804上方之金屬性電容板2806。金屬電容板2806及基板2802形成積體電容器之兩個電容板。可使用遮蔽罩2804之厚度來設定積體電容器之有效電容。另外，用以形成遮蔽罩2804之高K介電質的純度可用以設定積體電容器之有效電容。金屬電容板2806之表面積亦可用以設定積體電容器之有效電容。Figure 26b illustrates a metallic capacitor plate 2806 formed over the shield 2804. The metal capacitor plate 2806 and the substrate 2802 form two capacitor plates of the integrated capacitor. The thickness of shield 2804 can be used to set the effective capacitance of the integrated capacitor. Additionally, the purity of the high-K dielectric used to form shield 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of the metal capacitor plate 2806 can also be used to set the effective capacitance of the integrated capacitor.
圖26c說明形成於遮蔽罩2804、金屬電容板2806及基板2802之至少一部分上方之基礎介電層2808。根據一些實施例，基礎介電層2808係藉由沉積介電材料、圖案化介電材料以及使用包含此項技術中已知技術的技術固化介電材料來形成。可使用之介電材料之實例包括但不限於聚醯亞胺、SU-8、KMPR及硬烘烤光阻，諸如由IBM®出售之硬烘烤光阻。基礎介電層2808亦可經圖案化或蝕刻以形成通孔。舉例而言，跨接通孔2812及分路電容器通孔2810形成於基礎介電層2808中。分路電容器通孔2810經形成以將積體電容器互連至待形成之電路之剩餘部分。類似地，跨接通孔2812用以將待形成的電路元件互連至基板2802。Figure 26c illustrates a base dielectric layer 2808 formed over the mask 2804, the metal capacitor plate 2806, and at least a portion of the substrate 2802. According to some embodiments, base dielectric layer 2808 is formed by depositing dielectric material, patterning the dielectric material, and curing the dielectric material using techniques including those known in the art. Examples of dielectric materials that may be used include, but are not limited to, polyimide, SU-8, KMPR, and hard-bake photoresists, such as those sold by IBM®. Base dielectric layer 2808 may also be patterned or etched to form vias. For example, crossover vias 2812 and shunt capacitor vias 2810 are formed in base dielectric layer 2808 . Shunt capacitor vias 2810 are formed to interconnect the integrated capacitor to the remainder of the circuit to be formed. Similarly, crossover vias 2812 are used to interconnect circuit elements to be formed to substrate 2802.
圖26d說明使用高縱橫比電鍍結構形成於基礎介電層2808上方之線圈2814，以形成使用包括本文中所描述之彼等之技術的線圈。對於一些實施例，線圈2814為單層線圈。線圈2814包括連接至分路電容器通孔2810中之一者及與積體電容器之金屬電容板2806電接觸的跨接通孔2812中之一者的中心連接部分2816。線圈2814亦包括電容器連接部分2818以將線圈2814連接至分路電容器通孔2810中之另一者，該分路電容器通孔與經組態為積體電容器之下部板的基板2802電接觸。根據各種實施例，終端墊使用包括本文中所描述之彼等的技術由高縱橫比電鍍結構形成終端墊2820。可在與用於形成線圈2814的相同製程期間形成終端墊2820。Figure 26d illustrates a coil 2814 formed over a base dielectric layer 2808 using a high aspect ratio plating structure to form a coil using techniques including those described herein. For some embodiments, coil 2814 is a single layer coil. The coil 2814 includes a central connection portion 2816 connected to one of the shunt capacitor vias 2810 and one of the crossover vias 2812 in electrical contact with the metal capacitor plate 2806 of the integrated capacitor. The coil 2814 also includes a capacitor connection portion 2818 to connect the coil 2814 to another of the shunt capacitor vias 2810 that are in electrical contact with the substrate 2802 configured as a lower plate of the integrated capacitor. According to various embodiments, terminal pads 2820 are formed from high aspect ratio plating structures using techniques including those described herein. Terminal pad 2820 may be formed during the same process used to form coil 2814.
圖26e說明形成於線圈2814、終端墊2820及基礎介電層2808上方以包覆電感耦合線圈之線圈側的面層(covercoat) 2822。使用沉積、蝕刻及圖案化步驟(包括此項技術中已知之彼等步驟)形成面層2822。舉例而言，面層2822可由聚醯亞胺阻焊劑、SU-8、KMPR或環氧樹脂形成。Figure 26e illustrates a covercoat 2822 formed over the coil 2814, terminal pad 2820, and base dielectric layer 2808 to cover the coil side of the inductively coupled coil. Top layer 2822 is formed using deposition, etching, and patterning steps, including those known in the art. For example, the surface layer 2822 may be formed of polyimide solder resist, SU-8, KMPR, or epoxy resin.
圖26f說明根據一實施例形成的電感耦合線圈之背面。將至少第一焊接墊2824及第二焊接墊2826形成於基板2802與線圈2814相反之側上。根據一些實施例，使用包含此項技術中已知的彼等的沉積及圖案化技術由金形成第一焊接墊2824及第二焊接墊2826。形成第一焊接墊2824及第二焊接墊2826以提供用於將諸如RFID晶片之積體電路晶片附接至基板2802的電接點。Figure 26f illustrates the backside of an inductively coupled coil formed in accordance with an embodiment. At least a first bonding pad 2824 and a second bonding pad 2826 are formed on the side of the substrate 2802 opposite the coil 2814 . According to some embodiments, first bonding pad 2824 and second bonding pad 2826 are formed from gold using deposition and patterning techniques including those known in the art. First bonding pad 2824 and second bonding pad 2826 are formed to provide electrical contacts for attaching an integrated circuit chip, such as an RFID chip, to substrate 2802 .
圖26g說明根據一實施例形成之形成於感應耦合線圈之背面上的背面介電層2828。形成電感耦合線圈之方法可視情況包括在基板2802上形成背面介電層2828。使用類似於形成基礎介電層2808之彼等技術的技術形成背面介電層2828。根據一些實施例，背面介電層2828經圖案化以防止基板2802與所附接積體電路晶片之間的短路。根據各種實施例，背面介電層2828經圖案化以提供給待蝕刻基板2802跨接圖案2830以在後續步驟中形成跨接路徑。背面介電質中之其他圖案可經形成以亦蝕刻基板2802之其他部分。Figure 26g illustrates a backside dielectric layer 2828 formed on the backside of an inductive coupling coil formed in accordance with an embodiment. The method of forming the inductively coupled coil optionally includes forming a back dielectric layer 2828 on the substrate 2802. Backside dielectric layer 2828 is formed using techniques similar to those used to form base dielectric layer 2808 . According to some embodiments, the backside dielectric layer 2828 is patterned to prevent shorts between the substrate 2802 and the attached integrated circuit die. According to various embodiments, the backside dielectric layer 2828 is patterned to provide the substrate to be etched 2802 with a crossover pattern 2830 to form crossover paths in subsequent steps. Other patterns in the backside dielectric can be formed to also etch other portions of substrate 2802.
圖26h說明根據一實施例形成為其最終形狀之電感耦合線圈2834。蝕刻基板2802未由背面介電層2828覆蓋之部分。此經蝕刻之部分包括跨接圖案2830以形成跨接路徑2832。使用包括此項技術中已知之技術的技術進行蝕刻。熟習此項技術者將理解，基板2802之其他部分可經蝕刻以形成類似於跨接路徑2832之其他導電路徑。圖26i說明根據一實施例之包括跨接路徑2832之電感耦合線圈2834之線圈側。Figure 26h illustrates inductive coupling coil 2834 formed into its final shape according to one embodiment. The portion of substrate 2802 not covered by backside dielectric layer 2828 is etched. This etched portion includes a crossover pattern 2830 to form a crossover path 2832. The etching is performed using techniques including those known in the art. Those skilled in the art will appreciate that other portions of substrate 2802 may be etched to form other conductive paths similar to crossover path 2832. Figure 26i illustrates the coil side of an inductively coupled coil 2834 including a crossover path 2832, according to one embodiment.
圖26j說明根據一實施例之電感耦合線圈2834之線圈側，其包括附接至電感線圈之背面的積體晶片2836。用於形成電感耦合線圈2834之方法可視情況包括使用包括此項技術中已知之彼等技術的技術將積體晶片2836(諸如RFID晶片)附接至電感耦合線圈2834的步驟。使用包括但不限於導電環氧樹脂、焊料及用以連接電連接件之其他材料的黏著劑來附接此積體晶片2836。Figure 26j illustrates the coil side of an inductively coupled coil 2834 including an integrated die 2836 attached to the backside of the inductive coil, according to one embodiment. The method for forming the inductively coupled coil 2834 may optionally include the step of attaching an integrated die 2836 (such as an RFID die) to the inductively coupled coil 2834 using techniques including those known in the art. The integrated chip 2836 is attached using adhesives including, but not limited to, conductive epoxy, solder, and other materials used to connect electrical connections.
電容器整合至包括高縱橫比電鍍結構之裝置中能夠利用藉由使用高縱橫比電鍍結構實現之較小佔據面積需求。電感耦合線圈之其他實施例包括具有多個積體電容器之電感耦合線圈。如此項技術中已知，積體電容器可並聯或串聯連接。包括高縱橫比電鍍結構的其他裝置(亦可包括積體電容器)包括但不限於降壓式變壓器(buck transform)、信號調節裝置、調諧裝置及將包括一或多個電感器及一或多個電容器之其他裝置。Integrating capacitors into devices that include high aspect ratio plating structures can take advantage of the smaller footprint requirements achieved by using high aspect ratio plating structures. Other embodiments of inductively coupled coils include inductively coupled coils with multiple integrated capacitors. As is known in the art, integrated capacitors can be connected in parallel or in series. Other devices including high aspect ratio plating structures (which may also include integrated capacitors) include but are not limited to buck transformers, signal conditioning devices, tuning devices and will include one or more inductors and one or more Capacitors and other devices.
根據本文所描述之實施例的高縱橫比電鍍結構可用於形成裝置或形成裝置之部分，以最佳化性能且達成小佔據面積。此類裝置包括但不限於功率轉換器(例如，降壓式變壓器、分壓器、AC變壓器)、致動器(例如，線性、VCM)、天線(例如，RFID、用於電池充電之無線功率轉移及安全晶片)、無線被動線圈、蜂巢式電話及能再充電之醫療裝置電池、鄰近感測器、壓力感測器、非接觸式連接器、微型馬達、微型流體元件、封裝上之冷卻/散熱器、具有空氣芯電容及電感之長窄型可撓性電路(例如用於導管)、叉指形聲波換能器、觸感振動器、可植入裝置(例如起搏器、刺激器、骨生長裝置)、用於程序(例如食道、結腸鏡檢查)之磁共振成像(「MRI」)裝置、 超觸感(例如，服裝、手套)、經塗佈以用於偵測/過濾器釋放之表面、安全系統、高能量密度電池、感應加熱裝置(用於小局部區域)、用於經由通道脈衝之流體/藥物分散及劑量遞送之磁場、追蹤及資訊裝置(例如，農業、食品、貴重物品)、***安全、聲波系統(例如，揚聲器線圈、耳機中之再充電機構、耳塞)、熱傳遞、機械導熱密封件、能量收集器及互鎖成形件(類似於卡鉤及環圈扣件)。另外，如本文中所描述的高縱橫比電鍍結構可用以形成高頻寬、低阻抗互連件。在互連件中使用高縱橫比電鍍結構可用於改良電特徵(例如，電阻、電感、電容)、改良熱傳遞特性且定製尺寸要求(厚度控制)。包括如本文所描述的高縱橫比電鍍結構之互連件可用以針對既定頻率範圍調諧一或多個電路之頻寬。包括高縱橫比電鍍結構之其他互連件應用可整合不同電流 (例如，信號及功率)之一或多個電路。使用高縱橫比電鍍結構允許具有不同橫截面之電路，允許一些具有較多載流容量，以緊密接近地一起製造以維持經濃縮之整體封裝大小。出於機械目的，高縱橫比電鍍結構亦可用於互連件中。舉例而言，可能需要使電路之一些區域在其他區域上方凸起以充當機械止擋件、軸承、電接點區域或用於額外硬度。High aspect ratio electroplated structures according to embodiments described herein may be used to form devices or form portions of devices to optimize performance and achieve a small footprint. Such devices include, but are not limited to, power converters (e.g., step-down transformers, voltage dividers, AC transformers), actuators (e.g., linear, VCM), antennas (e.g., RFID, wireless power for battery charging) transfer and security chips), wireless passive coils, cellular phones and rechargeable medical device batteries, proximity sensors, pressure sensors, contactless connectors, micromotors, microfluidic components, on-package cooling/ Heat sinks, long narrow flexible circuits with air core capacitors and inductors (e.g. for catheters), interdigital acoustic transducers, tactile vibrators, implantable devices (e.g. pacemakers, stimulators, bone growth devices), magnetic resonance imaging ("MRI") devices for procedures (e.g., esophageal, colonoscopies), ultra-tactile (e.g., garments, gloves), coated for detection/filter release surfaces, safety systems, high energy density batteries, induction heating devices (for small localized areas), magnetic fields for fluid/drug dispersion and dose delivery via channel pulses, tracking and information devices (e.g., agricultural, food, precious items), credit card security, sonic systems (e.g., speaker coils, recharging mechanisms in headphones, earbuds), heat transfer, mechanical thermal seals, energy collectors, and interlocking moldings (similar to hook and loop fasteners ). Additionally, high aspect ratio electroplated structures as described herein can be used to form high bandwidth, low impedance interconnects. The use of high aspect ratio plating structures in interconnects can be used to improve electrical characteristics (eg, resistance, inductance, capacitance), improve heat transfer characteristics, and tailor dimensional requirements (thickness control). Interconnects including high aspect ratio plating structures as described herein can be used to tune the bandwidth of one or more circuits for a given frequency range. Other interconnect applications including high aspect ratio plating structures can integrate one or more circuits with different currents (e.g., signal and power). The use of high aspect ratio plating structures allows circuits with different cross-sections, some with greater current carrying capacity, to be fabricated in close proximity to maintain a condensed overall package size. High aspect ratio plated structures may also be used in interconnects for mechanical purposes. For example, it may be desirable to have some areas of the circuit raised above other areas to act as mechanical stops, bearings, electrical contact areas, or for additional stiffness.
圖27說明包括根據一實施例之高縱橫比電鍍結構之硬碟驅動機的懸掛件之撓曲件的平面圖。撓曲件2900包括遠端部分2901、環架部分2902、中間部分2904、間隙部分2906及近端部分2908。近端部分2908經組態以附接至底板以使得遠端部分2901在旋轉磁碟媒體上方延伸。根據一些實施例，環架部分2902經組態以包括一或多個馬達，諸如壓電馬達，及一或多個電組件，諸如用於讀取或寫入至磁碟媒體之磁頭浮動塊，及用於熱輔助式磁性記錄(「HAMR」)/熱輔助磁性記錄(「TAMR」)或微波輔助式磁性記錄(「MAMR」)之組件。一或多個馬達及一或多個電組件經由形成於撓曲件之導體層上之一或多個跡線電連接至其他電路，該撓曲件在間隙部分2906上自撓曲件2900之遠端部分2901延伸經過中間部分2904且超出近端部分2908。間隙部分2906為撓曲件之一部分，其中諸如不鏽鋼層之基板層經部分完全移除。因此，撓曲件之導體層中的跡線中之一或多者在無任何支撐件之情況下在間隙部分2906上方延伸。熟習此項技術者將理解，撓曲件可在沿著撓曲件之任何位置處具有一或多個間隙部分2906。27 illustrates a plan view of a flexure of a suspension for a hard disk drive including a high aspect ratio plating structure according to one embodiment. Flexure 2900 includes a distal portion 2901, a ring portion 2902, a middle portion 2904, a gap portion 2906, and a proximal portion 2908. Proximal portion 2908 is configured to attach to the base plate such that distal portion 2901 extends over rotating disk media. According to some embodiments, ring frame portion 2902 is configured to include one or more motors, such as piezoelectric motors, and one or more electrical components, such as a head slider for reading or writing to disk media, and components for heat-assisted magnetic recording (“HAMR”)/heat-assisted magnetic recording (“TAMR”) or microwave-assisted magnetic recording (“MAMR”). One or more motors and one or more electrical components are electrically connected to other circuits via one or more traces formed on the conductor layer of the flexure that separates from the flexure 2900 on gap portion 2906 Distal portion 2901 extends through intermediate portion 2904 and beyond proximal portion 2908. Gap portion 2906 is a portion of the flexure in which a substrate layer, such as a stainless steel layer, is partially completely removed. Therefore, one or more of the traces in the conductor layer of the flexure extend over gap portion 2906 without any support. Those skilled in the art will understand that the flexure may have one or more gap portions 2906 anywhere along the flexure.
圖28說明間隙部分處之撓曲件之間隙部分的橫截面，其沿著如圖27中所說明之線A截取。間隙部分2906包括安置於介電層3004上方之跡線3002。諸如聚醯亞胺層之介電層安置於諸如不鏽鋼層之基板3006上方。基板3006以及介電層3004界定空隙3008，使得跡線3002在空隙3008上方延伸。跡線3002包括金屬頂部部分以形成高縱橫比結構。使用本文中所描述之技術，金屬頂部部分選擇性地形成於跡線3002上。金屬頂部部分形成於跡線3002上以提供跨越空隙3008之額外強度，且當使用時用以與空隙3008之區域處之互連件電耦接。Figure 28 illustrates a cross-section of the gap portion of the flexure at the gap portion, taken along line A as illustrated in Figure 27. Gap portion 2906 includes trace 3002 disposed over dielectric layer 3004 . A dielectric layer, such as a polyimide layer, is disposed over the substrate 3006, such as a stainless steel layer. Substrate 3006 and dielectric layer 3004 define void 3008 such that trace 3002 extends over void 3008. Trace 3002 includes a metal top portion to form a high aspect ratio structure. Metal top portions are selectively formed on trace 3002 using techniques described herein. A metal top portion is formed on trace 3002 to provide additional strength across void 3008 and, when used, to electrically couple to the interconnect in the area of void 3008.
圖29說明根據一實施例之具有質量結構3102之環架部分2902。使用本文所描述之技術使用高縱橫比電鍍結構形成質量結構3102。對於一些實施例，質量結構3102用作平衡塊以調諧環架部分2902之共振。因此，質量結構3102之形狀、大小及部位可經判定以調諧環架部分2902之共振以增強硬碟驅動機懸掛件之性能。本文中所描述之用以形成高縱橫比結構之製程可用以維持高縱橫比結構之大小，使得可精細調諧共振。此外，製程能夠在超出當前微影製程之能力的尺寸下形成高縱橫比結構，從而實現對所形成之最終結構的更多控制。Figure 29 illustrates a ring frame portion 2902 with a mass structure 3102, according to one embodiment. Mass structure 3102 is formed using high aspect ratio electroplated structures using techniques described herein. For some embodiments, mass structure 3102 serves as a counterweight to tune the resonance of ring frame portion 2902. Accordingly, the shape, size, and location of the mass structure 3102 can be determined to tune the resonance of the ring frame portion 2902 to enhance the performance of the hard drive suspension. The processes described herein for forming high aspect ratio structures can be used to maintain the size of the high aspect ratio structures so that the resonance can be finely tuned. In addition, the process can form high aspect ratio structures at dimensions beyond the capabilities of current lithography processes, allowing for more control over the final structure formed.
質量結構3102亦可經組態以用作機械止擋件。舉例而言，一或多個機械止擋件可形成為任何形狀以充當反向止擋件及/或用以在環架部分2902或撓曲件之其他部分上對準組件之安裝。Mass structure 3102 may also be configured to act as a mechanical stop. For example, one or more mechanical stops may be formed in any shape to serve as counter stops and/or to align the mounting of components on the ring frame portion 2902 or other portions of the flexure.
圖30說明包括根據一實施例之高縱橫比電鍍結構之撓曲件的近端部分的橫截面，其沿著如圖27中所說明之線B截取。近端部分2904包括安置於介電層3004上方之包括跡線3002a、3002b、3002c、3002d之導體層。介電層3004安置於基板3006上方。覆蓋層3001安置於導體層及介電層上方。導體層包括習知跡線3002a、3002b及跡線3002c、300d，該等跡線用包括金屬頂部部分3202a、3202b之跡線之至少一部分形成以使用本文所描述之技術形成高縱橫比電鍍結構。跡線3002a、3002b、3002c、3002d之一或多個部分可經形成以包括金屬頂部部分3202a、3202b以調諧每一跡線之阻抗。舉例而言，可視需要調諧跡線之電阻以符合所要性能特徵。另一實例包括使用金屬頂部部分以藉由閉合鄰接跡線3002a、3002b、3002c、3002d之間的距離來調諧阻抗。30 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio electroplated structure according to one embodiment, taken along line B as illustrated in FIG. 27 . Proximal portion 2904 includes a conductor layer disposed over dielectric layer 3004 including traces 3002a, 3002b, 3002c, 3002d. A dielectric layer 3004 is disposed over the substrate 3006. Covering layer 3001 is disposed over the conductor layer and dielectric layer. The conductor layer includes conventional traces 3002a, 3002b and traces 3002c, 300d formed with at least a portion of the traces including metal top portions 3202a, 3202b to form high aspect ratio plated structures using techniques described herein. One or more portions of traces 3002a, 3002b, 3002c, 3002d may be formed to include metal top portions 3202a, 3202b to tune the impedance of each trace. For example, the resistance of the traces may be tuned as needed to meet the desired performance characteristics. Another example includes using a metal top portion to tune impedance by closing the distance between adjacent traces 3002a, 3002b, 3002c, 3002d.
圖31說明包括根據一實施例之高縱橫比結構之撓曲件的近端部分的橫截面，其沿著如圖27中所說明之線C截取。撓曲件之近端部分包括安置於介電層3004上方之包括至少一個跡線3002的導體層。介電層3004安置於基板3006上。此外，覆蓋層3001安置於所形成之介電層3004上方以包括金屬頂部部分以使用本文所描述之技術形成高縱橫比電鍍結構。跡線3002經組態為高縱橫比結構，以將跡線之阻抗與終端連接件匹配且提供強度至將跡線3002與連接件電耦接之接頭。圖32說明包括根據一實施例之高縱橫比結構之撓曲件的近端部分2908的平面視圖。如參考與撓曲件一起使用所描述之高縱橫比結構之使用亦適用於其他電路板技術，例如，適用於微電路及射頻(「RF」)電路中。31 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio structure according to an embodiment, taken along line C as illustrated in FIG. 27 . The proximal portion of the flexure includes a conductor layer including at least one trace 3002 disposed over a dielectric layer 3004 . Dielectric layer 3004 is disposed on substrate 3006. Additionally, a capping layer 3001 is disposed over the formed dielectric layer 3004 to include a metal top portion to form a high aspect ratio plated structure using the techniques described herein. Trace 3002 is configured as a high aspect ratio structure to match the impedance of the trace to the terminal connector and provide strength to the joint electrically coupling trace 3002 to the connector. Figure 32 illustrates a plan view of a proximal portion 2908 of a flexure including a high aspect ratio structure according to an embodiment. The use of high aspect ratio structures as described with reference to use with flexures is also applicable to other circuit board technologies, for example, in microcircuit and radio frequency ("RF") circuits.
圖33說明根據一實施例之用於形成高縱橫比電鍍結構之製程。如所說明，將銅層3318用作基板。然而，其他導電材料可用作基板。在3301處，介電層3320安置於銅層3318上，諸如本文所述之彼等，經標記及衝壓。可使用包括但不限於可光成像或不可光成像材料、聚合物、陶瓷及其他絕緣材料之材料形成介電層3320。對於一些實施例，銅層3318為諸如本文所描述之銅合金層的銅合金層。對於一些實施例，在介電層中標記及衝壓一或多個穿孔或通孔3322以暴露銅層3318。根據一些實施例，介電層3320為可光成像介電材料且使用包括本文所描述之彼等的圖案化及顯影技術產生一或多個穿孔或通孔3322。其他實施例包括使用雷射、鑽孔或蝕刻介電層3320以產生一或多個穿孔或通孔3322。對於一些實施例，銅合金層具有介於包括15微米至40微米之範圍內的厚度。在3302處，跡線3324或其他導電特徵安置於介電層3320上與銅層3318相對之側面上。對於一些實施例，使用包括本文所描述之技術的技術濺鍍晶種層以在介電層3320上形成圖案。其他實施例包括使用無電極電鍍以形成晶種層。使用包括本文中所描述之彼等技術的技術，將諸如本文中所描述之彼等的電鍍製程用於形成一或多個跡線3324及導電特徵至所要厚度。Figure 33 illustrates a process for forming high aspect ratio electroplated structures according to one embodiment. As illustrated, copper layer 3318 is used as the substrate. However, other conductive materials can be used as the substrate. At 3301, a dielectric layer 3320 is placed on a copper layer 3318, such as those described herein, marked and stamped. Dielectric layer 3320 may be formed using materials including, but not limited to, photoimageable or non-photoimageable materials, polymers, ceramics, and other insulating materials. For some embodiments, copper layer 3318 is a copper alloy layer such as a copper alloy layer described herein. For some embodiments, one or more holes or vias 3322 are marked and punched in the dielectric layer to expose the copper layer 3318. According to some embodiments, dielectric layer 3320 is a photoimageable dielectric material and one or more perforations or vias 3322 are created using patterning and development techniques including those described herein. Other embodiments include using a laser, drilling, or etching dielectric layer 3320 to create one or more holes or vias 3322. For some embodiments, the copper alloy layer has a thickness ranging from 15 microns to 40 microns. At 3302, traces 3324 or other conductive features are disposed on the dielectric layer 3320 on the side opposite the copper layer 3318. For some embodiments, a seed layer is sputtered to pattern dielectric layer 3320 using techniques including those described herein. Other embodiments include using electroless plating to form the seed layer. An electroplating process such as those described herein is used to form one or more traces 3324 and conductive features to a desired thickness using techniques including those described herein.
在3304處，使用包括本文中所描述之彼等技術之技術，將諸如本文中所描述之彼等的保形鍍覆製程用於建立一或多個跡線及導電特徵以增加介電層3320與銅層3318相對之側面上的一或多個跡線及導電特徵之厚度或進一步增強其形狀。對於一些實施例，在3304處，除了在介電層3320與銅層3318相對之側面上之保形鍍覆製程以外，亦使用頂部鍍覆製程，諸如本文中所描述之彼等製程。對於一些實施例，使用頂部鍍覆製程代替保形鍍覆製程。At 3304, a conformal plating process such as those described herein is used to create one or more traces and conductive features to add a dielectric layer 3320 using techniques including those described herein. The thickness of one or more traces and conductive features on the side opposite copper layer 3318 may further enhance its shape. For some embodiments, at 3304, a top plating process, such as those described herein, is used in addition to the conformal plating process on the side of the dielectric layer 3320 opposite the copper layer 3318. For some embodiments, a top plating process is used instead of a conformal plating process.
在3306處，使用包括本文中所描述之彼等技術之技術將介電層3326(諸如，面層)安置於介電層與銅層3318相對之側面上的一或多個跡線3324及導電特徵上。對於一些實施例，不包括面層。舉例而言，所形成之一或多個跡線3324及導電特徵可用金層鍍覆。在3308處，使用包括本文所描述之彼等技術的技術蝕刻銅層3318以形成圖案。對於一些實施例，蝕刻銅層3318以形成一或多個跡線3328及/或一或多個導電特徵。At 3306, a dielectric layer 3326 (such as a face layer) is disposed over one or more traces 3324 and conductive traces 3324 on the side of the dielectric layer opposite the copper layer 3318 using techniques including those described herein. Characteristically. For some embodiments, no topping is included. For example, one or more of the traces 3324 and conductive features formed may be plated with a gold layer. At 3308, the copper layer 3318 is etched to form a pattern using techniques including those described herein. For some embodiments, copper layer 3318 is etched to form one or more traces 3328 and/or one or more conductive features.
在3310處，使用保形鍍覆製程(諸如本文所描述之彼等鍍覆製程)來建立一或多個跡線3328及導電特徵以增加一或多個跡線3328及導電特徵的厚度或進一步增強其形狀，該一或多個跡線3328及導電特徵係使用包括本文所描述之彼等的技術形成於銅層3318中。對於一些實施例，在3310處，除銅層3318上之保形鍍覆製程以外，亦使用頂部鍍覆製程，諸如本文所述之彼等製程。對於一些實施例，使用頂部鍍覆製程代替保形鍍覆製程。At 3310, one or more traces 3328 and conductive features are created using a conformal plating process, such as those described herein, to increase the thickness of the one or more traces 3328 and conductive features or to further To enhance its shape, the one or more traces 3328 and conductive features are formed in the copper layer 3318 using techniques including those described herein. For some embodiments, at 3310, a top plating process, such as those described herein, is used in addition to the conformal plating process on copper layer 3318. For some embodiments, a top plating process is used instead of a conformal plating process.
在3312處，介電層3330(諸如，面層)係安置於一或多個使用包括本文中所描述之彼等技術之技術由銅層3318形成的跡線3328及導電特徵上。對於一些實施例，不包括面層。舉例而言，所形成之一或多個跡線3328及導電特徵可用金層鍍覆。對於一些實施例，製程用於在單一基板上製造多個電路或裝置。在3316處，對於此等實施例，電路或裝置經單粒化且視情況可使用包括此項技術中已知之彼等技術的技術封裝。對於一些實施例，使用包含但不限於雷射切除、斷裂、切割、蝕刻等之技術將電路及/或裝置單粒化。對於一些實施例，本文所描述之面層可使用本文所述之圖案化技術圖案化。舉例而言，面層在毯覆層中施加。根據一些實施例，使用槽模塗佈來施加面層以施加可光成像介電材料。可使用其他技術，諸如滾塗、噴塗、乾膜層壓或用於施加可光成像或不可光成像材料之其他已知方法。若材料為不可光成像的，隨後可使用其他方法將其圖案化(例如雷射或蝕刻)。對於一些實施例，一個或兩個介電層/面層可形成而具有表面修飾，例如以輔助附接至其他結構或基板。對於一些實施例，表面修飾藉由紋理化或圖案化介電層/面層而形成於介電層/面層上。At 3312, a dielectric layer 3330 (such as a surface layer) is disposed over one or more traces 3328 and conductive features formed from the copper layer 3318 using techniques including those described herein. For some embodiments, no topping is included. For example, one or more of the traces 3328 and conductive features formed may be plated with a gold layer. For some embodiments, a process is used to fabricate multiple circuits or devices on a single substrate. At 3316, for these embodiments, the circuit or device is singulated and optionally packaged using techniques including those known in the art. For some embodiments, circuits and/or devices are singulated using techniques including, but not limited to, laser ablation, fracturing, cutting, etching, and the like. For some embodiments, the facing layers described herein may be patterned using patterning techniques described herein. For example, the topcoat is applied in carpet covering. According to some embodiments, the topcoat is applied using slot die coating to apply the photoimageable dielectric material. Other techniques may be used, such as roller coating, spray coating, dry film lamination, or other known methods for applying photoimageable or non-photoimageable materials. If the material is not photoimageable, it can then be patterned using other methods (such as laser or etching). For some embodiments, one or both dielectric layers/surfacing layers may be formed with surface modifications, such as to aid attachment to other structures or substrates. For some embodiments, surface modifications are formed on the dielectric layer/top layer by texturing or patterning the dielectric layer/top layer.
在3314，在一些實施例中，可使用無電極電鍍將諸如鍍覆有金層之鎳終端的終端墊3332形成於基板3318上，且終端墊3332可具備焊料。根據一些實施例，使用鎳、金或其他工業標準表面修飾之無電鍍或電解電鍍來鍍覆形成於經暴露銅層(該銅層安置於頂面及/或底面上)上之表面修飾。另外，可將焊料施加於此等區域。At 3314, in some embodiments, terminal pads 3332, such as nickel terminals plated with a gold layer, may be formed on the substrate 3318 using electroless plating, and the terminal pads 3332 may be provided with solder. According to some embodiments, the surface modification formed on the exposed copper layer disposed on the top and/or bottom surface is plated using electroless or electrolytic plating of nickel, gold, or other industry standard surface modifications. Additionally, solder can be applied to these areas.
圖34說明根據一些實施例的類似於參看圖33用以形成高縱橫比電鍍結構所描述之類型的更詳細製程。Figure 34 illustrates a more detailed process similar to that described with reference to Figure 33 for forming high aspect ratio electroplated structures in accordance with some embodiments.
圖35說明使用本文中所描述之製程製造的線圈。線圈3501包括電耦接以形成線圈3501之多個線圈區段，例如，三個或三個以上線圈區段。對於一些實施例，諸如圖35中所說明之實施例，外部線圈區段3504中之匝的數目與兩個外部線圈區段3504之間的內部線圈區段3502相同。對於一些實施例，內部線圈區段3402包括比外部線圈區段3504更多之匝。其他實施例包括具有例如參看圖35電耦接之多個線圈區段之子集的多個線圈區段，多個線圈區段中之兩者經電耦接，且剩餘線圈區段不與其他兩個線圈區段電耦接。因此，可包括任何數目個線圈區段與其他線圈區段中之任一者電耦接的任何數目個線圈區段之任何組合。Figure 35 illustrates a coil fabricated using the process described herein. Coil 3501 includes a plurality of coil segments, eg, three or more coil segments, electrically coupled to form coil 3501 . For some embodiments, such as the one illustrated in Figure 35, the number of turns in the outer coil section 3504 is the same as the inner coil section 3502 between the two outer coil sections 3504. For some embodiments, inner coil section 3402 includes more turns than outer coil section 3504 . Other embodiments include a plurality of coil segments having a subset of the plurality of coil segments electrically coupled, such as with reference to Figure 35, two of the plurality of coil segments being electrically coupled, and the remaining coil segments not being connected to the other two. The coil sections are electrically coupled. Accordingly, any combination of any number of coil sections may be included with any number of coil sections electrically coupled to any of the other coil sections.
可藉由堆疊每一層來形成包括使用本文中所描述之技術製造的跡線及導電特徵中之任一者中之一者或多者的複數個層，且可藉由穿過層的通孔來產生每一層之間的連接，該等通孔填充有諸如導電黏接劑之導電材料。Multiple layers, including one or more of traces and conductive features fabricated using techniques described herein, may be formed by stacking each layer, and may be formed by vias through the layers. To create connections between each layer, the vias are filled with conductive material such as conductive adhesive.
根據一些實施例，將本文中所描述之製程用以形成合併有其他電路組件(例如，電阻溫度偵測器(RTD)、應變計及其他感測器)之線圈。According to some embodiments, the processes described herein are used to form coils that incorporate other circuit components such as resistance temperature detectors (RTDs), strain gauges, and other sensors.
圖36說明圖37中所說明之線圈的橫截面，該線圈包括第一介電層/覆蓋層3602、第一銅層3604、第二介電層3606、第二銅層3608及第三介電層3610。圖37說明根據一實施例之包括多個線圈區段3702之C形線圈結構3701。對於一些實施例，多個片件在邊角處連接。在一些實施例中，可使用包括本文中所描述之彼等的技術來形成C形線圈結構3701。C形線圈結構3701實現優於目前線圈幾何結構之製造效率。圖38說明根據一實施例之使得製造效率成為可能之C形線圈結構3701配置。交錯組態使得能夠在製造製程期間製造比目前先進技術之線圈結構更多的線圈結構。36 illustrates a cross-section of the coil illustrated in FIG. 37 including a first dielectric/covering layer 3602, a first copper layer 3604, a second dielectric layer 3606, a second copper layer 3608, and a third dielectric layer. Layer 3610. Figure 37 illustrates a C-shaped coil structure 3701 including a plurality of coil sections 3702, according to one embodiment. For some embodiments, multiple pieces are connected at the corners. In some embodiments, C-shaped coil structure 3701 may be formed using techniques including those described herein. The C-shaped coil structure 3701 enables manufacturing efficiencies that are superior to current coil geometries. Figure 38 illustrates a C-shaped coil structure 3701 configuration that enables manufacturing efficiency according to one embodiment. The staggered configuration enables the fabrication of more coil structures during the manufacturing process than are possible with current state-of-the-art coil structures.
圖39說明根據一實施例之可形成的/Z平面成型(例如自集合形成)線圈結構3901。線圈結構3901經組態以使得至少一部分或區段3902可在電路製造之後移動以形成部件，從而提供線圈或其他特徵，諸如實質上在不同於線圈結構之其他區段3902的平面中(例如，在Z平面中而非X、Y平面中)的焊墊。舉例而言，吾人可沿著虛線3904機械地形成區段3902以在Z平面中之部件之左側上呈現線圈。Figure 39 illustrates a /Z-plane formed (eg, self-assembled formed) coil structure 3901 that may be formed according to one embodiment. The coil structure 3901 is configured such that at least a portion or section 3902 can be moved to form a component after circuit fabrication to provide a coil or other feature, such as substantially in a plane different from other sections 3902 of the coil structure (e.g., pads in the Z plane rather than in the X, Y plane). For example, one may mechanically form segment 3902 along dashed line 3904 to present the coil on the left side of the component in the Z plane.
圖40說明根據一實施例之包括橋接器之C形線圈結構4001。橋接器4002經組態以將結構強度添加至結構以(例如)在處置期間或製造製程後減少損害。圖41說明根據圖40中所說明之實施例的C形線圈結構4001中之橋接器4002的橫截面。橋接器之其他實施例包括形成於C形線圈結構之部分之間的任何自由空間中的結構。對於一些實施例，橋接器可為一延伸部，其形成於C形線圈結構的至少一側上且藉由接合點連接，且隨後在接合點處彎曲以跨越C形線圈結構中的開口且附接至另一側以形成橋接器。圖42-44說明包括橋接器4202之C形線圈結構4201的實施例，該橋接器形成為C形線圈之至少一側上之延伸部。對於一些實施例，橋接器厚度可比部件之其餘部分薄。對於一些實施例，橋接器經組態以使線圈結構之一或多個表面，例如與線圈結構之黏著表面齊平。對於其他實施例，橋接器經組態以凹進或低於線圈結構之一或多個表面。對於一些實施例，使用黏著劑將橋接器附接至線圈結構。Figure 40 illustrates a C-shaped coil structure 4001 including a bridge according to one embodiment. Bridge 4002 is configured to add structural strength to the structure to reduce damage, for example, during handling or after a manufacturing process. Figure 41 illustrates a cross-section of bridge 4002 in C-shaped coil structure 4001 according to the embodiment illustrated in Figure 40. Other embodiments of bridges include structures formed in any free space between portions of a C-shaped coil structure. For some embodiments, the bridge may be an extension formed on at least one side of the C-shaped coil structure and connected by a joint, and then bent at the joint to span the opening in the C-shaped coil structure and attached Connect to the other side to form a bridge. Figures 42-44 illustrate an embodiment of a C-shaped coil structure 4201 including a bridge 4202 formed as an extension of the C-shaped coil on at least one side. For some embodiments, the bridge thickness may be thinner than the rest of the component. For some embodiments, the bridge is configured such that one or more surfaces of the coil structure are flush with, for example, an adhesive surface of the coil structure. For other embodiments, the bridge is configured to be recessed or lower than one or more surfaces of the coil structure. For some embodiments, adhesive is used to attach the bridge to the coil structure.
圖45說明根據一實施例之包括橋接器4502之C形線圈結構4501。橋接器4502為經安置以在線圈之部分4504之間的間隙中產生剛性結構之黏著劑。黏著劑可為可經分配及固化之任何附接材料。對於一些實施例，安置於線圈上之黏著劑之一部分比其在間隙中更薄。圖46說明根據圖45中所說明之實施例的C形線圈結構4501中之橋接器4502的橫截面。Figure 45 illustrates a C-shaped coil structure 4501 including a bridge 4502, according to one embodiment. Bridge 4502 is an adhesive positioned to create a rigid structure in the gap between portions 4504 of the coils. The adhesive can be any attachment material that can be dispensed and cured. For some embodiments, a portion of the adhesive disposed on the coil is thinner than it is in the gap. Figure 46 illustrates a cross-section of bridge 4502 in C-shaped coil structure 4501 according to the embodiment illustrated in Figure 45.
圖47說明根據一實施例之由多個個別部分4702形成之線圈結構4701。對於一些實施例，各部分包括用於與線圈結構之對應部分配合的總成突片4704。對於一些實施例，總成突片4704經組態以包括用於附接至對應部分之焊錫膏或其他黏著劑。此線圈結構4701將進一步最佳化可在既定時間製造之線圈結構之數目，從而進一步增加降低之成本及其他製造效率。Figure 47 illustrates a coil structure 4701 formed from a plurality of individual portions 4702, according to one embodiment. For some embodiments, each portion includes an assembly tab 4704 for mating with a corresponding portion of the coil structure. For some embodiments, assembly tab 4704 is configured to include solder paste or other adhesive for attachment to the corresponding portion. This coil structure 4701 will further optimize the number of coil structures that can be manufactured at a given time, thereby further increasing cost reduction and other manufacturing efficiencies.
圖48說明根據一實施例之包括經裝配以用於線圈之多個個別部分4802的線圈結構4801。圖49說明根據一實施例之線圈結構4901之至少一個部分4902之替代形狀。因此，各部分可由任何形狀組成且經組態以與其他對應部分配合以形成線圈結構。Figure 48 illustrates a coil structure 4801 including a plurality of individual portions 4802 assembled for a coil, according to one embodiment. Figure 49 illustrates an alternative shape of at least a portion 4902 of the coil structure 4901 according to one embodiment. Accordingly, each portion can be composed of any shape and configured to cooperate with other corresponding portions to form a coil structure.
圖50說明根據一實施例之用以形成線圈結構之表面安裝線圈。對於一些實施例，表面安裝線圈5002經組態以安置於基板5104上，例如圖51中所說明之基板，此說明在附接表面安裝線圈之前包括加強件5106之此基板5104的俯視圖。圖52說明根據一實施例之具有附接之表面安裝線圈5204之基板5202的俯視圖；對於一些實施例，基板包括一或多個跡線5206及基板5202上之視情況選用之加強件5106。根據一些實施例，基板包括一或多個跡線跨接線5208以將表面安裝線圈5204與另外一或多個表面安裝線圈5204電耦接。跡線跨接線5208亦可用以將一或多個表面安裝線圈5204電耦接至其他組件。或者，跡線跨接線5208可與表面安裝線圈5204整合，例如，如圖53中所說明。在此組態中，根據一些實施例，積體跡線跨接線5302並不增加最終總成之z高度或佔據面積，且消除需要在稍後步驟添加之跨接線。根據一些實施例，加強件(諸如本文所述之加強件)可為銅或其他材料，諸如安置於基板上之阻焊劑或聚醯亞胺。根據一些實施例，基板包括用於將表面安裝線圈電耦接至線圈之其他部分及/或電耦接至其他電路的連接器墊。個別線圈通常可為附接至以下各者之表面安裝結構：平坦表面，其可稍後形成為3D形狀或已形成3D形狀(3D形狀可為曲面的)。另外，對於一些實施例，表面安裝結構可包覆圓角且符合形狀，併有或黏著至其他結構(NFC、RFID、變壓器等)，及/或可經堆疊。Figure 50 illustrates a surface mount coil used to form a coil structure according to one embodiment. For some embodiments, surface mount coil 5002 is configured to rest on a substrate 5104, such as the substrate illustrated in Figure 51, which illustrates a top view of such substrate 5104 including stiffeners 5106 prior to attachment of the surface mount coil. 52 illustrates a top view of a substrate 5202 with an attached surface mount coil 5204 according to one embodiment; for some embodiments, the substrate includes one or more traces 5206 and optional reinforcements 5106 on the substrate 5202. According to some embodiments, the substrate includes one or more trace jumpers 5208 to electrically couple the surface mount coil 5204 to one or more other surface mount coils 5204 . Trace jumpers 5208 may also be used to electrically couple one or more surface mount coils 5204 to other components. Alternatively, trace jumpers 5208 may be integrated with surface mount coils 5204, for example, as illustrated in Figure 53. In this configuration, the integrated trace jumpers 5302 do not increase the z-height or footprint of the final assembly and eliminate the need to add jumpers at a later step, according to some embodiments. According to some embodiments, stiffeners, such as those described herein, may be copper or other materials, such as solder resist or polyimide disposed on the substrate. According to some embodiments, the substrate includes connector pads for electrically coupling the surface mount coil to other portions of the coil and/or to other circuitry. The individual coils may typically be surface mounted structures attached to a flat surface that may later be formed into a 3D shape or may already be formed into a 3D shape (the 3D shape may be curved). Additionally, for some embodiments, surface mount structures may be rounded and conformed, and may have or be adhered to other structures (NFC, RFID, transformers, etc.), and/or may be stacked.
一或多個表面安裝線圈可經由連接件附接至基板，該等連接件包括(但不限於)ACF結構及電連接件、超音波金滾珠接合及焊料(板、熱棒回焊等…)。形成與基板分離之表面安裝線圈進一步使得能夠形成具有任何數目形狀或大小之線圈結構。另外，(例如)使用包括本文中所描述之彼等的技術形成表面安裝線圈藉由能夠同時形成較高數目線圈，因此降低線圈之成本使得製造效率成為可能。另外，表面安裝線圈之製造實現更高銅鍍覆密度，從而幫助降低形成線圈結構之成本，而不會不利地影響線圈性能。One or more surface mount coils may be attached to the substrate via connections including (but not limited to) ACF structural and electrical connections, ultrasonic gold ball bonding and solder (board, hot rod reflow, etc...) . Forming surface mount coils separate from the substrate further enables the formation of coil structures having any number of shapes or sizes. Additionally, forming surface mount coils, for example using techniques including those described herein, enables manufacturing efficiencies by being able to form a higher number of coils simultaneously, thus reducing the cost of coils. In addition, the fabrication of surface mount coils enables higher copper plating densities, thereby helping to reduce the cost of forming the coil structure without adversely affecting coil performance.
圖54說明根據一實施例之表面安裝線圈部分5402。類似於本文中所描述之表面安裝線圈部分之其他實施例，此等線圈部分5402使得能夠將高密度線圈直接附接至諸如電路板(例如，FPC)之基板。舉例而言，一些線圈部分可包括內部電連接器墊5404及/或外部電連接器墊5406。圖55說明根據一實施例之經組態用於黏著線圈部分(諸如，如本文中所描述之表面安裝線圈)以形成線圈結構之電路板5501。另外，線圈結構之總成(例如，黏著基板上之表面安裝線圈)可包括使用如用於當前製造製程中之取放總成製程。因此，合併線圈結構之製造成本得以減少。此外，形成線圈結構之表面安裝線圈消除對額外基板(電路及直接設計至FPC中之支撐結構)之需求。Figure 54 illustrates a surface mount coil portion 5402 according to one embodiment. Similar to other embodiments of surface mount coil portions described herein, these coil portions 5402 enable direct attachment of high density coils to a substrate such as a circuit board (eg, FPC). For example, some coil portions may include internal electrical connector pads 5404 and/or external electrical connector pads 5406 . Figure 55 illustrates a circuit board 5501 configured for adhering coil portions, such as surface mount coils as described herein, to form a coil structure, according to one embodiment. Additionally, assembly of coil structures (eg, surface mount coils on adhesive substrates) may include the use of pick and place assembly processes such as those used in current manufacturing processes. Therefore, the manufacturing cost of the combined coil structure is reduced. Additionally, surface mount coils forming the coil structure eliminate the need for additional substrate (circuitry and support structures designed directly into the FPC).
圖56說明根據一實施例之線圈結構5601的多個視圖。圖57說明根據一實施例之包括表面安裝線圈之線圈結構之多個視圖5701。Figure 56 illustrates multiple views of a coil structure 5601 according to one embodiment. Figure 57 illustrates multiple views 5701 of a coil structure including a surface mount coil, according to one embodiment.
圖58說明根據一實施例之線圈部分。線圈部分5801包括使用包括本文中所描述之彼等的技術實質上以梯形形狀形成的的線圈5802。具有實質上以梯形形狀形成的線圈5802的一或多個線圈部分5801可與線圈結構(諸如本文中所描述之線圈結構)一起使用。具有實質上以梯形形狀形成的線圈5802之此線圈部分5801可與具有以其他形狀形成之線圈的一或多個其他線圈部分一起使用。另外，線圈部分的其他實施例包括具有實質上以不同於梯形之形狀形成的線圈。Figure 58 illustrates a coil portion according to one embodiment. Coil portion 5801 includes coil 5802 formed substantially in a trapezoidal shape using techniques including those described herein. One or more coil portions 5801 having coils 5802 formed in a substantially trapezoidal shape may be used with coil structures such as those described herein. This coil portion 5801 having coils 5802 formed in a substantially trapezoidal shape may be used with one or more other coil portions having coils formed in other shapes. Additionally, other embodiments of the coil portion include having coils formed substantially in a shape other than a trapezoid.
圖59說明根據一實施例之包括用於附接一或多個表面安裝線圈之焊接點的線圈結構。線圈結構5901包括一或多個表面安裝線圈5902。使用包括本文中所描述之技術的技術形成一或多個表面安裝線圈5902。線圈結構5901包括用於將一或多個表面安裝線圈5902以機械方式電耦接至一或多個跡線5906及/或一或多個跡線跨接線5908(諸如本文中所描述之彼等)的焊接點5904。對於一些實施例，在將表面安裝線圈5902焊接至焊接點5904之前，表面安裝線圈5902貼附至線圈結構。根據一些實施例，使用黏著劑將表面安裝線圈5902貼附至線圈結構。對於一些實施例，間隔件安置於表面安裝線圈5902與線圈結構5901之間。對於一些實施例，間隔件經組態以具有一定高度以將表面安裝線圈5902置放於距另一組件所需距離處。Figure 59 illustrates a coil structure including solder points for attaching one or more surface mount coils, according to one embodiment. Coil structure 5901 includes one or more surface mount coils 5902. One or more surface mount coils 5902 are formed using techniques including those described herein. Coil structure 5901 includes means for mechanically and electrically coupling one or more surface mount coils 5902 to one or more traces 5906 and/or one or more trace jumpers 5908 such as those described herein. ) welding point 5904. For some embodiments, surface mount coil 5902 is affixed to the coil structure before surface mount coil 5902 is soldered to solder point 5904. According to some embodiments, surface mount coil 5902 is attached to the coil structure using adhesive. For some embodiments, a spacer is disposed between surface mount coil 5902 and coil structure 5901. For some embodiments, the spacer is configured to have a height to place the surface mount coil 5902 at a desired distance from another component.
圖60說明包括焊接點的結構之俯視圖，該等焊接點用於將表面安裝電路以機械方式電耦接至根據一實施例之結構。結構6001包括表面安裝電路6002。表面安裝電路6002可為任何電路且不限於表面安裝線圈，諸如本文中所描述之彼等。使用焊接點(諸如本文中所描述之彼等)將表面安裝電路6002以機械方式電耦接至該結構。根據一些實施例，在使用包括本文中所描述之彼等的技術將表面安裝電路6002焊接至結構之焊接點之前，使用黏著劑將表面安裝電路6002貼附至結構6001。Figure 60 illustrates a top view of a structure including solder joints for mechanically and electrically coupling surface mount circuitry to the structure according to an embodiment. Structure 6001 includes surface mount circuitry 6002. Surface mount circuit 6002 may be any circuit and is not limited to surface mount coils, such as those described herein. Surface mount circuitry 6002 is mechanically and electrically coupled to the structure using solder joints such as those described herein. According to some embodiments, an adhesive is used to affix the surface mount circuit 6002 to the structure 6001 before soldering the surface mount circuit 6002 to the solder joints of the structure using techniques including those described herein.
61說明包括焊接點的結構之底視圖，該等焊接點用於將表面安裝電路以機械方式電耦接至圖60之結構。對於一些實施例，焊接點形成為接入於結構6001之一表面上，該表面與安置表面安裝電路之表面(例如，頂面)相對(例如，底面)。一旦使用包括本文中所描述之彼等的技術將表面安裝電路安置於該結構上，焊料便安置於焊接點6004中。可使用包括(但不限於)以下之技術將焊料安置於焊接點6004中：使用焊料噴射、焊錫膏施加及手動施加。對於其他實施例，使用導電黏著劑或電阻法焊接將包括表面安裝線圈之表面安裝電路與焊接點耦接。61 illustrates a bottom view of a structure including solder points used to mechanically and electrically couple surface mount circuitry to the structure of Figure 60. For some embodiments, the solder joints are formed to access a surface of the structure 6001 that is opposite (eg, the bottom surface) to the surface (eg, the top surface) on which the surface mount circuitry is mounted. Once surface mount circuitry is placed on the structure using techniques including those described herein, solder is placed in solder joints 6004. Solder may be placed in solder joints 6004 using techniques including, but not limited to, using solder jetting, solder paste application, and manual application. For other embodiments, surface mount circuitry including surface mount coils is coupled to the solder points using conductive adhesive or resistive soldering.
圖62說明根據一實施例之包括焊接點之結構。第一焊接點6204a包括基板焊接墊6206a及表面安裝電路焊接墊6208a。藉由在結構之基板6212中產生空隙6214以暴露導電層6210之一部分來形成基板焊接墊6206a。對於一些實施例，空隙6214可使用包括此項技術中已知之彼等的蝕刻技術形成於基板6212中。對於其他實施例，使用鑽孔或雷射剝蝕在基板6212中形成空隙6214以暴露導電層6210之一部分。使用包括本文所描述之彼等的技術將導電層6210安置於基板上。藉由產生空隙6214暴露之導電層6210之部分為基板焊接墊6206。對於一些實施例，焊接點6204包括基準6213。對於一些實施例，基準為通孔、空隙、導電層、基準件或用於對準之其他參考點。將基準用以使表面安裝焊接墊相對於基板焊接墊對準。舉例而言，光學檢查技術(諸如此項技術中已知之彼等)可用於偵測空隙6214內之基準6213，以確保在將焊料施加至焊接點6204之前將表面安裝電路適當對準。Figure 62 illustrates a structure including solder joints according to one embodiment. The first soldering point 6204a includes a substrate soldering pad 6206a and a surface mount circuit soldering pad 6208a. Substrate bonding pad 6206a is formed by creating a void 6214 in substrate 6212 of the structure to expose a portion of conductive layer 6210. For some embodiments, voids 6214 may be formed in substrate 6212 using etching techniques including those known in the art. For other embodiments, a void 6214 is formed in the substrate 6212 using drilling or laser ablation to expose a portion of the conductive layer 6210. Conductive layer 6210 is disposed on the substrate using techniques including those described herein. The portion of the conductive layer 6210 exposed by creating the void 6214 is the substrate bonding pad 6206. For some embodiments, weld point 6204 includes datum 6213 . For some embodiments, the datum is a via, void, conductive layer, datum, or other reference point for alignment. The datum is used to align the surface mount solder pads relative to the substrate solder pads. For example, optical inspection techniques, such as those known in the art, may be used to detect fiducials 6213 within voids 6214 to ensure proper alignment of the surface mount circuit before applying solder to solder joints 6204.
圖63說明根據一實施例之焊接點。焊接點6304包括基板焊接墊6306，諸如本文所述之彼等，其經由基板6312中之空隙6314暴露。使用包括本文所述之彼等的技術形成空隙6314。焊接點6304亦包括電路焊接墊6308。電路焊接墊6308包括諸如本文中所描述之彼等的焊接墊。電路焊接墊6308可形成於任何基板上，包括(但不限於)表面安裝線圈、表面安裝電路或其他組件之基板。Figure 63 illustrates a solder joint according to one embodiment. Bonding points 6304 include substrate bonding pads 6306, such as those described herein, which are exposed through voids 6314 in substrate 6312. Void 6314 is formed using techniques including those described herein. Solder points 6304 also include circuit solder pads 6308. Circuit bonding pads 6308 include bonding pads such as those described herein. Circuit bonding pads 6308 may be formed on any substrate, including (but not limited to) substrates for surface mount coils, surface mount circuits, or other components.
圖64說明根據一實施例之焊接點的橫截面圖。焊接點6404包括經由基板6412中之空隙6414暴露之基板焊接墊6406，諸如本文所述之彼等。使用包括本文所述之彼等的技術形成空隙6414。焊接點6404亦包括電路焊接墊6408。電路焊接墊6408包括諸如本文中所描述之彼等的焊接墊。電路焊接墊6408可形成於任何基板上，包括(但不限於)表面安裝線圈之基板、表面安裝電路6420之基板或任何類型之組件的基板。根據一些實施例，焊料6418係安置於空隙6414中以將基板焊接墊6406與電路焊接墊6408以機械方式電耦接。使用包括本文所描述之彼等的技術將焊料6418安置於空隙中。對於其他實施例，諸如導電黏著劑之黏著劑安置於空隙6414中。Figure 64 illustrates a cross-sectional view of a solder joint according to one embodiment. Bonding points 6404 include substrate bonding pads 6406 exposed through voids 6414 in substrate 6412, such as those described herein. Void 6414 is formed using techniques including those described herein. Solder points 6404 also include circuit solder pads 6408. Circuit bonding pads 6408 include bonding pads such as those described herein. Circuit bonding pads 6408 may be formed on any substrate, including, but not limited to, a substrate for surface mount coils, a substrate for surface mount circuitry 6420, or a substrate for any type of component. According to some embodiments, solder 6418 is disposed in void 6414 to mechanically and electrically couple substrate bonding pad 6406 and circuit bonding pad 6408. Solder 6418 is placed in the void using techniques including those described herein. For other embodiments, an adhesive such as a conductive adhesive is disposed in void 6414.
根據本文中所描述之實施例的焊接點使得能夠藉由在空隙之區域內含有焊料或導電黏著劑來減少或消除短路之電連接件。焊接點亦使得在將焊料添加至焊接點之前將表面安裝電路、表面安裝線圈或其他組件貼附至基板，此係因為焊接點之空隙形成於表面安裝電路、表面安裝線圈或其他組件係貼附的相對表面中。此亦使得能夠最小化基板與表面安裝電路、表面安裝線圈或其他組件之間的距離，此改良平坦度且消除例如表面安裝線圈與基板之間的空隙。安置於基板上之表面安裝電路、表面安裝線圈或其他組件的改良的平坦度使得能夠使用具有較大厚度(亦即，基板上方之高度)之組件。根據一些實施例，表面安裝電路、表面安裝線圈或其他組件之平坦度為100微米或更小。Solder joints according to embodiments described herein enable the reduction or elimination of shorted electrical connections by including solder or conductive adhesive in areas of the voids. Solder joints also allow surface mount circuitry, surface mount coils, or other components to be attached to the substrate before solder is added to the solder joints because voids in the solder joints are formed where the surface mount circuit, surface mount coil, or other component is attached in the relative surface. This also enables the distance between the substrate and surface mount circuitry, surface mount coils or other components to be minimized, which improves flatness and eliminates gaps between, for example, surface mount coils and the substrate. The improved flatness of surface mount circuits, surface mount coils or other components disposed on the substrate enables the use of components with greater thickness (ie, height above the substrate). According to some embodiments, surface mount circuits, surface mount coils, or other components have a flatness of 100 microns or less.
另外，在焊料添加至焊接點之後，空隙實現焊接點可目視檢查。此情形有助於電連接件之驗證。由空隙允許接入焊接點亦使得能夠在製造(若焊接點)之後焊接點再度使用(例如，重新施加焊料或黏著劑)。此外，焊接點可經組態以藉由修改尺寸以適應所需焊料體積及間隙高度變化來與行業標準焊接製程相容。焊接點亦實現改良製造製程之良率的穩固基板跡線。Additionally, the voids enable visual inspection of the solder joint after solder is added to the joint. This situation facilitates verification of electrical connections. Allowing access to the solder joint by the void also enables the solder joint to be reused (eg, re-applied with solder or adhesive) after fabrication (if the joint is soldered). In addition, solder joints can be configured to be compatible with industry standard soldering processes by modifying dimensions to accommodate required solder volume and gap height changes. The solder joints also enable stable substrate traces that improve the yield of the manufacturing process.
圖65說明用於根據一實施例之使用焊接點之製造製程的流程圖。製程包括將黏著劑施配在基板(6502)上，諸如本文中所描述之彼等。黏著劑安置於基板上以將表面安裝組件(例如，表面安裝線圈、表面安裝電路或其他組件)貼附至基板。例如藉由使用此項技術中已知之取放技術將表面安裝組件安置於黏著劑上(6504)。使用包括此項技術中已知之彼等的技術固化(6506)黏著劑以將一或多個表面安裝組件貼附至基板。使用包括本文所述之彼等的技術將焊料安置於根據本文所述實施例之焊接點之空隙中(6508)。或者，根據本文中所描述的實施例使用包括此項技術中已知之彼等的技術將導電黏著劑安置於焊接點的空隙中。視情況，製造製程包括測試表面安裝組件(6510)。此測試可包括(但不限於)焊接點之目視檢查、藉由添加表面安裝組件產生的表面安裝組件或電路之電驗證及其他製造測試。Figure 65 illustrates a flow diagram for a manufacturing process using solder joints according to one embodiment. The process includes dispensing adhesives, such as those described herein, on a substrate (6502). Adhesives are placed on the substrate to attach surface mount components (eg, surface mount coils, surface mount circuits, or other components) to the substrate. The surface mount component is placed on the adhesive (6504), such as by using pick and place techniques known in the art. The adhesive (6506) is cured using techniques including those known in the art to attach one or more surface mount components to the substrate. Solder is placed in the void of the solder joint according to embodiments described herein using techniques including those described herein (6508). Alternatively, conductive adhesive is placed in the void of the solder joint using techniques including those known in the art in accordance with embodiments described herein. Optionally, the manufacturing process includes testing surface mount components (6510). This testing may include (but is not limited to) visual inspection of solder joints, electrical verification of surface mount components or circuits created by adding surface mount components, and other manufacturing testing.
圖66說明根據一實施例之線圈結構。使用包括本文中所描述之彼等的技術形成線圈結構。線圈結構6601包括表面安裝線圈6602。使用包括本文中所描述之彼等的技術將表面安裝線圈6602貼附至線圈結構6601。表面安裝線圈6602安置於線圈結構6601之中心部分6610上。藉由一或多個連接部分6608將中心部分6610附接至外部部分6606。對於一些實施例，一或多個跡線安置於包括中心部分6610、外部部分6606及連接部分6608中之至少一者的基板上，以將表面安裝線圈6602電耦接至形成於外部部分6606上之一或多個終端墊6604上。Figure 66 illustrates a coil structure according to one embodiment. The coil structure is formed using techniques including those described herein. Coil structure 6601 includes surface mount coils 6602. Surface mount coil 6602 is attached to coil structure 6601 using techniques including those described herein. Surface mount coil 6602 is disposed on central portion 6610 of coil structure 6601. The central portion 6610 is attached to the outer portion 6606 by one or more connecting portions 6608. For some embodiments, one or more traces are disposed on the substrate including at least one of the central portion 6610, the outer portion 6606, and the connecting portion 6608 to electrically couple the surface mount coil 6602 to the surface formed on the outer portion 6606. on one or more terminal pads 6604.
圖67說明根據一實施例之線圈結構。使用包括本文中所描述之彼等的技術形成線圈結構6701。線圈結構6701包括平面內及平面外部分。平面內部分6702經安置以使得其實質上存在於同一平面中。平面內及平面外部分各自經組態以具有表面安裝組件，諸如安置於其上之表面安裝線圈。平面外部分6704實質上存在於獨立平面中，而非平面內部分6702。此組態使得線圈結構能夠具有非平面組態，使得基板之一或多個部分實質上並不存在於與基板之其他部分相同的平面中。此使得組態能夠滿足空間及設計要求，同時仍使得能夠使用線圈結構。一些實施例包括超過一個非平面部分。Figure 67 illustrates a coil structure according to one embodiment. Coil structure 6701 is formed using techniques including those described herein. Coil structure 6701 includes in-plane and out-of-plane portions. In-plane portion 6702 is positioned so that it exists substantially in the same plane. The in-plane and out-of-plane portions are each configured to have surface mount components, such as surface mount coils disposed thereon. Out-of-plane portion 6704 exists substantially in a separate plane than in-plane portion 6702. This configuration enables the coil structure to have a non-planar configuration, such that one or more portions of the substrate do not exist substantially in the same plane as other portions of the substrate. This allows configurations to meet space and design requirements while still enabling the use of coil structures. Some embodiments include more than one non-planar portion.
本文中所描述之所有線圈結構、表面安裝線圈、表面安裝電路及線圈部分可使用包括本文中所描述之彼等的技術來製造。All coil structures, surface mount coils, surface mount circuits, and coil portions described herein can be fabricated using techniques including those described herein.
根據一些實施例，將本文所描述之製程用於形成機械結構及機電結構中之任一者中之一或多者。According to some embodiments, the processes described herein are used to form one or more of any of mechanical structures and electromechanical structures.
儘管結合此等實施例描述，但熟習此項技術者將認識到，可在不背離本發明之精神及範疇之情況下在形式及細節上作出改變。Although described in connection with the embodiments, those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.
202:高縱橫比電鍍結構 204:高縱橫比電鍍結構 302:橫截面 304:磁體 306:最高電磁力 308:線圈層 310:線圈層 402a:層 402b:層 402c:層 402d:層 404:磁體 602:高縱橫比電鍍結構 702:高縱橫比電鍍結構 802a:高縱橫比電鍍結構 802b:高縱橫比電鍍結構 901:導體橫截面積 1002:上線 1004:下線 1102:跡線 1202:高縱橫比電鍍結構 1204:紋理線 1206:介電質 1302:高縱橫比電鍍結構 1402:線圈 1404:中心線圈通孔 1502a:第一導體層 1502b:第二導體層 1504:高縱橫比電鍍結構 1506:高縱橫比電鍍結構 1508:第一介電層 1510:第二介電層 1602a:第一導體層 1602b:第二導體層 1608:第一介電層 1610:第二介電層 1614:第一距離 1616:第二距離 1618:表面 1620:第三距離 1622:第一介電層 1624:基板 1802:跡線 1804:基板 1902:跡線 1904:光阻層 1906:金屬頂部 2102:撓曲件 2104:高縱橫比電鍍結構 2106:跡線 2302:跡線 2304:基板 2306:光阻部分 2308:金屬部分 2501:頂面 2502:電感耦合線圈 2504:高縱橫比電鍍結構 2604:背面 2704:晶片 2802:基板 2804:遮蔽罩 2806:金屬電容板 2808:基礎介電層 2810:分路電容器通孔 2812:跨接通孔 2814:線圈 2816:中心連接部分 2818:電容器連接部分 2820:終端墊 2822:面層 2824:第一焊接墊 2826:第二焊接墊 2828:背面介電層 2830:跨接圖案 2832:跨接路徑 2834:電感耦合線圈 2836:積體晶片 2900:撓曲件 2901:遠端部分 2902:環架部分 2904:中間部分 2906:間隙部分 2908:近端部分 3001:覆蓋層 3002:跡線 3002a:跡線 3002b:跡線 3002c:跡線 3002d:跡線 3004:介電層 3006:基板 3008:空隙 3102:質量結構 3202a:金屬頂部部分 3202b:金屬頂部部分 3301:步驟 3302:步驟 3304:步驟 3306:步驟 3308:步驟 3310:步驟 3312:步驟 3314:步驟 3316:步驟 3318:銅層 3320:介電層 3322:穿孔或通孔 3324:跡線 3326:介電層 3328:跡線 3330:介電層 3332:終端墊 3501:線圈 3502:內部線圈區段 3504a:外部線圈區段 3504b:外部線圈區段 3602:第一介電層/覆蓋層 3604:第一銅層 3606:第二介電層 3608:第二銅層 3610:第三介電層 3701:C形線圈結構 3701a:C形線圈結構 3701b:C形線圈結構 3701c:C形線圈結構 3702a:線圈區段 3702b:線圈區段 3702c:線圈區段 3901:線圈結構 3902a:區段 3902b:區段 3902c:區段 3904:虛線 4001:C形線圈結構 4002:橋接器 4201:C形線圈結構 4202:橋接器 4501:C形線圈結構 4502:橋接器 4504a:部分 4504b:部分 4701:線圈結構 4702a:個別部分 4702b:個別部分 4702c:個別部分 4702d:個別部分 4704:總成突片 4801:線圈結構 4802a:個別部分 4802b:個別部分 4802c:個別部分 4802d:個別部分 4901:線圈結構 4902:至少一個部分 5002a:表面安裝線圈 5002b:表面安裝線圈 5002c:表面安裝線圈 5104:基板 5106:加強件 5202:基板 5204a:表面安裝線圈 5204b:表面安裝線圈 5204c:表面安裝線圈 5206a:跡線 5206b:跡線 5208a:跡線跨接線 5208b:跡線跨接線 5302a:積體跡線跨接線 5302b:積體跡線跨接線 5402a:表面安裝線圈部分 5402b:表面安裝線圈部分 5402c:表面安裝線圈部分 5404a:內部電連接器墊 5406a:外部電連接器墊 5406b:外部電連接器墊 5501:電路板 5601:線圈結構5 5701:視圖 5801:線圈部分 5802:線圈 5901:線圈結構 5902a:表面安裝線圈 5902b:表面安裝線圈 5904a:焊接點 5904b:焊接點 5904c:焊接點 5904d:焊接點 5904e:焊接點 5904f:焊接點 5904g:焊接點 5906:跡線 5908a:跡線跨接線 5908b:跡線跨接線 6001:結構 6002a:表面安裝電路 6002b:表面安裝電路 6002c:表面安裝電路 6004a:焊接點 6004b:焊接點 6004c:焊接點 6004d:焊接點 6004e:焊接點 6004f:焊接點 6004g:焊接點 6004h:焊接點 6204a:第一焊接點 6204b:第一焊接點 6206a:基板焊接墊 6206b:基板焊接墊 6208a:表面安裝電路焊接墊 6208b:表面安裝電路焊接墊 6210:導電層 6212:基板 6213:基準 6214a:空隙 6214b:空隙 6304:焊接點 6306:基板焊接墊 6308:電路焊接墊 6312:基板 6314:空隙 6404:焊接點 6406:基板焊接墊 6408:電路焊接墊 6412:基板 6414:空隙 6418:焊料 6420:表面安裝電路 6502:步驟 6504:步驟 6506:步驟 6508:步驟 6510:步驟 6601:線圈結構 6602a:表面安裝線圈 6602b:表面安裝線圈 6604a:終端墊 6604b:終端墊 6606:外部部分 6608a:連接部分 6608b:連接部分 6610:中心部分 6701:線圈結構 6702a:平面內部分 6702b:平面內部分 6704:平面外部分 A:線 B:線 C:線 202: High aspect ratio plating structure 204: High aspect ratio plating structure 302: Cross Section 304:Magnet 306:Highest electromagnetic force 308: Coil layer 310: Coil layer 402a:Layer 402b:Layer 402c:Layer 402d: layer 404:Magnet 602: High aspect ratio plating structure 702: High aspect ratio electroplated structure 802a: High aspect ratio electroplated structure 802b: High aspect ratio electroplated structure 901: Conductor cross-sectional area 1002:online 1004:Offline 1102: Trace 1202: High aspect ratio plating structure 1204:Texture line 1206:Dielectric 1302: High aspect ratio plating structure 1402: coil 1404: Center coil through hole 1502a: First conductor layer 1502b: Second conductor layer 1504: High aspect ratio plating structure 1506: High aspect ratio plating structure 1508: First dielectric layer 1510: Second dielectric layer 1602a: First conductor layer 1602b: Second conductor layer 1608: First dielectric layer 1610: Second dielectric layer 1614:First distance 1616:Second distance 1618:Surface 1620:Third distance 1622: First dielectric layer 1624:Substrate 1802: trace 1804:Substrate 1902: trace 1904: Photoresist layer 1906: Metal top 2102: Flexure piece 2104: High aspect ratio electroplated structure 2106: Trace 2302: Trace 2304:Substrate 2306: Photoresist part 2308:Metal part 2501:Top surface 2502:Inductive coupling coil 2504: High aspect ratio electroplated structure 2604:Back 2704:Chip 2802:Substrate 2804:Shading cover 2806:Metal capacitor plate 2808:Basic dielectric layer 2810: Shunt capacitor through hole 2812: Jumper vias 2814:Coil 2816: Center connection part 2818: Capacitor connection part 2820:Terminal Pad 2822:Topping 2824: First soldering pad 2826: Second soldering pad 2828:Backside dielectric layer 2830: Jumper pattern 2832:crossover path 2834:Inductive coupling coil 2836:Integrated chip 2900: Flexure piece 2901:Remote part 2902: Ring frame part 2904:Middle part 2906: Gap part 2908: proximal part 3001: Covering layer 3002: Trace 3002a: trace 3002b: Trace 3002c: trace 3002d: trace 3004:Dielectric layer 3006:Substrate 3008:gap 3102:Quality structure 3202a: Metal top part 3202b: Metal top part 3301: Steps 3302: Steps 3304: Steps 3306: Steps 3308: Steps 3310: Steps 3312: Steps 3314: Steps 3316: Steps 3318:Copper layer 3320: Dielectric layer 3322: Perforated or through hole 3324: trace 3326:Dielectric layer 3328: trace 3330:Dielectric layer 3332:Terminal pad 3501: coil 3502: Internal coil section 3504a: External coil section 3504b: External coil section 3602: First dielectric layer/covering layer 3604: First copper layer 3606: Second dielectric layer 3608: Second copper layer 3610:Third dielectric layer 3701:C-shaped coil structure 3701a: C-shaped coil structure 3701b: C-shaped coil structure 3701c: C-shaped coil structure 3702a: Coil section 3702b: Coil section 3702c: Coil section 3901: Coil structure 3902a: Section 3902b: Section 3902c: Section 3904: dashed line 4001:C-shaped coil structure 4002:Bridge 4201: C-shaped coil structure 4202:Bridge 4501:C-shaped coil structure 4502:Bridge 4504a:Part 4504b:Part 4701: Coil structure 4702a: individual parts 4702b:Individual parts 4702c: individual parts 4702d:Individual parts 4704:Assembly tab 4801: Coil structure 4802a: individual parts 4802b:Individual parts 4802c: individual parts 4802d: individual parts 4901: Coil structure 4902:At least one part 5002a: Surface mount coil 5002b: Surface mount coil 5002c: Surface mount coil 5104:Substrate 5106:Reinforcement parts 5202:Substrate 5204a: Surface mount coil 5204b: Surface mount coil 5204c: Surface mount coil 5206a: Trace 5206b: Trace 5208a: Trace jumper 5208b: Trace jumper 5302a: Integrated trace jumper 5302b: Integrated trace jumper 5402a: Surface mount coil part 5402b: Surface mount coil part 5402c: Surface mount coil part 5404a: Internal electrical connector pad 5406a: External electrical connector pad 5406b: External electrical connector pad 5501:Circuit board 5601: Coil structure 5 5701:View 5801: Coil part 5802:Coil 5901: Coil structure 5902a: Surface mount coil 5902b: Surface mount coil 5904a:Welding point 5904b:Welding point 5904c: Welding point 5904d: Welding point 5904e:Welding point 5904f:Welding point 5904g: welding point 5906: Trace 5908a: Trace jumper 5908b: Trace jumper 6001: Structure 6002a: Surface mount circuit 6002b: Surface mount circuit 6002c: Surface mount circuit 6004a:Welding point 6004b:Welding point 6004c: Welding point 6004d: Welding point 6004e:Welding point 6004f: Welding point 6004g: welding point 6004h: Welding point 6204a: First welding point 6204b: First welding point 6206a:Substrate soldering pad 6206b:Substrate soldering pad 6208a: Surface mount circuit soldering pads 6208b: Surface mount circuit soldering pads 6210: Conductive layer 6212:Substrate 6213:baseline 6214a: Gap 6214b:gap 6304:Welding point 6306:Substrate soldering pad 6308:Circuit soldering pad 6312:Substrate 6314:gap 6404:Welding point 6406:Substrate soldering pad 6408:Circuit soldering pad 6412:Substrate 6414:gap 6418:Solder 6420: Surface mount circuit 6502:Step 6504:Step 6506:Step 6508:Step 6510:Step 6601: Coil structure 6602a: Surface mount coil 6602b: Surface mount coil 6604a:Terminal Pad 6604b:Terminal pad 6606:External part 6608a:Connection part 6608b:Connection part 6610:Center part 6701: Coil structure 6702a: In-plane part 6702b: In-plane part 6704: Out-of-plane part A: Line B:line C:line
在附圖之圖式中藉助於實例而非限制說明本發明之實施例，其中相同參考符號指示類似元件，且其中：Embodiments of the invention are illustrated by way of example and not limitation in the drawings of the accompanying drawings, in which like reference characters indicate similar elements, and in which:
圖 1說明使用電流印刷電路技術製造的線圈； Figure 1 illustrates a coil fabricated using current printed circuit technology;
圖 2說明根據一實施例之包括高縱橫比電鍍結構的高密度精密線圈； Figure 2 illustrates a high-density precision coil including a high aspect ratio electroplated structure according to one embodiment;
圖 3說明根據一實施例用以表示由包括高縱橫比電鍍結構之高密度精密線圈產生之電磁力的圖； 3 illustrates a diagram illustrating electromagnetic forces generated by a high-density precision coil including a high aspect ratio electroplated structure , according to one embodiment;
圖 4說明經組態以用於線性馬達類型應用之包括多層根據一實施例的高縱橫比電鍍結構之裝置； Figure 4 illustrates a device configured for linear motor type applications including multiple layers of a high aspect ratio electroplated structure according to an embodiment;
圖 5說明根據一些實施例之高縱橫比電鍍結構； Figure 5 illustrates a high aspect ratio electroplated structure according to some embodiments;
圖 6說明根據一些實施例之高縱橫比電鍍結構； Figure 6 illustrates a high aspect ratio electroplated structure according to some embodiments;
圖 7說明根據一些實施例之高縱橫比電鍍結構； Figure 7 illustrates a high aspect ratio electroplated structure according to some embodiments;
圖 8說明根據一些實施例之具有多層高縱橫比電鍍結構的裝置，該等高縱橫比電鍍結構具有高密度橫截面積； Figure 8 illustrates a device with multiple layers of high aspect ratio electroplated structures having high density cross-sectional areas in accordance with some embodiments;
圖 9說明根據一實施例之指示在高電流密度鍍覆技術期間及在低電流密度鍍覆技術期間之SPS覆蓋度的圖表； Figure 9 illustrates a graph indicating SPS coverage during high current density plating technology and during low current density plating technology, according to one embodiment;
圖 10a - f說明根據一實施例用於形成高縱橫比電鍍結構之製程； 10a - f illustrate a process for forming high aspect ratio electroplated structures according to one embodiment;
圖 11說明根據一些實施例之高縱橫比電鍍結構； Figure 11 illustrates a high aspect ratio electroplated structure according to some embodiments;
圖 12說明根據一些實施例之高縱橫比電鍍結構的透視圖； Figure 12 illustrates a perspective view of a high aspect ratio electroplated structure in accordance with some embodiments;
圖 13a 、圖 13b說明根據一實施例使用高縱橫比電鍍結構形成的高密度精密線圈； Figures 13a and 13b illustrate a high-density precision coil formed using a high aspect ratio electroplating structure according to an embodiment;
圖 14說明根據一實施例包括高解析度堆疊導體層的高縱橫比電鍍結構； Figure 14 illustrates a high aspect ratio electroplated structure including high resolution stacked conductor layers according to one embodiment;
圖 15說明根據一實施例之包括高縱橫比電鍍結構的高密度精密線圈； Figure 15 illustrates a high-density precision coil including a high aspect ratio electroplated structure according to one embodiment;
圖 16a - c說明根據另一實施例之用於形成高縱橫比電鍍結構的製程； 16a - c illustrate a process for forming a high aspect ratio electroplated structure according to another embodiment;
圖 17說明根據一實施例之高縱橫比電鍍結構之選擇性形成； Figure 17 illustrates the selective formation of high aspect ratio electroplated structures according to one embodiment;
圖 18說明根據一實施例之形成有金屬頂部部分之高縱橫比電鍍結構的透視圖，該等金屬頂部部分選擇性地形成於跡線上； 18 illustrates a perspective view of a high aspect ratio electroplated structure formed with metal top portions selectively formed on traces, according to one embodiment;
圖 19說明根據一實施例之包括高縱橫比之電鍍結構的硬碟驅動機懸掛件撓曲件； Figure 19 illustrates a hard drive suspension flexure including a high aspect ratio electroplated structure according to one embodiment;
圖 20說明圖19中所說明之硬碟驅動機懸掛件撓曲件之橫截面圖； Figure 20 illustrates a cross-sectional view of the hard drive suspension flexure illustrated in Figure 19;
圖 21a 、圖 21b說明用於在保形鍍覆製程期間使用光阻形成根據一實施例的高縱橫比電鍍結構之製程； 21a and 21b illustrate a process for using photoresist to form a high aspect ratio electroplated structure according to an embodiment during a conformal plating process;
圖 22說明根據各種實施例之用於形成初始金屬層之製程、標準/保形鍍覆製程及頂部鍍覆製程之例示性化學物質； Figure 22 illustrates exemplary chemistries for processes used to form an initial metal layer, a standard/conformal plating process, and a top plating process, in accordance with various embodiments;
圖 23說明根據一實施例之由高縱橫比電鍍結構形成之電感耦合線圈之頂面的透視圖； Figure 23 illustrates a perspective view of the top surface of an inductively coupled coil formed from a high aspect ratio electroplated structure according to one embodiment;
圖 24說明圖21中所說明之電感耦合線圈之實施例的背面之透視圖； Figure 24 illustrates a rear perspective view of the embodiment of the inductively coupled coil illustrated in Figure 21;
圖 25說明根據一實施例之電感耦合線圈2502之頂面與射頻識別晶片耦接的透視圖； 25 illustrates a perspective view of the top surface of the inductive coupling coil 2502 coupled to an RFID chip according to one embodiment;
圖 26a - j說明形成電感耦合線圈之方法，該電感耦合線圈由根據一實施例之高縱橫比電鍍結構形成； 26a - j illustrate a method of forming an inductive coupling coil formed from a high aspect ratio electroplated structure according to an embodiment;
圖 27說明包括根據一實施例之高縱橫比電鍍結構之硬碟驅動機的懸掛件之撓曲件的平面圖； 27 illustrates a plan view of a flexure of a suspension member of a hard disk drive including a high aspect ratio plating structure according to one embodiment;
圖 28說明間隙部分處之撓曲件之間隙部分的橫截面，其沿著如圖27中所說明之線A截取； Figure 28 illustrates a cross-section of the gap portion of the flexure at the gap portion, taken along line A as illustrated in Figure 27;
圖 29說明根據一實施例之具有質量結構之環架部分； Figure 29 illustrates a ring frame portion with a mass structure according to one embodiment;
圖 30說明包括根據一實施例之高縱橫比電鍍結構之撓曲件的近端部分的橫截面，其沿著如圖27中所說明之線B截取； Figure 30 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio electroplated structure according to one embodiment, taken along line B as illustrated in Figure 27;
圖 31說明包括根據一實施例之高縱橫比結構之撓曲件的近端部分的橫截面，其沿著如圖27中所說明之線C截取； Figure 31 illustrates a cross-section of a proximal portion of a flexure including a high aspect ratio structure according to an embodiment, taken along line C as illustrated in Figure 27;
圖 32說明根據一實施例之包括高縱橫比結構之撓曲件的近端部分的平面視圖； 32 illustrates a plan view of a proximal portion of a flexure including a high aspect ratio structure , according to one embodiment;
圖 33說明根據一實施例之用於形成高縱橫比電鍍結構之製程； Figure 33 illustrates a process for forming high aspect ratio electroplated structures according to one embodiment;
圖 34說明類似於參看圖33所描述之類型的更詳細製程；及 Figure 34 illustrates a more detailed process similar to that described with reference to Figure 33; and
圖 35說明使用本文中所描述之製程製造之根據實施例的線圈； Figure 35 illustrates a coil according to an embodiment manufactured using the process described herein;
圖 36說明圖37中所說明之線圈的橫截面； Figure 36 illustrates a cross-section of the coil illustrated in Figure 37;
圖 37說明根據一實施例之包括多個線圈區段之C形線圈組態； Figure 37 illustrates a C-shaped coil configuration including multiple coil segments, according to one embodiment;
圖 38說明根據一實施例之C形線圈組態； Figure 38 illustrates a C-shaped coil configuration according to an embodiment;
圖 39說明根據一實施例之可形成的/Z平面成型線圈結構； Figure 39 illustrates a /Z plane formed coil structure that can be formed according to one embodiment;
圖 40說明根據一實施例之包括橋接器之C形線圈結構； Figure 40 illustrates a C-shaped coil structure including a bridge according to one embodiment;
圖 42 - 44說明根據一實施例之包括橋接器之C形線圈結構的實施例； 42-44 illustrate an embodiment of a C - shaped coil structure including a bridge according to an embodiment;
圖 45說明根據一實施例之包括橋接器之C形線圈結構； Figure 45 illustrates a C-shaped coil structure including a bridge according to one embodiment;
圖 46說明根據圖45中所說明之實施例的C形線圈結構中之橋接器的橫截面； Figure 46 illustrates a cross-section of a bridge in a C-shaped coil structure according to the embodiment illustrated in Figure 45;
圖 47說明根據一實施例之由多個個別部分形成之線圈結構； Figure 47 illustrates a coil structure formed from multiple individual parts according to one embodiment;
圖 48說明根據一實施例的包括多個個別部分之線圈結構； Figure 48 illustrates a coil structure including multiple individual portions according to one embodiment;
圖 49說明根據一實施例之線圈結構之至少一部分的替代形狀； Figure 49 illustrates an alternative shape of at least a portion of a coil structure according to an embodiment;
圖 50說明根據一實施例之用以形成線圈結構之表面安裝線圈； Figure 50 illustrates a surface mount coil used to form a coil structure according to one embodiment;
圖 51說明根據一實施例之經組態以安置於基板上之表面安裝線圈； Figure 51 illustrates a surface mount coil configured to be placed on a substrate, according to one embodiment;
圖 52說明根據一實施例之具有附接之表面安裝線圈之基板的俯視圖； Figure 52 illustrates a top view of a substrate with attached surface mount coils according to one embodiment;
圖 53說明根據一實施例之包括積體跡線跨接線之表面安裝線圈； Figure 53 illustrates a surface mount coil including integrated trace jumpers according to one embodiment;
圖 54說明根據一實施例之表面安裝線圈部分； Figure 54 illustrates a surface mount coil portion according to one embodiment;
圖 55說明根據一實施例之經組態用於黏著線圈部分以形成線圈結構之電路板； Figure 55 illustrates a circuit board configured for adhering coil portions to form a coil structure, according to one embodiment;
圖 56說明根據一實施例之線圈結構之多個視圖； Figure 56 illustrates multiple views of a coil structure according to an embodiment;
圖 57說明根據一實施例之包括表面安裝線圈之線圈結構之多個視圖； Figure 57 illustrates multiple views of a coil structure including a surface mount coil according to one embodiment;
圖 58說明根據一實施例之線圈部分； Figure 58 illustrates a coil portion according to an embodiment;
圖 59說明根據一實施例之包括用於附接一或多個表面安裝線圈之焊接點的線圈結構； Figure 59 illustrates a coil structure including solder points for attaching one or more surface mount coils, according to one embodiment;
圖 60說明包括焊接點的結構之俯視圖，該等焊接點用於將表面安裝電路以機械方式電耦接至根據一實施例之結構； 60 illustrates a top view of a structure including solder joints for mechanically and electrically coupling surface mount circuitry to the structure according to an embodiment;
圖 61說明包括焊接點的結構之底視圖，該等焊接點用於將表面安裝電路以機械方式電耦接至圖60之結構； Figure 61 illustrates a bottom view of a structure including solder points for mechanically and electrically coupling surface mount circuitry to the structure of Figure 60;
圖 62說明根據一實施例之包括焊接點之結構； Figure 62 illustrates a structure including solder joints according to one embodiment;
圖 63說明根據一實施例之焊接點； Figure 63 illustrates a welding point according to one embodiment;
圖 64說明根據一實施例之焊接點的橫截面圖； Figure 64 illustrates a cross-sectional view of a solder joint according to one embodiment;
圖 65說明用於根據一實施例之使用焊接點之製造製程的流程圖； Figure 65 illustrates a flow diagram for a manufacturing process using solder joints according to one embodiment;
圖 66說明根據一實施例之線圈結構；及 Figure 66 illustrates a coil structure according to an embodiment; and
圖 67說明根據一實施例之線圈結構。 Figure 67 illustrates a coil structure according to one embodiment.
6001:結構 6001: Structure
6002a:表面安裝電路 6002a: Surface mount circuit
6002b:表面安裝電路 6002b: Surface mount circuit
6002c:表面安裝電路 6002c: Surface mount circuit
Claims (9)
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862774027P | 2018-11-30 | 2018-11-30 | |
| US62/774,027 | 2018-11-30 | ||
| US16/693,125 | 2019-11-22 | ||
| US16/693,125 US11521785B2 (en) | 2016-11-18 | 2019-11-22 | High density coil design and process |
| WOPCT/US19/62883 | 2019-11-23 | ||
| PCT/US2019/062883 WO2020112569A1 (en) | 2018-11-30 | 2019-11-23 | High density coil design and process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW202405253A true TW202405253A (en) | 2024-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW112140035A TW202405253A (en) | 2018-11-30 | 2019-11-26 | High density coil design and process |
| TW108143005A TW202028540A (en) | 2018-11-30 | 2019-11-26 | High density coil design and process |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
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| TW108143005A TW202028540A (en) | 2018-11-30 | 2019-11-26 | High density coil design and process |
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| JP (1) | JP2022510302A (en) |
| KR (1) | KR20210096196A (en) |
| CN (1) | CN113330524A (en) |
| PH (1) | PH12021551247A1 (en) |
| TW (2) | TW202405253A (en) |
| WO (1) | WO2020112569A1 (en) |
Family Cites Families (17)
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| US5867347A (en) * | 1997-06-13 | 1999-02-02 | Hutchinson Technology Incorporated | Head suspension with stacked coil microactuator for tracking axis adjustment of a read/write head |
| US6239979B1 (en) * | 1998-11-04 | 2001-05-29 | Intel Corporation | Printed circuit board bracket assembly and system |
| US7447037B2 (en) * | 1999-08-04 | 2008-11-04 | Super Talent Electronics, Inc. | Single chip USB packages by various assembly methods |
| FR2825228B1 (en) * | 2001-05-25 | 2003-09-19 | Framatome Connectors Int | METHOD FOR MANUFACTURING A PRINTED CIRCUIT AND PLANAR ANTENNA MANUFACTURED THEREWITH |
| JP4191506B2 (en) * | 2003-02-21 | 2008-12-03 | Ｔｄｋ株式会社 | High density inductor and manufacturing method thereof |
| US6924777B2 (en) * | 2003-03-17 | 2005-08-02 | Hewlett-Packard Development Company, L.P. | Enhanced antenna using flexible circuitry |
| US20050173152A1 (en) * | 2004-02-10 | 2005-08-11 | Post Scott E. | Circuit board surface mount package |
| JP3957000B1 (en) * | 2006-07-07 | 2007-08-08 | 株式会社村田製作所 | Antenna coil for board mounting and antenna device |
| JP4483869B2 (en) * | 2007-02-01 | 2010-06-16 | ソニー株式会社 | Image blur correction device, lens barrel, and imaging device |
| US9859043B2 (en) * | 2008-07-11 | 2018-01-02 | Cooper Technologies Company | Magnetic components and methods of manufacturing the same |
| US8344842B1 (en) * | 2010-01-20 | 2013-01-01 | Vlt, Inc. | Vertical PCB surface mount inductors and power converters |
| DE102012203251B8 (en) * | 2012-03-01 | 2013-11-07 | Bundesdruckerei Gmbh | Contactless data transmission device, this containing security or value document |
| JP5776867B1 (en) * | 2013-11-28 | 2015-09-09 | 株式会社村田製作所 | Electromagnet, camera lens driving apparatus, and electromagnet manufacturing method |
| KR102004791B1 (en) * | 2014-05-21 | 2019-07-29 | 삼성전기주식회사 | Chip electronic component and board having the same mounted thereon |
| JP6585912B2 (en) * | 2015-03-31 | 2019-10-02 | 旭化成エレクトロニクス株式会社 | The camera module |
| KR101762024B1 (en) * | 2015-11-19 | 2017-07-26 | 삼성전기주식회사 | Coil component and board for mounting the same |
| KR20190082295A (en) * | 2016-11-18 | 2019-07-09 | 허친슨 테크놀로지 인코포레이티드 | High aspect ratio electroplating structure and anisotropic electroplating process |
-
2019
- 2019-11-23 WO PCT/US2019/062883 patent/WO2020112569A1/en active Application Filing
- 2019-11-23 KR KR1020217020023A patent/KR20210096196A/en not_active Application Discontinuation
- 2019-11-23 JP JP2021531026A patent/JP2022510302A/en active Pending
- 2019-11-23 CN CN201980089827.5A patent/CN113330524A/en active Pending
- 2019-11-26 TW TW112140035A patent/TW202405253A/en unknown
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2022510302A (en) | 2022-01-26 |
| TW202028540A (en) | 2020-08-01 |
| CN113330524A (en) | 2021-08-31 |
| PH12021551247A1 (en) | 2022-02-14 |
| KR20210096196A (en) | 2021-08-04 |
| WO2020112569A1 (en) | 2020-06-04 |
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