TW202349811A - Surface emitting laser, method for fabricating surface emitting laser - Google Patents

Surface emitting laser, method for fabricating surface emitting laser Download PDF

Info

Publication number
TW202349811A
TW202349811A TW111120320A TW111120320A TW202349811A TW 202349811 A TW202349811 A TW 202349811A TW 111120320 A TW111120320 A TW 111120320A TW 111120320 A TW111120320 A TW 111120320A TW 202349811 A TW202349811 A TW 202349811A
Authority
TW
Taiwan
Prior art keywords
layer
group iii
region
nitride
oxide substrate
Prior art date
Application number
TW111120320A
Other languages
Chinese (zh)
Inventor
斯林凡斯 甘德羅圖拉
Original Assignee
日商三櫻工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三櫻工業股份有限公司 filed Critical 日商三櫻工業股份有限公司
Priority to TW111120320A priority Critical patent/TW202349811A/en
Publication of TW202349811A publication Critical patent/TW202349811A/en

Links

Abstract

A vertical cavity surface emitting laser includes an oxide substrate having a first face and a second face at an opposite side from the first face; a semiconductor section disposed on the first face; a dielectric filter layer disposed between the semiconductor section and the first face and having a reflective spectrum configured to provide an optical window; a first DBR mirror; and a second DBR mirror disposed at a curved surface of the second face. The first DBR mirror, the semiconductor section, the dielectric filter layer, the oxide substrate, and the second DBR mirror are arranged in a first axial direction to form an extended cavity. The semiconductor section is disposed between the dielectric filter layer and the first DBR mirror, and includes a p-type III nitride region, an n-type III nitride region, and a III nitride active region between the p-type and n-type III nitride regions.

Description

面射型雷射及製造面射型雷射之方法Surface emitting laser and method of manufacturing surface emitting laser

本揭露關於一種延伸腔體III族氮化物垂直共振腔面射型雷射(VCSEL)，及製造延伸腔體III族氮化物VCSEL之方法。The present disclosure relates to an extended cavity III-nitride vertical cavity surface emitting laser (VCSEL) and a method of manufacturing an extended cavity III-nitride VCSEL.

面射型雷射也被稱為垂直共振腔面射型雷射(vertical cavity surface emitting laser，VCSEL)。VCSEL包含設置在n側半導體區域與p側半導體區域之間的半導體主動區域、及作用為高反射鏡的二個分散式布拉格反射器(distributed Bragg reflector，DBR)。半導體主動區域，亦被稱為增益介質(gain medium)，設置於二個DBR之間以形成光學腔體。n側及p側區域分別注入載子，即電子及電洞，至主動區域，且該些載子在主動區域重新結合以產生光線。因此，產生的光線或電磁輻射會被該些DBR反射許多次以行進在光學腔體中，進而產生雷射發光(lasing)。VCSEL之該些DBR其中之一為較低反射率鏡，用以射出雷射光線。Surface emitting laser is also called vertical cavity surface emitting laser (VCSEL). The VCSEL includes a semiconductor active region disposed between the n-side semiconductor region and the p-side semiconductor region, and two distributed Bragg reflectors (DBR) that function as high-reflection mirrors. The semiconductor active region, also known as the gain medium, is placed between the two DBRs to form an optical cavity. The n-side and p-side regions inject carriers, namely electrons and holes, into the active region respectively, and these carriers recombine in the active region to generate light. Therefore, the generated light or electromagnetic radiation will be reflected many times by the DBRs to travel in the optical cavity, thereby generating laser luminescence (lasing). One of the DBRs in a VCSEL is a lower reflectivity mirror used to emit laser light.

本申請引用複數的專利及非專利出版物，說明書通篇以其等在括號(即[])中之引用號來指示。出版物依據其引用號排列之列表，記載於以下「非專利文獻」或「專利文獻」的段落。 [引用列表] [非專利文獻] This application cites numerous patent and non-patent publications, which are indicated throughout the specification by their reference numbers in parentheses (i.e., []). A list of publications, arranged according to their citation numbers, is found below under "Non-Patent Documents" or "Patent Documents". [citation list] [Non-patent literature]

[非專利文獻1] Appl. Phys. Express 12, 044004 (2019) [非專利文獻 2] Sci. Rep. 8, 10350 (2018) [非專利文獻 3] Applied Phys. Lett. 83, 2121 (2003) [非專利文獻 4] Appl. Phys. Express 2008, 1, 121102. [非專利文獻 5] Appl. Phys. Express 2012, 5, 092104 [非專利文獻 6] Optics Express, 27, 24717 (2019) [非專利文獻 7] Appl. Phys. Express, 13, 041003 (2020) [非專利文獻 8] Appl. Phys. Express, 14,031002 (2021) [非專利文獻 9] Applied Phys. Lett.119, 142103 (2021) [非專利文獻 10] Crystals, 11 (12) 1563, (2021) [非專利文獻 11] M. B. Stern and T. R. Jay, “Dry etching for coherent refractive micro-lens arrays,” Opt. Eng. 33, 3547-3551 (1994) [Non-patent document 1] Appl. Phys. Express 12, 044004 (2019) [Non-patent document 2] Sci. Rep. 8, 10350 (2018) [Non-patent document 3] Applied Phys. Lett. 83, 2121 (2003) [Non-patent document 4] Appl. Phys. Express 2008, 1, 121102. [Non-patent document 5] Appl. Phys. Express 2012, 5, 092104 [Non-patent document 6] Optics Express, 27, 24717 (2019) [Non-patent document 7] Appl. Phys. Express, 13, 041003 (2020) [Non-patent document 8] Appl. Phys. Express, 14,031002 (2021) [Non-patent document 9] Applied Phys. Lett.119, 142103 (2021) [Non-patent document 10] Crystals, 11 (12) 1563, (2021) [Non-patent document 11] M. B. Stern and T. R. Jay, “Dry etching for coherent refractive micro-lens arrays,” Opt. Eng. 33, 3547-3551 (1994)

[技術問題] 藉由VCSEL中之二個DBR鏡面所定義的光學腔體在增加腔體長度時，會產生過度的繞射損失。在VCSEL中使用彎曲鏡面或透鏡可使VCSEL具有長光學腔體。如非專利文獻1及非專利文獻2所示，彎曲鏡面或透鏡聚焦雷射光線之電場至增益介質來減少來自較長光學腔體所產生之繞射損失。調適腔模態來與VCSEL中的增益光譜對準可以達成高效率操作。在VCSEL中使用非常短的腔體長度，例如一或二個雷射發光波長，會使腔模態之間距較大。由於較大之間距，較不可能會有至少一腔模態落入VCSEL之增益光譜，因此會降低VCSEL的良率及雷射發光效率。相對的，增加腔體長度會使模態間距變窄。由於較窄間距，非常可能有至少一腔模態落入VCSEL之增益光譜，因此加強雷射發光的良率。 [Technical Issue] The optical cavity defined by the two DBR mirrors in the VCSEL will produce excessive diffraction losses when the cavity length is increased. The use of curved mirrors or lenses in VCSELs allows VCSELs to have long optical cavities. As shown in Non-Patent Document 1 and Non-Patent Document 2, curved mirrors or lenses focus the electric field of the laser light to the gain medium to reduce the diffraction loss generated from the longer optical cavity. High-efficiency operation can be achieved by adapting the cavity mode to align with the gain spectrum in the VCSEL. Using a very short cavity length in a VCSEL, such as one or two laser emission wavelengths, results in a large spacing between cavity modes. Due to the larger spacing, it is less likely that at least one cavity mode will fall into the gain spectrum of the VCSEL, thus reducing the yield and laser luminescence efficiency of the VCSEL. In contrast, increasing the cavity length narrows the mode spacing. Due to the narrow pitch, it is very likely that at least one cavity mode falls into the gain spectrum of the VCSEL, thereby enhancing the laser luminescence yield.

然而，在具有長腔體的VCSEL中，挑戰性在於除了主動區域以外，所有的裝置層都是利用對於傳播在VCSEL內之電磁輻射為透明的材料來製作。DBR鏡面之一可被設置在III族氮化物半導體主基板(host substrate)之彎曲背側，形成為透鏡結構。據此，此種結構之VCSEL不使用基板去除，造成III族氮化物主基板可能導致腔體內的中度損失。此種彎曲鏡面方式係在非專利文獻1及非專利文獻2中被提出，仍提供具有原生主基板之明顯部分的腔體，其藉由蝕刻形成透鏡結構以製作彎曲n側DBR鏡面於其上。這種方式係設計來給氮化鎵(GaN)之同質磊晶(homo-epitaxy)。除此之外，包含在腔體內之主基板之摻雜物濃度必須低到如p-i-n吸收之損失的程度。再者，主基板先被薄化來減少腔體內光學吸收損失。薄化基板在厚度上會是較難控制的製程，且可能因基板必須從初始厚度300至400微米薄化至目標厚度10至30微米來提供具有預期腔體長度之VCSEL，而損害基板。However, in VCSELs with long cavities, the challenge is that all device layers except the active region are fabricated from materials that are transparent to electromagnetic radiation propagating within the VCSEL. One of the DBR mirrors can be disposed on the curved back side of the III-nitride semiconductor host substrate to form a lens structure. Accordingly, the VCSEL of this structure does not use substrate removal, so the III-nitride main substrate may cause moderate losses in the cavity. This curved mirror method was proposed in Non-Patent Document 1 and Non-Patent Document 2, and still provides a cavity with an obvious part of the original main substrate, which forms a lens structure by etching to produce a curved n-side DBR mirror on it . This method is designed to achieve homo-epitaxy of gallium nitride (GaN). In addition, the dopant concentration of the host substrate contained within the cavity must be low enough to cause losses due to p-i-n absorption. Furthermore, the main substrate is first thinned to reduce optical absorption losses in the cavity. Thinning the substrate can be a more difficult process to control in terms of thickness and may damage the substrate as it must be thinned from an initial thickness of 300 to 400 microns to a target thickness of 10 to 30 microns to provide a VCSEL with the desired cavity length.

否則在腔體內包含主基板可能造成電磁輻射之每次往返之無意的吸收損失，因而阻礙雷射定限(lasing threshold)降低。然而，非專利文獻3之作者說明在延伸腔體方案中GaN基VCSEL的操作，其藉由直接在低吸收之藍寶石基板上成長GaN基裝置來製作。在此種方案中，藍寶石基板與裝置層之間的晶格不匹配仍限制裝置層之晶體品質，且相應地，此種裝置之壽命及良率也會產生問題。Otherwise, inclusion of the host substrate within the cavity may cause unintentional absorption losses on each round trip of electromagnetic radiation, thereby preventing the lasing threshold from being lowered. However, the authors of Non-Patent Document 3 describe the operation of GaN-based VCSELs in an extended cavity scheme, which is fabricated by growing GaN-based devices directly on a low-absorption sapphire substrate. In this solution, the lattice mismatch between the sapphire substrate and the device layer still limits the crystal quality of the device layer, and accordingly, the lifetime and yield of the device will also be problematic.

較佳為，在保持穩定的雷射操作時盡可能保持吸收源為薄的，且底部鏡面必須定位來形成腔體具有彼此位置相近的上部及底部鏡面，其結果為原生基板的移除。在異質磊晶(hetero-epitaxy)方式中，III族氮化物裝置層被成長在異質基板上，例如藍寶石或矽，且由於GaN在藍寶石基板的異質磊晶無法加強其晶體品質，如非專利文獻4所述，III族氮化物VCSEL裝置之異質基板可藉由化學蝕刻或雷射剝離(laser lift-off，以下稱LLO)來輕易地去除。然而，傳統的LLO製程無法使用於GaN同質磊晶。在其他方式中，從GaN同質磊晶結構移除III族氮化物裝置層被記載於非專利文獻5中，且在非專利文獻6至非專利文獻10中仍被熱烈地討論。It is preferred to keep the absorber as thin as possible while maintaining stable laser operation, and the bottom mirror must be positioned to form a cavity with upper and bottom mirrors located close to each other, with the result that the native substrate is removed. In the hetero-epitaxy method, the Group III nitride device layer is grown on a heterogeneous substrate, such as sapphire or silicon, and the crystal quality of GaN cannot be enhanced due to hetero-epitaxy on the sapphire substrate, as described in non-patent literature 4, the heterogeneous substrate of the III-nitride VCSEL device can be easily removed by chemical etching or laser lift-off (hereinafter referred to as LLO). However, the traditional LLO process cannot be used for GaN homoepitaxy. Among other approaches, removing III-nitride device layers from GaN epitaxial structures is described in Non-Patent Document 5 and is still being actively discussed in Non-Patent Document 6 to Non-Patent Document 10.

當腔體變得越長，就雷射發光及熱漂移來說穩定度越佳。另外，延伸腔體VCSEL設計可藉由仔細地從原生成長基板或異質基板去除VCSEL裝置層來實現，接著重新連接無損(lossless)透明氧化物(transparent oxide，以下稱TO)材料，例如氧化鋅(ZnO)及III族氧化物，其中III族氧化物可包括氧化鋁(Al 2O 3)及氧化鎵(Ga 2O 3)。這種設計需要在連接TO基板及去除的裝置層必須達到次奈米等級以下的表面準備，而也會因重新連接所形成的GaN/氧化物介面之間的折射率差異造成潛在不需要的反射。若反射導致裝置效能劣化，不需要的反射可以藉由在介面設置抗反射鍍膜來抑制。這些程序係耗時的，且對於額外成本也會導致其他問題。 As the cavity becomes longer, the stability becomes better in terms of laser luminescence and thermal drift. In addition, extended cavity VCSEL designs can be achieved by carefully removing the VCSEL device layer from the native growth substrate or a foreign substrate, and then reattaching a lossless transparent oxide (TO) material, such as zinc oxide (ZnO). ZnO) and Group III oxides, where the Group III oxides may include aluminum oxide (Al 2 O 3 ) and gallium oxide (Ga 2 O 3 ). This design requires sub-nanometer surface preparation before attaching the TO substrate and removing the device layer, and also creates potentially unwanted reflections due to the refractive index difference between the GaN/oxide interface formed by the reattachment. . If reflection degrades device performance, unwanted reflection can be suppressed by providing an anti-reflective coating on the interface. These procedures are time consuming and can lead to other problems at additional cost.

考量這些缺點，本揭露之目的為提供一種具有延伸腔體特徵之III族VCSEL之結構及一種製造具有延伸腔體特徵之VCSEL的方法。本揭露之另一目的為提供一種單一步驟整合方案，可使延伸腔體的形成不需要涉及複雜的接合及基板去除步驟。Considering these shortcomings, the purpose of the present disclosure is to provide a structure of a Group III VCSEL with extended cavity characteristics and a method of manufacturing a VCSEL with extended cavity characteristics. Another object of the present disclosure is to provide a single-step integration solution that enables the formation of the extended cavity without involving complicated bonding and substrate removal steps.

[解決手段] 本揭露提供一種VCSEL，其包含：氧化物基板，具有第一面及位在該第一面之相對側之第二面，第二面包括彎曲表面；半導體部分，設置於該氧化物基板之該第一面；介電濾波器層，設置在該半導體部分與該氧化物基板之該第一面之間，並具有反射光譜，該反射光譜提供光學窗口；第一分散式布拉格反射器(DBR)鏡面，該半導體部分設置在該介電濾波器層及該第一DBR鏡面之間；及第二DBR鏡面，設置於該氧化物基板之該彎曲表面，該第一DBR鏡面、該半導體部分、該介電濾波器層、該氧化物基板及該第二DBR鏡面於第一軸向上配置以形成延伸腔體。該半導體部分包括p型III族氮化物區域、III族氮化物區域、及位在該p型III族氮化物區域及該III族氮化物區域之間的該III族氮化物主動區域，該p型III族氮化物區域、該III族氮化物主動區域及該III族氮化物區域在該第一軸向上配置，且該III族氮化物區域包括n型III族氮化物區域。 [Solution] The present disclosure provides a VCSEL, which includes: an oxide substrate having a first side and a second side located on an opposite side of the first side; the second side includes a curved surface; and a semiconductor portion disposed on the oxide substrate. first side; a dielectric filter layer disposed between the semiconductor portion and the first side of the oxide substrate and having a reflection spectrum that provides an optical window; a first distributed Bragg reflector (DBR) A mirror surface, the semiconductor part is disposed between the dielectric filter layer and the first DBR mirror surface; and a second DBR mirror surface is disposed on the curved surface of the oxide substrate, the first DBR mirror surface, the semiconductor part, the The dielectric filter layer, the oxide substrate and the second DBR mirror are arranged in the first axis direction to form an extended cavity. The semiconductor portion includes a p-type Group III nitride region, a Group III nitride region, and the Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, the p-type Group III nitride region The Group III nitride region, the Group III nitride active region and the Group III nitride region are arranged in the first axis direction, and the Group III nitride region includes an n-type Group III nitride region.

本揭露提供一種製造垂直共振腔面射型雷射之方法，該方法包含：準備初始基底，該初始基板包括氧化物基底、III族氮化物模板插栓、及介電濾波器層，該氧化物基底具有第一面及位在該氧化物基底之該第一面之相對側之第二面，該介電濾波器層及該III族氮化物模板插栓位於該氧化物基底之該第一面，該介電濾波器層具有反射光譜，且該反射光譜提供光學窗口；從位於該介電濾波器層上之該III族氮化物模板插栓成長III族氮化物區域；在成長該III族氮化物區域後，成長包括n型III族氮化物區域、III族氮化物主動區域及p型III族氮化物區域之半導體積層；處理該氧化物基底之該第二面以形成具有彎曲表面之氧化物基板，該彎曲表面設置於該氧化物基板之第一面之相對側；在成長該半導體積層後，形成第一DBR積層於該氧化物基板之該第一面；及形成第二DBR積層於該氧化物基板之該彎曲表面。 [本揭露之功效] The present disclosure provides a method for manufacturing a vertical resonant cavity surface-emitting laser. The method includes: preparing an initial substrate. The initial substrate includes an oxide substrate, a group III nitride template plug, and a dielectric filter layer. The oxide The substrate has a first side and a second side located on an opposite side of the first side of the oxide substrate, and the dielectric filter layer and the III-nitride template plug are located on the first side of the oxide substrate , the dielectric filter layer has a reflection spectrum, and the reflection spectrum provides an optical window; growing a Group III nitride region from the Group III nitride template plug located on the dielectric filter layer; growing the Group III nitrogen After forming the oxide region, a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region and a p-type Group III nitride region is grown; the second side of the oxide substrate is processed to form an oxide with a curved surface A substrate, the curved surface is disposed on the opposite side of the first surface of the oxide substrate; after growing the semiconductor layer, a first DBR layer is formed on the first surface of the oxide substrate; and a second DBR layer is formed on the first surface of the oxide substrate. The curved surface of the oxide substrate. [Efficacy of this disclosure]

上述發明可提供一種具有延伸腔體特徵之III族VCSEL之結構及一種製造具有延伸腔體特徵之VCSEL的方法。The above invention can provide a structure of a Group III VCSEL with extended cavity characteristics and a method of manufacturing a VCSEL with extended cavity characteristics.

如本文中所使用的，諸如「第一」、「第二」、「第三」、「第四」及「第五」等用語描述了各種元件、組件、區域、層及/或部分，這些元件、組件、區域、層及/或部分不應受這些術語的限制。這些術語僅可用於將一個元素、組件、區域、層或部分與另一個做區分。除非上下文明確指出，否則本文中使用的諸如「第一」、「第二」、「第三」、「第四」及「第五」的用語並不暗示順序或次序。As used herein, terms such as “first”, “second”, “third”, “fourth” and “fifth” describe various elements, components, regions, layers and/or sections. Elements, components, regions, layers and/or sections shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Terms such as "first," "second," "third," "fourth" and "fifth" used herein do not imply a sequence or order unless otherwise clearly indicated by the context.

從說明、附圖和申請專利範圍，本說明書之主題的其他特徵、態樣與優點將顯得明瞭。參照圖式，表示本揭露之垂直共振腔面射型雷射(VCSEL)、製造VCSEL之方法之示意圖會詳述如下。為便於理解，於圖式中相同元件係利用相同符號來表示。Other features, aspects, and advantages of the subject matter herein will be apparent from the description, drawings, and claims. Referring to the drawings, a schematic diagram showing the vertical cavity surface emitting laser (VCSEL) of the present disclosure and the method of manufacturing the VCSEL will be described in detail below. For ease of understanding, the same components are represented by the same symbols in the drawings.

圖1是表示本揭露之一實施例之VCSEL之層結構的示意圖。圖2是表示本揭露之一實施例之VCSEL的俯視示意圖。具體而言，圖1顯示沿圖2之I-I剖線的剖面。圖1及圖2顯示一種VCSEL 11，其在VCSEL 11之彎曲DBR側利用焊錫凸塊10a接合至基座(sub-mount) 10b。在圖1之(1)、(2)及(3)各部分，縱軸表示反射率(R)，而橫軸表示波長(W)。FIG. 1 is a schematic diagram showing the layer structure of a VCSEL according to an embodiment of the present disclosure. FIG. 2 is a schematic top view of a VCSEL according to an embodiment of the present disclosure. Specifically, FIG. 1 shows a cross section along line I-I of FIG. 2 . Figures 1 and 2 show a VCSEL 11 that is bonded to a sub-mount 10b using solder bumps 10a on the curved DBR side of the VCSEL 11. In each of parts (1), (2) and (3) of Figure 1, the vertical axis represents reflectance (R), and the horizontal axis represents wavelength (W).

VCSEL 11包含第一分散式布拉格反射器(distributed Bragg reflector，DBR)鏡面13、半導體部分15、介電濾波器層17、第二DBR鏡面19及氧化物基板21。介電濾波器層17設置在第一DBR鏡面13與第二DBR鏡面19之間。氧化物基板21具有第一面21a及位在第一面21a之相對側之第二面21b，且第二面21b包括彎曲表面21c。半導體部分15設置於氧化物基板21之第一面21a，且位在第一DBR鏡面13與介電濾波器層17之間。第一DBR鏡面13、半導體部分15、介電濾波器層17、氧化物基板21及第二DBR鏡面19配置於第一軸向Ax1以形成延伸光學腔體CAV。第一DBR鏡面13設置於半導體部分15，第二DBR鏡面19設置於氧化物基板21之彎曲表面21c。介電濾波器層17設置於由第一DBR鏡面13及第二DBR鏡面19形成之延伸光學腔體CAV，並具有反射波長區域及由該等反射波長區域定義之光學窗口WIN，以作為波長λ0附近之帶通濾波器。光學窗口WIN允許光束以雷射發光波長行進在光學腔體CAV，而反射波長區域可以阻擋光學窗口WIN以外之波長的光。The VCSEL 11 includes a first distributed Bragg reflector (DBR) mirror 13 , a semiconductor part 15 , a dielectric filter layer 17 , a second DBR mirror 19 and an oxide substrate 21 . The dielectric filter layer 17 is disposed between the first DBR mirror 13 and the second DBR mirror 19 . The oxide substrate 21 has a first surface 21a and a second surface 21b located on the opposite side of the first surface 21a, and the second surface 21b includes a curved surface 21c. The semiconductor part 15 is disposed on the first surface 21 a of the oxide substrate 21 and is located between the first DBR mirror 13 and the dielectric filter layer 17 . The first DBR mirror 13, the semiconductor portion 15, the dielectric filter layer 17, the oxide substrate 21 and the second DBR mirror 19 are arranged in the first axis Ax1 to form an extended optical cavity CAV. The first DBR mirror 13 is provided on the semiconductor part 15 , and the second DBR mirror 19 is provided on the curved surface 21 c of the oxide substrate 21 . The dielectric filter layer 17 is disposed in the extended optical cavity CAV formed by the first DBR mirror 13 and the second DBR mirror 19, and has a reflection wavelength region and an optical window WIN defined by the reflection wavelength region as the wavelength λ0 Nearby bandpass filter. The optical window WIN allows the beam to travel in the optical cavity CAV at the laser luminescence wavelength, while the reflection wavelength region can block light of wavelengths other than the optical window WIN.

半導體部分15包括p型III族氮化物區域23、III族氮化物主動區域27及III族氮化物區域29。III族氮化物區域29包括n型III族氮化物區域25。III族氮化物主動區域27設置在p型III族氮化物區域23與III族氮化物區域29(n型III族氮化物區域25)之間。p型III族氮化物區域23、III族氮化物主動區域27及III族氮化物區域299(n型III族氮化物區域25)係配置於第一軸向Ax1。在VCSEL 11中，III族氮化物可包含任何氮及III族元素，例如鋁、鎵及銦，的化合物，具體來說，二元合金，例如氮化鎵(GaN)、氮化鋁(AlN)及氮化銦(InN)，三元合金，例如氮化鋁鎵(GaAlN)、氮化鋁銦(InAlN)及氮化銦鎵 (InGaN)，以及四元合金，例如氮化銦鎵鋁(InGaAlN)，其等可包括任何微量雜質。III族氮化物可摻雜p型摻雜物，例如鎂、碳及鈹，以形成p型區域，亦可摻雜n型摻雜物，例如矽及碲，以形成n型區域。III族氮化物亦可摻雜p型及n型摻雜物兩者。The semiconductor portion 15 includes a p-type Group III nitride region 23 , a Group III nitride active region 27 , and a Group III nitride region 29 . Group III nitride region 29 includes n-type Group III nitride region 25 . The III-nitride active region 27 is provided between the p-type III-nitride region 23 and the III-nitride region 29 (n-type III-nitride region 25). The p-type Group III nitride region 23, the Group III nitride active region 27, and the Group III nitride region 299 (n-type Group III nitride region 25) are arranged in the first axial direction Ax1. In VCSEL 11, the Group III nitride can include any compound of nitrogen and Group III elements, such as aluminum, gallium, and indium, specifically, binary alloys, such as gallium nitride (GaN), aluminum nitride (AlN) and indium nitride (InN), ternary alloys such as aluminum gallium nitride (GaAlN), aluminum indium nitride (InAlN) and indium gallium nitride (InGaN), and quaternary alloys such as indium gallium aluminum nitride (InGaAlN ), which may include any trace impurities. Group III nitrides can be doped with p-type dopants, such as magnesium, carbon, and beryllium, to form p-type regions, or with n-type dopants, such as silicon and tellurium, to form n-type regions. Group III nitrides can also be doped with both p-type and n-type dopants.

氧化物基板21包括一或多個氧化物材料，具體而言，氧化鋁(例如Al 2O 3，其能帶約為8.8電子伏特(eV))、氧化鋅(例如ZnO，其能帶約為3.37 eV)、或氧化鎵(例如Ga 2O 3，其能帶約為4.6至4.7 eV)其中之一。這些氧化物材料，如氧化鋁、氧化鋅及氧化鎵，對於可見光、紅外線或紫外線波長之光線是透明的，其可通過氧化物基板21。 The oxide substrate 21 includes one or more oxide materials, specifically, aluminum oxide (such as Al 2 O 3 , whose energy band is approximately 8.8 electron volts (eV)), zinc oxide (such as ZnO, whose energy band is approximately 8.8 electron volts (eV)), 3.37 eV), or one of gallium oxide (such as Ga 2 O 3 , whose energy band is about 4.6 to 4.7 eV). These oxide materials, such as aluminum oxide, zinc oxide and gallium oxide, are transparent to light of visible, infrared or ultraviolet wavelengths, which can pass through the oxide substrate 21 .

VCSEL 11更包含III族氮化物模板插栓18，其在介電濾波器層17所包括之通孔17a內，從氧化物基板21之第一面21a延伸至半導體部分15。通孔17a延伸在第一軸向Ax1。III族氮化物模板插栓18具有嵌設部分18a(其亦顯示於圖3D)及突起18b(其亦顯示於圖3D)。嵌設部分位於通孔17a，並設置與氧化物基板21之第一面21a接觸。突起突出至半導體部分15。The VCSEL 11 further includes a III-nitride template plug 18 extending from the first side 21 a of the oxide substrate 21 to the semiconductor portion 15 within the via 17 a included in the dielectric filter layer 17 . The through hole 17a extends in the first axial direction Ax1. III-nitride template plug 18 has an embedded portion 18a (also shown in Figure 3D) and a protrusion 18b (also shown in Figure 3D). The embedded portion is located in the through hole 17a and is arranged to be in contact with the first surface 21a of the oxide substrate 21. The protrusion projects to the semiconductor portion 15 .

如圖1所示，氧化物基板21之彎曲表面21c具有中心線CNT，且III族氮化物模板插栓18及彎曲表面21c之中心線CNT彼此錯位。As shown in FIG. 1 , the curved surface 21 c of the oxide substrate 21 has a center line CNT, and the center lines CNT of the group III nitride template plug 18 and the curved surface 21 c are misaligned with each other.

介電濾波器層17具有反射光譜R3，其配置以提供光學窗口WIN，如圖1之部分(2)所示。參考圖1所示，介電濾波器層17包括，具體而言，複數設置於氧化物基板21之介電層30，且該等介電層30被配置來構成法布里-培洛濾波器，其可提供具有光學窗口WIN之反射光譜R3。The dielectric filter layer 17 has a reflection spectrum R3 configured to provide an optical window WIN, as shown in part (2) of Figure 1 . Referring to FIG. 1 , the dielectric filter layer 17 includes, specifically, a plurality of dielectric layers 30 disposed on the oxide substrate 21 , and the dielectric layers 30 are configured to form a Fabry-Perot filter. , which can provide the reflection spectrum R3 with the optical window WIN.

第一DBR鏡面13具有反射光譜R1，如圖1之部分(1)所示。第二DBR鏡面19具有反射光譜R2，如圖1之部分(3)所示。反射光譜R1及R2各具有包括波長λ0之反射波長頻寬。The first DBR mirror 13 has a reflection spectrum R1, as shown in part (1) of Figure 1 . The second DBR mirror 19 has a reflection spectrum R2, as shown in part (3) of Figure 1 . Reflection spectra R1 and R2 each have a reflection wavelength bandwidth including wavelength λ0.

反射光譜R1、R2及R3之間的量級關係如下：反射光譜R1及R2各者之反射率值遠大於反射光譜R3之反射率值；且反射光譜R2之反射率值可大於反射光譜R1之反射率值。The magnitude relationship between the reflection spectra R1, R2 and R3 is as follows: the reflectance value of each of the reflection spectrum R1 and R2 is much greater than the reflectance value of the reflection spectrum R3; and the reflectance value of the reflection spectrum R2 can be greater than that of the reflection spectrum R1 Reflectance value.

III族氮化物主動區域27具有量子井結構，以產生具有波長位在第一反射光譜R1、第二反射光譜R2及介電濾波器層17之光學窗口WIN的光線。雷射光線可通過，例如具有反射率低於第二DBR鏡面19的第一DBR鏡面13，來射出。The III-nitride active region 27 has a quantum well structure to generate light having wavelengths located in the first reflection spectrum R1, the second reflection spectrum R2 and the optical window WIN of the dielectric filter layer 17. The laser light may be emitted through, for example, the first DBR mirror 13 having a lower reflectivity than the second DBR mirror 19 .

具體而言，第一DBR鏡面13包括第一介電層13a及第二介電層13b，交替地配置在第一軸向Ax1以作為例如頂部鏡面。第二DBR鏡面19包括第三介電層19a及第四介電層19b，交替地配置在第一軸向Ax1以作為例如底部鏡面。介電濾波器層17延伸在半導體部分15與氧化物基板21之第一面21a之間。Specifically, the first DBR mirror 13 includes a first dielectric layer 13a and a second dielectric layer 13b, which are alternately arranged in the first axial direction Ax1 as, for example, a top mirror. The second DBR mirror 19 includes a third dielectric layer 19a and a fourth dielectric layer 19b, which are alternately arranged in the first axial direction Ax1 to serve as, for example, a bottom mirror. The dielectric filter layer 17 extends between the semiconductor portion 15 and the first side 21 a of the oxide substrate 21 .

在VCSEL 11中，延伸光學腔體CAV之長度可大於50微米(＞ 50微米)。彎曲表面21c具有曲率半徑大於50微米(＞ 50微米)。In the VCSEL 11, the length of the extended optical cavity CAV may be greater than 50 microns (>50 microns). The curved surface 21c has a radius of curvature greater than 50 microns (>50 microns).

在VCSEL 11中，第一DBR鏡面為平面，而第二DBR鏡面為曲面，且第一DBR鏡面13與第二DBR鏡面19之間的距離可在50微米以上。半導體部分15可具有約0.5微米以上之厚度。In the VCSEL 11, the first DBR mirror is a flat surface, while the second DBR mirror is a curved surface, and the distance between the first DBR mirror 13 and the second DBR mirror 19 can be more than 50 microns. Semiconductor portion 15 may have a thickness of approximately 0.5 microns or more.

VCSEL 11更包含導電層35設置於半導體部分15上。導電層35可包括III族氮化物半導體(如n型GaN)或導電無機材料(如氧化銦錫(ITO))任一者，或兩者。導電層35之一部分設置在第一DBR鏡面13與半導體部分15之間。The VCSEL 11 further includes a conductive layer 35 disposed on the semiconductor portion 15 . The conductive layer 35 may include either a Group III nitride semiconductor (such as n-type GaN) or a conductive inorganic material (such as indium tin oxide (ITO)), or both. A portion of the conductive layer 35 is disposed between the first DBR mirror 13 and the semiconductor portion 15 .

在VCSEL 11中，半導體部分15具有孔徑結構39以限制電性載子及雷射光線。若需要，半導體部分15可更包括穿隧結構在半導體部分15之最上層，除了或替代孔徑結構39。穿隧結構改變導電性種類，亦即電子或電洞之一者至另一者。穿隧結構可以是穿隧接面或嵌入穿隧接面其中之一。穿隧接面可以利用孔徑結構39限制載子之路徑，而嵌入穿隧接面可以不需要徑結構39來限制載子之路徑。In the VCSEL 11, the semiconductor portion 15 has an aperture structure 39 to confine electrical carriers and laser light. If desired, the semiconductor portion 15 may further include a tunnel structure on the uppermost layer of the semiconductor portion 15 in addition to or instead of the aperture structure 39 . Tunneling structures change the type of conductivity, that is, one of electrons or holes to the other. The tunnel structure may be one of a tunnel junction or an embedded tunnel junction. The tunnel junction can use the aperture structure 39 to limit the path of carriers, while the embedded tunnel junction does not need the aperture structure 39 to limit the path of carriers.

參考圖1及圖2所示，半導體部分15具有台面結構37。台面結構37包括基座區域37a及設置於基座區域37a上之台面區域37b。台面區域37b亦具有p型III族氮化物區域23、III族氮化物主動區域27、及III族氮化物區域25之n型III族氮化物區域之一部分。基座區域37a包括III族氮化物區域25之n型III族氮化物區域之剩餘部分，而在台面區域37b之底部，台面區域37b可被位在基座區域37a之頂部之n型III族氮化物前面25a所環繞。Referring to FIGS. 1 and 2 , the semiconductor portion 15 has a mesa structure 37 . The mesa structure 37 includes a base area 37a and a mesa area 37b disposed on the base area 37a. The mesa region 37 b also has a p-type Group III nitride region 23 , a Group III nitride active region 27 , and a portion of the Group III nitride region 25 that is an n-type Group III nitride region. The pedestal region 37a includes the remainder of the n-type III-nitride region of the III-nitride region 25, and at the bottom of the mesa region 37b, the mesa region 37b may be located at the top of the pedestal region 37a. Surrounded by 25a in front of the compound.

VCSEL 11更包含第一電極31，例如陽極電極，在台面區域37b、及第二電極33，例如陰極電極，在台面區域37b外側。在VCSEL 11的某一實施例中，陽極電極設置與ITO或延展之半導體層接觸，而陰極電極設置與基座區域37a之n型III族氮化物區域25之頂面25a接觸。第一電極31設置在導電層35或第一DBR鏡面13外側之半導體部分15上，且可與導電層35或半導體部分15接觸。陰極電極33可設置於台面區域37b外側之基座區域37a之n型III族氮化物前面37c(25a)上。The VCSEL 11 further includes a first electrode 31, such as an anode electrode, on the mesa region 37b, and a second electrode 33, such as a cathode electrode, outside the mesa region 37b. In one embodiment of the VCSEL 11, the anode electrode is disposed in contact with the ITO or extended semiconductor layer, and the cathode electrode is disposed in contact with the top surface 25a of the n-type Group III nitride region 25 of the base region 37a. The first electrode 31 is disposed on the conductive layer 35 or the semiconductor portion 15 outside the first DBR mirror 13 and can be in contact with the conductive layer 35 or the semiconductor portion 15 . The cathode electrode 33 may be disposed on the n-type Group III nitride front surface 37c (25a) of the base region 37a outside the mesa region 37b.

在包括導電層31的VCSEL 11中，半導體部分15具有第一面15a及位在第一面15a相對側的第二面15b。介電濾波器層17設置與半導體部分15之第一面15a接觸，而導電層35設置與第二面15b接觸。In the VCSEL 11 including the conductive layer 31, the semiconductor portion 15 has a first surface 15a and a second surface 15b located on the opposite side of the first surface 15a. The dielectric filter layer 17 is arranged in contact with the first side 15a of the semiconductor portion 15, and the conductive layer 35 is arranged in contact with the second side 15b.

參考圖1所示，其顯示VCSEL 11之概要，VCSEL 11具有二個高反射DBR鏡面13及19，其中一個鏡面設置在氧化物基板21之彎曲表面，氧化物基板21將二個DBR鏡面13及19彼此分離以讓延伸光學腔體在單一步驟整合。根據VCSEL 11之製造，半導體部分15藉由磊晶側向延長成長(epitaxial lateral overgrowth (ELO))從III族氮化物模板插栓18開始沿介電濾波器層17來成長，且介電濾波器層17可具有法布里-培洛多層膜，其允許波長上窄帶通及窄帶通外側之大光學抑制區域兩者。介電濾波器層17之反射率被設計為相較於DBR鏡面13及19之各者之反射率，在雷射波長下非常小。Referring to Figure 1, which shows an overview of the VCSEL 11, the VCSEL 11 has two highly reflective DBR mirrors 13 and 19, one of which is disposed on the curved surface of the oxide substrate 21. The oxide substrate 21 combines the two DBR mirrors 13 and 19. 19 are separated from each other to allow the extended optical cavity to be integrated in a single step. According to the fabrication of the VCSEL 11, the semiconductor portion 15 is grown by epitaxial lateral overgrowth (ELO) starting from the III-nitride template plug 18 along the dielectric filter layer 17, and the dielectric filter Layer 17 may have a Fabry-Perot multilayer film that allows both a narrow bandpass at wavelength and a large optical suppression area outside the narrow bandpass. The reflectivity of the dielectric filter layer 17 is designed to be very small at the laser wavelength compared to the reflectivity of each of the DBR mirrors 13 and 19 .

DBR鏡面13及19藉由氧化物基板21之分隔，其形成延伸腔體，越大，可使延伸腔體之縱向模態之間隔為非常小，而這個非常小間隔可使縱向模態之至少一者容易位在介電濾波器層17之窄帶通窗口WIN內。相對的，DBR鏡面13與介電濾波器層17藉由半導體部分15之分隔，其可能形成寄生腔體(parasitic cavity)，越短，會使寄生腔體之縱向模態之間隔變大，而這個大間隔會使寄生腔體之縱向模態之大部分或全部容易位在窄帶通窗口WIN外側。寄生腔體之縱向模態之全部非常可能位在窄帶通窗口WIN外側。介電濾波器層17之窄帶通窗口係與高反射DBR鏡面13及19之較寬的反射波長範圍結合，以演示延伸光學腔體。主動區域，即增益介質，可對準於DBR鏡面13及19，藉此被抑制之寬分隔的縱向模態之場最大值，會與增益介質之位置錯位。雖然VCSEL 11包括複數腔體，在窄帶通窗口WIN內之延伸腔體之至少一單一縱向模態被選擇，而在窄帶通窗口WIN內被選擇之模態的光線，可行進在延伸腔體內於平的與彎曲的鏡面之間來雷射發光。據此，小模態間隔會使對準選擇的模態與增益光譜較不複雜，且長腔體亦可使對準選擇的模態與增益介質較不複雜。The DBR mirrors 13 and 19 are separated by the oxide substrate 21, which forms an extended cavity. The larger the space between the longitudinal modes of the extended cavity is, the smaller the spacing between the longitudinal modes of the extended cavity will be. This very small spacing will allow at least One is easily located within the narrow bandpass window WIN of the dielectric filter layer 17 . In contrast, the DBR mirror 13 and the dielectric filter layer 17 are separated by the semiconductor part 15, which may form a parasitic cavity. The shorter the length, the larger the distance between the longitudinal modes of the parasitic cavity will be. This large spacing will make it easy for most or all of the longitudinal modes of the parasitic cavity to be located outside the narrow bandpass window WIN. It is very likely that all the longitudinal modes of the parasitic cavity are located outside the narrow bandpass window WIN. The narrow bandpass window of dielectric filter layer 17 is combined with the wider reflection wavelength range of highly reflective DBR mirrors 13 and 19 to demonstrate an extended optical cavity. The active region, ie the gain medium, can be aligned with the DBR mirrors 13 and 19, whereby the field maxima of the suppressed wide-separated longitudinal modes are misaligned with the position of the gain medium. Although the VCSEL 11 includes a plurality of cavities, at least one single longitudinal mode of the extended cavity within the narrow bandpass window WIN is selected, and the light of the selected mode within the narrow bandpass window WIN can travel within the extended cavity in Laser light shines between flat and curved mirror surfaces. Accordingly, a small modal spacing will make the alignment of selected modes and gain spectra less complex, and a long cavity will also make the alignment of selected modes and gain media less complex.

VCSEL 11有關於彎曲鏡面在氧化物基板21上的設置，而介電濾波器層17(如法布里-培洛濾波器)嵌設在VCSEL 11之平的及彎曲的鏡面之間。彎曲鏡面可藉由重新聚焦以近90%的反射率，將入射的電磁輻射反射回增益介質，以提供具有較低繞射損失之VCSEL 11之延伸光學腔體。除此之外，氧化物基板21由透明氧化物(TO)材料製成，其包含ZnO、Ga 2O 3、或 Al 2O 3，且透明氧化物材料及彎曲鏡面可使其內之光學吸收可忽略的小，而可達成在VCSEL 11之光學腔體之實質部分內無損光學傳遞。本揭露之裝置結構可在VCSEL 11內達成長腔體及較佳之熱效能。 The VCSEL 11 has a curved mirror disposed on the oxide substrate 21 , and a dielectric filter layer 17 (such as a Fabry-Perot filter) is embedded between the flat and curved mirrors of the VCSEL 11 . The curved mirror can reflect incident electromagnetic radiation back to the gain medium with a reflectivity of nearly 90% by refocusing, providing an extended optical cavity for the VCSEL 11 with lower diffraction losses. In addition, the oxide substrate 21 is made of a transparent oxide (TO) material, which includes ZnO, Ga 2 O 3 , or Al 2 O 3 , and the transparent oxide material and the curved mirror surface can make the optical absorption inside It is negligibly small and can achieve lossless optical transmission within a substantial part of the optical cavity of the VCSEL 11 . The disclosed device structure can achieve a long cavity and better thermal performance within the VCSEL 11.

參考圖1所示，VCSEL 11具有設置在基板21背側之彎曲DBR鏡面，作為底部鏡面。根據VCSEL 11之製造，彎曲DBR鏡面被設計為整合在簡單的製造步驟，例如沿基板21之彎曲背側形成圖案化之介電積層，即DBR鏡面19。VCSEL 11亦具有位在基板21前側之平面DBR鏡面，作為上部鏡面。根據VCSEL 11之製造，平面DBR鏡面被設計為整合在簡單的製造步驟，例如沿半導體部分15之平面形成圖案化之介電積層作為上部鏡面，即DBR鏡面13。平面DBR鏡面13及彎曲DBR鏡面19形成具有介電濾波器層17嵌入其間的延伸腔體。介電濾波器層17較佳為包括抗反射塗層或法布里-培洛結構(包含介電材料)，以在期望之波長附近顯出窄帶通特性。且反射帶通波長外之光學波長的光線。根據VCSEL 11之製造，藉由磊晶側向延長成長(ELO)形成之半導體部分15，係從可藉由沉積及蝕刻製作於氧化物基板21上之模板插栓18開始成長。半導體部分15包括光線產生結構，其具有p型III族氮化物區域23、III族氮化物區域29之n型III族氮化物區域25、及在p型III族氮化物區域23及n型III族氮化物區域25之間的III族氮化物主動區域27。Referring to FIG. 1 , the VCSEL 11 has a curved DBR mirror disposed on the back side of the substrate 21 as a bottom mirror. According to the fabrication of VCSEL 11, the curved DBR mirror is designed to be integrated into a simple manufacturing step, such as forming a patterned dielectric build-up along the curved backside of substrate 21, namely DBR mirror 19. The VCSEL 11 also has a flat DBR mirror located on the front side of the substrate 21 as an upper mirror. According to the fabrication of VCSEL 11, the planar DBR mirror is designed to be integrated in a simple manufacturing step, such as forming a patterned dielectric buildup along the plane of the semiconductor portion 15 as the upper mirror, ie DBR mirror 13. Planar DBR mirror 13 and curved DBR mirror 19 form an extended cavity with dielectric filter layer 17 embedded therebetween. The dielectric filter layer 17 preferably includes an anti-reflective coating or a Fabry-Perot structure (including dielectric material) to exhibit narrow bandpass characteristics near a desired wavelength. And reflects light of optical wavelengths other than the bandpass wavelength. According to the fabrication of VCSEL 11, semiconductor portion 15 formed by epitaxial lateral elongation (ELO) is grown starting from template plugs 18 that can be fabricated on oxide substrate 21 by deposition and etching. The semiconductor portion 15 includes a light generating structure having a p-type Group III nitride region 23, an n-type Group III nitride region 25 of the Group III nitride region 29, and a p-type Group III nitride region 23 and an n-type Group III nitride region 25. III-nitride active region 27 between nitride regions 25.

介電濾波器層17較佳可為法布里-培洛結構，全由介電質構成。根據VCSEL 11之製造，介電濾波器層17可工作如ELO掩膜，讓III族氮化物從III族氮化物模板插栓18磊晶側向地延長成長，以避免III族氮化物沉積於其上，並於氧化物基板21上工作如對於藉由ELO成長之III族氮化物之支撐結構。對於半導體部分15之III族氮化物之ELO沉積係將介電濾波器層17之一部分嵌入。因此，層積濾波器層17(具有ELO掩膜結構)被設計為不需基板之去除及接合，來提供在TO基板21上之薄半導體部分15之簡單步驟整合。這個濾波器層17具有提供窄帶通(讓雷射發光在主要光學腔體的模態)及拒絕波段(可避免寄生光學腔體之一或多個模態雷射發光)兩者之光學特性。The dielectric filter layer 17 is preferably a Fabry-Perot structure and is entirely composed of dielectric material. According to the fabrication of VCSEL 11, dielectric filter layer 17 can operate as an ELO mask, allowing III-nitride to grow epitaxially laterally from III-nitride template plug 18 to avoid III-nitride deposition thereon. on the oxide substrate 21 as a support structure for III-nitride grown by ELO. The ELO deposition of III-nitride for the semiconductor portion 15 embeds a portion of the dielectric filter layer 17 . Therefore, the stacked filter layer 17 (with the ELO mask structure) is designed to provide simple step integration of the thin semiconductor portion 15 on the TO substrate 21 without requiring substrate removal and bonding. This filter layer 17 has optical properties of both providing a narrow bandpass (allowing the laser to emit light in the mode of the main optical cavity) and rejecting the band (avoiding one or more modes of the parasitic optical cavity to emit laser light).

VCSEL 11具有於半導體部分15上之第一DBR鏡面13，其延伸在濾波器層17之上。第一DBR鏡面13具有第一介電層13a及第二介電層13b交替地配置在第一軸向Ax1，且第一介電層13a之材料與第二介電層13b不同。The VCSEL 11 has a first DBR mirror 13 on the semiconductor portion 15 extending over the filter layer 17 . The first DBR mirror 13 has first dielectric layers 13a and second dielectric layers 13b alternately arranged in the first axial direction Ax1, and the materials of the first dielectric layer 13a and the second dielectric layer 13b are different.

VCSEL 11具有第二DBR鏡面19，其藉由半導體部分15及氧化物基板21來與第一DBR鏡面13分隔。第二DBR鏡面19包括第三介電層19a及第四介電層19b交替地配置在第一軸向Ax1，且第三介電層19a之材料與第四介電層19b不同。The VCSEL 11 has a second DBR mirror 19 separated from the first DBR mirror 13 by a semiconductor portion 15 and an oxide substrate 21 . The second DBR mirror 19 includes third dielectric layers 19a and fourth dielectric layers 19b alternately arranged in the first axial direction Ax1, and the material of the third dielectric layer 19a is different from that of the fourth dielectric layer 19b.

VCSEL 11更包括全向反射器(omnidirectional reflector，ODR)層40。全向反射器層40覆蓋半導體部分15及介電濾波器層17，以將雷射發光波長之雜散光向外反射，藉此避免雜散光干涉腔體內之雷射發光。全向反射器層40亦工作如陰極33及陽極31間的鈍化層。The VCSEL 11 further includes an omnidirectional reflector (ODR) layer 40 . The omnidirectional reflector layer 40 covers the semiconductor part 15 and the dielectric filter layer 17 to reflect stray light of the laser luminescence wavelength outward, thereby preventing the stray light from interfering with the laser luminescence in the cavity. The omnidirectional reflector layer 40 also acts as a passivation layer between the cathode 33 and the anode 31 .

腔體CAV具有總腔體長度，可定義為彎曲表面21c及設置與第一DBR鏡面19接觸之實質平坦表面之間的距離。在VCSEL 11之一實施例結構中，彎曲表面21c與TO基板21之平坦頂面21a之間的距離可為50至1000微米，用來作為延伸腔體，且半導體部分15之厚度約為0.5至4微米，亦用來作為延伸腔體。The cavity CAV has a total cavity length, which can be defined as the distance between the curved surface 21 c and a substantially flat surface disposed in contact with the first DBR mirror 19 . In one embodiment structure of the VCSEL 11, the distance between the curved surface 21c and the flat top surface 21a of the TO substrate 21 can be 50 to 1000 microns, used as an extension cavity, and the thickness of the semiconductor portion 15 is about 0.5 to 1000 microns. 4 microns, also used as an extension cavity.

半導體部分15具有孔徑結構39。孔徑結構39具有導電孔徑部分39a及環繞導電孔徑部分39a之低導電部分39b。導電孔徑部分39a提供VCSEL 11形成在陽極電極31及陰極電極33之間的電性路徑。載子(如電子與電洞)流過電性路徑，並在III族氮化物主動區域27重新結合以產生光線，從DBR鏡面(例如第一DBR鏡面13)之一射出。導電孔徑部分39a設置為側向地遠離模板插栓18，以降低模板插栓18可能造成的光學干涉。較佳為，導電孔徑部分39a可與模板插栓18的側壁分離至少約3微米，其係沿介電濾波器層17測量。主要部分由氧化物基板21構成之延伸腔體應在空間上經過設計，以使模板插栓18位在相關於彎曲DBR鏡面19之圓錐的主要部分外側。Semiconductor part 15 has an aperture structure 39 . The aperture structure 39 has a conductive aperture portion 39a and a low conductive portion 39b surrounding the conductive aperture portion 39a. The conductive aperture portion 39a provides an electrical path for the VCSEL 11 to be formed between the anode electrode 31 and the cathode electrode 33. Carriers (such as electrons and holes) flow through the electrical path and recombine in the III-nitride active region 27 to generate light, which is emitted from one of the DBR mirrors (eg, the first DBR mirror 13 ). Conductive aperture portion 39a is disposed laterally away from stencil plug 18 to reduce possible optical interference caused by stencil plug 18. Preferably, conductive aperture portion 39a is separated from the sidewalls of template plug 18 by at least about 3 microns, measured along dielectric filter layer 17. The extended cavity consisting mainly of the oxide substrate 21 should be spatially designed so that the template plug 18 is located outside the main part of the cone relative to the curved DBR mirror 19 .

參考圖2所示，III族氮化物模板插栓18、彎曲表面21c及孔徑結構39以虛線表示。除了第一軸向Ax1，另亦表示第二軸向Ax2及第三軸向Ax3，三個軸向彼此垂直。例如，導電孔徑部分39a相對於線狀模板插栓18不對稱地設置，不對稱設計可易於配置位於前側之陽極及陰極電極、及設置位於背側之彎曲DBR鏡面19。半導體部分15藉由從III族氮化物模板插栓18之暴露的側壁面及頂面往外側向成長於介電濾波器層上。這種形成方式使III族氮化物模板插栓18將半導體部分15與TO基板21連接，而模板插栓18形成III族氮化物熱路徑，可使主動區域27散熱至氧化物基板21。這種結構，即提供VCSEL 11熱路徑，可保證熱能可以通過模板插栓18藉由較佳導熱性之TO基板21被逸散。Referring to FIG. 2 , the Group III nitride template plug 18 , the curved surface 21 c and the aperture structure 39 are represented by dotted lines. In addition to the first axis Ax1, it also represents the second axis Ax2 and the third axis Ax3, and the three axes are perpendicular to each other. For example, the conductive aperture portion 39a is disposed asymmetrically relative to the linear template plug 18. The asymmetric design facilitates the placement of the anode and cathode electrodes on the front side and the curved DBR mirror 19 on the backside. Semiconductor portions 15 are grown on the dielectric filter layer by growing outwardly from the exposed sidewalls and top surfaces of III-nitride template plugs 18 . This formation method enables the Group III nitride template plugs 18 to connect the semiconductor portion 15 to the TO substrate 21 , and the template plugs 18 form a Group III nitride thermal path to dissipate heat from the active region 27 to the oxide substrate 21 . This structure, which provides a thermal path for the VCSEL 11, ensures that heat energy can be dissipated through the template plug 18 through the TO substrate 21 with better thermal conductivity.

以下參考圖3A至圖3R說明根據本實施例之製造VCSEL之方法。圖3A至圖3R各者為剖面圖，顯示製造方法中之製程步驟，且剖面係沿圖2中所示之線I-I。為了避免以下重複描述，以下可行之處使用圖1及圖2中已使用之符號。在以下描述，III族氮化物可藉由例如金屬有機物化學氣相沉積(metal organic chemical vapor deposition，MOCVD)或分子束磊晶(molecular beam epitaxy，MBE)來沉積。The method of manufacturing a VCSEL according to this embodiment will be described below with reference to FIGS. 3A to 3R. 3A to 3R are each a cross-sectional view showing process steps in the manufacturing method, and the cross-section is along line I-I shown in FIG. 2 . In order to avoid repeated description below, the symbols already used in Figures 1 and 2 will be used where possible below. As described below, Group III nitrides may be deposited by, for example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

參考圖3A所示，準備相關於VCSEL 11之氧化物基板21的氧化物晶圓41，其包括透明材料，如ZnO、Ga 2O 3、Al 2O 3，接著III族氮化物膜43，如氮化鎵(GaN)，被沉積於氧化物晶圓41之頂面。 Referring to FIG. 3A , an oxide wafer 41 related to the oxide substrate 21 of the VCSEL 11 is prepared, which includes transparent materials, such as ZnO, Ga 2 O 3 , and Al 2 O 3 , followed by a group III nitride film 43, such as Gallium nitride (GaN) is deposited on the top surface of oxide wafer 41 .

參考圖3B所示，光阻掩膜45被形成於III族氮化物膜43上，且III族氮化物膜43連同掩膜45被蝕刻，以形成一或多個III族氮化物模板插栓18，各III族氮化物模板插栓18具有寬度「W」及高度「H」。III族氮化物模板插栓18各者包括具有非常低缺陷密度之單晶III族氮化物。例如，III族氮化物模板插栓18可沿氧化物晶圓41之頂面線性延伸，且可以間距「P」彼此平行配置。Referring to FIG. 3B , a photoresist mask 45 is formed on the Group III nitride film 43 , and the Group III nitride film 43 together with the mask 45 is etched to form one or more Group III nitride template plugs 18 , each III-nitride template plug 18 has a width "W" and a height "H". III-nitride template plugs 18 each include single crystal III-nitride with very low defect density. For example, III-nitride template plugs 18 may extend linearly along the top surface of oxide wafer 41 and may be arranged parallel to each other at a distance "P".

參考圖3C所示，介電多層膜47被沉積於氧化物晶圓41上，且在III族氮化物模板插栓18之上。介電多層膜47具有厚度小於III族氮化物模板插栓18之高度及III族氮化物膜43之厚度，且具有可形成法布里-培洛濾波器之結構。Referring to FIG. 3C , a dielectric multilayer film 47 is deposited on oxide wafer 41 over III-nitride template plug 18 . The dielectric multilayer film 47 has a thickness smaller than the height of the III-nitride template plug 18 and the thickness of the III-nitride film 43, and has a structure capable of forming a Fabry-Perot filter.

對於法布里-培洛結構之一實施例的介電多層膜47具有以下例示層結構：「(HL)m2nH(LH)m」，其中「H」及「L」分別表示具有高及低折射率的層，這些層分別具有四分之一波光厚度(quarter wave optical thickness)，而「m」及「n」為整數。具體而言，「(HL)m」表示高折射率層及低折射率層交替m次；「2nH」表示高折射率層2n次之厚度；及「(LH)m」表示低折射率層及高折射率層交替m次。以介電材料之折射率及層厚度來設計法布里-培洛光譜(R3)可在中央波長λ0達成高透射光學窗口，以及在高透射光學窗口之兩側達成高反射光譜區。The dielectric multilayer film 47 of one embodiment of the Fabry-Perot structure has the following exemplary layer structure: "(HL)m2nH(LH)m", where "H" and "L" represent high and low refraction, respectively. Each of these layers has a quarter wave optical thickness, and "m" and "n" are integers. Specifically, "(HL)m" represents the high refractive index layer and the low refractive index layer alternating m times; "2nH" represents the thickness of the high refractive index layer 2n times; and "(LH)m" represents the low refractive index layer and The high refractive index layer is alternated m times. Designing the Fabry-Perot spectrum (R3) based on the refractive index and layer thickness of the dielectric material can achieve a high-transmission optical window at the central wavelength λ0 and a high-reflection spectral region on both sides of the high-transmission optical window.

參考圖3D所示，介電濾波器層17藉由以蝕刻處理介電多層膜47來製作，而在蝕刻程序，掩膜(圖未顯示)可被使用，其形成在介電多層膜47上，且在III族氮化物模板插栓18分別具有開口。各III族氮化物模板插栓18位在之後形成之介電濾波器層17之對應開口，並具有下部部分及上部部分。III族氮化物模板插栓18之下部部分18a嵌設於介電濾波器層17之開口，而III族氮化物模板插栓18之上部部分18b從介電濾波器層17之頂面突出。Referring to FIG. 3D , the dielectric filter layer 17 is formed by etching the dielectric multilayer film 47 . During the etching process, a mask (not shown) may be used, which is formed on the dielectric multilayer film 47 . , and the Group III nitride template plugs 18 respectively have openings. Each III-nitride template plug 18 is located in a corresponding opening of a later formed dielectric filter layer 17 and has a lower portion and an upper portion. The lower portion 18 a of the III-nitride template plug 18 is embedded in the opening of the dielectric filter layer 17 , and the upper portion 18 b of the III-nitride template plug 18 protrudes from the top surface of the dielectric filter layer 17 .

在取得如圖3D所示中間產品之程序中，初始基底51已被準備，其具有氧化基底作為氧化物晶圓41、III族氮化物模板插栓18之配置及介電濾波器層17。氧化物晶圓41具有第一面41a及位在第一面41a之相對側之第二面41b。介電濾波器層17及III族氮化物模板插栓18配置於第一面41a。沿第一面41a延伸之介電濾波器層17之反射光譜(R3)用來提供光學窗口(WIN)。光線行進在平坦及彎曲DBR鏡面13及19之間的延伸光學腔體，以在每一光學往返穿過介電法布里-培洛濾波器兩次。介電濾波器層17具有法布里-培洛濾波器結構，來提供窄帶通及窄帶通兩側之拒絕波段。視需求，介電多層膜47可被沉積，接著圖案化來形成週期性配置之條狀開口於氧化物晶圓41之第一面41a，且III族氮化物可選擇性地成長於條狀開口，以形成III族氮化物模板插栓18。In the process of obtaining an intermediate product as shown in FIG. 3D , an initial substrate 51 has been prepared, which has an oxidized substrate as an oxide wafer 41 , a configuration of III-nitride template plugs 18 and a dielectric filter layer 17 . The oxide wafer 41 has a first surface 41a and a second surface 41b located on the opposite side of the first surface 41a. The dielectric filter layer 17 and the III-nitride template plug 18 are disposed on the first surface 41a. The reflection spectrum (R3) of the dielectric filter layer 17 extending along the first face 41a is used to provide an optical window (WIN). Light travels through the extended optical cavity between flat and curved DBR mirrors 13 and 19 to pass through the dielectric Fabry-Perot filter twice on each optical round trip. The dielectric filter layer 17 has a Fabry-Perot filter structure to provide a narrow bandpass and rejection bands on both sides of the narrow bandpass. If desired, the dielectric multilayer film 47 can be deposited and then patterned to form periodically arranged strip-shaped openings on the first side 41a of the oxide wafer 41, and Group III nitride can be selectively grown in the strip-shaped openings. , to form the Group III nitride template plug 18 .

參考圖3E所示，在形成配置包括介電濾波器層17及III族氮化物模板插栓18的初始基底51後，將III族氮化物區域52從III族氮化物模板插栓18沿介電濾波器層17磊晶成長於初始基底51上。III族氮化物區域52藉由ELO從III族氮化物模板插栓18之側邊及頂邊來成長，以形成翼狀III族氮化物島，且相鄰III族氮化物區域52彼此隔離。III族氮化物島以ELO從模板插栓18藉由沉積III族氮化物材料來形成，並定義切割道(dicing street)「D」在相鄰之III族氮化物島之間。切割道「D」亦定義單個VCSEL部分，相關於VCSEL晶片。III族氮化物區域52可部分或全部摻雜n型摻雜物，並從模板插栓18向外延伸。Referring to FIG. 3E , after forming the initial substrate 51 configured to include the dielectric filter layer 17 and the Group III nitride template plug 18 , the Group III nitride region 52 is moved from the Group III nitride template plug 18 along the dielectric The filter layer 17 is epitaxially grown on the initial substrate 51 . III-nitride regions 52 are grown from the sides and top edges of III-nitride template plug 18 by ELO to form wing-like III-nitride islands, and adjacent III-nitride regions 52 are isolated from each other. III-nitride islands are formed with ELO by depositing III-nitride material from template plug 18 and defining dicing streets "D" between adjacent III-nitride islands. Dictionary "D" also defines a single VCSEL section, associated with the VCSEL die. Group III nitride region 52 may be partially or fully doped with n-type dopants and extends outwardly from template plug 18 .

參考圖3F所示，視需求，在成長之後的半導體積層之前，III族氮化物區域52可藉由研磨或蝕刻至少一者來平坦化，以形成具有平坦頂面53a之III族氮化物區域53。Referring to FIG. 3F , if required, before the semiconductor layering after growth, the III-nitride region 52 can be planarized by at least one of grinding or etching to form the III-nitride region 53 with a flat top surface 53a. .

參考圖3G所示，在成長III族氮化物區域53後，磊晶成長包括III族氮化物裝置層之半導體積層55。III族氮化物裝置層具有n型III族氮化物區域25、III族氮化物主動區域27及p型III族氮化物區域23。具體而言，n型III族氮化物區域25、III族氮化物主動區域27及p型III族氮化物區域23係依序成長於III族氮化物區域53之平坦面上。Referring to FIG. 3G , after growing the Group III nitride region 53 , a semiconductor stack 55 including a Group III nitride device layer is epitaxially grown. The III-nitride device layer has an n-type III-nitride region 25, a III-nitride active region 27, and a p-type III-nitride region 23. Specifically, the n-type Group III nitride region 25 , the Group III nitride active region 27 and the p-type Group III nitride region 23 are sequentially grown on the flat surface of the Group III nitride region 53 .

具體而言，氮化物區域25可包括GaN或AlN基材料摻雜n型摻雜物，其可提供電子至III族氮化物主動區域27，而p型III族氮化物區域23可包括GaN或AlN基材料摻雜p型摻雜物，其可提供電洞至III族氮化物主動區域27。III族氮化物主動區域27可包括GaN或AlN基材料，例如GaN、InGaN、AlN、AlGaN或 AlInGaN。III族氮化物主動區域27可具有單一井層或量子井結構，如單量子井(SQW)或多量子井(MQWs)。視需求，可在沉積p型III族氮化物區域23後，成長嵌入穿隧接面或穿隧接面層。Specifically, nitride region 25 may include GaN or AlN-based materials doped with n-type dopants that may provide electrons to Group III nitride active region 27 , while p-type Group III nitride region 23 may include GaN or AlN The base material is doped with p-type dopants, which can provide holes to the III-nitride active region 27 . Group III nitride active region 27 may include GaN or AlN-based materials, such as GaN, InGaN, AIN, AlGaN, or AlInGaN. The III-nitride active region 27 may have a single well layer or a quantum well structure, such as single quantum wells (SQWs) or multiple quantum wells (MQWs). Depending on the requirements, an embedded tunnel junction or a tunnel junction layer can be grown after depositing the p-type Group III nitride region 23 .

參考圖3H所示，在成長半導體積層55之後，於第二面41b處理氧化物晶圓41以形成彎曲表面41c及從第二面41b製作而來的新製作之背面41d。視需求，第二面41b可為研磨過表面。具體而言，氧化物晶圓41之彎曲表面41c係作為微透鏡45a。氧化物晶圓41之彎曲表面41c具有中心軸CNT，且如圖3H所示，III族氮化物模板插栓18及彎曲表面41c之中心軸CNT彼此不對齊。氧化物晶圓41(如藍寶石晶圓)係在其研磨過表面被處理來製造彎曲表面41c，如微透鏡45a及背面41d。彎曲表面41c可被定位於預先定義之已校準的位置，以使微透鏡45a之焦距可用來決定限制載子之孔徑結構的位置。孔徑結構會在以下詳述。Referring to FIG. 3H , after growing the semiconductor stack 55 , the oxide wafer 41 is processed on the second side 41 b to form a curved surface 41 c and a newly fabricated back surface 41 d formed from the second side 41 b. Depending on the requirements, the second surface 41b can be a ground surface. Specifically, the curved surface 41c of the oxide wafer 41 serves as the microlens 45a. The curved surface 41 c of the oxide wafer 41 has a central axis CNT, and as shown in FIG. 3H , the central axes CNT of the Group III nitride template plug 18 and the curved surface 41 c are not aligned with each other. Oxide wafer 41 (such as sapphire wafer) is processed on its ground surface to produce curved surfaces 41c, such as microlenses 45a and backside 41d. The curved surface 41c can be positioned in a predefined calibrated position such that the focal length of the microlens 45a can be used to determine the position of the aperture structure that confines the carriers. The pore structure is detailed below.

參考圖3H至圖3J，彎曲表面41c，其工作如微透鏡，可利用如非專利文獻11中之熱回流(thermal reflow)技術來製造。具體而言，如圖3I所示，光阻膜可被形成於氧化物晶圓41之背側，並藉由標準微影製程處理來形成圖案化光阻57，如光阻微圓盤45a。接著，如圖3J所示，圖案化光阻57在高溫下受到熱處理，例如利用熱板，高溫熱處理會使圖案化光阻57變形為透鏡狀，其可被使用作為犧牲光阻掩膜58。進一步，如圖3H所示，透鏡狀光阻58及氧化物晶圓41之背側41b可藉由反應離子蝕刻(RIE)來處理，因此透鏡狀光阻58之形狀轉移至氧化物晶圓41。具體而言，氧化物晶圓41被薄化，而彎曲表面41c(如微透鏡45a)被保留在薄化之氧化物晶圓(以下稱為氧化物基板42)之背側41d。薄化氧化物晶圓41可以調整延伸光學腔體之長度。因此，本製程不僅可形成彎曲表面41c，亦可調整腔體長度。Referring to FIGS. 3H to 3J , the curved surface 41c, which works like a microlens, can be manufactured using thermal reflow technology as in Non-Patent Document 11. Specifically, as shown in FIG. 3I , a photoresist film can be formed on the backside of the oxide wafer 41 and processed by a standard photolithography process to form a patterned photoresist 57 , such as photoresist microdisks 45 a. Next, as shown in FIG. 3J , the patterned photoresist 57 is subjected to heat treatment at high temperature, such as using a hot plate. The high-temperature heat treatment will deform the patterned photoresist 57 into a lens shape, which can be used as a sacrificial photoresist mask 58 . Further, as shown in FIG. 3H , the lenticular photoresist 58 and the backside 41b of the oxide wafer 41 can be processed by reactive ion etching (RIE), so that the shape of the lenticular photoresist 58 is transferred to the oxide wafer 41 . Specifically, the oxide wafer 41 is thinned, and the curved surface 41c (eg, the microlens 45a) is retained on the backside 41d of the thinned oxide wafer (hereinafter referred to as the oxide substrate 42). Thinning the oxide wafer 41 can adjust the length of the extended optical cavity. Therefore, this process can not only form the curved surface 41c, but also adjust the length of the cavity.

參考圖3K所示，光阻膜59被形成於氧化物基板42之前面，以覆蓋半導體積層55及介電濾波器層17。接著，在氧化物基板42之背面41d的彎曲表面41c利用曝照光線60通過光罩56被照射，曝照光線60穿過彎曲表面41c來聚焦於一點，例如覆蓋半導體積層55之頂面之光阻膜59的一部分，藉此形成光阻膜59的曝光部分59a。Referring to FIG. 3K , a photoresist film 59 is formed on the front surface of the oxide substrate 42 to cover the semiconductor build-up layer 55 and the dielectric filter layer 17 . Next, the curved surface 41c on the back surface 41d of the oxide substrate 42 is irradiated with exposure light 60 through the photomask 56. The exposure light 60 passes through the curved surface 41c and is focused on a point, such as the light covering the top surface of the semiconductor stack 55. A portion of the resist film 59 thereby forms the exposed portion 59 a of the photoresist film 59 .

參考圖3L所示，曝光之光阻膜59的顯影形成具有圖案化開口61a的光阻掩膜61。接著，膜63被沉積在光阻掩膜61上及圖案化開口61a內，而光阻掩膜61的去除會留下由膜63製作的掩膜64。膜63可由Ti/Au或介電層製成。Referring to FIG. 3L , the exposed photoresist film 59 is developed to form a photoresist mask 61 having patterned openings 61 a. Next, film 63 is deposited on photoresist mask 61 and within patterned opening 61a, and removal of photoresist mask 61 leaves mask 64 made of film 63. Membrane 63 may be made of Ti/Au or a dielectric layer.

參考圖3M所示，不包括嵌入穿隧接面之VCSEL 11之製造需要形成孔徑結構65。具體而言，掩膜64用來進行離子佈植以形成孔徑結構65。形成後之孔徑結構65包括孔徑區域65a及環繞孔徑區域65a之隔離區域65b。配合掩膜64將離子(如氫原子、n型摻雜物原子及/或p型摻雜物原子)佈植至半導體積層55可在半導體積層55製作孔徑結構65。孔徑結構65具有半導體孔徑區域65a(其可形成載子流過之電性路徑)及隔離區域65b(其可限制光線及載子進入半導體孔徑區域65a)。在離子佈植後，掩膜64被去除。Referring to FIG. 3M , the fabrication of the VCSEL 11 without the embedded tunnel junction requires the formation of the aperture structure 65 . Specifically, mask 64 is used to perform ion implantation to form aperture structure 65 . The formed aperture structure 65 includes an aperture area 65a and an isolation area 65b surrounding the aperture area 65a. The aperture structure 65 can be fabricated in the semiconductor stack 55 by implanting ions (eg, hydrogen atoms, n-type dopant atoms, and/or p-type dopant atoms) into the semiconductor stack 55 in conjunction with the mask 64 . The aperture structure 65 has a semiconductor aperture region 65a (which can form an electrical path for carriers to flow through) and an isolation region 65b (which can restrict light and carriers from entering the semiconductor aperture region 65a). After ion implantation, mask 64 is removed.

另一方面，半導體積層55包括嵌入穿隧接面之VCSEL 11之製造需要圖案化半導體積層55可包括之穿隧層，如p ++GaN及n ++GaN。具體而言，穿隧層可配合掩膜64來蝕刻以形成嵌入穿隧接面。在蝕刻之後，掩膜64被去除，接著進行III族氮化物之再成長，以沉積覆蓋嵌入穿隧接面之摻雜半導體層，作為電流散布層。 On the other hand, the fabrication of the semiconductor stack 55 including the VCSEL 11 embedded in the tunnel junction requires patterning the tunnel layers that the semiconductor stack 55 may include, such as p ++ GaN and n ++ GaN. Specifically, the tunnel layer can be etched using the mask 64 to form an embedded tunnel junction. After etching, mask 64 is removed, followed by III-nitride regrowth to deposit a doped semiconductor layer covering the embedded tunnel junction as a current spreading layer.

參考圖3N所示，在不包括嵌入穿隧接面之VCSEL 11之製造中去除掩膜64後，導電層67被沉積在半導體積層55上，以覆蓋半導體孔徑區域65a及隔離區域65b。導電層67可包括重摻雜III族氮化物半導體層(如GaN或AlGaN)及/或無機層(如氧化銦錫(ITO))，且對於來自III族氮化物主動區域27之光線為透明的。例如，導電層67可不需掩膜被沉積在氧化物基板42上。Referring to FIG. 3N , after the mask 64 is removed during the fabrication of the VCSEL 11 not including the embedded tunnel junction, a conductive layer 67 is deposited on the semiconductor build-up 55 to cover the semiconductor aperture region 65 a and the isolation region 65 b. The conductive layer 67 may include a heavily doped Group III nitride semiconductor layer (such as GaN or AlGaN) and/or an inorganic layer (such as indium tin oxide (ITO)), and is transparent to light from the Group III nitride active region 27 . For example, conductive layer 67 may be deposited on oxide substrate 42 without a mask.

參考圖3O所示，從半導體積層55製作台面結構69。具體而言，光阻被形成在氧化物基板42a上以覆蓋半導體積層55，接著被圖案化來形成光阻掩膜71。光阻掩膜71用來藉由蝕刻暴露下層之半導體積層55之n型GaN區域，藉此形成包括III族氮化物主動區域27及p型III族氮化物區域23之台面結構69。在台面結構69外側，從半導體積層55製作n型III族氮化物區域之蝕刻面69a。Referring to FIG. 3O , a mesa structure 69 is fabricated from the semiconductor stack 55 . Specifically, a photoresist is formed on the oxide substrate 42 a to cover the semiconductor build-up layer 55 , and is then patterned to form the photoresist mask 71 . The photoresist mask 71 is used to expose the n-type GaN region of the underlying semiconductor stack 55 by etching, thereby forming a mesa structure 69 including the Group III nitride active region 27 and the p-type Group III nitride region 23 . Outside the mesa structure 69, an etched surface 69a of the n-type Group III nitride region is formed from the semiconductor stack 55.

參考圖3P及圖3Q所示，在形成台面結構69後且光阻掩膜71保留在氧化物基板42上，藉由沉積全向性反射膜73在氧化物基板42及光阻掩膜71之上來形成全向反射器(omnidirectional reflector，ODR)層73，接著去除光阻掩膜71，亦即藉由剝離。如圖3P所示，形成後之ODR層73覆蓋台面結構69之側面及介電濾波器層17之頂部，並在台面結構69之頂部具有開口。ODR層73作用為VCSEL 11之雷射波長之雜散光的反射器，且亦作用為之後步驟形成之陽極電極與陰極電極間的鈍化層。Referring to FIG. 3P and FIG. 3Q , after the mesa structure 69 is formed and the photoresist mask 71 remains on the oxide substrate 42 , an omnidirectional reflective film 73 is deposited between the oxide substrate 42 and the photoresist mask 71 . An omnidirectional reflector (ODR) layer 73 is formed, and then the photoresist mask 71 is removed, that is, by lift-off. As shown in FIG. 3P , the formed ODR layer 73 covers the sides of the mesa structure 69 and the top of the dielectric filter layer 17 , and has an opening on the top of the mesa structure 69 . The ODR layer 73 functions as a reflector for stray light of the laser wavelength of the VCSEL 11, and also functions as a passivation layer between the anode electrode and the cathode electrode formed in subsequent steps.

再請參考圖3Q所示，在形成ODR層73之後，藉由剝離將第一r(DBR)積層75及第一電極77形成於導電層67上，藉由剝離將第二電極79形成於位在台面結構69外側之n型III族氮化物區域25之蝕刻面69a上。Please refer to FIG. 3Q again. After the ODR layer 73 is formed, the first r(DBR) layer 75 and the first electrode 77 are formed on the conductive layer 67 by peeling, and the second electrode 79 is formed on the conductive layer 67 by peeling. On the etched surface 69 a of the n-type Group III nitride region 25 outside the mesa structure 69 .

具體而言，第一DBR積層75可藉由剝離來形成，且對齊於孔徑結構65或嵌入穿隧接面。第一電極77，如陽極電極，可位在第一DBR積層75外側，且設置與導電層67或再成長半導體層接觸。第二電極79，如陰極電極，在圖案化ODR層73以形成ODR層73之開口後，可位在台面結構69外側。ODR層73之開口可使第二電極79設置與III族氮化物區域25之蝕刻後的n型III族氮化物面69a接觸。Specifically, the first DBR buildup 75 may be formed by lift-off and aligned with the aperture structure 65 or embedded in the tunnel junction. A first electrode 77, such as an anode electrode, may be located outside the first DBR buildup 75 and disposed in contact with the conductive layer 67 or the re-grown semiconductor layer. The second electrode 79 , such as the cathode electrode, may be positioned outside the mesa structure 69 after the ODR layer 73 is patterned to form openings in the ODR layer 73 . The opening of the ODR layer 73 allows the second electrode 79 to be placed in contact with the etched n-type Group III nitride surface 69 a of the Group III nitride region 25 .

參考圖3R所示，第二DBR鏡面積層81被形成於氧化物基板42之彎曲表面41c上。視需求，第二DBR鏡面積層81被圖案化來暴露氧化物基板42之背表面41d的一部分，接著接合材料，如焊球，可被形成於氧化物基板42之暴露的背表面41d。Referring to FIG. 3R , the second DBR mirror area layer 81 is formed on the curved surface 41 c of the oxide substrate 42 . If desired, the second DBR mirror area layer 81 is patterned to expose a portion of the back surface 41d of the oxide substrate 42, and then bonding materials, such as solder balls, can be formed on the exposed back surface 41d of the oxide substrate 42.

這些程序完成VCSEL，例如VCSEL 11。這個結構可使製造後之VCSEL 11利用焊錫凸塊在彎曲DBR側接合至基座。These programs complete VCSEL, such as VCSEL 11. This structure allows the VCSEL 11 to be bonded to the base on the curved DBR side using solder bumps after fabrication.

圖4A是顯示包含模板插栓18、作為透鏡結構之彎曲表面41c及台面結構69內之孔徑結構65之晶片部分的示意圖。圖4B是應用上述製造程序之氧化物基板42上之二個晶片的平面圖。4A is a schematic diagram showing a portion of the wafer including the template plug 18, the curved surface 41c as a lens structure, and the aperture structure 65 within the mesa structure 69. Figure 4B is a plan view of two wafers on an oxide substrate 42 using the above manufacturing process.

在上述製造方法中，製造後之氧化物基板藉由分離製程(如切割及/或蝕刻)來分離為VCSEL晶片。需注意的是，此處之氧化物基板具有台面結構及位在相鄰台面結構之間之切割道的配置。本揭露之製造後之產品的切割道不包括半導體結構。全向性濾波器層覆蓋氧化物基板之頂面，除了台面結構的頂部，且視需求，可藉由光微影製程及蝕刻在切割道被去除。由於第二DBR積層可被圖案化來位於及圍繞彎曲表面41c，沒有材料覆蓋位在氧化物基板之背側面之切割道。In the above manufacturing method, the manufactured oxide substrate is separated into VCSEL wafers through a separation process (such as cutting and/or etching). It should be noted that the oxide substrate here has a configuration of mesa structures and dicing lanes located between adjacent mesa structures. The dicing lanes of the fabricated products of the present disclosure do not include semiconductor structures. The omnidirectional filter layer covers the top surface of the oxide substrate, except for the top of the mesa structure, and can be removed at the scribe line by photolithography processes and etching if desired. Since the second DBR buildup can be patterned to lie on and around curved surface 41c, no material covers the scribe lines on the back side of the oxide substrate.

在製造後之VCSEL 11中，延伸光學腔體CAV之長度可大於50微米(＞50微米)。彎曲表面41c具有曲率半徑大於50微米(＞50微米)。In the VCSEL 11 after fabrication, the length of the extended optical cavity CAV may be greater than 50 microns (>50 microns). The curved surface 41c has a radius of curvature greater than 50 microns (>50 microns).

在VCSEL 11中，第一DBR鏡面13為平面的，而第二DBR鏡面19為彎曲的，且第一DBR鏡面13與第二DBR鏡面19之間的距離在50微米以上。半導體部分15具有0.5微米以上之厚度。In the VCSEL 11, the first DBR mirror 13 is flat, while the second DBR mirror 19 is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 is more than 50 microns. The semiconductor portion 15 has a thickness of 0.5 micron or more.

在圖4A及圖4B中，半球形圓圈44用來表示沿彎曲表面41c延伸的虛擬球面。例如，當彎曲鏡面21c之曲率半徑R0約100微米時，半球形圓圈44在頂面21a具有200微米之直徑「DIA」。In FIGS. 4A and 4B , the hemispherical circle 44 is used to represent a virtual spherical surface extending along the curved surface 41 c. For example, when the radius of curvature R0 of the curved mirror surface 21c is about 100 microns, the hemispherical circle 44 has a diameter "DIA" of 200 microns on the top surface 21a.

相鄰模板插栓18之間隔相關於填充率(fill rate)，其表示單一晶圓上裝置部分之總面積相對於晶圓之頂部面積的比率。切割道定義晶片區的配置，各者係準備給單一VCSEL裝置。模板插栓18可週期性地配置於一方向，或是跨越整個晶圓的長微帶線(long micro strip)，或是縱向於單一晶片維度內之中斷的微帶線，或是配置為棋盤圖案之中斷的帶線，且視需求，在端點部分地交錯以取得成長的優點，亦即降低邊緣效應。The spacing between adjacent stencil plugs 18 is related to the fill rate, which represents the ratio of the total area of the device portion on a single wafer relative to the top area of the wafer. The scribe lanes define the configuration of wafer areas, each of which is intended for a single VCSEL device. The template plugs 18 may be periodically arranged in one direction, as long microstrips spanning the entire wafer, as interrupted microstrips longitudinally within a single wafer dimension, or as a checkerboard. The interrupted strip lines of the pattern are, if necessary, partially staggered at the end points to obtain the advantage of growth, i.e. reducing edge effects.

模板插栓18的配置相關於切割道的位置。從模板插栓成長之半導體部分因ELO無法做得較大，而半導體部分之ELO在到達相鄰者之前被終止。The configuration of the template plugs 18 is relative to the position of the cutting lane. The semiconductor portion growing from the template plug cannot be made larger due to ELO, and the ELO of the semiconductor portion is terminated before reaching its neighbor.

較佳地，半導體部分應具有尺寸寬於孔徑結構之設計的孔徑部分的尺寸，且小於模板插栓18之配置之週期的尺寸。Preferably, the semiconductor portion should have dimensions wider than the dimensions of the aperture portion for which the aperture structure is designed, and smaller than the dimensions of the periodicity of the arrangement of the template plugs 18 .

較佳地，切割道應排除被切割之III族氮化物材料。氧化物基板之切割可在切割道藉由切割刀、雷射刻劃及/或電漿蝕刻來進行。切割道內不具有III族氮化物材料的好處之一為避免浪費半導體層。Preferably, the dicing lanes should exclude the Group III nitride material being cut. Cutting of the oxide substrate can be performed by cutting knives, laser scribing and/or plasma etching in the dicing lanes. One benefit of not having III-nitride material in the scribe line is the avoidance of wasted semiconductor layers.

孔徑結構之導電孔徑部分可被設置於靠近藉由ELO從模板插栓向外成長之翼狀半導體島的邊緣。本裝置的優點為將電性墊容置於晶片表面，以降低可能存在於鄰近於模板插栓之晶體缺陷或不規則。本裝置的另一優點為將孔徑結構與在模板插栓中央之垂直延伸至氧化物基板之頂面之基準面分離，藉此消除光學損失。The conductive aperture portion of the aperture structure may be positioned close to the edge of the wing-shaped semiconductor island that grows outward from the template plug by ELO. The advantage of this device is that the electrical pads are accommodated on the wafer surface to reduce crystal defects or irregularities that may exist adjacent to the template plugs. Another advantage of this device is the separation of the aperture structure from the reference plane in the center of the template plug extending vertically to the top surface of the oxide substrate, thereby eliminating optical losses.

較窄之切割道可配置較多的裝置部分於單一晶圓上。Narrower scribe lanes allow more device parts to be placed on a single wafer.

圖5至圖7是表示TO基板上之裝置部分的配置實施例的示意圖。參考圖5至圖7，其表示TO基板上之裝置部分的一般配置方式。將裝置部分配置來形成二維陣列，且切割道D設置來定義陣列。在圖5及圖6中，半球形圓圈44彼此分離。在圖7中，半球形圓圈44部分重疊，而彎曲表面21c彼此分離。裝置部分46之邊界以虛線表示。5 to 7 are schematic diagrams showing an example of the arrangement of device parts on a TO substrate. Referring to Figures 5 to 7, general arrangements of device portions on a TO substrate are shown. The device portions are configured to form a two-dimensional array, and cutting lanes D are provided to define the array. In FIGS. 5 and 6 , the hemispherical circles 44 are separated from each other. In Figure 7, the hemispherical circles 44 are partially overlapped, while the curved surfaces 21c are separated from each other. The boundaries of device portion 46 are shown in dashed lines.

本揭露所屬技術領域中具有通常知識者可從上述配置了解不同的變化例，例如VCSEL裝置部分之配置的較常使用版本及較少使用版本。A person of ordinary skill in the art to which this disclosure belongs can understand different variations from the above configuration, such as more commonly used versions and less commonly used versions of the configuration of the VCSEL device portion.

圖8是表示本揭露之一實施例之VCSEL之示意圖。VCSEL 11具有導電層35及限制載子及雷射光線之孔徑結構39。導電層35形成從第一電極31(位在鄰近於第一DBR鏡面13)至孔徑結構39之導電孔徑部分39a(位在第一DBR鏡面13正下方以與腔體對齊)之電性路徑。FIG. 8 is a schematic diagram showing a VCSEL according to an embodiment of the present disclosure. VCSEL 11 has a conductive layer 35 and an aperture structure 39 that confines carriers and laser light. The conductive layer 35 forms an electrical path from the first electrode 31 (located adjacent to the first DBR mirror 13) to the conductive aperture portion 39a of the aperture structure 39 (located directly below the first DBR mirror 13 to align with the cavity).

以下將說明製造VCSEL 11之方法的流程的一實施例，VCSEL 11包括導電層作用為電流散布層。An embodiment of the flow of a method for manufacturing the VCSEL 11 will be described below. The VCSEL 11 includes a conductive layer serving as a current spreading layer.

該方法包含以下步驟。 1、準備初始基底。其中，準備初始基底包括形成GaN之模板插栓，其在TO晶圓上沿垂直於第一軸向Ax1之第二軸向Ax2呈直線；及形成介電法布里-培洛濾波器結構於整個TO晶圓之上，且模板插栓之側壁部分地暴露及模板插栓之頂表面完全地暴露； 2、沿法布里-培洛濾波器結構之頂面從暴露的GaN之模板插栓成長，藉由ELO，非刻意摻雜的GaN層(n-GaN)，以形成在垂直第一及第二軸向Ax1、Ax2之第三軸向Ax3上具有約30至50微米之總寬度之半導體基底區域； 3、對半導體基底區域進行平坦化，以形成平坦化之n-GaN層； 4、在平坦化之n-GaN層上成長半導體積層，其包括裝置層，例如，用於包覆及n接觸之n-GaN、InGaN多量子井、AlGaN電子阻隔層、及p-GaN層，且視需求，p ++GaN層； 5、研磨TO晶圓之背側； 6、利用反應離子蝕刻轉移藉由迴流形成之光阻圖案至TO晶圓之背側，以形成單片(monolithic)微透鏡； 7、通過背側曝光從覆蓋裝置層之光阻膜製作光阻掩膜，在其間單片微透鏡用作聚焦曝光光線於定位在光阻膜附近之焦點； 8、利用光阻掩膜形成掩膜於裝置層上； 9、藉由掩膜執行離子佈植，以定義孔徑結構； 10、沉積透明導電氧化物(TCO)； 11、在半導體積層內製作台面結構； 12、沉積全向反射器(ODR)材料之鈍化層，其在台面結構之頂部具有開口； 13、沉積介電分散式布拉格反射器積層於台面結構之裝置層之平坦頂部上； 14、沉積電極金屬墊於包括台面結構之半導體積層上； 15、沉積介電分散式布拉格反射器積層於TO基板之彎曲表面； 16、設置接合材料於TO基板之背側； 17、分離製造後之TO晶圓，以形成VCSEL晶片； 18、接合VCSEL晶片至基座。 The method consists of the following steps. 1. Prepare the initial base. Among them, preparing the initial substrate includes forming a GaN template plug, which is in a straight line on the TO wafer along the second axis Ax2 perpendicular to the first axis Ax1; and forming a dielectric Fabry-Perot filter structure on the TO wafer. On the entire TO wafer, with the sidewalls of the template plugs partially exposed and the top surface of the template plugs completely exposed; 2. From the exposed GaN template plugs along the top surface of the Fabry-Perot filter structure Grow, by ELO, a non-intentionally doped GaN layer (n-GaN) to form a third axis Ax3 perpendicular to the first and second axes Ax1, Ax2 with a total width of about 30 to 50 microns. Semiconductor base region; 3. Planarize the semiconductor base region to form a planarized n-GaN layer; 4. Grow a semiconductor build-up layer on the planarized n-GaN layer, which includes a device layer, for example, for cladding And n-contact n-GaN, InGaN multi-quantum wells, AlGaN electron blocking layer, and p-GaN layer, and if required, p ++ GaN layer; 5. Grind the back side of the TO wafer; 6. Use reactive ion etching Transfer the photoresist pattern formed by reflow to the backside of the TO wafer to form a monolithic microlens; 7. Make a photoresist mask from the photoresist film covering the device layer through backside exposure, in which a single The microlens is used to focus the exposure light at a focus located near the photoresist film; 8. Use the photoresist mask to form a mask on the device layer; 9. Perform ion implantation through the mask to define the aperture structure; 10 , Deposit a transparent conductive oxide (TCO); 11. Create a mesa structure within a semiconductor stack; 12. Deposit a passivation layer of omnidirectional reflector (ODR) material with openings on the top of the mesa structure; 13. Deposit dielectric dispersion The Bragg reflector is laminated on the flat top of the device layer of the mesa structure; 14. The electrode metal pad is deposited on the semiconductor layer including the mesa structure; 15. The dielectric dispersed Bragg reflector is deposited on the curved surface of the TO substrate; 16 . Set the bonding material on the back side of the TO substrate; 17. Separate the manufactured TO wafer to form a VCSEL chip; 18. Bond the VCSEL chip to the base.

VCSEL晶片可被使用於使用者定義之應用，如光源、感測器或兩者。VCSEL chips can be used in user-defined applications such as light sources, sensors, or both.

圖9為本揭露之VCSEL之另一實施例的示意圖。VCSEL 11a具有穿隧接面結構36及孔徑結構39。穿隧接面結構36形成從第一電極31(位在相鄰於第一DBR鏡面13)至導電孔徑部分39a(位在第一DBR鏡面13之正下方且限制載子及雷射光線)之電性路徑。穿隧接面結構36包括p ++III族氮化物層36a於孔徑結構39內及n ++III族氮化物層36b於台面結構36上，且p ++III族氮化物層36a及n ++III族氮化物層36a彼此接觸，以形成穿隧接面。穿隧接面被附加的III族氮化物層36c所埋設。 FIG. 9 is a schematic diagram of another embodiment of the VCSEL of the present disclosure. The VCSEL 11a has a tunnel junction structure 36 and an aperture structure 39. The tunnel junction structure 36 is formed from the first electrode 31 (located adjacent to the first DBR mirror 13) to the conductive aperture portion 39a (located directly below the first DBR mirror 13 and limiting carriers and laser light). electrical path. The tunnel junction structure 36 includes a p ++ III nitride layer 36 a within the aperture structure 39 and an n ++ III nitride layer 36 b on the mesa structure 36 , and the p ++ III nitride layers 36 a and n + The + III nitride layers 36a contact each other to form a tunnel junction. The tunnel junction is buried by an additional III-nitride layer 36c.

以下將說明製造VCSEL 11a之方法的流程的一實施例，VCSEL 11a包括重摻雜n ++層及作為電流散布層之n型半導體層，n ++半導體層與最上層之p ++半導體層接觸，以形成穿隧接面36。 An embodiment of the flow of a method for manufacturing VCSEL 11a will be described below. VCSEL 11a includes a heavily doped n ++ layer and an n-type semiconductor layer as a current spreading layer, an n ++ semiconductor layer and an uppermost p ++ semiconductor layer. contact to form a tunnel junction 36.

該方法包含以下步驟。 1、準備初始基底。其中，準備初始基底包括形成GaN之模板插栓，其在TO晶圓上沿垂直於第一軸向Ax1之第二軸向Ax2呈直線；及形成介電法布里-培洛濾波器結構於整個TO晶圓之上，且模板插栓之側壁部分地暴露及模板插栓之頂表面完全地暴露； 2、沿法布里-培洛濾波器結構之頂面從暴露的GaN之模板插栓成長，藉由ELO，非刻意摻雜的GaN層(n-GaN)，以形成在垂直第一及第二軸向Ax1、Ax2之第三軸向Ax3上具有約30至50微米之總寬度之半導體基底區域； 3、對半導體基底區域進行平坦化，以形成平坦化之n-GaN層； 4、在平坦化之n-GaN層上成長半導體積層，其包括裝置層，例如，用於包覆及n接觸之n-GaN、InGaN多量子井、AlGaN電子阻隔層、p-GaN層、及p ++GaN層； 5、研磨TO晶圓之背側； 6、利用反應離子蝕刻轉移藉由迴流形成之光阻圖案至TO晶圓之背側，以形成單片(monolithic)微透鏡； 7、通過背側曝光從覆蓋裝置層之光阻膜製作光阻掩膜，在其間單片微透鏡用作聚焦曝光光線於定位在光阻膜附近之焦點； 8、利用光阻掩膜形成掩膜於裝置層上； 9、藉由掩膜執行離子佈植，以定義孔徑結構； 10、在形成孔徑結構後，再成長n ++GaN層以完成穿隧接面，並更沉積n-GaN層在n ++GaN層用來接觸及電流散布； 11、從包括裝置層及穿隧接面之半導體積層製作台面結構； 12、沉積全向反射器(ODR)材料之鈍化層，其在台面結構之頂面具有用作接觸區之開口； 13、沉積介電分散式布拉格反射器積層於裝置層之平坦頂部上； 14、沉積電極金屬墊於包括台面結構之半導體積層上； 15、沉積介電分散式布拉格反射器積層於TO基板之彎曲表面； 16、設置接合材料於TO晶圓之背側； 17、分離製造後之TO晶圓，以形成VCSEL晶片； 18、接合VCSEL晶片至基座。 The method consists of the following steps. 1. Prepare the initial base. Among them, preparing the initial substrate includes forming a GaN template plug, which is in a straight line on the TO wafer along the second axis Ax2 perpendicular to the first axis Ax1; and forming a dielectric Fabry-Perot filter structure on the TO wafer. On the entire TO wafer, with the sidewalls of the template plugs partially exposed and the top surface of the template plugs completely exposed; 2. From the exposed GaN template plugs along the top surface of the Fabry-Perot filter structure Grow, by ELO, a non-intentionally doped GaN layer (n-GaN) to form a third axis Ax3 perpendicular to the first and second axes Ax1, Ax2 with a total width of about 30 to 50 microns. Semiconductor base region; 3. Planarize the semiconductor base region to form a planarized n-GaN layer; 4. Grow a semiconductor build-up layer on the planarized n-GaN layer, which includes a device layer, for example, for cladding and n-contact n-GaN, InGaN multi-quantum wells, AlGaN electron blocking layer, p-GaN layer, and p ++ GaN layer; 5. Grind the back side of the TO wafer; 6. Use reactive ion etching to transfer by reflow The formed photoresist pattern is applied to the back side of the TO wafer to form a monolithic microlens; 7. Make a photoresist mask from the photoresist film covering the device layer through backside exposure, during which the monolithic microlens is Focus the exposure light on a focus positioned near the photoresist film; 8. Use the photoresist mask to form a mask on the device layer; 9. Perform ion implantation through the mask to define the aperture structure; 10. Form the aperture After the structure, an n ++ GaN layer is grown to complete the tunnel junction, and an n-GaN layer is deposited on the n ++ GaN layer for contact and current distribution; 11. From the semiconductor including the device layer and the tunnel junction Stack up to make the mesa structure; 12. Deposit a passivation layer of omnidirectional reflector (ODR) material, which has an opening for a contact area on the top surface of the mesa structure; 13. Deposit a dielectric dispersed Bragg reflector and stack it on the flat surface of the device layer on the top; 14. Deposit electrode metal pads on the semiconductor laminate including the mesa structure; 15. Deposit dielectric dispersed Bragg reflector lamination on the curved surface of the TO substrate; 16. Place bonding material on the back side of the TO wafer; 17 . Separate the manufactured TO wafer to form a VCSEL wafer; 18. Join the VCSEL wafer to the base.

VCSEL晶片可被使用於使用者定義之應用，如光源、感測器或兩者。VCSEL chips can be used in user-defined applications such as light sources, sensors, or both.

圖10為本揭露之VCSEL之再一實施例的示意圖。VCSEL 11b具有嵌入穿隧接面結構38，而不具有孔徑結構39。嵌入穿隧接面38位在第一DBR鏡面13正下方以與腔體對準，且覆蓋電流散布層以定義從第一電極31(位在相鄰於第一DBR鏡面13)至嵌入穿隧接面38(位在第一DBR鏡面13之正下方且限制載子及雷射光線)之電性路徑。FIG. 10 is a schematic diagram of yet another embodiment of the VCSEL of the present disclosure. VCSEL 11b has an embedded tunnel junction structure 38 without an aperture structure 39. The embedded tunnel junction 38 is located directly below the first DBR mirror 13 to align with the cavity, and covers the current spreading layer to define the embedded tunnel from the first electrode 31 (located adjacent to the first DBR mirror 13 ). The electrical path of the junction 38 (located directly below the first DBR mirror 13 and restricting carriers and laser light).

以下將說明製造VCSEL 11b之方法的流程的一實施例，VCSEL 11b包括具有重摻雜n ++及p ++半導體層之嵌入穿隧接面38、及覆蓋嵌入穿隧接面38及作為電流散布層之n型半導體層。嵌入穿隧接面結構38包括圖案化之p ++III族氮化物層38a及圖案化之n ++III族氮化物層38b，其等設置於台面結構37。p ++III族氮化物層38a及n ++III族氮化物層38b彼此接觸，以形成穿隧介面，並被附加的III族氮化物層38c所埋設。附加的III族氮化物層38c成長於台面結構37，以形成其實質上平坦的頂表面。第一電極31設置與III族氮化物層38c接觸，第一DBR鏡面13設置於III族氮化物層38c之頂部上。 An embodiment of the flow of a method for manufacturing VCSEL 11b will be described below. VCSEL 11b includes an embedded tunnel junction 38 with heavily doped n ++ and p ++ semiconductor layers, and covers the embedded tunnel junction 38 and acts as a current The n-type semiconductor layer of the diffusion layer. The embedded tunnel junction structure 38 includes a patterned p ++ III nitride layer 38 a and a patterned n ++ III nitride layer 38 b, which are disposed on the mesa structure 37 . The p ++ Group III nitride layer 38 a and the n ++ Group III nitride layer 38 b contact each other to form a tunneling interface and are buried by the additional Group III nitride layer 38 c. An additional III-nitride layer 38c is grown on the mesa structure 37 to form its substantially planar top surface. The first electrode 31 is disposed in contact with the III-nitride layer 38c, and the first DBR mirror 13 is disposed on top of the III-nitride layer 38c.

該方法包含以下步驟。 1、準備初始基底。其中，準備初始基底包括形成GaN之模板插栓，其在TO晶圓上沿垂直於第一軸向Ax1之第二軸向Ax2呈直線；及形成介電法布里-培洛濾波器結構於整個TO晶圓之上，且模板插栓之側壁部分地暴露及模板插栓之頂表面完全地暴露； 2、沿法布里-培洛濾波器結構之頂面從暴露的GaN之模板插栓成長，藉由ELO，非刻意摻雜的GaN層(n-GaN)，以形成在垂直第一及第二軸向Ax1、Ax2之第三軸向Ax3上具有約30至50微米之總寬度之半導體基底區域； 3、對半導體基底區域進行平坦化，以形成平坦化之n-GaN層； 4、在平坦化之n-GaN層上成長半導體積層，其包括裝置層，例如，用於包覆及n接觸之n-GaN、InGaN多量子井、AlGaN電子阻隔層、p-GaN層、及p ++GaN層； 5、研磨TO晶圓之背側； 6、利用反應離子蝕刻轉移藉由迴流形成之光阻圖案至TO晶圓之背側，以形成單片(monolithic)微透鏡； 7、再成長n ++GaN層於p ++GaN層上，以完成穿隧接面； 8、通過背側曝光從覆蓋裝置層之光阻膜製作光阻掩膜，在其間單片微透鏡用作聚焦曝光光線於定位在光阻膜附近之焦點； 9、利用光阻掩膜圖案化穿隧接面，以完成裝置層上之嵌入穿隧接面； 10、在形成嵌入穿隧接面後，沉積覆蓋嵌入穿隧接面之n-GaN層以形成平坦化之n-GaN頂面； 11、從半導體積層製作台面結構； 12、沉積全向反射器(ODR)材料之鈍化層，其在台面結構之頂面具有用作接觸區之開口； 13、沉積介電分散式布拉格反射器積層於裝置層之平坦頂部上； 14、沉積電極金屬墊於包括台面結構之半導體積層上； 15、沉積介電分散式布拉格反射器積層於TO基板之彎曲表面； 16、設置接合材料於TO晶圓之背側； 17、分離製造後之TO晶圓，以形成VCSEL晶片； 18、接合VCSEL晶片至基座。 The method consists of the following steps. 1. Prepare the initial base. Among them, preparing the initial substrate includes forming a GaN template plug, which is in a straight line on the TO wafer along the second axis Ax2 perpendicular to the first axis Ax1; and forming a dielectric Fabry-Perot filter structure on the TO wafer. On the entire TO wafer, with the sidewalls of the template plugs partially exposed and the top surface of the template plugs completely exposed; 2. From the exposed GaN template plugs along the top surface of the Fabry-Perot filter structure Grow, by ELO, a non-intentionally doped GaN layer (n-GaN) to form a third axis Ax3 perpendicular to the first and second axes Ax1, Ax2 with a total width of about 30 to 50 microns. Semiconductor base region; 3. Planarize the semiconductor base region to form a planarized n-GaN layer; 4. Grow a semiconductor build-up layer on the planarized n-GaN layer, which includes a device layer, for example, for cladding and n-contact n-GaN, InGaN multi-quantum wells, AlGaN electron blocking layer, p-GaN layer, and p ++ GaN layer; 5. Grind the back side of the TO wafer; 6. Use reactive ion etching to transfer by reflow The formed photoresist pattern reaches the back side of the TO wafer to form a monolithic microlens; 7. Then grow an n ++ GaN layer on the p ++ GaN layer to complete the tunnel junction; 8. Pass Backside exposure: Make a photoresist mask from the photoresist film covering the device layer, during which a single microlens is used to focus the exposure light at a focus positioned near the photoresist film; 9. Use the photoresist mask to pattern the tunnel connection surface to complete the embedded tunnel junction on the device layer; 10. After forming the embedded tunnel junction, deposit an n-GaN layer covering the embedded tunnel junction to form a planarized n-GaN top surface; 11. Fabricate the mesa structure from semiconductor laminations; 12. Deposit a passivation layer of omnidirectional reflector (ODR) material with openings for contact areas on the top surface of the mesa structure; 13. Deposit dielectric dispersed Bragg reflector laminations on the device layer on the flat top; 14. Deposit the electrode metal pad on the semiconductor laminate including the mesa structure; 15. Deposit the dielectric dispersed Bragg reflector laminate on the curved surface of the TO substrate; 16. Place the bonding material on the back side of the TO wafer ; 17. Separate the manufactured TO wafer to form a VCSEL chip; 18. Join the VCSEL chip to the base.

VCSEL晶片可被使用於使用者定義之應用，如光源、感測器或兩者。VCSEL chips can be used in user-defined applications such as light sources, sensors, or both.

更甚者，在背景技術裡之半導體晶片之製造當然包括成長磊晶裝置層於晶圓上；及切割裝置層及晶圓兩者。用以切割及晶片單一化的面積可能需要晶圓之處理面積的至少10%。What's more, the manufacturing of semiconductor wafers in the background art certainly includes growing an epitaxial device layer on the wafer; and cutting both the device layer and the wafer. The area used for dicing and wafer singulation may require at least 10% of the wafer processing area.

可能有三種方式來製造半導體晶片，例如延伸腔體VCSEL。There are three possible ways to fabricate semiconductor wafers such as extended cavity VCSELs.

方式1 首先，整個裝置層磊晶成長在平面的GaN基板上。在成長之後，GaN基板藉由在其背側研磨來薄化，接著形成用於光學腔體(如微透鏡)之彎曲表面在研磨之背側。 Way 1 First, the entire device layer is epitaxially grown on a flat GaN substrate. After growth, the GaN substrate is thinned by grinding on its back side, and then curved surfaces for optical cavities (such as microlenses) are formed on the grinding back side.

方式2 首先，整個裝置層磊晶成長在平面的GaN基板上。在成長之後，去除GaN基板來形成包含裝置層之裝置積層，接著將裝置積層接合至具有用於光學腔體(如微透鏡)之彎曲表面在其背側的外部基板。 Way 2 First, the entire device layer is epitaxially grown on a flat GaN substrate. After growth, the GaN substrate is removed to form a device buildup including the device layer, which is then bonded to an external substrate with curved surfaces for optical cavities (such as microlenses) on its backside.

方式3 方式3包括根據本揭露之製造流程。相比於方式1與方式2，在方式3中整合延伸腔體為不需要去除及薄化基板之簡單的步驟流程。切割道可配置在半導體部分之間。根據本揭露之製造流程允許裝置部分之各種配置，例如裝置部分在晶圓上之高堆積密度。 Way 3 Method 3 includes a manufacturing process according to the present disclosure. Compared with Method 1 and Method 2, integrating the extension cavity in Method 3 is a simple step process that does not require removal and thinning of the substrate. Cleats may be disposed between semiconductor portions. Fabrication processes in accordance with the present disclosure allow for various configurations of device parts, such as high packing densities of device parts on a wafer.

範例Example

透明氧化物(TO)基板材料 微透鏡在TO基板上與裝置層整合。裝置層亦成長在TO基板上。TO基板之材料可包括ZnO、Ga 2O 3、Al 2O 3、及其他對於紅外線、可見光、近紫外線、及/或深紫外線波長為透明之材料。根據本揭露之VCSEL裝置具有主要由低吸收之TO基板所主導的腔體。此可使VCSEL裝置之製造使用大尺寸之TO晶圓，如尺寸大於6吋之藍寶石晶圓，而可從單一製程中得到更多的裝置。 Transparent oxide (TO) substrate material microlenses are integrated with the device layer on the TO substrate. The device layer is also grown on the TO substrate. The material of the TO substrate may include ZnO, Ga 2 O 3 , Al 2 O 3 , and other materials that are transparent to infrared, visible, near ultraviolet, and/or deep ultraviolet wavelengths. VCSEL devices according to the present disclosure have a cavity dominated by a low-absorption TO substrate. This allows VCSEL devices to be manufactured using large-sized TO wafers, such as sapphire wafers larger than 6 inches, and more devices can be obtained from a single process.

模板插栓 從III族氮化物模板插栓設置之TO晶圓來說，III族氮化物模板插栓之高度可為1微米至10微米。用於模板插栓之III族氮化物層之晶體品質隨著其厚度增加。增加III族氮化物層之厚度可終結其內的螺旋差排(threading dislocation)，其源自在基板介面之晶格不匹配。再者，較大厚度可提供介電濾波器層厚的法布里-培洛濾波器結構，其在特性化及形成非常窄之帶通及較佳之帶通外側之抑制區域上有幫助。較厚之法布里-培洛濾波器嵌入模板插栓之下側壁部分，其可包括大部分缺陷。 template plug For TO wafers with III-nitride template plugs, the height of the III-nitride template plugs can range from 1 micron to 10 microns. The crystal quality of the III-nitride layer used for template plugging increases with its thickness. Increasing the thickness of the III-nitride layer terminates threading dislocation within it, which results from lattice mismatch at the substrate interface. Furthermore, a larger thickness can provide a Fabry-Perot filter structure with a dielectric filter layer thickness, which is helpful in characterizing and forming a very narrow bandpass and a better suppression region outside the bandpass. The thicker Fabry-Perot filter is embedded in the sidewall portion below the template plug, which can contain most defects.

例如，模板插栓可為條狀平行於六角形III族氮化物(如GaN)之＜11-20＞軸。在形成模板插栓中，蝕刻具有(0001)-極性方向III族氮化物膜之III族氮化物膜，可提供(11-22)側壁給之後形成之模板插栓條。這種側壁方向可加強從其而來隨後的側向成長。視需求，III族氮化物模板插栓側壁可具有可加強側向成長之另一方向。另一方面，模板插栓可具有使III族氮化物層沿介電濾波器層加強成長之期望方向。For example, the template plugs may be strips parallel to the <11-20> axis of a hexagonal III-nitride (eg, GaN). In forming the template plug, etching the Group III nitride film having the (0001)-polarity direction of the Group III nitride film can provide (11-22) sidewalls for the template plug strips formed later. This sidewall orientation may enhance subsequent lateral growth therefrom. If desired, the III-nitride template plug sidewalls may have another direction that enhances lateral growth. On the other hand, the template plugs may have a desired direction that enhances the growth of the III-nitride layer along the dielectric filter layer.

法布里-培洛濾波器/抗反射 使用法布里-培洛濾波器結構係用於製作窄帶通濾波器所期望之設計。法布里-培洛濾波器提供窄帶通及在帶通兩側之抑制區域。法布里-培洛濾波器可設在單一雷射腔體內，並包括具有一定厚度，通常為雷射波長之一半，之中央間隔物、及二個相同之反射鏡面，相同於DBR鏡面結構，夾置中央間隔物。 Fabry-Perot filter/anti-reflection The use of Fabry-Perot filter structures is a desirable design for making narrow bandpass filters. Fabry-Perot filters provide a narrow bandpass and suppression regions on both sides of the bandpass. The Fabry-Perot filter can be installed in a single laser cavity and includes a central spacer with a certain thickness, usually half the laser wavelength, and two identical reflecting mirrors, which are the same as the DBR mirror structure. Sandwich the center spacer.

通常的全介電結構如下：「基板1/(HL)m/2nH/(LH)m/基板2」。基板1及基板2可分別為GaN層及TO基板，亦即藍寶石。「H」及「L」分別表示具有高及低折射係數及其四分之一波光厚度之層，而「m」及「n」為整數。整體結構之通常厚度在450 nm之操作波長實施例可在1至2微米或更厚之範圍內。最佳化設計之法布里-培洛結構可允許非常窄之帶通，例如圍繞中央操作波長「λ0」之光學窗口「WIN」，且可具有2微米以上之厚度。「WIN」可藉由增加介電層及微調各層厚度來進一步窄化。法布里-培洛結構可具有小於1奈米之表面粗糙度，且較佳地，粗糙度在均方根(RMS)下可為0.1至1 nm。法布里-培洛結構之介電層可藉由濺鍍、原子層沉積、離子束沉積或其他方式來沉積。法布里-培洛濾波器包含二反射器及高係數材料中心層。二反射器之各者包括交替沉積高及低折射係數材料，如SiO 2and HfO 2，各者具有四分之一波厚度。高係數材料中心層具有中央操作波長一半之厚度，且設置在反射器之間。 The usual all-dielectric structure is as follows: "Substrate 1/(HL)m/2nH/(LH)m/Substrate 2". The substrate 1 and the substrate 2 can be a GaN layer and a TO substrate, that is, sapphire, respectively. "H" and "L" represent layers with high and low refractive index and quarter-wave optical thickness respectively, while "m" and "n" are integers. Operating wavelength embodiments with a typical thickness of 450 nm for the monolithic structure may be in the range of 1 to 2 microns or more. The optimally designed Fabry-Perot structure allows for very narrow bandpasses, such as an optical window "WIN" around the central operating wavelength "λ0", and can have a thickness of more than 2 microns. "WIN" can be further narrowed by adding dielectric layers and fine-tuning the thickness of each layer. The Fabry-Perot structure may have a surface roughness of less than 1 nm, and preferably, the roughness may be 0.1 to 1 nm in root mean square (RMS). The dielectric layer of the Fabry-Perot structure can be deposited by sputtering, atomic layer deposition, ion beam deposition or other methods. The Fabry-Perot filter consists of two reflectors and a central layer of high coefficient material. Each of the two reflectors consists of alternating deposits of high and low refractive index materials, such as SiO 2 and HfO 2 , each having a quarter wave thickness. A central layer of high coefficient material has a thickness of half the central operating wavelength and is disposed between the reflectors.

磊晶側向延長成長 配置在TO基板上之III族氮化物模板插栓可成形為條狀，且模板插栓之下側壁係嵌入法布里-培洛濾波器結構，其全由介電材料(如SiO 2、Ta 2O 5、HfO 5或其他類似材料)製成，且模板插栓之頂面係較少缺陷的。較佳地，插栓之厚度被設計為可達成產生非常窄帶通分布「WIN」之厚的法布里-培洛濾波器。插栓的側壁大約暴露1或2微米，且插栓之頂面寬度約1至10微米。該等長條以週期50至200微米來配置。該等長條可具有長度匹配於或更長於裝置部分之長度。極性模板插栓具有c-面(0001)之頂面方向，且據此模板插栓之長條可沿＜11-20＞軸定向。另一方面，無極性模板插栓具有a-面(11-20)或m-面(1100)之頂面方向，且相應地，模板插栓之長條可沿＜0001＞軸定向。再者，半極性模板插栓具有(20-21)面或(20-2-1)面之頂面方向，且相應地，模板插栓之長條可沿平行於[-1014]或[10-14]之方向定向。其他方向亦可對應於長條之定向來使用。 The III nitride template plugs arranged on the TO substrate by epitaxial lateral extension growth can be formed into strips, and the side walls under the template plugs are embedded with Fabry-Perot filter structures, which are all made of dielectric materials. (such as SiO 2 , Ta 2 O 5 , HfO 5 or other similar materials), and the top surface of the template plug has fewer defects. Preferably, the thickness of the plug is designed to achieve a thick Fabry-Perot filter that produces a very narrow bandpass distribution "WIN". The sidewalls of the plug are approximately 1 or 2 microns exposed, and the top surface of the plug is approximately 1 to 10 microns wide. The strips are arranged with a periodicity of 50 to 200 microns. The strips may have a length matching or longer than the length of the device portion. The polar template plug has a top surface orientation of the c-plane (0001) and accordingly the strip of the template plug can be oriented along the <11-20> axis. On the other hand, non-polar stencil plugs have a top surface orientation of a-plane (11-20) or m-plane (1100), and accordingly, the strips of the stencil plug can be oriented along the <0001> axis. Furthermore, the semi-polar template plug has a top surface direction of (20-21) plane or (20-2-1) plane, and accordingly, the long strip of the template plug can be along a direction parallel to [-1014] or [10 -14] direction orientation. Other directions can also be used corresponding to the orientation of the strip.

設置部分地暴露側壁之模板插栓的TO晶圓係被裝載至MOCVD反應器，來成長III族氮化物島。在某些實施例中，成長壓力的範圍為50至760 Torr，成長壓力較佳範圍為100至300 Torr以提供具較大寬度之島狀III族氮化物半導體層；成長溫度的範圍為900至1200℃；V族/III族比例的範圍為10至30,000；TMG流量的範圍為2至20每分鐘的標準立方釐米(sccm)；NH 3流量的範圍為0.1至10每分鐘的標準升(slm)；且僅氫氣、或氫氣及氮氣兩者被使用為載體氣體。為取得平滑表面，III族氮化物島之成長條件可被最佳化。最後，III族氮化物層，例如GaN層25，藉由ELO被成長來完成各島，以使GaN層25具有約1至10微米的厚度及50微米的寬度，且成長後之III族氮化物島彼此間隔約15微米。 TO wafers with template plugs that partially expose the sidewalls are loaded into the MOCVD reactor to grow III-nitride islands. In some embodiments, the growth pressure ranges from 50 to 760 Torr, and the growth pressure preferably ranges from 100 to 300 Torr to provide an island-shaped Group III nitride semiconductor layer with a larger width; the growth temperature ranges from 900 to 1200°C; Group V/III ratio range from 10 to 30,000; TMG flow rate from 2 to 20 standard cubic centimeters per minute (sccm); NH flow rate from 0.1 to 10 standard liters per minute (slm ); and only hydrogen, or both hydrogen and nitrogen are used as carrier gases. To obtain a smooth surface, the growth conditions of III-nitride islands can be optimized. Finally, a Group III nitride layer, such as GaN layer 25, is grown by ELO to complete each island, so that the GaN layer 25 has a thickness of about 1 to 10 microns and a width of 50 microns, and the grown Group III nitride The islands are approximately 15 microns apart from each other.

具有部分地暴露側壁之模板插栓的TO晶圓具有III族氮化物介面(暴露的模板插栓)及介電介面(法布里-培洛濾波器層)在其頂部，且這兩個介面之比例以「填充因子(fill factor)」指稱。在反應器中，III族氮化物可被沉積在III族氮化物介面，且不能被沉積在介電介面，即以「填充因子」表示。在本揭露之TO晶圓，填充因子小於1。填充因子偏離1之沉積可能因大量的III族氮化物原子，而造成反應器內之III族氮化物原子積聚較多在成長面的邊緣，其發生在成長與不成長介面間的邊界附近，且據此，相比於中央區域，其可能在III族氮化物島之邊緣產生較厚的GaN層。A TO wafer with a stencil plug with partially exposed sidewalls has a III-nitride interface (exposed stencil plug) and a dielectric interface (Fabry-Perot filter layer) on top of it, and these two interfaces The ratio is referred to as the "fill factor". In the reactor, III-nitride can be deposited at the III-nitride interface but cannot be deposited at the dielectric interface, which is represented by the "fill factor." In the TO wafer of the present disclosure, the fill factor is less than 1. Depositions with a filling factor that deviates from 1 may cause a large number of Group III nitride atoms in the reactor to accumulate at the edge of the growth surface, which occurs near the boundary between the growth and non-growth interfaces, and Accordingly, it is possible to produce a thicker GaN layer at the edge of the III-nitride island compared to the central region.

研磨 由於大量的III族氮化物原子，從各模板插栓成長之III族氮化物島在其頂部可能具有凹狀。為了取得平面的裝置層，III族氮化物島初始成長到5至10微米之厚度，接著藉由研磨或蝕刻來平坦化以形成具有平頂面之III族氮化物基底。在這個平頂面，成長包含p-GaN、n-GaN、InGaN及AlGaN層之裝置層。具體而言，由於包括n-GaN、MQW、及p-GaN、及/或穿隧接面層之裝置層整體厚度可能不會超過700 nm，於再成長，大量III族氮化物原子造成的邊緣成長為可忽略的小。 Grind Due to the large number of III-nitride atoms, the III-nitride islands grown from each template plug may have a concave shape on their tops. To obtain a planar device layer, III-nitride islands are initially grown to a thickness of 5 to 10 microns and then planarized by grinding or etching to form a III-nitride substrate with a flat top surface. On this flat top surface, device layers including p-GaN, n-GaN, InGaN and AlGaN layers are grown. Specifically, since the overall thickness of the device layer including n-GaN, MQW, and p-GaN, and/or the tunnel junction layer may not exceed 700 nm, during re-growth, the edge caused by a large number of Group III nitride atoms Grow into negligibly small.

裝置層成長 III族氮化物基半導體層、及穿隧接面或嵌入的穿隧接面層被再成長於III族氮化物基底之研磨面。半導體積層及半導體部分15各者包括III族氮化物化合物之半導體裝置層，III族氮化物化合物可包括In、Al、及/或B，以及摻雜物或不純物，如Mg、Si、Zn、O、C、及H。III族氮化物基半導體之裝置層通常包含大於三層，包括n型層、未摻雜層及p-型層。裝置層具體包含氮化鎵基材料，如GaN層、AlGaN層、InGaN層、及AlGaInN層。例如，這些裝置層之磊晶成長係在MOCVD或MBE反應器內進行。裝置區域包含厚的n-GaN層、多量子井(例如，3 nm厚MQW及7 nm厚屏障)、10 nm厚p-AlGaN電子阻障層(EBL)、10 0nm厚p-GaN層、及10 nm厚p ++GaN層。 The device layer grows a Group III nitride-based semiconductor layer, and the tunnel junction or embedded tunnel junction layer is re-grown on the polished surface of the Group III nitride substrate. The semiconductor stack and semiconductor portion 15 each include a semiconductor device layer of a Group III nitride compound, which may include In, Al, and/or B, and dopants or impurities such as Mg, Si, Zn, O , C, and H. Device layers of Group III nitride-based semiconductors typically include more than three layers, including an n-type layer, an undoped layer, and a p-type layer. The device layer specifically includes gallium nitride-based materials, such as GaN layer, AlGaN layer, InGaN layer, and AlGaInN layer. For example, epitaxial growth of these device layers is performed in MOCVD or MBE reactors. The device area includes a thick n-GaN layer, multiple quantum wells (e.g., 3 nm thick MQWs and 7 nm thick barrier), a 10 nm thick p-AlGaN electronic barrier layer (EBL), a 10 0 nm thick p-GaN layer, and 10 nm thick p ++ GaN layer.

當ITO作用為電流散布層，最上層之裝置層可為p ++GaN。反之，附加的10 nm厚n ++GaN層被沉積在p ++GaN之頂部來用作穿隧結構。對於嵌入穿隧接面及穿隧接面之設計，50 nm厚n-GaN層之電流散布層被沉積在附加的n ++GaN層之上。 When ITO acts as a current spreading layer, the uppermost device layer can be p ++ GaN. Instead, an additional 10 nm thick n ++ GaN layer is deposited on top of the p ++ GaN to serve as a tunneling structure. For embedded tunnel junction and tunnel junction designs, a current spreading layer of a 50 nm thick n-GaN layer is deposited on top of an additional n ++ GaN layer.

具體而言，在穿隧接面設計中，半導體積層之成長在成長p ++GaN層之後停止，接著離子佈植被執行以形成孔徑結構，其後n ++GaN層及n型GaN層被沉積在孔徑結構上。 Specifically, in the tunnel junction design, the growth of the semiconductor stack is stopped after growing the p ++ GaN layer, then ion implantation is performed to form the aperture structure, and then the n ++ GaN layer and the n-type GaN layer are deposited on the pore structure.

具體而言，在嵌入穿隧接面設計中，半導體積層之成長在成長n ++GaN層於p ++GaN層之上後停止，接著n ++GaN層及p ++GaN層被圖案化來形成圖案化穿隧接面，其後n型GaN層被沉積在圖案化穿隧接面。再成長可利用MOCVD或MBE(molecular beam epitaxy)反應器任一者來執行。利用MBE而非MOCVD可於穿隧接面再成長中消除p-GaN之氫氣再鈍化(hydrogen re-passivation)。 Specifically, in the embedded tunnel junction design, the growth of the semiconductor stack stops after growing the n ++ GaN layer on top of the p ++ GaN layer, and then the n ++ GaN layer and the p ++ GaN layer are patterned To form a patterned tunnel junction, an n-type GaN layer is then deposited on the patterned tunnel junction. Regrowth can be performed using either MOCVD or MBE (molecular beam epitaxy) reactors. Using MBE instead of MOCVD can eliminate hydrogen re-passivation of p-GaN during tunnel junction re-growth.

另一方面，本揭露所描述之設計可包括處理島狀III族氮化物裝置層。為了回復氫氣再鈍化，p型氮化鎵基材料(如p-GaN)之活化可通過側向擴散來達成，而被穿隧接面或電流散布層(n-GaN)嵌設的p-GaN層可被活化。據此，特定的裝置層的設計可根據製造參數(如成本或良率)來選擇MBE或MOCVD。On the other hand, the designs described in this disclosure may include processing island III-nitride device layers. In order to restore hydrogen re-passivation, activation of p-type gallium nitride-based materials (such as p-GaN) can be achieved through lateral diffusion, and p-GaN embedded in the tunnel junction or current spreading layer (n-GaN) Layers can be activated. Accordingly, the design of a specific device layer may select MBE or MOCVD based on manufacturing parameters such as cost or yield.

微透鏡之形成 單片微透鏡被使用於孔徑製造程序中，尤其是在背側之單片透鏡可通過彎曲表面之透鏡效應來聚焦曝光光線於孔徑結構之位置，彎曲表面係用來形成彎曲第二DBR鏡面於VCSEL產品中。 The formation of microlenses Single-chip microlenses are used in the aperture manufacturing process. Especially the single-chip lens on the back side can focus the exposure light at the position of the aperture structure through the lens effect of the curved surface. The curved surface is used to form a curved second DBR mirror. in VCSEL products.

TO基板可為雙側研磨基板，且相應地，在背表面之微透鏡圖案被定位，以使透鏡之最後位置及形狀可有用地來正確地與在半導體部分之頂面之孔徑部分的位置對位。單片微透鏡通過光阻(PR)迴流及乾蝕刻製程來製造。例如，雙側研磨藍寶石基板可為(0001)-定向2-in 晶圓，且若可行，較大直徑之晶圓亦可被使用。具體而言，圓PR盤之陣列藉由標準光微影技術被圖案化於研磨藍寶石基板之背側。在到達PR之相變溫度後，PR圖案開始迴流以形成各圖案之中央為最厚之凸狀。接著，凸狀被轉移至藍寶石基板，例如利用電感耦合等離子體(ICP)系統。最佳化之蝕刻條件可達成表面粗糙度低於1奈米，且較佳地，藍寶石之蝕刻表面可具有表面粗糙度介於0.1 nm至0.5 nm，以避免光學散射及相關光學耗損。The TO substrate can be a double-sided ground substrate, and accordingly the microlens pattern on the back surface is positioned so that the final position and shape of the lens can be usefully aligned correctly with the position of the aperture portion on the top surface of the semiconductor portion Bit. Single-chip microlenses are manufactured through photoresist (PR) reflow and dry etching processes. For example, a double-sided ground sapphire substrate can be a (0001)-oriented 2-in wafer, and if feasible, larger diameter wafers can also be used. Specifically, an array of circular PR disks is patterned on the backside of a ground sapphire substrate using standard photolithography techniques. After reaching the phase transition temperature of PR, the PR pattern begins to reflow to form a convex shape with the thickest center in each pattern. Next, the bumps are transferred to a sapphire substrate, for example using an inductively coupled plasma (ICP) system. Optimized etching conditions can achieve a surface roughness of less than 1 nanometer, and preferably, the etched surface of sapphire can have a surface roughness between 0.1 nm and 0.5 nm to avoid optical scattering and related optical losses.

離子佈植 離子佈植用來藉由在孔徑外側損害GaN基層，以在GaN基層形成電子、光學孔徑，且損害的GaN基材料不再有導電性。這個方法可保持頂面平坦，且可在孔徑區域與損害區域之間創造非常輕微的折射率引導(index guiding)。損害區域可具有高於孔徑區域之未佈植材料之吸收值，然而在腔體內會具有增加的光學耗損。重離子，如鋁(Al)、硼(B)及其他，可被使用於離子佈植程序。離子佈植之基本概念為創造導電性孔徑。 ion implantation Ion implantation is used to form electronic and optical apertures in the GaN base layer by damaging the GaN base layer outside the aperture, and the damaged GaN base material is no longer conductive. This approach keeps the top surface flat and creates a very slight index guiding between the aperture area and the damage area. The damaged area may have a higher absorption value than the unimplanted material in the aperture area, however there will be increased optical loss within the cavity. Heavy ions, such as aluminum (Al), boron (B), and others, can be used in ion implantation procedures. The basic concept of ion implantation is to create conductive pores.

透明導電層 在離子佈植後，透明導電層可被積層於裝置層之上，或對於穿隧接面之III族氮化物之再成長，配合或不配合離子佈植程序在裝置層上進行。ITO可被用作通常使用的透明電流散布層。將ITO包括至VCSEL可能導致額外吸收，但這個吸收可藉由使電磁波之強度在ITO層附近較低來減少。另一種方式，如穿隧接面，亦可被用來散布電流，並使光吸收較低。 Transparent conductive layer After ion implantation, a transparent conductive layer may be laminated on the device layer, or regrowth of III-nitride at the tunnel junction may be performed on the device layer with or without the ion implantation process. ITO can be used as a commonly used transparent current spreading layer. Including ITO into the VCSEL may result in additional absorption, but this absorption can be reduced by making the intensity of the electromagnetic waves lower near the ITO layer. Another method, such as a tunnel junction, can also be used to spread the current and make the light absorption lower.

穿隧接面 穿隧接面方式可使電洞載子經由n型半導體被注入裝置之主動層，因為高摻雜n型區域及高摻雜p型區域之間的接面允許電子在逆向偏壓下，從p型區域之價帶穿隧至n型區域的導帶，藉此造成導電載子之型態改變。由於穿隧機率指數性地關聯於穿隧距離，較佳為高摻雜區域(~10 19/cm 3或以上) 以製作薄空乏寬度來有效率地操作。在藉由離子佈植形成孔徑結構後，n ++/n-GaN層(厚度10/50 nm)被磊晶地再成長於裝置層之最上層p ++GaN，以形成穿隧接面及電流散布層。 Tunnel junction The tunnel junction method allows hole carriers to be injected into the active layer of the device through the n-type semiconductor because the junction between the highly doped n-type region and the highly doped p-type region allows electrons to be reversely deflected Press down, tunneling from the valence band in the p-type region to the conduction band in the n-type region, thereby causing a change in the pattern of conductive carriers. Since the tunneling probability is exponentially related to the tunneling distance, highly doped regions (~10 19 /cm 3 or above) are preferred to create thin depletion widths for efficient operation. After forming the aperture structure through ion implantation, the n ++ /n-GaN layer (thickness 10/50 nm) is epitaxially grown on the uppermost p ++ GaN layer of the device layer to form the tunnel junction and current spreading layer.

嵌入穿隧接面 嵌入穿隧接面不僅可工作如載子型態改變者，亦可如電流孔徑，且藉由成長高摻雜p ++/n ++層(厚度10/10 nm)之平面穿隧接面來形成；利用TO基板之微透鏡在期望的孔徑位置，形成掩膜於高摻雜接面層；及透過掩膜蝕刻高摻雜接面層。嵌入穿隧接面不一定與電流孔徑(藉由離子佈植形成)結合，視需求可與電流孔徑結合。 Embedded Tunneling Junction Embedded tunneling junction operates not only as a carrier pattern changer, but also as a current aperture, and by growing a highly doped p ++ /n ++ layer (thickness 10/10 nm) The planar tunnel junction is formed; the microlens of the TO substrate is used to form a mask on the highly doped junction layer at the desired aperture position; and the highly doped junction layer is etched through the mask. The embedded tunnel junction is not necessarily combined with a current aperture (formed by ion implantation), but can be combined with a current aperture if desired.

DBR鏡面 本揭露之DBR鏡面各包括交替的介電層彼此結合以形成反射鏡面，且設置於VCSEL之頂部與底部以形成光學腔體。介電DBR鏡面例如可包括介電四分之一波長厚SiO 2/Ta 2O 5層。對(pair)數相關於其反射率，而在VCSEL之p側之DBR鏡面的反射率可小於彎曲表面的反射率，以提高光線出射。 DBR Mirrors The DBR mirrors of the present disclosure each include alternating dielectric layers bonded to each other to form reflective mirrors, and are disposed on the top and bottom of the VCSEL to form an optical cavity. A dielectric DBR mirror may include, for example, a dielectric quarter-wavelength thick SiO 2 /Ta 2 O 5 layer. The pair number is related to its reflectivity, and the reflectivity of the DBR mirror on the p side of the VCSEL can be smaller than the reflectivity of the curved surface to improve light emission.

全向反射器(ODR) ODR設置於光學腔體外側，且可反射從行進路徑洩漏的光線。ODR亦設置於陽極電極及陰極電極之間，並作用來保護及/或鈍化裝置層避免可能的汙染及直接接觸。 Omnidirectional Reflector (ODR) The ODR is placed outside the optical cavity and can reflect light leaking from the traveling path. The ODR is also disposed between the anode and cathode electrodes and serves to protect and/or passivate the device layers from possible contamination and direct contact.

金屬墊 金屬，如金(Au)、鋁(Al)、鎳(Ni)、鉑(Pd)、鈦(Ti)、銦(In)及其他，可在VCSEL之製造中被使用作為金屬墊之材料。金屬層可藉由濺鍍、蒸鍍或電鍍來形成。 metal pad Metals, such as gold (Au), aluminum (Al), nickel (Ni), platinum (Pd), titanium (Ti), indium (In) and others, can be used as metal pad materials in the manufacture of VCSELs. The metal layer can be formed by sputtering, evaporation or electroplating.

應用Application

資料中心 隨著雲端運算及串流服務的增加，資料通訊之要求增加了資訊傳遞硬體(如邊射型雷射及VCSEL)的需求，其提供伺服器在資料中心中之伺服器資料傳遞。在大部分的資料通訊，VCSEL操作於紅外線(IR)波長。根據上述實施例之III族氮化物VCSEL可被用於相關於資料中心之資料通訊。 Data Center With the increase in cloud computing and streaming services, data communication requirements have increased the demand for information delivery hardware (such as edge-fire lasers and VCSELs), which provide server data delivery to servers in data centers. In most data communications, VCSELs operate at infrared (IR) wavelengths. III-nitride VCSELs according to the above embodiments can be used for data communications related to data centers.

光源 GaN基光源，如LED，已在住宅及汽車光源造成巨大的轉變。在未來的智慧城市及智慧基礎建設，光源與通訊服務結合是非常令人期待的。VCSEL可能是LED及邊射型雷射二極體較佳的替代品。上述實施例中發展之程序可被用於製造可應用於光源應用的VCSEL單元。 light source GaN-based light sources, such as LEDs, have caused a huge shift in residential and automotive lighting. In future smart cities and smart infrastructure, the combination of light sources and communication services is very exciting. VCSEL may be a better alternative to LED and edge-emitting laser diodes. The procedures developed in the above embodiments can be used to fabricate VCSEL units that can be used in light source applications.

可見光通訊 雷射光線可通過光照上網技術(Li-Fi)被用於資料傳遞及通訊應用。隨著IoT裝置的快速增加，資料傳輸之需求持續擴大。RF頻譜逐漸飽和，而新的頻率需要趕上持續增加的需求。採用GaN基VCSEL至存在的LED架構係比利用邊射型雷射取代他們更簡單。根據上述實施例之III族氮化物VCSEL可被使用於可見光通訊。 visible light communication Laser light can be used for data transmission and communication applications through lighting Internet technology (Li-Fi). With the rapid increase of IoT devices, the demand for data transmission continues to expand. The RF spectrum is becoming saturated, and new frequencies are needed to keep up with increasing demand. It is simpler to adapt GaN-based VCSELs to existing LED architectures than to replace them with edge-emitting lasers. The Group III nitride VCSEL according to the above embodiments can be used for visible light communication.

近眼顯示器(Near eye displays) 近眼顯示器會代表消費電子之下一波主流浪潮，且為虛擬實境(VR)及擴增實境(AR)技術的基礎。目前，微LED為顯示器的大多數選擇，然而，即使目前VCSEL研究的有限進展，VCSEL仍可能被導入微型顯示器及近眼顯示器。VCSEL可提供相對低光功率，其對保持眼睛安全有益，及相對低發散及圓對稱，其可降低附加光學元件的數量，因此可使裝置小型化。VCSEL之2D陣列整合比邊射型雷射簡單。根據上述實施例之III族氮化物VCSEL可被使用於這些應用。 Near eye displays Near-eye displays will represent the next mainstream wave of consumer electronics and are the basis for virtual reality (VR) and augmented reality (AR) technologies. Currently, micro-LEDs are the majority choice for displays. However, even with the current limited progress in VCSEL research, VCSELs may still be introduced into micro-displays and near-eye displays. VCSELs can provide relatively low optical power, which is beneficial for eye safety, and relatively low divergence and circular symmetry, which can reduce the number of additional optical components and therefore allow for device miniaturization. VCSEL 2D array integration is simpler than edge-emitting lasers. III-nitride VCSELs according to the embodiments described above can be used in these applications.

根據上述實施例之功效如下： 以二反射鏡面定義VCSEL腔體來使用足夠長的腔體，而不產生過多的繞射耗損，且增加法布里-培洛濾波器來降低為單一模態操作； 因夠長的腔體及/或III族氮化物層上電性接觸配置，而有較佳的熱管理； 藉由與TO基板連接之GaN模板插栓而有較佳熱導性，藉此改善熱效率； 使用低成本之大尺寸模板基板，如GaN on Sapphire； 藉由使用島狀III族氮化物來最小化半導體層的浪費； 消除製程中之基板去除及接合程序，因此改善製造參數；及 藉由使用ELO技術解鎖在VCSEL之製作中使用外部基板。 上述實施例可在效率、減少製造成本及消除複雜程序提供明顯的改善。 上述實施例提出在VCSEL中整合法布里-培洛濾波器，可讓磊晶側向延長成長改善裝置層之晶體品質。 使用包括類似於GaN/藍寶石之結構的模板TO材料基板可使裝置層成長於磊晶側向延長成長翼部，其通常提供無缺陷或低缺陷，因此可達成高晶體品質。 The effects according to the above embodiment are as follows: Define the VCSEL cavity with two reflecting mirrors to use a sufficiently long cavity without causing excessive diffraction losses, and add a Fabry-Perot filter to reduce the operation to a single mode; Better thermal management due to long enough cavity and/or electrical contact arrangement on the III-nitride layer; The GaN template plug connected to the TO substrate has better thermal conductivity, thereby improving thermal efficiency; Use low-cost large-size template substrates, such as GaN on Sapphire; Minimize semiconductor layer waste by using island III nitrides; Eliminate substrate removal and bonding procedures in the manufacturing process, thus improving manufacturing parameters; and Unlocking the use of external substrates in VCSEL fabrication by using ELO technology. The above-described embodiments can provide significant improvements in efficiency, reduced manufacturing costs, and elimination of complex procedures. The above embodiment proposes integrating a Fabry-Perot filter in the VCSEL to allow lateral epitaxial growth to improve the crystal quality of the device layer. Using a template TO material substrate that includes a GaN/sapphire-like structure allows device layers to be grown in epitaxial lateral extension wings, which typically provide no or low defects, thus achieving high crystal quality.

觀點1 一種VCSEL，其包含： 氧化物基板，具有第一面及位在該第一面之相對側之第二面，第二面包括彎曲表面；半導體部分，設置於該氧化物基板之該第一面；介電濾波器層，設置在該半導體部分與該氧化物基板之該第一面之間，並具有反射光譜，該反射光譜提供光學窗口；第一分散式布拉格反射器(DBR)鏡面，該半導體部分設置在該介電濾波器層及該第一DBR鏡面之間；及第二DBR鏡面，設置於該氧化物基板之該彎曲表面，該第一DBR鏡面、該半導體部分、該介電濾波器層、該氧化物基板及該第二DBR鏡面於第一軸向上配置以形成延伸腔體，其中該半導體部分包括p型III族氮化物區域、III族氮化物區域、及位在該p型III族氮化物區域及該III族氮化物區域之間的該III族氮化物主動區域，該p型III族氮化物區域、該III族氮化物主動區域及該III族氮化物區域在該第一軸向上配置，且該III族氮化物區域包括n型III族氮化物區域。 Viewpoint 1 A VCSEL containing: An oxide substrate having a first side and a second side located on an opposite side of the first side, the second side including a curved surface; a semiconductor portion disposed on the first side of the oxide substrate; a dielectric filter layer , is disposed between the semiconductor portion and the first surface of the oxide substrate, and has a reflection spectrum that provides an optical window; a first distributed Bragg reflector (DBR) mirror, the semiconductor portion is disposed in the medium between the electrical filter layer and the first DBR mirror; and a second DBR mirror disposed on the curved surface of the oxide substrate, the first DBR mirror, the semiconductor part, the dielectric filter layer, and the oxide The substrate and the second DBR mirror are arranged in the first axis direction to form an extended cavity, wherein the semiconductor portion includes a p-type Group III nitride region, a Group III nitride region, and a p-type Group III nitride region and The Group III nitride active region between the Group III nitride regions, the p-type Group III nitride region, the Group III nitride active region and the Group III nitride region are arranged in the first axis direction, and the The Group III nitride region includes an n-type Group III nitride region.

觀點2 如觀點1所述的垂直共振腔面射型雷射，其中該介電濾波器層具有延伸在該第一軸向的通孔，該垂直共振腔面射型雷射更包含：III族氮化物模板插栓，設置於該通孔內，並從該氧化物基板延伸至該通孔內之該半導體部分。 Viewpoint 2 The vertical resonant cavity surface-emitting laser as described in viewpoint 1, wherein the dielectric filter layer has a through hole extending in the first axial direction, and the vertical resonant cavity surface-emitting laser further includes: Group III nitride A template plug is disposed in the through hole and extends from the oxide substrate to the semiconductor portion in the through hole.

觀點3 如觀點2所述的垂直共振腔面射型雷射，其中該 III族氮化物模板插栓包含在該通孔內之嵌設部分及突出至該半導體部分之突起，且該III族氮化物模板插栓之該嵌設部分設置與該氧化物基板之該第一面接觸。 Viewpoint 3 The vertical resonant cavity surface-emitting laser as described in viewpoint 2, wherein the III-nitride template plug includes an embedded part in the through hole and a protrusion protruding to the semiconductor part, and the III-nitride template plug The embedded portion of the plug is disposed in contact with the first surface of the oxide substrate.

觀點4 如觀點1~3任一者所述的垂直共振腔面射型雷射， 其中該氧化物基板之該彎曲表面具有中心線，該III族氮化物模板插栓與該彎曲表面之該中心線彼此錯位。 Viewpoint 4 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the curved surface of the oxide substrate has a centerline, and the group III nitride template plug and the centerline of the curved surface are mutually exclusive. Dislocation.

觀點5 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該延伸腔體之長度大於50微米。 Viewpoint 5 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the length of the extended cavity is greater than 50 microns.

觀點6 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該彎曲表面具有大於50微米之曲率半徑。 Viewpoint 6 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the curved surface has a radius of curvature greater than 50 microns.

觀點7 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該第二分散式布拉格反射器鏡面係彎曲的，該第一分散式布拉格反射器鏡面係平面的，且該第一分散式布拉格反射器鏡面與該第二分散式布拉格反射器鏡面之間的距離係50微米以上。 Viewpoint 7 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the second dispersed Bragg reflector mirror is curved, the first dispersed Bragg reflector mirror is planar, and the third dispersed Bragg reflector mirror is planar. The distance between a dispersed Bragg reflector mirror surface and the second dispersed Bragg reflector mirror surface is more than 50 microns.

觀點8 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該半導體部分包含台面結構，該台面結構包括基座區域及設置於該基座區域之台面區域，該垂直共振腔面射型雷射更包含：導電層，設置於該半導體部分，該導電層之一部分設置在該第一分散式布拉格反射器鏡面與該半導體部分之間；第一電極，設置於該導電層並位於該第一分散式布拉格反射器鏡面外側，該第一電極設置與該導電層接觸；及第二電極，設置於該台面結構之該基座區域之一面。 Viewpoint 8 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the semiconductor part includes a mesa structure, the mesa structure includes a base region and a mesa region provided in the base region, and the vertical resonant cavity The surface-emitting laser further includes: a conductive layer disposed on the semiconductor part, a part of the conductive layer being disposed between the first distributed Bragg reflector mirror and the semiconductor part; a first electrode disposed on the conductive layer and Located outside the first distributed Bragg reflector mirror, the first electrode is arranged in contact with the conductive layer; and the second electrode is arranged on one surface of the base area of the mesa structure.

觀點9 如觀點8所述的垂直共振腔面射型雷射，其中該半導體部分具有第一面及位在該半導體部分之該第一面之相對側之第二面，該介電濾波器層設置於該半導體部分之該第一面，且該導電層設置於該半導體部分之該第二面。 Viewpoint 9 The vertical resonant cavity surface emitting laser as described in viewpoint 8, wherein the semiconductor part has a first surface and a second surface located on the opposite side of the first surface of the semiconductor part, and the dielectric filter layer is disposed on The first side of the semiconductor part, and the conductive layer is disposed on the second side of the semiconductor part.

觀點10 如觀點1~3任一者所述的垂直共振腔面射型雷射， 其中該半導體部分包括孔徑結構，該孔徑結構包括延伸在該第一軸向之孔徑區域、及圍繞該孔徑區域之隔離區域，且該第一分散式布拉格反射器鏡面、該孔徑區域及該第二分散式布拉格反射器鏡面沿不通過該III族氮化物模板插栓之軸來配置。 Viewpoint 10 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the semiconductor part includes an aperture structure, the aperture structure includes an aperture area extending in the first axial direction, and an isolation surrounding the aperture area area, and the first DBR mirror, the aperture area, and the second DBR mirror are configured along an axis that does not pass through the Group III nitride template plug.

觀點11 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該半導體部分之總厚度係約0.5微米以上。 Viewpoint 11 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the total thickness of the semiconductor part is about 0.5 microns or more.

觀點12 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該介電濾波器層包括法布里-培洛濾波器，提供該反射光譜給該光學窗口。 Viewpoint 12 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the dielectric filter layer includes a Fabry-Perot filter to provide the reflection spectrum to the optical window.

觀點13 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該氧化物基板包括氧化鋁、氧化鋅、或氧化鎵其中之一。 Viewpoint 13 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

觀點14 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該第一分散式布拉格反射器鏡面之反射率低於該第二分散式布拉格反射器鏡面之反射率。 Viewpoint 14 The vertical resonant cavity surface emitting laser as described in any one of viewpoints 1 to 3, wherein the reflectivity of the first dispersed Bragg reflector mirror is lower than the reflectivity of the second dispersed Bragg reflector mirror.

觀點15 如觀點1~3任一者所述的垂直共振腔面射型雷射，其中該III族氮化物主動區域包含量子井結構，產生具有波長在該第一分散式布拉格反射器鏡面之第一反射光譜中、在該第二分散式布拉格反射器鏡面之第二反射光譜中、及在該介電濾波器層之該光學窗口中之光線。 Viewpoint 15 The vertical resonant cavity surface-emitting laser as described in any one of viewpoints 1 to 3, wherein the group III nitride active region includes a quantum well structure, generating a first reflection with a wavelength on the mirror surface of the first dispersed Bragg reflector light in the spectrum, in the second reflection spectrum of the second dispersed Bragg reflector mirror, and in the optical window of the dielectric filter layer.

觀點16 一種製造垂直共振腔面射型雷射之方法，該方法包含：準備初始基底，該初始基板包括氧化物基底、III族氮化物模板插栓、及介電濾波器層，該氧化物基底具有第一面及位在該氧化物基底之該第一面之相對側之第二面，該介電濾波器層及該III族氮化物模板插栓位於該氧化物基底之該第一面，該介電濾波器層具有反射光譜，且該反射光譜提供光學窗口；從位於該介電濾波器層上之該III族氮化物模板插栓成長III族氮化物區域；在成長該III族氮化物區域後，成長包括n型III族氮化物區域、III族氮化物主動區域及p型III族氮化物區域之半導體積層；處理該氧化物基底之該第二面以形成具有彎曲表面之氧化物基板，該彎曲表面設置於該氧化物基板之第一面之相對側；在成長該半導體積層後，形成第一分散式布拉格反射器積層於該氧化物基板之該第一面；及形成第二分散式布拉格反射器積層於該氧化物基板之該彎曲表面。 Viewpoint 16 A method for manufacturing a vertical resonant cavity surface-emitting laser, the method includes: preparing an initial substrate, the initial substrate includes an oxide substrate, a group III nitride template plug, and a dielectric filter layer, the oxide substrate has a third One side and a second side located on the opposite side of the first side of the oxide substrate, the dielectric filter layer and the III-nitride template plug are located on the first side of the oxide substrate, the dielectric The electrical filter layer has a reflection spectrum, and the reflection spectrum provides an optical window; a Group III nitride region is grown from the Group III nitride template plug located on the dielectric filter layer; after growing the Group III nitride region , growing a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region and a p-type Group III nitride region; processing the second side of the oxide substrate to form an oxide substrate with a curved surface, the A curved surface is disposed on an opposite side of the first surface of the oxide substrate; after growing the semiconductor layer, forming a first distributed Bragg reflector layer on the first surface of the oxide substrate; and forming a second distributed Bragg reflector layer. A reflector is laminated on the curved surface of the oxide substrate.

觀點17 如觀點16所述的方法，更包含：在成長該半導體積層之前，藉由研磨或蝕刻之至少其中之一平坦化該III族氮化物區域。 Viewpoint 17 The method of aspect 16 further includes: planarizing the Group III nitride region by at least one of grinding or etching before growing the semiconductor stack.

觀點18 如觀點16或17所述的方法，更包含：在成長該半導體積層之後且在形成該第一分散式布拉格反射器積層之前，沉積導電層於該氧化物基板之該第一面；及形成第一電極於該導電層。 Viewpoint 18 The method of aspect 16 or 17, further comprising: after growing the semiconductor stack and before forming the first distributed Bragg reflector stack, depositing a conductive layer on the first side of the oxide substrate; and forming a third An electrode is on the conductive layer.

觀點19 如觀點16或17所述的方法，更包含：藉由蝕刻從該半導體積層製作台面結構以形成該n型III族氮化物區域之蝕刻面，該台面結構包括該III族氮化物主動區域。 Viewpoint 19 The method of aspect 16 or 17 further includes: fabricating a mesa structure from the semiconductor stack by etching to form an etched surface of the n-type Group III nitride region, the mesa structure including the Group III nitride active region.

觀點20 如觀點19所述的方法，更包含：形成第二電極於位在該台面結構外側之該n型III族氮化物區域之該蝕刻面。 Viewpoint 20 The method of aspect 19 further includes: forming a second electrode on the etched surface of the n-type Group III nitride region located outside the mesa structure.

觀點21 如觀點16或17所述的方法，其中該半導體積層更包括穿隧接面或嵌入穿隧接面其中之一。 Viewpoint 21 The method of aspect 16 or 17, wherein the semiconductor stack further includes one of a tunnel junction or an embedded tunnel junction.

觀點22 如觀點16或17所述的方法，其中該氧化物基板包含氧化鋁、氧化鋅、或氧化鎵其中之一。 Viewpoint 22 The method as described in viewpoint 16 or 17, wherein the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

觀點23 如觀點16或17所述的方法，其中準備初始基底包含：沉積III族氮化物層於該氧化物基底之該第一面；圖案化該III族氮化物層以形成該III族氮化物模板插栓；沉積複數介電層以覆蓋該氧化物基底之該第一面及該III族氮化物模板插栓；及處理該等介電層以形成該介電濾波器層，以使該III族氮化物模板插栓位於該介電濾波器層之通孔內，且該III族氮化物模板插栓具有高度大於該介電濾波器層之厚度。 Viewpoint 23 The method of aspect 16 or 17, wherein preparing the initial substrate includes: depositing a Group III nitride layer on the first side of the oxide substrate; patterning the Group III nitride layer to form the Group III nitride template insert plug; depositing a plurality of dielectric layers to cover the first side of the oxide substrate and the III-nitride template plug; and processing the dielectric layers to form the dielectric filter layer so that the III-nitride The III-nitride template plug is located in the through hole of the dielectric filter layer, and the III-nitride template plug has a height greater than the thickness of the dielectric filter layer.

觀點24 如觀點23所述的方法，其中該等介電層被成長來形成法布里-培洛濾波器以提供該反射光譜給該光學窗口。 Viewpoint 24 The method of aspect 23, wherein the dielectric layers are grown to form a Fabry-Perot filter to provide the reflection spectrum to the optical window.

觀點25 如觀點16或17所述的方法，其中該III族氮化物區域藉由磊晶側向延長成長從該III族氮化物模板插栓被成長，以形成III族氮化物島狀物。 Viewpoint 25 The method of aspect 16 or 17, wherein the III-nitride region is grown from the III-nitride template plug by epitaxial lateral extension growth to form III-nitride islands.

觀點26 如觀點25所述的方法，其中該III族氮化物島狀物從該III族氮化物模板插栓沿該介電濾波器層之頂面向外延伸，且該介電濾波器層之該頂面之粗糙度係1奈米以下。 Viewpoint 26 The method of aspect 25, wherein the III-nitride island extends outwardly from the III-nitride template plug along the top surface of the dielectric filter layer, and the top surface of the dielectric filter layer The roughness is below 1 nanometer.

觀點27 如觀點16或17所述的方法，其中該III族氮化物主動區域被成長來形成量子井結構，以產生具有波長在該第一分散式布拉格反射器積層之第一反射光譜中、在該第二分散式布拉格反射器積層之第二反射光譜中、及在該介電濾波器層之該光學窗口中之光線。 Viewpoint 27 The method of aspect 16 or 17, wherein the III-nitride active region is grown to form a quantum well structure to produce a first reflection spectrum having wavelengths in the first distributed Bragg reflector stack, in the first Light in the second reflection spectrum of the bidisperse Bragg reflector stack and in the optical window of the dielectric filter layer.

觀點28 如觀點16或17所述的方法，其中處理該氧化物基底之該第二面以形成氧化物基板包含：形成圖案化光阻層在該氧化物基底之該第二面，熱處理該圖案化光阻層以形成凸出光阻區域，且藉由蝕刻該凸出光阻區域及該氧化物基底來將該凸出光阻區域之形狀轉移至該氧化物基底，以形成該彎曲表面，及其中，停止蝕刻該凸出光阻區域及氧化物基底來滿足以下情況：在形成該第一分散式布拉格反射器積層及該第二分散式布拉格反射器積層後，該第二分散式布拉格反射器積層與該第一分散式布拉格反射器積層之間的距離係50微米以上。 Viewpoint 28 The method of viewpoint 16 or 17, wherein processing the second side of the oxide substrate to form an oxide substrate includes: forming a patterned photoresist layer on the second side of the oxide substrate, and heat-treating the patterned photoresist layer. The resist layer is used to form a protruding photoresist region, and the shape of the protruding photoresist region is transferred to the oxide substrate by etching the protruding photoresist region and the oxide substrate to form the curved surface, and wherein the etching is stopped The protruding photoresist region and the oxide substrate meet the following conditions: after forming the first distributed Bragg reflector stack and the second distributed Bragg reflector stack, the second distributed Bragg reflector stack and the first The distance between the stacks of dispersed Bragg reflectors is more than 50 microns.

觀點29 如觀點16或17所述的方法，其中該彎曲表面具有大於50微米之曲率半徑。 Viewpoint 29 The method as described in viewpoint 16 or 17, wherein the curved surface has a radius of curvature greater than 50 microns.

觀點30 如觀點16或17所述的方法，更包含：在成長該半導體積層後且在形成該導電層之前，形成光阻膜在該氧化物基板之該第一面；經由該氧化物基板之該彎曲表面照射該光阻層，以從該光阻膜製作圖案化掩膜；及利用該圖案化掩膜進行離子佈植，以形成包括孔徑區域及圍繞該孔徑區域之隔離區域的孔徑結構。 Viewpoint 30 The method as described in viewpoint 16 or 17, further comprising: after growing the semiconductor stack and before forming the conductive layer, forming a photoresist film on the first side of the oxide substrate; through the bending of the oxide substrate The photoresist layer is surface-irradiated to produce a patterned mask from the photoresist film; and the patterned mask is used to perform ion implantation to form an aperture structure including an aperture area and an isolation area surrounding the aperture area.

使用於此且未另外定義，「實質上」及「大約」等用語係用於描述及敘述小變化。當結合於一事件或情況，該用語可包含事件或情況發生精確的當下、以及事件或情況發生至一接近的近似點。例如，當結合於一數值，該用語可包含一變化範圍小於或等於該數值之±10%，如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%。As used herein and not otherwise defined, the terms "substantially" and "approximately" are used to describe and describe small changes. When used in connection with an event or situation, the term may include the precise moment at which the event or situation occurs, as well as the event or situation occurring to a close approximation. For example, when combined with a numerical value, the term may include a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

以上概述了數個實施例的部件、使得在本揭露所屬技術領域中具有通常知識者可以更理解本揭露實施例的概念。在本揭露所屬技術領域中具有通常知識者應該理解、可以使用本揭露實施例作為基礎、來設計或修改其他製程和結構、以實現與在此所介紹的實施例相同的目的及/或達到相同的好處。在本揭露所屬技術領域中具有通常知識者也應該理解、這些等效的結構並不背離本揭露的精神和範圍、並且在不背離本揭露的精神和範圍的情況下、在此可以做出各種改變、取代和其他選擇。因此、本揭露之保護範圍當視後附之申請專利範圍所界定為準。The components of several embodiments are summarized above so that those with ordinary skill in the technical field to which this disclosure belongs can better understand the concepts of the embodiments of this disclosure. It should be understood by those of ordinary skill in the art that the embodiments of the present disclosure can be used as a basis to design or modify other processes and structures to achieve the same purposes and/or achieve the same results as the embodiments introduced herein. benefits. Those of ordinary skill in the technical field to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure, and that various modifications can be made herein without departing from the spirit and scope of the present disclosure. Changes, Substitutions and Alternatives. Therefore, the protection scope of the present disclosure shall be determined by the appended patent application scope.

10a:焊錫凸塊 11、11a~11c:VCSEL 13、19:分散式布拉格反射器(DBR) 13a、13b、19a、19b:介電層 15:半導體部分 15a、15b、21a、21b:面 17:介電濾波器層 18:模板插栓 18a:嵌設部分 18b:突起 21:氧化物基板 21c:彎曲表面 23:p型III族氮化物區域 25:n型III族氮化物區域 25a、37c:前面 25b:背面 27:III族氮化物主動區域 29:II族氮化物區域 31:陽極電極 33:陰極電極 35:導電層 37:台面 37a:基座區域 37b:台面區域 39:孔徑結構 39a:導電孔徑部分 39b:低導電部分 CAV:光學腔體 CNT:中心軸 Ax1、Ax2、AX3:軸向 10a:Solder bump 11. 11a~11c:VCSEL 13, 19: Distributed Bragg Reflector (DBR) 13a, 13b, 19a, 19b: dielectric layer 15:Semiconductor part 15a, 15b, 21a, 21b: noodles 17: Dielectric filter layer 18: Template plug 18a: Embedded part 18b:Protrusion 21:Oxide substrate 21c: Curved surface 23: p-type III nitride region 25: n-type III nitride region 25a, 37c: front 25b: Back 27: Group III nitride active region 29: Group II nitride region 31: Anode electrode 33:Cathode electrode 35: Conductive layer 37: Countertop 37a: Base area 37b: Countertop area 39: Pore structure 39a: Conductive aperture part 39b: Low conductive part CAV: optical cavity CNT: central axis Ax1, Ax2, AX3: axial direction

[圖1]是表示本揭露之一實施例之包含二鏡面及法布里-培洛濾波器之延伸腔體VCSEL的剖面示意圖。 [圖2]是表示本揭露之一實施例之VCSEL的俯視示意圖。 [圖3A]是表示本揭露之一實施例之製造延伸腔體VCSEL之製程步驟之示意圖。 [圖3B]是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3C] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3D] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3E] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3F] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3G] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3H] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3I] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3J] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3K] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3L] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3M] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3N] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3O] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3P] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3Q] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖3R] 是表示本揭露之一實施例之VCSEL製造方法之製程步驟之示意圖。 [圖4A]是表示本揭露之一實施例之依據製造方法製造之VCSEL產品之主要元件之立體示意圖。 [圖4A]是表示本揭露之一實施例之VCSEL產品之主要元件之俯視示意圖。 [圖5]是表示本揭露之一實施例之VCSEL製造方法中VCSEL產品之裝置部分之一配置之俯視示意圖。 [圖6]是表示本揭露之一實施例之VCSEL製造方法中VCSEL產品之裝置部分之另一配置之俯視示意圖。 [圖7]是表示本揭露之一實施例之VCSEL製造方法中VCSEL產品之裝置部分之又一配置之俯視示意圖。 [圖8]是表示本揭露之一實施例之VCSEL之範例裝置結構之剖面示意圖。 [圖9]是表示本揭露之一實施例之VCSEL之範例裝置結構之剖面示意圖。 [圖10]是表示本揭露之一實施例之VCSEL之範例裝置結構之剖面示意圖。 [Fig. 1] is a schematic cross-sectional view of an extended cavity VCSEL including two mirrors and a Fabry-Perot filter according to an embodiment of the present disclosure. [Fig. 2] is a schematic top view of a VCSEL according to an embodiment of the present disclosure. [Fig. 3A] is a schematic diagram showing the process steps of manufacturing an extended cavity VCSEL according to an embodiment of the present disclosure. [Fig. 3B] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3C] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3D] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3E] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3F] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3G] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3H] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3I] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3J] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3K] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3L] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3M] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3N] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3O] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3P] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [Fig. 3Q] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [FIG. 3R] is a schematic diagram showing the process steps of a VCSEL manufacturing method according to an embodiment of the present disclosure. [Fig. 4A] is a three-dimensional schematic diagram showing the main components of a VCSEL product manufactured according to a manufacturing method according to an embodiment of the present disclosure. [Fig. 4A] is a schematic top view showing the main components of a VCSEL product according to an embodiment of the present disclosure. [Fig. 5] is a schematic top view showing a configuration of a device part of a VCSEL product in a VCSEL manufacturing method according to an embodiment of the present disclosure. [Fig. 6] is a schematic top view showing another configuration of the device part of the VCSEL product in the VCSEL manufacturing method according to one embodiment of the present disclosure. [Fig. 7] is a schematic top view showing another configuration of the device part of the VCSEL product in the VCSEL manufacturing method according to an embodiment of the present disclosure. [Fig. 8] is a schematic cross-sectional view showing an example device structure of a VCSEL according to an embodiment of the present disclosure. [Fig. 9] is a schematic cross-sectional view showing an example device structure of a VCSEL according to an embodiment of the present disclosure. [Fig. 10] is a schematic cross-sectional view showing an example device structure of a VCSEL according to an embodiment of the present disclosure.

10a:焊錫凸塊 10a:Solder bump

11:VCSEL 11:VCSEL

13、19:分散式布拉格反射器(DBR) 13, 19: Distributed Bragg Reflector (DBR)

13a、13b、19a、19b:介電層 13a, 13b, 19a, 19b: dielectric layer

15:半導體部分 15:Semiconductor part

15a、15b、21a、21b:面 15a, 15b, 21a, 21b: noodles

17:介電濾波器層 17: Dielectric filter layer

18:模板插栓 18: Template plug

18a:嵌設部分 18a: Embedded part

18b:突起 18b:Protrusion

21:氧化物基板 21:Oxide substrate

21c:彎曲表面 21c: Curved surface

23:p型III族氮化物區域 23: p-type III nitride region

25:n型III族氮化物區域 25: n-type III nitride region

25a、37c:前面 25a, 37c: front

25b:背面 25b: Back

27:III族氮化物主動區域 27: Group III nitride active region

29:II族氮化物區域 29: Group II nitride region

31:陽極電極 31: Anode electrode

33:陰極電極 33:Cathode electrode

35:導電層 35:Conductive layer

37:台面 37: Countertop

37a:基座區域 37a: Base area

37b:台面區域 37b: Countertop area

39:孔徑結構 39: Pore structure

39a:導電孔徑部分 39a: Conductive aperture part

39b:低導電部分 39b: Low conductive part

CAV:光學腔體 CAV: optical cavity

CNT:中心軸 CNT: central axis

Ax1:軸向 Ax1: axial direction

Claims (30)

一種垂直共振腔面射型雷射，其包含： 氧化物基板，具有第一面及位在該第一面之相對側之第二面，第二面包括彎曲表面； 半導體部分，設置於該氧化物基板之該第一面； 介電濾波器層，設置在該半導體部分與該氧化物基板之該第一面之間，並具有反射光譜，該反射光譜提供光學窗口； 第一分散式布拉格反射器鏡面，該半導體部分設置在該介電濾波器層及該第一分散式布拉格反射器鏡面之間；及 第二分散式布拉格反射器鏡面，設置於該氧化物基板之該彎曲表面，該第一分散式布拉格反射器鏡面、該半導體部分、該介電濾波器層、該氧化物基板及該第二分散式布拉格反射器鏡面於第一軸向上配置以形成延伸腔體， 其中該半導體部分包括p型III族氮化物區域、III族氮化物區域、及位在該p型III族氮化物區域及該III族氮化物區域之間的該III族氮化物主動區域，該p型III族氮化物區域、該III族氮化物主動區域及該III族氮化物區域在該第一軸向上配置，且該III族氮化物區域包括n型III族氮化物區域。 A vertical resonant cavity surface-emitting laser, which includes: An oxide substrate having a first surface and a second surface located on an opposite side of the first surface, the second surface including a curved surface; a semiconductor part disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor portion and the first side of the oxide substrate and having a reflection spectrum that provides an optical window; a first distributed Bragg reflector mirror, the semiconductor portion disposed between the dielectric filter layer and the first distributed Bragg reflector mirror; and The second dispersed Bragg reflector mirror is disposed on the curved surface of the oxide substrate, the first dispersed Bragg reflector mirror, the semiconductor part, the dielectric filter layer, the oxide substrate and the second dispersed Bragg reflector. The Bragg reflector mirror is arranged in the first axis direction to form an extended cavity, The semiconductor portion includes a p-type Group III nitride region, a Group III nitride region, and the Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, and the p-type Group III nitride region The type III nitride region, the group III nitride active region, and the group III nitride region are arranged in the first axis direction, and the group III nitride region includes an n-type group III nitride region. 如請求項1所述的垂直共振腔面射型雷射，其中該介電濾波器層具有延伸在該第一軸向的通孔， 該垂直共振腔面射型雷射更包含： III族氮化物模板插栓，設置於該通孔內，並從該氧化物基板延伸至該通孔內之該半導體部分。 The vertical resonant cavity surface-emitting laser as claimed in claim 1, wherein the dielectric filter layer has a through hole extending in the first axial direction, This vertical resonant cavity surface-emitting laser also includes: A Group III nitride template plug is disposed in the through hole and extends from the oxide substrate to the semiconductor portion in the through hole. 如請求項2所述的垂直共振腔面射型雷射，其中該 III族氮化物模板插栓包含在該通孔內之嵌設部分及突出至該半導體部分之突起，且該III族氮化物模板插栓之該嵌設部分設置與該氧化物基板之該第一面接觸。The vertical resonant cavity surface-emitting laser according to claim 2, wherein the III-nitride template plug includes an embedded part in the through hole and a protrusion protruding to the semiconductor part, and the III-nitride template plug The embedded portion of the template plug is disposed in contact with the first surface of the oxide substrate. 如請求項1~3任一項所述的垂直共振腔面射型雷射， 其中該氧化物基板之該彎曲表面具有中心線，該III族氮化物模板插栓與該彎曲表面之該中心線彼此錯位。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the curved surface of the oxide substrate has a centerline, and the group III nitride template plug is consistent with the centerline of the curved surface. misaligned with each other. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該延伸腔體之長度大於50微米。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the length of the extended cavity is greater than 50 microns. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該彎曲表面具有大於50微米之曲率半徑。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the curved surface has a radius of curvature greater than 50 microns. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該第二分散式布拉格反射器鏡面係彎曲的，該第一分散式布拉格反射器鏡面係平面的，且該第一分散式布拉格反射器鏡面與該第二分散式布拉格反射器鏡面之間的距離係50微米以上。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the second dispersed Bragg reflector mirror is curved, the first dispersed Bragg reflector mirror is planar, and the The distance between the first dispersed Bragg reflector mirror surface and the second dispersed Bragg reflector mirror surface is more than 50 microns. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該半導體部分包含台面結構，該台面結構包括基座區域及設置於該基座區域之台面區域， 該垂直共振腔面射型雷射更包含： 導電層，設置於該半導體部分，該導電層之一部分設置在該第一分散式布拉格反射器鏡面與該半導體部分之間； 第一電極，設置於該導電層並位於該第一分散式布拉格反射器鏡面外側，該第一電極設置與該導電層接觸；及 第二電極，設置於該台面結構之該基座區域之一面。 The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the semiconductor part includes a mesa structure, and the mesa structure includes a base region and a mesa region disposed on the base region, This vertical resonant cavity surface-emitting laser also includes: A conductive layer is provided on the semiconductor part, and a part of the conductive layer is provided between the first distributed Bragg reflector mirror and the semiconductor part; A first electrode is disposed on the conductive layer and located outside the mirror surface of the first distributed Bragg reflector, and the first electrode is disposed in contact with the conductive layer; and The second electrode is disposed on one surface of the base area of the mesa structure. 如請求項8所述的垂直共振腔面射型雷射，其中該半導體部分具有第一面及位在該半導體部分之該第一面之相對側之第二面，該介電濾波器層設置於該半導體部分之該第一面，且該導電層設置於該半導體部分之該第二面。The vertical resonant cavity surface emitting laser according to claim 8, wherein the semiconductor part has a first surface and a second surface located on the opposite side of the first surface of the semiconductor part, and the dielectric filter layer is provided on the first side of the semiconductor part, and the conductive layer is disposed on the second side of the semiconductor part. 如請求項1~3任一項所述的垂直共振腔面射型雷射， 其中該半導體部分包括孔徑結構，該孔徑結構包括延伸在該第一軸向之孔徑區域、及圍繞該孔徑區域之隔離區域，且該第一分散式布拉格反射器鏡面、該孔徑區域及該第二分散式布拉格反射器鏡面沿不通過該III族氮化物模板插栓之軸來配置。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the semiconductor part includes an aperture structure, and the aperture structure includes an aperture area extending in the first axial direction, and an aperture area surrounding the aperture area. Isolate the area, and the first DBR mirror, the aperture area, and the second DBR mirror are configured along an axis that does not pass through the III-nitride template plug. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該半導體部分之總厚度係約0.5微米以上。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the total thickness of the semiconductor part is about 0.5 microns or more. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該介電濾波器層包括法布里-培洛濾波器，提供該反射光譜給該光學窗口。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the dielectric filter layer includes a Fabry-Perot filter to provide the reflection spectrum to the optical window. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該氧化物基板包括氧化鋁、氧化鋅、或氧化鎵其中之一。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該第一分散式布拉格反射器鏡面之反射率低於該第二分散式布拉格反射器鏡面之反射率。The vertical resonant cavity surface emitting laser according to any one of claims 1 to 3, wherein the reflectivity of the first dispersed Bragg reflector mirror is lower than the reflectivity of the second dispersed Bragg reflector mirror. 如請求項1~3任一項所述的垂直共振腔面射型雷射，其中該III族氮化物主動區域包含量子井結構，產生具有波長在該第一分散式布拉格反射器鏡面之第一反射光譜中、在該第二分散式布拉格反射器鏡面之第二反射光譜中、及在該介電濾波器層之該光學窗口中之光線。The vertical resonant cavity surface-emitting laser according to any one of claims 1 to 3, wherein the III-nitride active region includes a quantum well structure to generate a first beam with a wavelength at the first dispersed Bragg reflector mirror. Light in the reflection spectrum, in the second reflection spectrum of the second dispersed Bragg reflector mirror, and in the optical window of the dielectric filter layer. 一種製造垂直共振腔面射型雷射之方法，該方法包含： 準備初始基底，該初始基板包括氧化物基底、III族氮化物模板插栓、及介電濾波器層，該氧化物基底具有第一面及位在該氧化物基底之該第一面之相對側之第二面，該介電濾波器層及該III族氮化物模板插栓位於該氧化物基底之該第一面，該介電濾波器層具有反射光譜，且該反射光譜提供光學窗口； 從位於該介電濾波器層上之該III族氮化物模板插栓成長III族氮化物區域； 在成長該III族氮化物區域後，成長包括n型III族氮化物區域、III族氮化物主動區域及p型III族氮化物區域之半導體積層； 處理該氧化物基底之該第二面以形成具有彎曲表面之氧化物基板，該彎曲表面設置於該氧化物基板之第一面之相對側； 在成長該半導體積層後，形成第一分散式布拉格反射器積層於該氧化物基板之該第一面；及 形成第二分散式布拉格反射器積層於該氧化物基板之該彎曲表面。 A method of manufacturing a vertical resonant cavity surface-emitting laser, which method includes: Preparing an initial substrate, the initial substrate including an oxide substrate, a Group III nitride template plug, and a dielectric filter layer, the oxide substrate having a first side and an opposite side of the first side of the oxide substrate On the second side, the dielectric filter layer and the Group III nitride template plug are located on the first side of the oxide substrate, the dielectric filter layer has a reflection spectrum, and the reflection spectrum provides an optical window; Growing a III-nitride region from the III-nitride template plug located on the dielectric filter layer; After growing the Group III nitride region, growing a semiconductor stack including an n-type Group III nitride region, a Group III nitride active region, and a p-type Group III nitride region; processing the second side of the oxide substrate to form an oxide substrate having a curved surface, the curved surface being disposed on an opposite side of the first side of the oxide substrate; After growing the semiconductor stack, forming a first distributed Bragg reflector stack on the first side of the oxide substrate; and A second distributed Bragg reflector is formed and laminated on the curved surface of the oxide substrate. 如請求項16所述的方法，更包含： 在成長該半導體積層之前，藉由研磨或蝕刻之至少其中之一平坦化該III族氮化物區域。 The method described in request item 16 further includes: Prior to growing the semiconductor stack, the III-nitride region is planarized by at least one of grinding or etching. 如請求項16或17所述的方法，更包含： 在成長該半導體積層之後且在形成該第一分散式布拉格反射器積層之前，沉積導電層於該氧化物基板之該第一面；及 形成第一電極於該導電層。 The method described in request item 16 or 17 further includes: After growing the semiconductor stack and before forming the first distributed Bragg reflector stack, depositing a conductive layer on the first side of the oxide substrate; and A first electrode is formed on the conductive layer. 如請求項16或17所述的方法，更包含： 藉由蝕刻從該半導體積層製作台面結構以形成該n型III族氮化物區域之蝕刻面，該台面結構包括該III族氮化物主動區域。 The method described in request item 16 or 17 further includes: A mesa structure is fabricated from the semiconductor stack by etching to form an etched surface of the n-type Group III nitride region, the mesa structure including the Group III nitride active region. 如請求項19所述的方法，更包含： 形成第二電極於位在該台面結構外側之該n型III族氮化物區域之該蝕刻面。 The method described in request item 19 further includes: A second electrode is formed on the etched surface of the n-type Group III nitride region outside the mesa structure. 如請求項16或17所述的方法，其中該半導體積層更包括穿隧接面或嵌入穿隧接面其中之一。The method of claim 16 or 17, wherein the semiconductor stack further includes one of a tunnel junction or an embedded tunnel junction. 如請求項16或17所述的方法，其中該氧化物基板包含氧化鋁、氧化鋅、或氧化鎵其中之一。The method of claim 16 or 17, wherein the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide. 如請求項16或17所述的方法，其中準備初始基底包含： 沉積III族氮化物層於該氧化物基底之該第一面； 圖案化該III族氮化物層以形成該III族氮化物模板插栓； 沉積複數介電層以覆蓋該氧化物基底之該第一面及該III族氮化物模板插栓；及 處理該等介電層以形成該介電濾波器層，以使該III族氮化物模板插栓位於該介電濾波器層之通孔內，且該III族氮化物模板插栓具有高度大於該介電濾波器層之厚度。 The method of claim 16 or 17, wherein preparing the initial substrate includes: depositing a Group III nitride layer on the first side of the oxide substrate; Patterning the III-nitride layer to form the III-nitride template plug; depositing a plurality of dielectric layers to cover the first side of the oxide substrate and the III-nitride template plug; and Processing the dielectric layers to form the dielectric filter layer such that the Group III nitride template plug is located within the via hole of the dielectric filter layer, and the Group III nitride template plug has a height greater than the The thickness of the dielectric filter layer. 如請求項23所述的方法，其中該等介電層被成長來形成法布里-培洛濾波器以提供該反射光譜給該光學窗口。The method of claim 23, wherein the dielectric layers are grown to form a Fabry-Perot filter to provide the reflection spectrum to the optical window. 如請求項16或17所述的方法，其中該III族氮化物區域藉由磊晶側向延長成長從該III族氮化物模板插栓被成長，以形成III族氮化物島狀物。The method of claim 16 or 17, wherein the III-nitride region is grown from the III-nitride template plug by epitaxial lateral extension growth to form III-nitride islands. 如請求項25所述的方法，其中該III族氮化物島狀物從該III族氮化物模板插栓沿該介電濾波器層之頂面向外延伸，且該介電濾波器層之該頂面之粗糙度係1奈米以下。The method of claim 25, wherein the III-nitride island extends outwardly from the III-nitride template plug along a top surface of the dielectric filter layer, and the top surface of the dielectric filter layer The surface roughness is less than 1 nanometer. 如請求項16或17所述的方法，其中該III族氮化物主動區域被成長來形成量子井結構，以產生具有波長在該第一分散式布拉格反射器積層之第一反射光譜中、在該第二分散式布拉格反射器積層之第二反射光譜中、及在該介電濾波器層之該光學窗口中之光線。The method of claim 16 or 17, wherein the III-nitride active region is grown to form a quantum well structure to produce a first reflection spectrum having wavelengths in the first distributed Bragg reflector stack, in the Light in the second reflection spectrum of the second dispersed Bragg reflector stack and in the optical window of the dielectric filter layer. 如請求項16或17所述的方法，其中處理該氧化物基底之該第二面以形成氧化物基板包含：形成圖案化光阻層在該氧化物基底之該第二面，熱處理該圖案化光阻層以形成凸出光阻區域，且藉由蝕刻該凸出光阻區域及該氧化物基底來將該凸出光阻區域之形狀轉移至該氧化物基底，以形成該彎曲表面，及 其中，停止蝕刻該凸出光阻區域及氧化物基底來滿足以下情況：在形成該第一分散式布拉格反射器積層及該第二分散式布拉格反射器積層後，該第二分散式布拉格反射器積層與該第一分散式布拉格反射器積層之間的距離係50微米以上。 The method of claim 16 or 17, wherein processing the second side of the oxide substrate to form an oxide substrate includes: forming a patterned photoresist layer on the second side of the oxide substrate, and heat treating the patterned a photoresist layer to form a protruding photoresist region, and transfer the shape of the protruding photoresist region to the oxide substrate by etching the protruding photoresist region and the oxide substrate to form the curved surface, and Wherein, the etching of the protruding photoresist region and the oxide substrate is stopped to meet the following conditions: after forming the first distributed Bragg reflector stack and the second distributed Bragg reflector stack, the second distributed Bragg reflector stack The distance from the first distributed Bragg reflector stack is 50 microns or more. 如請求項16或17所述的方法，其中該彎曲表面具有大於50微米之曲率半徑。The method of claim 16 or 17, wherein the curved surface has a radius of curvature greater than 50 microns. 如請求項16或17所述的方法，更包含： 在成長該半導體積層後且在形成該導電層之前，形成光阻膜在該氧化物基板之該第一面； 經由該氧化物基板之該彎曲表面照射該光阻層，以從該光阻膜製作圖案化掩膜；及 利用該圖案化掩膜進行離子佈植，以形成包括孔徑區域及圍繞該孔徑區域之隔離區域的孔徑結構。 The method described in request item 16 or 17 further includes: After growing the semiconductor layer and before forming the conductive layer, forming a photoresist film on the first side of the oxide substrate; irradiating the photoresist layer through the curved surface of the oxide substrate to produce a patterned mask from the photoresist film; and The patterned mask is used to perform ion implantation to form an aperture structure including an aperture area and an isolation area surrounding the aperture area.
TW111120320A 2022-05-31 2022-05-31 Surface emitting laser, method for fabricating surface emitting laser TW202349811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW111120320A TW202349811A (en) 2022-05-31 2022-05-31 Surface emitting laser, method for fabricating surface emitting laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111120320A TW202349811A (en) 2022-05-31 2022-05-31 Surface emitting laser, method for fabricating surface emitting laser

Publications (1)

Publication Number Publication Date
TW202349811A true TW202349811A (en) 2023-12-16

Family

ID=90039224

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111120320A TW202349811A (en) 2022-05-31 2022-05-31 Surface emitting laser, method for fabricating surface emitting laser

Country Status (1)

Country Link
TW (1) TW202349811A (en)

Similar Documents

Publication Publication Date Title
US11258231B2 (en) GaN-based VCSEL chip based on porous DBR and manufacturing method of the same
US20240042166A1 (en) Semiconductor light-emitting device
US8163575B2 (en) Grown photonic crystals in semiconductor light emitting devices
US6967981B2 (en) Nitride based semiconductor structures with highly reflective mirrors
US8053789B2 (en) Light emitting device and fabrication method thereof
US7675084B2 (en) Photonic crystal light emitting device
US8354679B1 (en) Microcavity light emitting diode method of manufacture
US8093607B2 (en) Optoelectronic semiconductor component
EP1326290B1 (en) Method of fabricating semiconductor structures
TWI390759B (en) Method for fabricating group iii nitride devices and devices fabricated using method
TWI420687B (en) Polarization-reversed iii-nitride light-emitting device
US20210104504A1 (en) Contact architectures for tunnel junction devices
US7352788B2 (en) Nitride semiconductor vertical cavity surface emitting laser
KR20070013299A (en) Lift-off process for gan films formed on sic substrate and devices fabricated using the method
EP2675024B1 (en) Electron beam pumped vertical cavity surface emitting laser
JP2013544436A (en) Group III nitride light-emitting device
JP2010219502A (en) Light emitting device
TWI714146B (en) Led utilizing internal color conversion with light extraction enhancements
JP2018125404A (en) Surface emitting laser element
CN115868090A (en) Photonic crystal surface emitting laser element
CN105679904B (en) Optical pumping luminescent device and preparation method of monolithic integrated optical pumping luminescent device
TW202349811A (en) Surface emitting laser, method for fabricating surface emitting laser
WO2023233541A1 (en) Surface emitting laser, method for fabricating surface emitting laser
WO2023058405A1 (en) Surface-emitting laser element
TW202341594A (en) Surface emitting laser, method for fabricating surface emitting laser