TW202329404A - Semiconductor structure having fins - Google Patents
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Description
本申請案主張美國第17/573,759及17/573,787號專利申請案之優先權（即優先權日為「2022年1月12日」），其內容以全文引用之方式併入本文中。This application claims priority to US Patent Application Nos. 17/573,759 and 17/573,787 (ie, the priority date is "January 12, 2022"), the contents of which are incorporated herein by reference in their entirety.
本揭露關於一種半導體結構，特別是關於一種具有一個或多個鰭片的半導體結構。The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having one or more fins.
隨著電子產業的快速發展，半導體元件的發展已經實現了高性能和小型化。隨著半導體元件(如動態隨機存取記憶體(DRAM)元件)尺寸的縮小，半導體元件內導電特徵的線寬也隨之減少，這可能會增加製造難度，降低製造產量。With the rapid development of the electronics industry, the development of semiconductor components has achieved high performance and miniaturization. As the dimensions of semiconductor devices, such as dynamic random access memory (DRAM) devices, shrink, the line widths of conductive features within the semiconductor devices also decrease, which may increase manufacturing difficulty and reduce manufacturing yield.
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.
本揭露的一個方面提供一種半導體結構，包括一半導體基底和一隔離結構。該半導體基底包括一第一鰭片。該隔離結構定義該第一鰭片。該隔離結構包括位於該第一鰭片的兩個相對側面的一第一部分和一第二部分。該第一部分的頂面標高與該第二部分的頂面標高之間的差值大於0且小於約5奈米。One aspect of the present disclosure provides a semiconductor structure, including a semiconductor substrate and an isolation structure. The semiconductor base includes a first fin. The isolation structure defines the first fin. The isolation structure includes a first portion and a second portion located on two opposite sides of the first fin. The difference between the top surface elevation of the first portion and the top surface elevation of the second portion is greater than 0 and less than about 5 nanometers.
本揭露的另一個方面提供一種半導體結構的製備方法。該製備方法包括提供一半導體基底，包括複數個初始鰭片結構。該製備方法還包括形成一隔離材料以覆蓋複數個初始鰭結構。該製備方法還包括對該隔離材料和該複數個初始鰭片結構執行一非等向性的蝕刻操作，以形成該複數個鰭片。該製備方法還包括在該隔離材料上執行一等向性的蝕刻操作，以形成一隔離結構，以圍繞該複數個鰭片。Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form the plurality of fins. The manufacturing method further includes performing an isotropic etching operation on the isolation material to form an isolation structure to surround the plurality of fins.
本揭露的另一個方面提供一種半導體結構的製備方法。該製備方法包括提供一半導體基底，包括複數個初始鰭片結構。該製備方法還包括形成一隔離材料以覆蓋該複數個初始鰭片結構。該製備方法還包括對該複數個初始鰭片結構和該隔離材料執行一第一移除操作，以形成複數個鰭片和圍繞該複數個鰭片的一隔離層。該複數個鰭片的頂面與該隔離層的頂面之間的高度差小於約10奈米。該製備方法還包括對該隔離層執行一第二移除操作，以形成一隔離結構，以圍繞該複數個鰭片，其中該隔離結構的頂面低於該複數個鰭片的頂面約20奈米至約40奈米。Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method also includes performing a first removal operation on the plurality of initial fin structures and the isolation material to form the plurality of fins and an isolation layer surrounding the plurality of fins. The height difference between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nm. The manufacturing method further includes performing a second removal operation on the isolation layer to form an isolation structure to surround the plurality of fins, wherein the top surface of the isolation structure is about 20° lower than the top surface of the plurality of fins. nm to about 40 nm.
在半導體結構的製備方法中，形成鰭片和定義鰭片的隔離結構包括用於移除初始鰭片結構和隔離材料的相對較大部分的乾式蝕刻操作，和更用於移除隔離材料(或隔離層)的一部分以定義鰭片高度的濕式蝕刻操作。濕式蝕刻操作的蝕刻劑液相的流動性可以使蝕刻劑穿透小的特徵(例如，兩個相對靠近的鰭片之間的隔離部分)。因此，蝕刻的均勻性明顯提高，因此，鰭片之間的隔離部分可以被蝕刻掉的高度或數量實質上相等，因此可顯著提高成型鰭片高度的均勻性。此外，執行濕式蝕刻的時間可以相對較短，並且更可防止隔離材料(或隔離層)以外的結構和/或元件的過度蝕刻。In a method of fabricating a semiconductor structure, forming the fins and defining the isolation structures of the fins includes a dry etch operation for removing a relatively large portion of the initial fin structure and isolation material, and moreover for removing the isolation material (or part of the isolation layer) to define the fin height wet etch operation. The fluidity of the etchant liquid phase of the wet etch operation may allow the etchant to penetrate small features (eg, an isolated portion between two relatively close fins). Therefore, the uniformity of etching is significantly improved, and therefore, the height or amount of the isolation portions between the fins that can be etched away is substantially equal, and thus the uniformity of the height of the formed fins can be significantly improved. In addition, the time for performing wet etching can be relatively short, and over-etching of structures and/or elements other than the isolation material (or isolation layer) can be more prevented.
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.
現在用具體的語言來描述附圖中說明的本揭露的實施例，或實例。應理解的是，在此不限制本揭露的範圍。對所描述的實施例的任何改變或修改，以及對本文所描述的原理的任何進一步應用，都應被認為是與本揭露內容有關的技術領域的普通技術人員通常會做的。參考數字可以在整個實施例中重複，但這不旨在一個實施例的特徵適用於另一個實施例，即使它們共用相同的參考數位。Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is hereby intended. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numerals may be repeated throughout the embodiments, but it is not intended that features of one embodiment apply to another, even if they share the same reference numeral.
應理解的是，儘管用語第一、第二、第三等可用於描述各種元素、元件、區域、層或部分。可用於描述各種元素、部件、區域、層或部分，但這些元素、部件、區域、層或部分不受這些用語的限制。相反，這些用語只是用來區分一個元素、元件、區域、層或部分與另一個區域、層或部分。因此，下面討論的第一個元素、元件、區域、層或部分可以被稱為第二個元素、元件、區域、層或部分而不偏離本發明概念的教導。It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections, but these elements, components, regions, layers or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
本文使用的用語僅用於描述特定的實施例，並不旨在局限於本發明的概念。正如本文所使用的，單數形式的"一"、"一個"和"該"旨在包括複數形式，除非上下文明確指出。應進一步理解，用語”包括”和”包含”在本說明書中使用時，指出了所述特徵、整數、步驟、操作、元素或元件的存在，但不排除存在或增加一個或多個其他特徵、整數、步驟、操作、元素、元件或其組。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly dictates otherwise. It should be further understood that when the words "comprise" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.
圖1是頂視圖，例示本揭露一些實施例之半導體結構1，圖1A是橫截面圖，例示本揭露一些實施例之半導體結構1。在一些實施例中，圖1A是沿圖1的線1A-1A'的橫截面圖。半導體結構1包括半導體基底10，隔離結構20，和一個或多個導電元件30。應當理解，為了清楚起見，一些元件可以省略。FIG. 1 is a top view illustrating a semiconductor structure 1 of some embodiments of the present disclosure, and FIG. 1A is a cross-sectional view illustrating a semiconductor structure 1 of some embodiments of the present disclosure. In some embodiments, FIG. 1A is a cross-sectional view along line 1A-1A' of FIG. 1 . The semiconductor structure 1 includes a semiconductor substrate 10 , an isolation structure 20 , and one or more conductive elements 30 . It should be understood that some elements may be omitted for clarity.
半導體基底10可以包括一個或多個主動區。半導體基底10可包括一個或複數個鰭片(fin)(例如，鰭片110、120、130、140和150)。半導體基底10的主動區可以包括鰭片和摻雜區。摻雜區可以是源極/汲極區。半導體基底10的鰭片數量可根據實際應用而變化，並且不限於此。The semiconductor substrate 10 may include one or more active regions. The semiconductor substrate 10 may include one or a plurality of fins (eg, fins 110 , 120 , 130 , 140 and 150 ). The active region of the semiconductor substrate 10 may include fins and doped regions. The doped regions may be source/drain regions. The number of fins of the semiconductor substrate 10 may vary according to practical applications, and is not limited thereto.
在一些實施例中，半導體基底10的鰭片110、120、130、140和150與隔離結構20相鄰並由其定義。在一些實施例中，鰭片110、120、130、140和150藉由隔離結構20的部分彼此間隔開。在一些實施例中，鰭片110和鰭片120之間的距離D2小於鰭片120和鰭片130之間的距離D3。在一些實施例中，鰭片130和鰭片140之間的距離D2A小於鰭片150和鰭片130之間的距離D3A。在一些實施例中，距離D2實質上等於距離D2A。在一些實施例中，距離D3實質上等於距離D3A。半導體基底10可由下列材料形成或包含下列材料，例如，矽、摻雜矽、矽鍺、絕緣體上的矽、藍寶石上的矽、絕緣體上的矽鍺、碳化矽、鍺、砷化鎵、磷化鎵、磷化砷、磷化銦、磷化鎵銦、或任何其他IV-IV族、III-V族或I-VI族的半導體材料。在一些實施例中，半導體基底10的鰭片110、120、130、140和150可由一種或多種含矽的材料形成或包含一種或多種含矽的材料，例如，矽、摻雜矽或矽鍺。In some embodiments, the fins 110 , 120 , 130 , 140 , and 150 of the semiconductor substrate 10 are adjacent to and defined by the isolation structure 20 . In some embodiments, fins 110 , 120 , 130 , 140 , and 150 are separated from each other by portions of isolation structure 20 . In some embodiments, the distance D2 between the fins 110 and 120 is less than the distance D3 between the fins 120 and 130 . In some embodiments, distance D2A between fin 130 and fin 140 is less than distance D3A between fin 150 and fin 130 . In some embodiments, distance D2 is substantially equal to distance D2A. In some embodiments, distance D3 is substantially equal to distance D3A. Semiconductor substrate 10 may be formed of or include materials such as silicon, doped silicon, silicon germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, phosphide Gallium, arsenic phosphide, indium phosphide, indium gallium phosphide, or any other group IV-IV, III-V or I-VI semiconductor material. In some embodiments, the fins 110, 120, 130, 140, and 150 of the semiconductor substrate 10 may be formed of or include one or more silicon-containing materials, such as silicon, doped silicon, or silicon germanium. .
隔離結構20可定義半導體基底10的鰭片110、120、130、140和150。隔離結構20可由絕緣材料形成或包含絕緣材料，如氧化矽、氮化矽、氮氧化矽(silicon oxynitride)或其組合。The isolation structure 20 may define the fins 110 , 120 , 130 , 140 and 150 of the semiconductor substrate 10 . The isolation structure 20 can be formed of or include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
在一些實施例中，隔離結構20包括與鰭片110、120、130、140和150相鄰的複數個部分。在一些實施例中，隔離結構20包括在鰭片120的兩個相對側面上的部分210和部分220。在一些實施例中，鰭片110藉由隔離結構20的部分210與鰭片120間隔開。在一些實施例中，鰭片130藉由隔離結構20的部分220與鰭片120間隔開。在一些實施例中，隔離結構20的部分210的寬度(例如，距離D2)小於隔離結構20的部分220的寬度(例如，距離D3)。在一些實施例中，隔離結構20的部分210的厚度T3小於隔離結構20的部分220的厚度T4。In some embodiments, isolation structure 20 includes a plurality of portions adjacent to fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, isolation structure 20 includes portion 210 and portion 220 on two opposite sides of fin 120 . In some embodiments, fin 110 is spaced apart from fin 120 by portion 210 of isolation structure 20 . In some embodiments, fin 130 is spaced apart from fin 120 by portion 220 of isolation structure 20 . In some embodiments, the width (eg, distance D2 ) of portion 210 of isolation structure 20 is smaller than the width (eg, distance D3 ) of portion 220 of isolation structure 20 . In some embodiments, the thickness T3 of the portion 210 of the isolation structure 20 is less than the thickness T4 of the portion 220 of the isolation structure 20 .
在一些實施例中，隔離結構20更包括在鰭片140的兩個相對側面上的部分230和部分240。在一些實施例中，鰭片130藉由隔離結構20的部分230與鰭片140間隔開。在一些實施例中，鰭片150藉由隔離結構20的部分240與鰭片140間隔開。在一些實施例中，隔離結構20的部分230的寬度(例如，距離D2A)小於隔離結構20的部分240的寬度(例如，距離D3A)。在一些實施例中，隔離結構20的部分230的厚度T3A小於隔離結構20的部分240的厚度T4A。在一些實施例中，厚度T3實質上等於厚度T3A。在一些實施例中，厚度T4實質上等於厚度T4A。In some embodiments, the isolation structure 20 further includes a portion 230 and a portion 240 on two opposite sides of the fin 140 . In some embodiments, fin 130 is spaced apart from fin 140 by portion 230 of isolation structure 20 . In some embodiments, fin 150 is spaced apart from fin 140 by portion 240 of isolation structure 20 . In some embodiments, the width of portion 230 of isolation structure 20 (eg, distance D2A) is less than the width of portion 240 of isolation structure 20 (eg, distance D3A). In some embodiments, the thickness T3A of the portion 230 of the isolation structure 20 is less than the thickness T4A of the portion 240 of the isolation structure 20 . In some embodiments, thickness T3 is substantially equal to thickness T3A. In some embodiments, thickness T4 is substantially equal to thickness T4A.
在一些實施例中，部分210的頂面210a的標高與部分220的頂面220a的標高之間的差值D1大於0且小於約5奈米。在一些實施例中，部分210的頂面210a的標高與部分220的頂面220a的標高之間的差值D1等於或小於約3奈米。在一些實施例中，部分210的頂面210a的標高與部分220的頂面220a的標高之間的差值D1等於或小於約2奈米。在一些實施例中，部分210的頂面210a的標高與部分220的頂面220a的標高之間的差值D1等於或小於約1奈米。In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is greater than 0 and less than about 5 nm. In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is equal to or less than about 3 nanometers. In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is equal to or less than about 2 nanometers. In some embodiments, the difference D1 between the elevation of the top surface 210a of the portion 210 and the elevation of the top surface 220a of the portion 220 is equal to or less than about 1 nanometer.
在一些實施例中，部分230的頂面230a的標高與部分240的頂面240a的標高之間的差值D1A大於0且小於約5奈米。在一些實施例中，部分230的頂面230a的標高與部分240的頂面240a的標高之間的差值D1A等於或小於約3奈米。在一些實施例中，部分230的頂面230a的標高與部分240的頂面240a的標高之間的差值D1A等於或小於約2奈米。在一些實施例中，部分230的頂面230a的標高與部分240的頂面240a的標高之間的差值D1A等於或小於約1奈米。在一些實施例中，距離D1實質上等於距離D1A。In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is greater than 0 and less than about 5 nanometers. In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is equal to or less than about 3 nanometers. In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is equal to or less than about 2 nanometers. In some embodiments, the difference D1A between the elevation of top surface 230a of portion 230 and the elevation of top surface 240a of portion 240 is equal to or less than about 1 nanometer. In some embodiments, distance D1 is substantially equal to distance D1A.
在一些實施例中，鰭片120的頂面120a與隔離結構20的部分210的頂面210a之間的距離T1小於鰭片120的頂面120a與隔離結構20的部分220的頂面220a之間的距離T2。在一些實施例中，部分210的頂面210a的標高高於部分220的頂面220a的標高。In some embodiments, the distance T1 between the top surface 120a of the fin 120 and the top surface 210a of the portion 210 of the isolation structure 20 is smaller than the distance T1 between the top surface 120a of the fin 120 and the top surface 220a of the portion 220 of the isolation structure 20 The distance T2. In some embodiments, the elevation of the top surface 210a of the portion 210 is higher than the elevation of the top surface 220a of the portion 220 .
在一些實施例中，鰭片140的頂面140a與隔離結構20的部分230的頂面230a之間的距離T1A小於鰭片140的頂面140a與隔離結構20的部分240的頂面240a之間的距離T2A。在一些實施例中，部分230的頂面230a的標高高於部分240的頂面240a的標高。在一些實施例中，距離T1實質上等於距離T1A。在一些實施例中，距離T2實質上等於距離T2A。In some embodiments, the distance T1A between the top surface 140a of the fin 140 and the top surface 230a of the portion 230 of the isolation structure 20 is smaller than the distance T1A between the top surface 140a of the fin 140 and the top surface 240a of the portion 240 of the isolation structure 20 The distance T2A. In some embodiments, the elevation of the top surface 230a of the portion 230 is higher than the elevation of the top surface 240a of the portion 240 . In some embodiments, distance T1 is substantially equal to distance T1A. In some embodiments, distance T2 is substantially equal to distance T2A.
導電元件30可設置在半導體基底10和隔離結構20上。在一些實施例中，半導體基底10和隔離結構20共同定義一個或多個溝槽30A，並且鰭片110、120、130、140和150在溝槽30A中。在一些實施例中，導電元件30設置在溝槽30A中的鰭片110、120、130、140和150上。在一些實施例中，導電元件30共形地形成在溝槽30A中的鰭片110、120、130、140和150上。在一些實施例中，半導體結構1包括複數個溝槽30A中的複數個導電元件30。在一些實施例中，導電元件30包括導電材料，例如，摻雜的多晶矽、金屬或金屬矽化物。金屬可以是，例如，鋁，銅，鎢，鈷，或其合金。金屬矽化物可以是，例如，矽化鎳、矽化鉑、矽化鈦、矽化鉬、矽化鈷、矽化鉭、矽化鎢，或類似物。在一些實施例中，導電元件30可以是或包括字元線。The conductive element 30 may be disposed on the semiconductor substrate 10 and the isolation structure 20 . In some embodiments, semiconductor substrate 10 and isolation structure 20 together define one or more trenches 30A, and fins 110 , 120 , 130 , 140 , and 150 are in trenches 30A. In some embodiments, conductive elements 30 are disposed on fins 110 , 120 , 130 , 140 , and 150 in trenches 30A. In some embodiments, conductive elements 30 are conformally formed on fins 110 , 120 , 130 , 140 , and 150 in trenches 30A. In some embodiments, the semiconductor structure 1 includes a plurality of conductive elements 30 in a plurality of trenches 30A. In some embodiments, conductive element 30 includes a conductive material, such as doped polysilicon, metal, or metal silicide. The metal can be, for example, aluminum, copper, tungsten, cobalt, or alloys thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, conductive element 30 may be or include a word line.
在一些實施例中，溝槽30A中的鰭片110、120、130、140和150的鰭片高度由鰭片110、120、130、140和150與隔離結構20之間的標高差來定義。根據本揭露的一些實施例，儘管當鰭片110和鰭片120之間的距離D2小於鰭片120和鰭片130之間的距離D3時可能會出現負載效應，但隔離結構20的部分210和部分220之間標高的差值D1相對較小，因此鰭片的高度相對均勻。因此，半導體結構1可避免包括兩個鰭片彼此相對靠近的區域，以及在其間形成的隔離部分不預期的降低鰭片的高度。因此，半導體結構1(例如，包括鰭片的電晶體)可具有令人滿意的性能，例如，具有令人滿意的開關靈敏度和/或功能。In some embodiments, the fin height of fins 110 , 120 , 130 , 140 , and 150 in trench 30A is defined by the difference in elevation between fins 110 , 120 , 130 , 140 , and 150 and isolation structure 20 . According to some embodiments of the present disclosure, portions 210 and The difference D1 in elevation between sections 220 is relatively small, so the height of the fins is relatively uniform. Therefore, the semiconductor structure 1 can avoid including regions where two fins are relatively close to each other, and an isolation portion formed therebetween undesirably reduces the height of the fins. Accordingly, the semiconductor structure 1 (eg, a transistor comprising fins) may have satisfactory performance, eg, have satisfactory switching sensitivity and/or functionality.
圖2、圖2A、圖2B、圖3、圖3A、圖3B、圖4、圖4A、圖5、圖5A、圖5B例示本揭露一些實施例之半導體結構1的製備方法的各個階段。2 , 2A, 2B, 3 , 3A, 3B, 4 , 4A, 5 , 5A, and 5B illustrate various stages of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure.
參照圖2、圖2A和圖2B，圖2是頂視圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，圖2A是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，以及圖2B是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段。在一些實施例中，圖2A是沿圖2的2A-2A'線的橫截面圖，圖2B是沿圖2的2B-2B'線的橫截面圖。Referring to FIG. 2, FIG. 2A and FIG. 2B, FIG. 2 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 2A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method of , and FIG. 2B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 2A is a cross-sectional view along line 2A-2A' of FIG. 2 , and FIG. 2B is a cross-sectional view along line 2B-2B' of FIG. 2 .
可提供包括複數個初始鰭片結構(例如，初始鰭片結構110A、120A、130A、140A、150A、160A和170A)的半導體基底10。半導體基底10可由，例如，矽、摻雜矽、矽鍺、絕緣體上的矽、藍寶石上的矽、絕緣體上的矽鍺、碳化矽、鍺、砷化鎵、磷化鎵、磷化銦、磷化鎵銦、或任何其他IV-IV族、III-V族或I-VI族半導體材料形成。半導體基底10的初始鰭片結構的數量可根據實際應用而變化，並且不限於此。A semiconductor substrate 10 including a plurality of initial fin structures (eg, initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A) may be provided. The semiconductor substrate 10 can be made of, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, indium phosphide, phosphorus GaIn2, or any other IV-IV, III-V, or I-VI semiconductor material. The number of initial fin structures of the semiconductor substrate 10 may vary according to practical applications, and is not limited thereto.
可執行黃光微影(Photolithography)來對半導體基底10進行圖案化處理，以定義複數個初始鰭片結構110A、120A、130A、140A、150A、160A和170A的位置。在黃光微影製程之後可進行蝕刻，以在半導體基底10中形成複數個溝槽。Photolithography can be performed to pattern the semiconductor substrate 10 to define the positions of the plurality of initial fin structures 110A, 120A, 130A, 140A, 150A, 160A and 170A. Etching may be performed after the lithography process to form a plurality of trenches in the semiconductor substrate 10 .
經蝕刻以在半導體基底10中形成複數個溝槽之後，可形成隔離材料20A以覆蓋複數個初始鰭片結構110A、120A、130A、140A、150A、160A和170A。隔離材料20A可藉由沉積來填充半導體基底10的複數個溝槽。隔離材料20A可包括例如氧化矽、氮化矽、氮氧化矽或其組合。After being etched to form trenches in semiconductor substrate 10 , isolation material 20A may be formed to cover initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A. The isolation material 20A can be deposited to fill the plurality of trenches of the semiconductor substrate 10 . The isolation material 20A may include, for example, silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
可在隔離材料20A和半導體基底10的初始鰭片結構110A、120A、130A、140A、150A、160A和170A上設置一圖案化的硬遮罩HM。可在隔離材料20A和半導體基底10的初始鰭片結構110A、120A、130A、140A、150A、160A和170A上沉積一硬遮罩，然後可根據一圖案化光阻層對硬遮罩進行圖案化，以形成具有複數個開口，以曝露半導體基底10的隔離材料20A和初始鰭片結構110A、120A、130A、140A、150A、160A和170A部分的圖案化的硬遮罩HM。圖案化的硬遮罩HM可以有一預定的圖案，用於形成複數個穿過半導體基底10的隔離材料20A以及初始鰭片結構110A、120A、130A、140A、150A、160A和170A的溝槽(例如，隨後形成導電元件30的溝槽30A，這將在下文討論)。圖案化的硬遮罩HM的開口對應於穿過半導體基底10的隔離材料20A以及初始鰭片結構110A、120A、130A、140A、150A、160A和170A的溝槽(例如，形成導電元件30的溝槽30A)的位置。A patterned hard mask HM may be disposed on the isolation material 20A and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A of the semiconductor substrate 10 . A hard mask can be deposited over the isolation material 20A and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A of the semiconductor substrate 10, which can then be patterned according to a patterned photoresist layer , to form a patterned hard mask HM having a plurality of openings to expose portions of the isolation material 20A and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A of the semiconductor substrate 10 . The patterned hard mask HM may have a predetermined pattern for forming a plurality of trenches (eg, , followed by the formation of the trench 30A of the conductive element 30, which will be discussed below). The openings of the patterned hard mask HM correspond to trenches (eg, trenches forming conductive elements 30 ) through the isolation material 20A of the semiconductor substrate 10 and the initial fin structures 110A, 120A, 130A, 140A, 150A, 160A, and 170A. slot 30A) position.
在一些實施例中，圖案化的硬遮罩HM可包括一雙抗反射塗層(DARC)、DARC上的一碳層以及碳層上的一氮化物層。DARC和碳層可根據一圖案化光阻層進行圖案化，將一預定圖案從圖案化光阻層轉移到DARC和碳層。接下來，可以移除圖案化光阻層，並根據圖案化的DARC和圖案化的碳層對氮化物層進行圖案化，將預定圖案從DARC和碳層轉移到氮化物層。在一些實施例中，圖案化的DARC、圖案化的碳層和圖案化的氮化物層共同構成圖案化的硬遮罩HM。In some embodiments, the patterned hard mask HM may include a dual anti-reflective coating (DARC), a carbon layer on the DARC, and a nitride layer on the carbon layer. The DARC and carbon layer can be patterned according to a patterned photoresist layer, transferring a predetermined pattern from the patterned photoresist layer to the DARC and carbon layer. Next, the patterned photoresist layer may be removed, and the nitride layer is patterned according to the patterned DARC and patterned carbon layer, transferring a predetermined pattern from the DARC and carbon layer to the nitride layer. In some embodiments, the patterned DARC, the patterned carbon layer, and the patterned nitride layer together constitute the patterned hard mask HM.
在一些實施例中，圖2A是圖案化的硬遮罩HM的開口所在的橫截面，圖2B是圖案化的硬遮罩HM所在的橫截面。In some embodiments, FIG. 2A is a cross-section where the opening of the patterned hard mask HM is located, and FIG. 2B is a cross-section where the patterned hard mask HM is located.
參照圖3、圖3A和圖3B，圖3是頂視圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，圖3A是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，以及圖3B是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段。在一些實施例中，圖3A是沿圖3的3A-3A'線的橫截面圖，而圖3B是沿圖3的3B-3B'線的橫截面圖。Referring to FIG. 3, FIG. 3A and FIG. 3B, FIG. 3 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 3A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method of , and FIG. 3B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 3A is a cross-sectional view along line 3A- 3A' of FIG. 3 , and FIG. 3B is a cross-sectional view along line 3B-3B' of FIG. 3 .
可對半導體基底10的初始鰭片結構110A、120A、130A、140A和150A和隔離材料20A執行移除操作E1，以形成複數個溝槽30A。在一些實施例中，對半導體基底10的初始鰭片結構110A、120A、130A、140A和150A和隔離材料20A執行移除操作，以在溝槽30A中形成複數個鰭片(例如，鰭片110、120、130、140和150)以及圍繞複數個鰭片的隔離層20B。在一些實施例中，鰭片(例如，鰭片120)的頂面(例如，頂面120a)與隔離層20B的頂面201B之間的標高差D5小於約10奈米。在一些實施例中，鰭片(例如鰭片120)的頂面(例如頂面120a)與隔離層20B的頂面201B之間的標高差D5小於約5奈米。在一些實施例中，鰭片(例如鰭片120)的頂面(例如頂面120a)與隔離層20B的頂面201B之間的標高差D5小於約3奈米。The removal operation E1 may be performed on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form a plurality of trenches 30A. In some embodiments, the removal operation is performed on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form a plurality of fins (eg, fins 110A) in the trenches 30A. , 120, 130, 140 and 150) and an isolation layer 20B surrounding a plurality of fins. In some embodiments, the elevation difference D5 between the top surface (eg, top surface 120a ) of the fin (eg, fin 120 ) and the top surface 201B of the isolation layer 20B is less than about 10 nm. In some embodiments, the elevation difference D5 between the top surface (eg, top surface 120a ) of the fin (eg, fin 120 ) and the top surface 201B of the isolation layer 20B is less than about 5 nm. In some embodiments, the elevation difference D5 between the top surface (eg, top surface 120a ) of the fin (eg, fin 120 ) and the top surface 201B of the isolation layer 20B is less than about 3 nm.
在一些實施例中，移除操作E1可以是或包括對半導體基底10的初始鰭片結構110A、120A、130A、140A和150A以及隔離材料20A執行一非等向性的蝕刻操作，以形成複數個溝槽30A。在一些實施例中，移除操作E1可以是或包括對半導體基底10的初始鰭片結構110A、120A、130A、140A和150A以及隔離材料20A執行一非等向性的蝕刻操作，以在溝槽30A中形成鰭片110、120、130、140和150。In some embodiments, the removal operation E1 may be or include performing an anisotropic etching operation on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form a plurality of Groove 30A. In some embodiments, the removal operation E1 may be or include performing an anisotropic etching operation on the initial fin structures 110A, 120A, 130A, 140A, and 150A and the isolation material 20A of the semiconductor substrate 10 to form Fins 110, 120, 130, 140 and 150 are formed in 30A.
在一些實施例中，非等向性的蝕刻操作是根據圖案化的硬遮罩HM來執行。在一些實施例中，非等向性的蝕刻操作包括一乾式蝕刻操作。在一些實施例中，乾式蝕刻製程包括例如電漿蝕刻或反應性離子蝕刻。在一些實施例中，乾式蝕刻製程可使用HBr和O2做為蝕刻氣體。在一些實施例中，乾式蝕刻製程可使用CF4/O2/Ar做為蝕刻氣體。在一些實施例中，非等向性的蝕刻操作移除部分初始鰭片結構110A、120A、130A、140A和150A以形成鰭片110、120、130、140和150。在一些實施例中，非等向性的蝕刻操作移除隔離材料20的一部分以形成隔離層20B。In some embodiments, the anisotropic etch operation is performed according to the patterned hard mask HM. In some embodiments, the anisotropic etching operation includes a dry etching operation. In some embodiments, the dry etching process includes, for example, plasma etching or reactive ion etching. In some embodiments, the dry etching process may use HBr and O2 as etching gases. In some embodiments, the dry etching process may use CF4/O2/Ar as the etching gas. In some embodiments, an anisotropic etch operation removes portions of initial fin structures 110A, 120A, 130A, 140A, and 150A to form fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, the anisotropic etch operation removes a portion of isolation material 20 to form isolation layer 20B.
如圖3A所示，輔助線20A1可指示在移除操作E1之前隔離材料20A的頂面的標高或位置，而輔助線110a1和120a1可指示初始鰭片結構110A和120A的頂面的標高或位置。在一些實施例中，由移除操作E1移除的隔離材料20A的部分具有厚度D6。在一些實施例中，由移除操作E1移除的初始鰭片結構110A的部分和由移除操作E1移除的初始鰭片結構120A的部分具有厚度D4。As shown in FIG. 3A , auxiliary line 20A1 may indicate the elevation or location of the top surface of isolation material 20A prior to removal operation E1, while auxiliary lines 110a1 and 120a1 may indicate the elevation or location of the top surface of initial fin structures 110A and 120A. . In some embodiments, the portion of isolation material 20A removed by removal operation E1 has a thickness D6. In some embodiments, the portion of the initial fin structure 110A removed by the removal operation E1 and the portion of the initial fin structure 120A removed by the removal operation E1 have a thickness D4.
如圖3B所示，在移除操作E1之後，在圖案化的硬遮罩HM下的初始鰭片結構110A、120A、130A、140A和150A的剩餘部分可以形成結構110A'、120A'、130A'、140A'和150A'。As shown in FIG. 3B , after removal operation E1 , the remainder of the initial fin structures 110A, 120A, 130A, 140A, and 150A under the patterned hard mask HM may form structures 110A′, 120A′, 130A′ , 140A' and 150A'.
參照圖4、圖4A和圖4B，圖4是頂視圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，圖4A是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，以及圖4B是橫截面圖，例示本揭露的一些實施例之半導體結構1的製備方法的一個階段。在一些實施例中，圖4A是沿圖4的線4A-4A'的橫截面圖，圖4B是沿圖4的線4B-4B'的橫截面圖。Referring to FIG. 4, FIG. 4A and FIG. 4B, FIG. 4 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 4A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method of , and FIG. 4B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 4A is a cross-sectional view along line 4A-4A' of FIG. 4 and FIG. 4B is a cross-sectional view along line 4B-4B' of FIG. 4 .
可對隔離層20B執行移除操作E2，以形成圍繞鰭片110、120、130、140和150的隔離結構20。在一些實施例中，隔離結構20的頂面低於鰭片110、120、130、140和150的頂面約20奈米至約40奈米。在一些實施例中，隔離結構20的頂面低於鰭片110、120、130、140和150的頂面約25奈米至約35奈米。The removal operation E2 may be performed on the isolation layer 20B to form the isolation structure 20 surrounding the fins 110 , 120 , 130 , 140 and 150 . In some embodiments, the top surface of the isolation structure 20 is about 20 nm to about 40 nm lower than the top surface of the fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, the top surface of isolation structure 20 is about 25 nm to about 35 nm lower than the top surface of fins 110 , 120 , 130 , 140 , and 150 .
在一些實施例中，鰭片110、120、130、140和150的頂面與隔離層20B的頂面201B之間的標高差D5在移除操作E2之前小於約5奈米。在一些實施例中，隔離結構20的頂面在移除操作E2後低於複數個鰭片110、120、130、140和150的頂面約20奈米至約40奈米。在一些實施例中，隔離結構20的頂面在移除操作E2後低於複數個鰭片110、120、130、140和150的頂面約25奈米至約35奈米。In some embodiments, the elevation difference D5 between the top surfaces of the fins 110 , 120 , 130 , 140 , and 150 and the top surface 201B of the isolation layer 20B is less than about 5 nm prior to the removal operation E2 . In some embodiments, the top surface of the isolation structure 20 is lower than the top surfaces of the plurality of fins 110 , 120 , 130 , 140 and 150 by about 20 nm to about 40 nm after the removal operation E2 . In some embodiments, the top surface of the isolation structure 20 is lower than the top surfaces of the plurality of fins 110 , 120 , 130 , 140 and 150 by about 25 nm to about 35 nm after the removal operation E2 .
在一些實施例中，移除操作E2可以是或包括對隔離層20B執行一等向性的蝕刻操作，以形成隔離結構20。在一些實施例中，等向性的蝕刻操作包括一濕式蝕刻操作。在一些實施例中，濕式蝕刻操作的蝕刻劑包括含氟的蝕刻劑。在一些實施例中，在濕式蝕刻操作中使用氫氟酸做為蝕刻劑。在一些實施例中，稀釋的氫氟酸(DHF 200:1)被做為濕式蝕刻操作的蝕刻劑。在一些實施例中，濕式蝕刻操作(即移除操作E2)相對於隔離層20B而言，對鰭片110、120、130、140和150具有高度選擇性。在一些實施例中，鰭片110、120、130、140和150幾乎沒有或甚至實質上上沒有被移除操作E2移除或蝕刻。In some embodiments, the removing operation E2 may be or include performing an isotropic etching operation on the isolation layer 20B to form the isolation structure 20 . In some embodiments, the isotropic etching operation includes a wet etching operation. In some embodiments, the etchant of the wet etching operation includes a fluorine-containing etchant. In some embodiments, hydrofluoric acid is used as an etchant in wet etching operations. In some embodiments, dilute hydrofluoric acid (DHF 200:1) is used as the etchant for the wet etching operation. In some embodiments, the wet etching operation (ie, removal operation E2 ) is highly selective to fins 110 , 120 , 130 , 140 , and 150 relative to isolation layer 20B. In some embodiments, fins 110 , 120 , 130 , 140 , and 150 are hardly or even substantially not removed or etched by removal operation E2 .
在一些實施例中，等向性的蝕刻操作(即，移除操作E2)移除隔離層20B的一部分，以形成曝露鰭片110、120、130、140和150的隔離結構20。在一些實施例中，等向性的蝕刻操作(即移除操作E2)被執行約10秒至約40秒。在一些實施例中，等向性的蝕刻操作(即移除操作E2)被執行約20秒至約30秒。在一些實施例中，等向性的蝕刻操作(即移除操作E2)的執行時間少於約60秒。在一些實施例中，等向性的蝕刻操作(即移除操作E2)的執行時間比非等向性的蝕刻操作(即移除操作E1)的時間短。在一些實施例中，等向性的蝕刻操作(即移除操作E2)被執行足夠長的時間，以確定鰭片110、120、130、140和150的鰭片高度。在一些實施例中，等向性的蝕刻操作(即，移除操作E2)被執行的時間段短到足以防止過度蝕刻除隔離層20B以外的結構和/或元件。In some embodiments, the isotropic etching operation (ie, removal operation E2 ) removes a portion of the isolation layer 20B to form the isolation structure 20 exposing the fins 110 , 120 , 130 , 140 and 150 . In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for about 10 seconds to about 40 seconds. In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for about 20 seconds to about 30 seconds. In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for less than about 60 seconds. In some embodiments, the execution time of the isotropic etching operation (ie, removal operation E2 ) is shorter than that of the anisotropic etching operation (ie, removal operation E1 ). In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed long enough to determine the fin heights of the fins 110 , 120 , 130 , 140 , and 150 . In some embodiments, the isotropic etching operation (ie, removal operation E2 ) is performed for a period of time short enough to prevent over-etching of structures and/or elements other than isolation layer 20B.
在一些實施例中，移除操作E2是在移除操作E1之後執行。在一些實施例中，非等向性的蝕刻操作(即，移除操作E2)在非等向性的蝕刻操作(即，移除操作E1)之後執行。在一些實施例中，非等向性的蝕刻操作(即，移除操作E1)和等向性蝕刻操作(即，移除操作E2)都是根據圖案化的硬遮罩HM執行。In some embodiments, the removal operation E2 is performed after the removal operation E1. In some embodiments, the anisotropic etching operation (ie, removal operation E2 ) is performed after the anisotropic etching operation (ie, removal operation E1 ). In some embodiments, both anisotropic etching operation (ie, removal operation E1 ) and isotropic etching operation (ie, removal operation E2 ) are performed according to the patterned hard mask HM.
如圖4A所示，輔助線201B1可以表示在移除操作E2之前隔離層20B的頂面的標高或位置。在一些實施例中，藉由移除操作E2移除的隔離層20B的部分具有厚度D7。在一些實施例中，厚度D7為約20奈米至約40奈米。在一些實施例中，厚度D7為約25奈米至約35奈米。在一些實施例中，厚度D7實質上等於一預定的鰭片高度。在一些實施例中，移除操作E2移除隔離層20B的一部分，確定溝槽30A中的鰭片110、120、130、140和150的鰭片高度。As shown in FIG. 4A , the auxiliary line 201B1 may indicate the elevation or position of the top surface of the isolation layer 20B before the removal operation E2. In some embodiments, the portion of isolation layer 20B removed by removal operation E2 has a thickness D7. In some embodiments, thickness D7 is about 20 nm to about 40 nm. In some embodiments, thickness D7 is about 25 nm to about 35 nm. In some embodiments, the thickness D7 is substantially equal to a predetermined fin height. In some embodiments, removal operation E2 removes a portion of isolation layer 20B, determining the fin heights of fins 110 , 120 , 130 , 140 , and 150 in trenches 30A.
參照圖5、圖5A和圖5B，圖5是頂視圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，圖5A是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段，和圖5B是橫截面圖，例示本揭露一些實施例之半導體結構1的製備方法的一個階段的。在一些實施例中，圖5A是沿圖5的線5A-5A'的橫截面圖，圖5B是沿圖5的線5B-5B'的橫截面圖。Referring to FIG. 5, FIG. 5A and FIG. 5B, FIG. 5 is a top view illustrating a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 5A is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. A stage of the fabrication method, and FIG. 5B is a cross-sectional view illustrating a stage of the fabrication method of the semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 5A is a cross-sectional view along line 5A-5A' of FIG. 5 and FIG. 5B is a cross-sectional view along line 5B-5B' of FIG. 5 .
在一些實施例中，一個或複數個導電元件30可以形成在鰭片110、120、130、140和150上。在一些實施例中，一個或複數個導電元件30可以形成在溝槽30A中的鰭片110、120、130、140和150上。在一些實施例中，一個或複數個導電元件30可以形成在溝槽30A的隔離結構20上。In some embodiments, one or a plurality of conductive elements 30 may be formed on the fins 110 , 120 , 130 , 140 and 150 . In some embodiments, one or a plurality of conductive elements 30 may be formed on the fins 110 , 120 , 130 , 140 and 150 in the trench 30A. In some embodiments, one or a plurality of conductive elements 30 may be formed on the isolation structure 20 of the trench 30A.
根據本揭露的一些實施例，移除操作E1包括一等向性的蝕刻操作(或一定向操作)，因此，鰭片和隔離層可在由圖案化的硬遮罩定義的溝槽中形成一實質上相同標高的頂面。因此，移除操作E2可用於精確地定義鰭片的高度。According to some embodiments of the present disclosure, the removal operation E1 includes an isotropic etching operation (or an directional operation), so that the fins and isolation layers can form an Top surfaces of substantially the same elevation. Therefore, removal operation E2 can be used to precisely define the height of the fin.
此外，根據本揭露的一些實施例，移除操作E2包括一等向性的蝕刻操作(例如，一濕式蝕刻操作)，因此，蝕刻劑的液相的流動性可以使蝕刻劑穿透小特徵(例如，相對靠近的兩個鰭片之間的隔離部分)。因此，蝕刻的均勻性明顯提高，因此鰭片之間的隔離部分可以被蝕刻掉的高度或數量實質上相等，因此可以明顯提高成型鰭片高度的均勻性。In addition, according to some embodiments of the present disclosure, the removal operation E2 includes an isotropic etching operation (eg, a wet etching operation), and thus, the fluidity of the liquid phase of the etchant allows the etchant to penetrate small features. (For example, the isolation part between two fins that are relatively close together). Therefore, the uniformity of etching is significantly improved, so the height or quantity of the isolation portions between the fins that can be etched away is substantially equal, and thus the uniformity of the height of the formed fins can be significantly improved.
此外，根據本揭露的一些實施例，鰭片和隔離結構的形成包括用於移除初始鰭片結構和隔離材料的相對較大部分的一乾式蝕刻操作和更用於移除隔離材料(或隔離層)的一部分以定義鰭片高度的一濕式蝕刻操作。因此，由於濕式蝕刻操作只是負責移除相對較小部分的隔離材料(或隔離層)以確定鰭片高度，所以執行濕式蝕刻的時間可以相對較短，並且還可以防止隔離材料(或隔離層)以外的結構和/或元件的過度蝕刻。Furthermore, according to some embodiments of the present disclosure, the formation of the fin and isolation structures includes a dry etch operation for removing a relatively large portion of the initial fin structure and isolation material and further for removing the isolation material (or isolation layer) in a wet etch operation that defines the height of the fin. Therefore, since the wet etching operation is only responsible for removing a relatively small portion of the isolation material (or isolation layer) to determine the height of the fin, the time for performing the wet etching can be relatively short, and it can also prevent the isolation material (or isolation layer). layer) and/or overetching of elements other than
圖6是一個橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。6 is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.
在一些實施例中，在執行移除操作E1之後，對圖3、圖3A和圖3B所示的結構執行額外的移除操作E1(例如，一非等向性的蝕刻操作)，而不是執行一等向性操作(或移除操作E2)，可以形成隔離結構20C，隔離結構20C包括在鰭片120的相對兩側的部分210C和部分220C。在一些實施例中，由於負載效應，部分210C的頂面和部分220C的頂面之間的標高差D8可能相對較大。雖然由隔離結構20C的部分210C定義的鰭片110和120的鰭片高度相對較短，但包括鰭片110和120的電晶體當施加相對較低的電壓時可能會不預期地被打開，或者甚至一些負電荷在鰭片110和120之間通過。因此，由包括圖6所示階段的方法形成的半導體結構(例如，包括鰭片110和120的電晶體)可能無法具有令人滿意的性能，例如，具有低開關靈敏度In some embodiments, after performing the removal operation E1, an additional removal operation E1 (for example, an anisotropic etching operation) is performed on the structure shown in FIG. 3 , FIG. 3A and FIG. 3B , instead of performing An isotropic operation (or removal operation E2 ), the isolation structure 20C may be formed, and the isolation structure 20C includes a portion 210C and a portion 220C on opposite sides of the fin 120 . In some embodiments, the difference in elevation D8 between the top surface of portion 210C and the top surface of portion 220C may be relatively large due to loading effects. Although the fin height of fins 110 and 120 defined by portion 210C of isolation structure 20C is relatively short, the transistors comprising fins 110 and 120 may be turned on unexpectedly when a relatively low voltage is applied, or Even some negative charges pass between fins 110 and 120 . Therefore, semiconductor structures (eg, transistors including fins 110 and 120) formed by a method including the stages shown in FIG. 6 may not have satisfactory performance, eg, low switching sensitivity
圖7是流程圖，例示本揭露一些實施例之半導體結構的製備方法70。FIG. 7 is a flowchart illustrating a method 70 of fabricating a semiconductor structure according to some embodiments of the present disclosure.
製備方法70從操作S71開始，其中提供包括複數個初始鰭片結構的半導體基底。The fabrication method 70 begins with operation S71, wherein a semiconductor substrate including a plurality of initial fin structures is provided.
製備方法70繼續進行操作S72，其中形成覆蓋複數個初始鰭片結構的隔離材料。The manufacturing method 70 proceeds to operation S72, wherein an isolation material covering the plurality of initial fin structures is formed.
製備方法70繼續進行操作S73，其中對隔離材料和複數個初始鰭片結構執行非等向性的蝕刻操作，以形成複數個鰭片。The fabrication method 70 proceeds to operation S73 , wherein an anisotropic etching operation is performed on the isolation material and the plurality of initial fin structures to form the plurality of fins.
製備方法70繼續進行操作S74，其中對隔離材料執行等向性的蝕刻操作，以形成圍繞複數個鰭片的隔離結構。The fabrication method 70 continues with operation S74 , wherein an isotropic etching operation is performed on the isolation material to form an isolation structure surrounding the plurality of fins.
製備方法70僅僅是一個例子，並不旨在將本揭露內容限制在申請專利範圍中明確提到的範圍之外。可以在製備方法70的每個操作之前、期間或之後提供額外的操作，並且所述的一些操作可以被替換、消除或移動，以用於該方法的其他實施例。在一些實施例中，製備方法70還可以包括圖7中未描繪的操作。在一些實施例中，製備方法70可以包括圖7中描述的一個或複數個操作。The preparation method 70 is just an example, and is not intended to limit the present disclosure beyond what is expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 70, and some of the operations described may be replaced, eliminated, or moved for use in other embodiments of the method. In some embodiments, preparation method 70 may also include operations not depicted in FIG. 7 . In some embodiments, preparation method 70 may include one or more of the operations described in FIG. 7 .
圖8是流程圖，例示本揭露一些實施例之半導體結構的製備方法80。FIG. 8 is a flowchart illustrating a method 80 of fabricating a semiconductor structure according to some embodiments of the present disclosure.
製備方法80從操作S81開始，其中提供包括複數個初始鰭片結構的半導體基底。The fabrication method 80 begins with operation S81, wherein a semiconductor substrate including a plurality of initial fin structures is provided.
製備方法80繼續進行操作S82，其中形成覆蓋複數個初始鰭片結構的隔離材料。The manufacturing method 80 continues with operation S82, wherein an isolation material covering the plurality of initial fin structures is formed.
製備方法80繼續進行操作S83，其中對複數個初始鰭片結構和隔離材料執行第一移除操作，以形成複數個鰭片和圍繞複數個鰭片的隔離層。在一些實施例中，複數個鰭片的頂面與隔離層的頂面之間的標高差小於約10奈米The fabrication method 80 proceeds to operation S83 , wherein a first removal operation is performed on the plurality of initial fin structures and the isolation material to form the plurality of fins and the isolation layer surrounding the plurality of fins. In some embodiments, the difference in elevation between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nanometers
製備方法80繼續進行操作S84，其中對隔離層執行第二移除操作，以形成圍繞複數個鰭片的隔離結構。在一些實施例中，隔離結構的頂面低於複數個鰭片的頂面約20奈米至約40奈米。The manufacturing method 80 continues with operation S84 , wherein a second removal operation is performed on the isolation layer to form an isolation structure surrounding the plurality of fins. In some embodiments, the top surface of the isolation structure is about 20 nm to about 40 nm lower than the top surface of the plurality of fins.
製備方法80僅僅是一個例子，並不旨在將本揭露內容限制在申請專利範圍明確提到的範圍之外。可以在製備方法80的每個操作之前、期間或之後提供額外的操作，並且所述的一些操作可以被替換、消除或移動，以用於該方法的其他實施例。在一些實施例中，製備方法80還可以包括圖8中未描繪的操作。在一些實施例中，製備方法80可以包括圖8中描述的一個或複數個操作。The preparation method 80 is merely an example, and is not intended to limit the present disclosure beyond what is expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 80, and some of the operations described may be replaced, eliminated, or moved for use in other embodiments of the method. In some embodiments, preparation method 80 may also include operations not depicted in FIG. 8 . In some embodiments, preparation method 80 may include one or more of the operations described in FIG. 8 .
本揭露的一個方面提供一種半導體結構，包括一半導體基底和一隔離結構。該半導體基底包括一第一鰭片。該隔離結構定義該第一鰭片。該隔離結構包括位於該第一鰭片的兩個相對側面的一第一部分和一第二部分。該第一部分的頂面標高與該第二部分的頂面標高之間的差值大於0且小於約5奈米。One aspect of the present disclosure provides a semiconductor structure, including a semiconductor substrate and an isolation structure. The semiconductor base includes a first fin. The isolation structure defines the first fin. The isolation structure includes a first portion and a second portion located on two opposite sides of the first fin. The difference between the top surface elevation of the first portion and the top surface elevation of the second portion is greater than 0 and less than about 5 nanometers.
本揭露的另一個方面提供一種半導體結構的製備方法。該製備方法包括提供一半導體基底，包括複數個初始鰭片結構。該製備方法還包括形成一隔離材料以覆蓋複數個初始鰭結構。該製備方法還包括對該隔離材料和該複數個初始鰭片結構執行一非等向性的蝕刻操作，以形成該複數個鰭片。該製備方法還包括在該隔離材料上執行一等向性的蝕刻操作，以形成一隔離結構，以圍繞該複數個鰭片。Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form the plurality of fins. The manufacturing method further includes performing an isotropic etching operation on the isolation material to form an isolation structure to surround the plurality of fins.
本揭露的另一個方面提供一種半導體結構的製備方法。該製備方法包括提供一半導體基底，包括複數個初始鰭片結構。該製備方法還包括形成一隔離材料以覆蓋該複數個初始鰭片結構。該製備方法還包括對該複數個初始鰭片結構和該隔離材料執行一第一移除操作，以形成複數個鰭片和圍繞該複數個鰭片的一隔離層。該複數個鰭片的頂面與該隔離層的頂面之間的高度差小於約10奈米。該製備方法還包括對該隔離層執行一第二移除操作，以形成一隔離結構，以圍繞該複數個鰭片，其中該隔離結構的頂面低於該複數個鰭片的頂面約20奈米至約40奈米。Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes providing a semiconductor substrate including a plurality of initial fin structures. The fabrication method further includes forming an isolation material to cover the plurality of initial fin structures. The fabrication method also includes performing a first removal operation on the plurality of initial fin structures and the isolation material to form the plurality of fins and an isolation layer surrounding the plurality of fins. The height difference between the top surfaces of the plurality of fins and the top surface of the isolation layer is less than about 10 nm. The manufacturing method further includes performing a second removal operation on the isolation layer to form an isolation structure to surround the plurality of fins, wherein the top surface of the isolation structure is about 20° lower than the top surface of the plurality of fins. nm to about 40 nm.
在半導體結構的製備方法中，形成鰭片和定義鰭片的隔離結構包括用於移除初始鰭片結構和隔離材料的相對較大部分的乾式蝕刻操作，和更用於移除隔離材料(或隔離層)的一部分以定義鰭片高度的濕式蝕刻操作。濕式蝕刻操作的蝕刻劑液相的流動性可以使蝕刻劑穿透小的特徵(例如，兩個相對靠近的鰭片之間的隔離部分)。因此，蝕刻的均勻性明顯提高，因此，鰭片之間的隔離部分可以被蝕刻掉的高度或數量實質上相等，因此可顯著提高成型鰭片高度的均勻性。此外，執行濕式蝕刻的時間可以相對較短，並且更可防止隔離材料(或隔離層)以外的結構和/或元件的過度蝕刻。In a method of fabricating a semiconductor structure, forming the fins and defining the isolation structures of the fins includes a dry etch operation for removing a relatively large portion of the initial fin structure and isolation material, and moreover for removing the isolation material (or part of the isolation layer) to define the fin height wet etch operation. The fluidity of the etchant liquid phase of the wet etch operation may allow the etchant to penetrate small features (eg, an isolated portion between two relatively close fins). Therefore, the uniformity of etching is significantly improved, and therefore, the height or amount of the isolation portions between the fins that can be etched away is substantially equal, and thus the uniformity of the height of the formed fins can be significantly improved. In addition, the time for performing wet etching can be relatively short, and over-etching of structures and/or elements other than the isolation material (or isolation layer) can be more prevented.
雖然已詳述本揭露及其優點，然而應理解可以進行其他變化、取代與替代而不脫離揭露專利範圍所界定之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.
再者，本揭露案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解以根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包括於本揭露案之揭露專利範圍內。Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.
1:半導體結構 1A-1A':截面線 2A-2A':線 2B-2B':線 10:半導體基底 20:隔離結構 20A:隔離材料 20A1:輔助線 20B:隔離層 20C:隔離結構 30:導電元件 30A:溝槽 3A-3A':線 3B-3B':線 4A-4A':線 4B-4B':線 5A-5A':線 5B-5B':線 70:製備方法 80:製備方法 110:鰭片 110A:初始鰭片結構 110A':結構 110a1:輔助線 120:鰭片 120A:初始鰭片結構 120a:頂面 120A':結構 120a1:輔助線 130:鰭片 130A:初始鰭片結構 130A':結構 140:鰭片 140A:初始鰭片結構 140A':結構 140a:頂面 150:鰭片 150A:初始鰭片結構 150A':結構 160A:初始鰭片結構 170A:初始鰭片結構 201B:頂面 201B1:輔助線 210:部分 210a:頂面 210C:部分 220:部分 220a:頂面 220C:部分 230:部分 230a:頂面 240:部分 240a:頂面 D1:差值 D1A:差值 D2:距離 D2A:距離 D3:距離 D3A:距離 D4:厚度 D5:標高差 D6:厚度 D7:厚度 D8:標高差 E1:移除操作 E2:移除操作 HM:圖案化的硬遮罩 S71:操作 S72:操作 S73:操作 S74:操作 S81:操作 S82:操作 S83:操作 S84:操作 T1:距離 T1A:距離 T2:距離 T2A:距離 T3:厚度 T4:厚度 T3A:厚度 T4A:厚度 1: Semiconductor structure 1A-1A': section line 2A-2A': line 2B-2B': line 10: Semiconductor substrate 20: Isolation structure 20A: Isolation material 20A1: Auxiliary line 20B: isolation layer 20C: Isolation structure 30: Conductive element 30A: Groove 3A-3A': line 3B-3B': line 4A-4A': line 4B-4B': line 5A-5A': line 5B-5B': line 70: Preparation method 80: Preparation method 110: fins 110A: Initial fin structure 110A': structure 110a1: Auxiliary line 120: fins 120A: Initial fin structure 120a: top surface 120A': structure 120a1: auxiliary line 130: fins 130A: Initial fin structure 130A': structure 140: fins 140A: Initial fin structure 140A': structure 140a: top surface 150: fins 150A: Initial fin structure 150A': structure 160A: Initial fin structure 170A: Initial fin structure 201B: top surface 201B1: Auxiliary line 210: part 210a: top surface 210C: part 220: part 220a: top surface 220C: part 230: part 230a: top surface 240: part 240a: top surface D1: difference D1A: difference D2: distance D2A: Distance D3: Distance D3A: Distance D4: Thickness D5: Elevation difference D6: Thickness D7: Thickness D8: Elevation difference E1: remove operation E2: remove operation HM: patterned hard mask S71: Operation S72: Operation S73: Operation S74: Operation S81: Operation S82: Operation S83: Operation S84: Operation T1: Distance T1A: Distance T2: Distance T2A: Distance T3: Thickness T4: Thickness T3A: Thickness T4A: Thickness
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1是頂視圖，例示本揭露一些實施例之半導體結構。 圖1A是橫截面圖，例示本揭露一些實施例之半導體結構。 圖2是頂視圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖2A是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖2B是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖3是頂視圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖3A是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖3B是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖4是頂視圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖4A是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖4B是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖5是頂視圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖5A是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖5B是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖6是橫截面圖，例示本揭露一些實施例之半導體結構的製備方法的一個階段。 圖7是流程圖，例示本揭露一些實施例之半導體結構的製備方法。 圖8是流程圖，例示本揭露一些實施例之半導體結構的製備方法。 The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1 is a top view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 1A is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 2 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 2A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 2B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 3 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 3A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 3B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 4B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 5 is a top view illustrating a stage of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 5A is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 5B is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 6 is a cross-sectional view illustrating a stage in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. FIG. 7 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. FIG. 8 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.
1:半導體結構 1: Semiconductor structure
10:半導體基底 10: Semiconductor substrate
20:隔離結構 20: Isolation structure
30:導電元件 30: Conductive element
110:鰭片 110: fins
120:鰭片 120: fins
120a:頂面 120a: top surface
130:鰭片 130: fins
130A:初始鰭片結構 130A: Initial fin structure
140:鰭片 140: fins
140a:頂面 140a: top surface
150:鰭片 150: fins
210:部分 210: part
210a:頂面 210a: top surface
220:部分 220: part
220a:頂面 220a: top surface
230:部分 230: part
230a:頂面 230a: top surface
240:部分 240: part
240a:頂面 240a: top surface
D1:差值 D1: difference
D1A:差值 D1A: difference
D2:距離 D2: distance
D2A:距離 D2A: Distance
D3:距離 D3: Distance
D3A:距離 D3A: Distance
T1:距離 T1: Distance
T1A:距離 T1A: Distance
T2:距離 T2: Distance
T2A:距離 T2A: Distance
T3:厚度 T3: Thickness
T4:厚度 T4: Thickness
T3A:厚度 T3A: Thickness
T4A:厚度 T4A: Thickness
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| US17/573,787 US20230223298A1 (en) | 2022-01-12 | 2022-01-12 | Method of manufacturing semiconductor structure having fins |
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