TW202327065A - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- TW202327065A TW202327065A TW110146879A TW110146879A TW202327065A TW 202327065 A TW202327065 A TW 202327065A TW 110146879 A TW110146879 A TW 110146879A TW 110146879 A TW110146879 A TW 110146879A TW 202327065 A TW202327065 A TW 202327065A
- Authority
- TW
- Taiwan
- Prior art keywords
- electrode
- circuit substrate
- display device
- pads
- filler
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 239000000945 filler Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims description 32
- 239000004020 conductor Substances 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000012811 non-conductive material Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 125
- 239000004065 semiconductor Substances 0.000 description 17
- 238000000034 method Methods 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- 230000008439 repair process Effects 0.000 description 9
- 239000010408 film Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- -1 region Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Led Device Packages (AREA)
- Electroluminescent Light Sources (AREA)
- Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
- Vehicle Body Suspensions (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
Abstract
Description
本發明是有關於一種顯示裝置，具有提高的發光元件修補良率。The invention relates to a display device with improved repair yield of light-emitting elements.
微型發光元件（例如微型發光二極體，Micro-LED）顯示裝置具有省電、高效率、高亮度及反應時間快等優點。由於微型發光元件的尺寸極小，目前製作微型發光元件顯示裝置的方法是採用巨量轉移（Mass Transfer）技術，亦即利用微機電陣列技術進行微型發光元件取放，以將大量的微型發光元件一次搬運到電路基板上。Micro-light-emitting elements (such as micro-light-emitting diodes, Micro-LED) display devices have the advantages of power saving, high efficiency, high brightness, and fast response time. Due to the extremely small size of micro-light-emitting elements, the current method of manufacturing micro-light-emitting element display devices is to use mass transfer (Mass Transfer) technology, that is, to use micro-electromechanical array technology to pick and place micro-light-emitting elements, so as to transfer a large number of micro-light-emitting elements at one time. Transfer to the circuit board.
但是，巨量轉移技術常有發光元件錯位的情況發生，目前的一種做法是先移除錯位的微型發光元件及電路基板表面上的導電接墊，再重新置入導電材及發光元件來進行修補。然而，在修補過程中，由於電路基板的表面平坦度不佳，時常有對位影像模糊的現象出現，導致置入導電材及發光元件時不易對位。另外，電路基板的表面還存在供轉層走線連接的開口，造成上述導電材容易流入開口中，而無法順利連接後續置入的發光元件，導致發光元件修補良率不佳。However, the mass transfer technology often has misalignment of light-emitting elements. The current method is to remove the misplaced micro-light-emitting elements and the conductive pads on the surface of the circuit substrate, and then re-insert the conductive materials and light-emitting elements for repair. . However, during the repair process, due to the poor surface flatness of the circuit substrate, blurred alignment images often appear, which makes it difficult to align when placing conductive materials and light-emitting elements. In addition, there are openings on the surface of the circuit substrate for the connection of transfer layer wiring, so that the above-mentioned conductive materials are easy to flow into the openings, and cannot be successfully connected to the subsequently inserted light-emitting elements, resulting in a poor repair yield of the light-emitting elements.
本發明提供一種顯示裝置，具有提高的發光元件修補良率。The invention provides a display device with improved repair yield of light-emitting elements.
本發明的一個實施例提出一種顯示裝置，包括：電路基板，其表面具有多個開口，且包括位於表面上的多個接墊；發光元件，位於電路基板上，且發光元件包括第一電極、第二電極及發光疊層，其中，第一電極及第二電極分別電性連接對應的接墊與發光疊層中的不同層，且第一電極及第二電極於電路基板的正投影在多個開口之外；以及填充物，位於多個開口中。One embodiment of the present invention proposes a display device, comprising: a circuit substrate having a plurality of openings on its surface and including a plurality of pads on the surface; a light emitting element located on the circuit substrate, and the light emitting element includes a first electrode, The second electrode and the light-emitting stack, wherein the first electrode and the second electrode are respectively electrically connected to the corresponding pads and different layers in the light-emitting stack, and the orthographic projections of the first electrode and the second electrode on the circuit substrate are in multiple openings; and fillers, located in multiple openings.
在本發明的一實施例中，上述的填充物還從開口延伸至電路基板的表面上。In an embodiment of the present invention, the above-mentioned filler also extends from the opening to the surface of the circuit substrate.
在本發明的一實施例中，上述的填充物於表面上呈現L形、U形、中空多邊形或環形。In an embodiment of the present invention, the above-mentioned filler is L-shaped, U-shaped, hollow polygonal or ring-shaped on the surface.
在本發明的一實施例中，上述的填充物的頂面與電路基板的間距小於發光疊層與電路基板的間距。In an embodiment of the present invention, the distance between the top surface of the filler and the circuit substrate is smaller than the distance between the light emitting stack and the circuit substrate.
在本發明的一實施例中，上述的填充物包括不導電材料或導電材料。In an embodiment of the present invention, the above-mentioned filler includes non-conductive material or conductive material.
在本發明的一實施例中，上述的不導電材料為負型光阻。In an embodiment of the present invention, the above-mentioned non-conductive material is a negative photoresist.
在本發明的一實施例中，上述的導電材料為導電膠。In an embodiment of the present invention, the above-mentioned conductive material is conductive glue.
在本發明的一實施例中，上述的發光元件於電路基板的正投影位於開口之間。In an embodiment of the present invention, the above-mentioned orthographic projection of the light-emitting element on the circuit substrate is located between the openings.
在本發明的一實施例中，上述的填充物於電路基板的正投影不重疊發光元件的第一電極及第二電極於電路基板的正投影及其間的區域。In an embodiment of the present invention, the above-mentioned orthographic projection of the filler on the circuit substrate does not overlap the orthographic projection of the first electrode and the second electrode of the light-emitting element on the circuit substrate and the area therebetween.
在本發明的一實施例中，上述的多個接墊包括不同的材料。In an embodiment of the invention, the above-mentioned plurality of pads include different materials.
在本發明的一實施例中，上述的多個接墊分別包括金屬或導電膠。In an embodiment of the present invention, the above-mentioned plurality of pads respectively include metal or conductive glue.
在本發明的一實施例中，上述的第一電極及第二電極分別透過連接件電性連接接墊。In an embodiment of the present invention, the above-mentioned first electrode and the second electrode are respectively electrically connected to the pads through the connectors.
在本發明的一實施例中，上述的電路基板包括至少一導電層，且接墊通過開口電性連接導電層。In an embodiment of the present invention, the above-mentioned circuit substrate includes at least one conductive layer, and the pads are electrically connected to the conductive layer through the opening.
在本發明的一實施例中，上述的電路基板還包括至少一絕緣層，位於接墊與導電層之間，且開口位於絕緣層中。In an embodiment of the present invention, the above-mentioned circuit substrate further includes at least one insulating layer located between the pad and the conductive layer, and the opening is located in the insulating layer.
在本發明的一實施例中，上述的電路基板還包括開關元件，且第一電極及第二電極中之一者通過開口電性連接開關元件。In an embodiment of the present invention, the above-mentioned circuit substrate further includes a switch element, and one of the first electrode and the second electrode is electrically connected to the switch element through the opening.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
在附圖中，為了清楚起見，放大了層、膜、面板、區域等的厚度。在整個說明書中，相同的附圖標記表示相同的元件。應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時，其可以直接在另一元件上或與另一元件連接，或者中間元件可以也存在。相反地，當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時，不存在中間元件。如本文所使用的，「連接」可以指物理及/或電性連接。再者，「電性連接」或「耦接」可為二元件間存在其它元件。In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.
應當理解，儘管術語「第一」、「第二」、「第三」等在本文中可以用於描述各種元件、部件、區域、層及/或部分，但是這些元件、部件、區域、層及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此，下面討論的第一「元件」、「部件」、「區域」、「層」或「部分」可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
這裡使用的術語僅僅是為了描述特定實施例的目的，而不是限制性的。如本文所使用的，除非內容清楚地指示，否則單數形式「一」、「一個」和「該」旨在包括複數形式，包括「至少一個」或表示「及/或」。如本文所使用的，術語「及/或」包括一個或多個相關所列項目的任何和所有組合。還應當理解，當在本說明書中使用時，術語「包含」及/或「包括」指定所述特徵、區域、整體、步驟、操作、元件及/或部件的存在，但不排除一個或多個其它特徵、區域、整體、步驟、操作、元件、部件及/或其組合的存在或添加。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" or meaning "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the existence of said features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more Existence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.
此外，諸如「下」或「底部」和「上」或「頂部」的相對術語可在本文中用於描述一個元件與另一元件的關係，如圖所示。應當理解，相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如，如果一個附圖中的裝置翻轉，則被描述為在其他元件的「下」側的元件將被定向在其他元件的「上」側。因此，示例性術語「下」可以包括「下」和「上」的取向，取決於附圖的特定取向。類似地，如果一個附圖中的裝置翻轉，則被描述為在其它元件「下」或「下方」的元件將被定向為在其它元件「上方」。因此，示例性術語「下」或「下方」可以包括上方和下方的取向。Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
除非另有定義，本文使用的所有術語（包括技術和科學術語）具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義，並且將不被解釋為理想化的或過度正式的意義，除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.
本文參考作為理想化實施例的示意圖的截面圖來描述示例性實施例。因此，可以預期到作為例如製造技術及/或公差的結果的圖示的形狀變化。因此，本文所述的實施例不應被解釋為限於如本文所示的區域的特定形狀，而是包括例如由製造導致的形狀偏差。例如，示出或描述為平坦的區域通常可以具有粗糙及/或非線性特徵。此外，所示的銳角可以是圓的。因此，圖中所示的區域本質上是示意性的，並且它們的形狀不是旨在示出區域的精確形狀，並且不是旨在限制權利要求的範圍。Exemplary embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, may, typically, have rough and/or non-linear features. Additionally, acute corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.
圖1A是依照本發明一實施例的顯示裝置10的局部上視示意圖。圖1B是沿圖1A的剖面線A-A’所作的剖面示意圖。為了使圖式的表達較為簡潔，圖1A省略圖1B中的導電層C2及其下方的膜層。FIG. 1A is a schematic partial top view of a display device 10 according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. In order to make the expression of the figure more concise, FIG. 1A omits the conductive layer C2 and the film layer below it in FIG. 1B .
請參照圖1A至圖1B，顯示裝置10包括：電路基板110，其表面S1具有多個開口OP，且包括位於表面S1上的多個接墊P1、P2；發光元件120，位於電路基板110上，且發光元件120包括第一電極121、第二電極122及發光疊層123，其中，第一電極121及第二電極122分別電性連接接墊P1、P2與發光疊層123中的不同層，且第一電極121及第二電極122於電路基板110的正投影在多個開口OP之外；以及填充物FM，位於多個開口OP中。1A to 1B, the display device 10 includes: a circuit substrate 110, the surface S1 of which has a plurality of openings OP, and includes a plurality of pads P1, P2 on the surface S1; a light emitting element 120, located on the circuit substrate 110 , and the light-emitting element 120 includes a first electrode 121, a second electrode 122, and a light-emitting stack 123, wherein the first electrode 121 and the second electrode 122 are electrically connected to different layers of the pads P1, P2 and the light-emitting stack 123, respectively. , and the orthographic projections of the first electrode 121 and the second electrode 122 on the circuit substrate 110 are outside the plurality of openings OP; and the filler FM is located in the plurality of openings OP.
在本發明的一實施例的顯示裝置10中，藉由設置填入開口OP中的填充物FM，能夠避免後續形成接墊P1、P2的材料流入開口OP中，同時填充物FM還能夠充當對位標記，藉以提高修補製程的對位精準度。In the display device 10 according to an embodiment of the present invention, by providing the filler FM filled in the opening OP, it is possible to prevent the material for subsequently forming the pads P1 and P2 from flowing into the opening OP, and the filler FM can also serve as a countermeasure. Position marks to improve the alignment accuracy of the repair process.
以下，配合圖1A至圖1B，繼續說明顯示裝置10的各個元件的實施方式，但本發明不以此為限。Hereinafter, with reference to FIG. 1A to FIG. 1B , the implementation of each element of the display device 10 will be continuously described, but the present invention is not limited thereto.
在本實施例中，電路基板110可以包括底板112以及驅動電路層114。電路基板110的底板112可以是透明基板、不透明基板、撓性基板或不可撓基板，其材質可以是石英基板、玻璃基板、高分子基板或其他適當材質。驅動電路層114可以包括顯示裝置10需要的元件或線路，例如驅動元件、開關元件、儲存電容、電源線、驅動訊號線、時序訊號線、電流補償線、檢測訊號線等等。在一些實施例中，可以利用薄膜沉積製程、微影製程以及蝕刻製程，在底板112上形成驅動電路層114。驅動電路層114可以包括至少一絕緣層及至少一導電層，且驅動電路層114可以視需要包括更多的絕緣層以及導電層。In this embodiment, the circuit substrate 110 may include a bottom plate 112 and a driving circuit layer 114 . The bottom plate 112 of the circuit substrate 110 can be a transparent substrate, an opaque substrate, a flexible substrate or an inflexible substrate, and its material can be a quartz substrate, a glass substrate, a polymer substrate or other suitable materials. The driving circuit layer 114 may include elements or circuits required by the display device 10 , such as driving elements, switching elements, storage capacitors, power lines, driving signal lines, timing signal lines, current compensation lines, detection signal lines, and so on. In some embodiments, the driving circuit layer 114 can be formed on the base plate 112 by thin film deposition process, lithography process and etching process. The driving circuit layer 114 may include at least one insulating layer and at least one conductive layer, and the driving circuit layer 114 may include more insulating layers and conductive layers as required.
在本實施例中，驅動電路層114可以包括開關元件陣列，其中開關元件陣列包括排列成陣列的多個開關元件SW，且開關元件SW可以電性連接位於表面S1上的接墊P1、P2中之一者。舉例而言，驅動電路層114可以包括開關元件SW、緩衝層I1、閘極絕緣層I2、層間絕緣層I3、絕緣層I4、I5、I6以及導電層C1、C2、C3。開關元件SW是由半導體層CH、閘極GE、源極SE與汲極DE所構成。半導體層CH重疊閘極GE的區域可視為開關元件SW的通道區。緩衝層I1位於底板112與半導體層CH之間，用於防止底板112中的雜質移入半導體層CH中，並增強半導體層CH與底板112之間的黏合性。閘極絕緣層I2位於閘極GE與半導體層CH之間。層間絕緣層I3設置在源極SE與閘極GE之間以及汲極DE與閘極GE之間。閘極GE及源極SE可分別接收來自例如驅動元件的訊號。絕緣層I4設置於源極SE以及汲極DE與導電層C1之間，絕緣層I5設置於導電層C1與導電層C2之間，且絕緣層I6設置於導電層C2與導電層C3之間。導電層C1可以通過絕緣層I4中的通孔V1電性連接開關元件SW的汲極DE，導電層C2可以通過絕緣層I5中的通孔V2電性連接導電層C1，導電層C3可以延伸於絕緣層I6的開口OP中而電性連接導電層C2。接墊P1、P2可以設置於導電層C3上，且接墊P1、P2可以分別通過導電層C3電性連接導電層C2的不同區段。在本實施例中，接墊P2可以電性連接開關元件SW的汲極DE。In this embodiment, the driving circuit layer 114 may include a switch element array, wherein the switch element array includes a plurality of switch elements SW arranged in an array, and the switch elements SW may be electrically connected to the pads P1 and P2 on the surface S1 one of them. For example, the driving circuit layer 114 may include a switching element SW, a buffer layer I1 , a gate insulating layer I2 , an interlayer insulating layer I3 , insulating layers I4 , I5 , I6 , and conductive layers C1 , C2 , C3 . The switch element SW is composed of a semiconductor layer CH, a gate GE, a source SE and a drain DE. The region where the semiconductor layer CH overlaps the gate GE can be regarded as the channel region of the switching element SW. The buffer layer I1 is located between the base plate 112 and the semiconductor layer CH for preventing impurities in the base plate 112 from moving into the semiconductor layer CH and enhancing the adhesion between the semiconductor layer CH and the base plate 112 . The gate insulating layer I2 is located between the gate GE and the semiconductor layer CH. The interlayer insulating layer I3 is disposed between the source SE and the gate GE and between the drain DE and the gate GE. The gate GE and the source SE can respectively receive signals from, for example, driving elements. The insulating layer I4 is disposed between the source SE and the drain DE and the conductive layer C1 , the insulating layer I5 is disposed between the conductive layer C1 and the conductive layer C2 , and the insulating layer I6 is disposed between the conductive layer C2 and the conductive layer C3 . The conductive layer C1 can be electrically connected to the drain electrode DE of the switching element SW through the through hole V1 in the insulating layer I4, the conductive layer C2 can be electrically connected to the conductive layer C1 through the through hole V2 in the insulating layer I5, and the conductive layer C3 can extend to The opening OP of the insulating layer I6 is electrically connected to the conductive layer C2. The pads P1 , P2 can be disposed on the conductive layer C3 , and the pads P1 , P2 can be electrically connected to different sections of the conductive layer C2 through the conductive layer C3 . In this embodiment, the pad P2 can be electrically connected to the drain DE of the switch element SW.
半導體層CH的材質可以包括矽質半導體材料(例如多晶矽、非晶矽等)、氧化物半導體材料、有機半導體材料，但不限於此。閘極GE、源極SE、汲極DE以及導電層C1、C2的材質可以包括導電性良好的金屬，例如鋁、鉬、鈦、銅等金屬，但不限於此。導電層C3的材質可以包括銦錫氧化物（ITO）、銦鋅氧化物（IZO）、銦鎵鋅氧化物（IGZO）或其他適合的導電氧化物。在一些實施例中，導電層C1、C2、C3也可以分別具有單層結構或多層結構，多層結構例如上述導電金屬或導電氧化物中任意兩層或更多層的疊層，可視需要進行組合與變化。舉例而言，導電層C1可以包括依續堆疊的鈦層、鋁層以及鈦層或是依續堆疊的鉬層、鋁層以及鉬層，但不以此為限。The material of the semiconductor layer CH may include silicon semiconductor materials (such as polysilicon, amorphous silicon, etc.), oxide semiconductor materials, organic semiconductor materials, but not limited thereto. Materials of the gate GE, the source SE, the drain DE and the conductive layers C1 and C2 may include metals with good conductivity, such as aluminum, molybdenum, titanium, copper, etc., but not limited thereto. The material of the conductive layer C3 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) or other suitable conductive oxides. In some embodiments, the conductive layers C1, C2, and C3 can also have a single-layer structure or a multi-layer structure, and the multi-layer structure, such as a stack of any two or more layers of the above-mentioned conductive metal or conductive oxide, can be combined as required with change. For example, the conductive layer C1 may include a sequentially stacked titanium layer, an aluminum layer, and a titanium layer or a sequentially stacked molybdenum layer, an aluminum layer, and a molybdenum layer, but not limited thereto.
緩衝層I1、閘極絕緣層I2以及層間絕緣層I3的材質可以包括透明的無機絕緣材料，例如氧化矽、氮化矽、氮氧化矽或上述材料的疊層，但不限於此。絕緣層I4、I5、I6的材質可以包括透明的絕緣材料，例如有機材料、壓克力(acrylic)材料、矽氧烷(siloxane)材料、聚醯亞胺(polyimide)材料、環氧樹脂(epoxy)材料等，但不限於此。緩衝層I1、閘極絕緣層I2、層間絕緣層I3以及絕緣層I4、I5、I6也可以分別具有單層結構或多層結構，多層結構例如上述絕緣材料中任意兩層或更多層的疊層，可視需要進行組合與變化。Materials of the buffer layer I1 , the gate insulating layer I2 and the interlayer insulating layer I3 may include transparent inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or a stack of the above materials, but are not limited thereto. The materials of the insulating layers I4, I5, and I6 may include transparent insulating materials, such as organic materials, acrylic materials, siloxane materials, polyimide materials, epoxy resins, etc. ) materials, etc., but not limited thereto. The buffer layer I1, the gate insulating layer I2, the interlayer insulating layer I3, and the insulating layers I4, I5, and I6 can also have a single-layer structure or a multi-layer structure, such as a stack of any two or more layers of the above-mentioned insulating materials. , can be combined and changed as required.
接墊P1、P2可以設置於電路基板110的表面S1上，且接墊P1、P2於電路基板110的正投影較佳不重疊開口OP。接墊P1、P2例如可以藉由噴墨印刷或點膠的方式形成於導電層C3上。在一些實施例中，接墊P1、P2的材質可以是導電膠，例如銀膠，但不限於此。The pads P1 and P2 can be disposed on the surface S1 of the circuit substrate 110 , and the orthographic projections of the pads P1 and P2 on the circuit substrate 110 preferably do not overlap the opening OP. The pads P1 and P2 can be formed on the conductive layer C3 by inkjet printing or dispensing, for example. In some embodiments, the material of the pads P1 and P2 may be conductive glue, such as silver glue, but not limited thereto.
在本實施例中，發光元件120可以包括第一電極121、第二電極122及發光疊層123，且第一電極121及第二電極122分別電性連接發光疊層123中的不同層。舉例而言，發光疊層123可以包括兩層半導體層及夾於上述的兩層半導體層之間的發光層，且第一電極121可電性連接上述的兩層半導體層中的一層，而第二電極122可電性連接上述的兩層半導體層中的另一層。第一電極121及第二電極122的材質可以包括例如金屬、合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物或其他合適的材料或是金屬材料與其他導電材料的堆疊層或其他低阻值的導電材料。In this embodiment, the light emitting element 120 may include a first electrode 121 , a second electrode 122 and a light emitting stack 123 , and the first electrode 121 and the second electrode 122 are respectively electrically connected to different layers in the light emitting stack 123 . For example, the light emitting stack 123 may include two semiconductor layers and a light emitting layer interposed between the two semiconductor layers, and the first electrode 121 may be electrically connected to one of the two semiconductor layers, and the second electrode 121 may be electrically connected to one of the two semiconductor layers. The second electrode 122 can be electrically connected to the other one of the above two semiconductor layers. The material of the first electrode 121 and the second electrode 122 may include, for example, metal, alloy, nitride of metal material, oxide of metal material, oxynitride of metal material or other suitable materials or a combination of metal material and other conductive materials. stacked layers or other low-resistance conductive material.
在本實施例中，發光元件120可以是在巨量轉移製程之後透過修補製程設置於電路基板110上，而且發光元件120的第一電極121以及第二電極122可以分別透過連接件N1、N2電性連接至接墊P1、P2。連接件N1、N2的材質例如為金屬、導電膠（例如銀膠）、焊料或其他材料。在一些實施例中，連接件N1、N2與接墊P1、P2之間還可以分別包括其他導電材料或導電膠。如此一來，當開關元件SW透過閘極GE接收的訊號而開啟時，可將源極SE接收的訊號傳遞至發光元件120的第二電極122。此外，由於接墊P1、P2於電路基板110的正投影不重疊開口OP，發光元件120於電路基板110的正投影可以不重疊開口OP，且發光元件120於電路基板110的正投影可以位於開口OP之間。In this embodiment, the light-emitting element 120 can be disposed on the circuit substrate 110 through a repair process after the mass transfer process, and the first electrode 121 and the second electrode 122 of the light-emitting element 120 can be electrically connected through the connectors N1 and N2 respectively. connected to pads P1, P2. The material of the connectors N1 and N2 is, for example, metal, conductive glue (such as silver glue), solder or other materials. In some embodiments, other conductive materials or conductive glue may be included between the connectors N1 , N2 and the pads P1 , P2 respectively. In this way, when the switch element SW is turned on by the signal received by the gate GE, the signal received by the source SE can be transmitted to the second electrode 122 of the light emitting element 120 . In addition, since the orthographic projections of the pads P1 and P2 on the circuit substrate 110 do not overlap the opening OP, the orthographic projection of the light emitting element 120 on the circuit substrate 110 may not overlap the opening OP, and the orthographic projection of the light emitting element 120 on the circuit substrate 110 may be located in the opening. between OPs.
在本實施例中，顯示裝置10還可以包括多個發光元件120T，發光元件120T可以是於生長基板上製造後，透過巨量轉移製程轉置於電路基板110上，而且發光元件120T的第一電極121以及第二電極122可以分別透過連接件N1、N2而電性連接至接墊P3、P4。接墊P3、P4例如可以藉由薄膜沉積製程、微影製程以及蝕刻製程形成於導電層C3上。接墊P3、P4的材質可以是導電性良好的金屬，例如鋁、鉬、鈦、銅等金屬或其合金、或上述材料的疊層，但不限於此。在一些實施例中，接墊P2、P4可以電性連接至不同的開關元件SW的汲極DE，且接墊P1、P3可以電性連接至共用電極。In this embodiment, the display device 10 may further include a plurality of light-emitting elements 120T. The light-emitting elements 120T may be fabricated on the growth substrate and transferred to the circuit substrate 110 through a mass transfer process. The first light-emitting element 120T The electrode 121 and the second electrode 122 can be electrically connected to the pads P3 and P4 through the connectors N1 and N2 respectively. The pads P3 and P4 can be formed on the conductive layer C3 by, for example, a thin film deposition process, a lithography process, and an etching process. The material of the pads P3 and P4 can be a metal with good electrical conductivity, such as aluminum, molybdenum, titanium, copper, or an alloy thereof, or a laminate of the above materials, but is not limited thereto. In some embodiments, the pads P2 and P4 may be electrically connected to drains DE of different switching elements SW, and the pads P1 and P3 may be electrically connected to a common electrode.
在本實施例中，填充物FM可以不填滿開口OP，且填充物FM可以從開口OP中延伸至電路基板110的表面S1上，使得從電路基板110的表面S1上方俯視時，填充物FM可以呈現局部圍繞接墊P1、P2的L形。如此一來，在形成接墊P1、P2的過程中，填充物FM不僅可以防止形成接墊P1、P2的材料流入開口OP中，還可以充當對位標記，使得接墊P1、P2可被以高精準度設置於電路基板110的表面S1上的預定位置。In this embodiment, the filler FM may not fill the opening OP, and the filler FM may extend from the opening OP to the surface S1 of the circuit substrate 110, so that when viewed from above the surface S1 of the circuit substrate 110, the filler FM An L-shape partially surrounding the pads P1, P2 may be present. In this way, during the process of forming the pads P1, P2, the filler FM can not only prevent the material forming the pads P1, P2 from flowing into the opening OP, but also serve as an alignment mark, so that the pads P1, P2 can be It is disposed at a predetermined position on the surface S1 of the circuit substrate 110 with high precision.
在一些實施例中，由於填充物FM可能重疊導電層C3的不同區段，填充物FM可以包括不導電材料，例如負型光阻。在一些實施例中，填充物FM於電路基板110的正投影不重疊發光元件120的第一電極121及第二電極122於電路基板110的正投影及其間的區域。換言之，填充物FM可以局部圍繞於同一個發光元件120的第一電極121及第二電極122的外周。在一些實施例中，填充物FM的頂面與電路基板110的間距D1可以小於發光元件120的發光疊層123與電路基板110的間距D2，以免影響發光元件120的第一電極121以及第二電極122與接墊P1、P2之間的電性連接。In some embodiments, since the filler FM may overlap different sections of the conductive layer C3, the filler FM may include a non-conductive material, such as a negative photoresist. In some embodiments, the orthographic projection of the filler FM on the circuit substrate 110 does not overlap the orthographic projection of the first electrode 121 and the second electrode 122 of the light emitting element 120 on the circuit substrate 110 and the area therebetween. In other words, the filler FM may partially surround the outer circumference of the first electrode 121 and the second electrode 122 of the same light emitting element 120 . In some embodiments, the distance D1 between the top surface of the filler FM and the circuit substrate 110 may be smaller than the distance D2 between the light emitting stack 123 of the light emitting element 120 and the circuit substrate 110, so as not to affect the first electrode 121 and the second electrode 121 of the light emitting element 120. The electrical connection between the electrode 122 and the pads P1, P2.
以下，使用圖2A至圖4B繼續說明本發明的其他實施例，並且，沿用圖1A至圖1B的實施例的元件標號與相關內容，其中，採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明，可參考圖1A至圖1B的實施例，在以下的說明中不再重述。In the following, other embodiments of the present invention are continued to be described using FIGS. 2A to 4B , and the element numbers and related contents of the embodiment in FIGS. 1A to 1B are used, wherein the same or similar elements are represented by the same numbers, and Descriptions of the same technical contents are omitted. For the description of the omitted parts, reference may be made to the embodiment shown in FIG. 1A to FIG. 1B , which will not be repeated in the following description.
圖2A是依照本發明一實施例的顯示裝置20的局部上視示意圖。圖2B是沿圖2A的剖面線B-B’所作的剖面示意圖。為了使圖式的表達較為簡潔，圖2A省略圖2B中的導電層C2及其下方的膜層。FIG. 2A is a schematic partial top view of a display device 20 according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the section line B-B' of Fig. 2A. In order to make the expression of the figure more concise, FIG. 2A omits the conductive layer C2 and the film layer below it in FIG. 2B .
請參照圖2A至圖2B，顯示裝置20包括：電路基板110，其表面S1具有多個開口OP，且包括位於表面S1上的多個接墊P1、P2、P3、P4；發光元件120、120T，位於電路基板110上，且發光元件120、120T分別包括第一電極121、第二電極122及發光疊層123，其中，發光元件120的第一電極121及第二電極122分別電性連接接墊P1、P2與發光疊層123中的不同層，發光元件120T的第一電極121及第二電極122分別電性連接接墊P3、P4與發光疊層123中的不同層，且第一電極121及第二電極122於電路基板110的正投影在多個開口OP之外；以及填充物FMb，位於多個開口OP中。2A to 2B, the display device 20 includes: a circuit substrate 110, the surface S1 of which has a plurality of openings OP, and includes a plurality of pads P1, P2, P3, P4 located on the surface S1; light emitting elements 120, 120T , located on the circuit substrate 110, and the light emitting elements 120, 120T respectively include a first electrode 121, a second electrode 122 and a light emitting stack 123, wherein the first electrode 121 and the second electrode 122 of the light emitting element 120 are respectively electrically connected to The pads P1, P2 are connected to different layers in the light emitting stack 123, the first electrode 121 and the second electrode 122 of the light emitting element 120T are respectively electrically connected to the pads P3, P4 and different layers in the light emitting stack 123, and the first electrode Orthographic projections of 121 and the second electrode 122 on the circuit substrate 110 are outside the plurality of openings OP; and the filler FMb is located in the plurality of openings OP.
與如圖1A至圖1B所示的顯示裝置10相比，圖2A至圖2B所示的顯示裝置20的不同之處在於：顯示裝置20的填充物FMb於電路基板110的表面S1上可以呈現U形，且填充物FMb可以填滿開口OP。Compared with the display device 10 shown in FIGS. 1A to 1B , the display device 20 shown in FIGS. 2A to 2B is different in that: the filler FMb of the display device 20 can appear on the surface S1 of the circuit substrate 110 U-shaped, and the filler FMb can fill up the opening OP.
在本實施例中，填充物FMb可以填滿開口OP，且填充物FMb可以從開口OP中延伸至電路基板110的表面S1上，使得從電路基板110的表面S1上方俯視時，填充物FMb可以呈現三面圍繞接墊P1、P2的U形。如此一來，在形成接墊P1、P2的過程中，填充物FMb不僅可以防止形成接墊P1、P2的材料流入開口OP中，還可以充當對位標記，使得接墊P1、P2可被以高精準度設置於電路基板110的表面S1上的預定位置。在一些實施例中，填充物FMb還可以四面環繞接墊P1、P2而呈現中空多邊形或環形。In this embodiment, the filler FMb can fill the opening OP, and the filler FMb can extend from the opening OP to the surface S1 of the circuit substrate 110, so that when viewed from above the surface S1 of the circuit substrate 110, the filler FMb can be It presents a U-shape surrounding the pads P1 and P2 on three sides. In this way, during the process of forming the pads P1, P2, the filler FMb can not only prevent the material forming the pads P1, P2 from flowing into the opening OP, but also serve as an alignment mark, so that the pads P1, P2 can be It is disposed at a predetermined position on the surface S1 of the circuit substrate 110 with high precision. In some embodiments, the filler FMb may also surround the pads P1 , P2 in a hollow polygon or ring shape.
圖3A是依照本發明一實施例的顯示裝置30的局部上視示意圖。圖3B是沿圖3A的剖面線C-C’所作的剖面示意圖。為了使圖式的表達較為簡潔，圖3A省略圖3B中的導電層C2及其下方的膜層。FIG. 3A is a schematic partial top view of a display device 30 according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along the section line C-C' of Fig. 3A. In order to make the expression of the drawing more concise, FIG. 3A omits the conductive layer C2 and the film layer below it in FIG. 3B .
請參照圖3A至圖3B，顯示裝置30包括：電路基板110，其表面S1具有多個開口OP，且包括位於表面S1上的多個接墊P1、P2、P3、P4；發光元件120、120T，位於電路基板110上，且發光元件120、120T分別包括第一電極121、第二電極122及發光疊層123，其中，發光元件120的第一電極121及第二電極122分別電性連接接墊P1、P2與發光疊層123中的不同層，發光元件120T的第一電極121及第二電極122分別電性連接接墊P3、P4與發光疊層123中的不同層，且第一電極121及第二電極122於電路基板110的正投影在多個開口OP之外；以及填充物FMc，位於多個開口OP中。3A to 3B, the display device 30 includes: a circuit substrate 110, the surface S1 of which has a plurality of openings OP, and includes a plurality of pads P1, P2, P3, P4 located on the surface S1; light emitting elements 120, 120T , located on the circuit substrate 110, and the light emitting elements 120, 120T respectively include a first electrode 121, a second electrode 122 and a light emitting stack 123, wherein the first electrode 121 and the second electrode 122 of the light emitting element 120 are respectively electrically connected to The pads P1, P2 are connected to different layers in the light emitting stack 123, the first electrode 121 and the second electrode 122 of the light emitting element 120T are respectively electrically connected to the pads P3, P4 and different layers in the light emitting stack 123, and the first electrode Orthographic projections of 121 and the second electrode 122 on the circuit substrate 110 are outside the plurality of openings OP; and the filler FMc is located in the plurality of openings OP.
與如圖2A至圖2B所示的顯示裝置20相比，圖3A至圖3B所示的顯示裝置30的不同之處在於：顯示裝置30的填充物FMc是在修補發光元件120以及巨量轉移發光元件120T之前形成於電路基板110的整個表面S1上，且填充物FMc具有多個通孔Vc，多個通孔Vc可以分別暴露出導電層C3的不同區段，且接墊P1、P2、P3、P4可以分別形成於通孔Vc中。Compared with the display device 20 shown in FIGS. 2A to 2B , the display device 30 shown in FIGS. 3A to 3B is different in that: the filler FMc of the display device 30 is repairing the light emitting element 120 and mass transfer The light-emitting element 120T is formed on the entire surface S1 of the circuit substrate 110 before, and the filler FMc has a plurality of through holes Vc, and the plurality of through holes Vc can respectively expose different sections of the conductive layer C3, and the pads P1, P2, P3, P4 may be respectively formed in the via holes Vc.
在本實施例中，當從電路基板110的表面S1上方俯視時，填充物FMc可以分別圍繞接墊P1、P2、P3、P4。如此一來，在形成接墊P1、P2、P3、P4的過程中，填充物FMc不僅可以防止形成接墊P1、P2、P3、P4的材料流入開口OP中，還可以充當對位標記，使得接墊P1、P2、P3、P4可被以高精準度設置於電路基板110的表面S1上的預定位置。In this embodiment, when viewed from above the surface S1 of the circuit substrate 110 , the fillers FMc may respectively surround the pads P1 , P2 , P3 , and P4 . In this way, during the process of forming the pads P1, P2, P3, and P4, the filler FMc can not only prevent the material forming the pads P1, P2, P3, and P4 from flowing into the opening OP, but also serve as an alignment mark, so that The pads P1 , P2 , P3 , P4 can be disposed at predetermined positions on the surface S1 of the circuit substrate 110 with high precision.
圖4A是依照本發明一實施例的顯示裝置40的局部上視示意圖。圖4B是沿圖4A的剖面線D-D’所作的剖面示意圖。為了使圖式的表達較為簡潔，圖4A省略圖4B中的導電層C2及其下方的膜層。FIG. 4A is a schematic partial top view of a display device 40 according to an embodiment of the invention. Fig. 4B is a schematic cross-sectional view taken along the section line D-D' of Fig. 4A. In order to make the expression of the drawing more concise, FIG. 4A omits the conductive layer C2 and the film layer below it in FIG. 4B .
請參照圖4A至圖4B，顯示裝置40包括：電路基板110，其表面S1具有多個開口OP，且包括位於表面S1上的多個接墊P1、P2、P3、P4；發光元件120、120T，位於電路基板110上，且發光元件120、120T分別包括第一電極121、第二電極122及發光疊層123，其中，發光元件120的第一電極121及第二電極122分別電性連接接墊P1、P2與發光疊層123中的不同層，發光元件120T的第一電極121及第二電極122分別電性連接接墊P3、P4與發光疊層123中的不同層，且第一電極121及第二電極122於電路基板110的正投影在多個開口OP之外；以及填充物FMd，位於多個開口OP中。4A to 4B, the display device 40 includes: a circuit substrate 110, the surface S1 of which has a plurality of openings OP, and includes a plurality of pads P1, P2, P3, P4 located on the surface S1; light emitting elements 120, 120T , located on the circuit substrate 110, and the light emitting elements 120, 120T respectively include a first electrode 121, a second electrode 122 and a light emitting stack 123, wherein the first electrode 121 and the second electrode 122 of the light emitting element 120 are respectively electrically connected to The pads P1, P2 are connected to different layers in the light emitting stack 123, the first electrode 121 and the second electrode 122 of the light emitting element 120T are respectively electrically connected to the pads P3, P4 and different layers in the light emitting stack 123, and the first electrode Orthographic projections of 121 and the second electrode 122 on the circuit substrate 110 are outside the plurality of openings OP; and the filler FMd is located in the plurality of openings OP.
與如圖1A至圖1B所示的顯示裝置10相比，圖4A至圖4B所示的顯示裝置40的不同之處在於：顯示裝置40的填充物FMd可以包括導電材料。Compared with the display device 10 shown in FIGS. 1A-1B , the display device 40 shown in FIGS. 4A-4B is different in that the filler FMd of the display device 40 may include a conductive material.
在本實施例中，各個開口OP中的填充物FMd可以僅重疊導電層C3的一個區段，因此，填充物FMd可以包括導電材料。在一些實施例中，填充物FMd的材質可以與接墊P1、P2相同。舉例而言，填充物FMd可以藉由點膠的方式形成，且在填充物FMd形成之後，可以同樣藉由點膠的方式來形成接墊P1、P2。在一些實施例中，填充物FMd的材質可以包括銀膠，但不以此為限。In this embodiment, the filler FMd in each opening OP may only overlap a section of the conductive layer C3, and therefore, the filler FMd may include a conductive material. In some embodiments, the material of the filler FMd may be the same as that of the pads P1 and P2 . For example, the filler FMd can be formed by dispensing glue, and after the filler FMd is formed, the pads P1 and P2 can also be formed by dispensing glue. In some embodiments, the material of the filler FMd may include silver colloid, but not limited thereto.
在本實施例中，填充物FMd可以從開口OP中延伸至電路基板110的表面S1上，使得從電路基板110的表面S1上方俯視時，填充物FMd可以呈現兩面圍繞接墊P1、P2的L形。如此一來，在形成接墊P1、P2的過程中，填充物FMd不僅可以防止形成接墊P1、P2的材料流入開口OP中，還可以充當對位標記，使得接墊P1、P2可被以高精準度設置於電路基板110的表面S1上的預定位置。In this embodiment, the filler FMd can extend from the opening OP to the surface S1 of the circuit substrate 110, so that when viewed from above the surface S1 of the circuit substrate 110, the filler FMd can present an L that surrounds the pads P1 and P2 on both sides. shape. In this way, during the process of forming the pads P1, P2, the filler FMd can not only prevent the material forming the pads P1, P2 from flowing into the opening OP, but also serve as an alignment mark, so that the pads P1, P2 can be It is disposed at a predetermined position on the surface S1 of the circuit substrate 110 with high precision.
綜上所述，本發明的顯示裝置藉由藉由設置填入開口中的填充物，能夠避免後續形成接墊的材料流入開口中，同時填充物還能夠充當對位標記，藉以提高修補製程的對位精準度，從而改善發光元件修補良率。To sum up, the display device of the present invention can prevent the subsequent material forming the pad from flowing into the opening by setting the filler filled in the opening, and the filler can also serve as an alignment mark, thereby improving the efficiency of the repair process. Alignment accuracy, thereby improving the repair yield of light-emitting elements.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
10、20、30、40:顯示裝置 110:電路基板 112:底板 114:驅動電路層 120、120T:發光元件 121:第一電極 122:第二電極 123:發光疊層 A-A’、B-B’、C-C’、D-D’:剖面線 C1、C2、C3:導電層 CH:半導體層 D1、D2:間距 DE:汲極 FM、FMb、FMc、FMd:填充物 GE:閘極 I1:緩衝層 I2:閘極絕緣層 I3:層間絕緣層 I4、I5、I6:絕緣層 N1、N2:連接件 OP:開口 P1、P2、P3、P4:接墊 S1:表面 SE:源極 SW:開關元件 V1、V2、Vc:通孔 10, 20, 30, 40: display device 110: circuit substrate 112: Bottom plate 114: Drive circuit layer 120, 120T: light emitting element 121: the first electrode 122: second electrode 123: Luminous Lamination A-A', B-B', C-C', D-D': hatching C1, C2, C3: conductive layer CH: semiconductor layer D1, D2: Spacing DE: drain FM, FMb, FMc, FMd: filler GE: Gate I1: buffer layer I2: Gate insulating layer I3: interlayer insulating layer I4, I5, I6: insulating layer N1, N2: connectors OP: opening P1, P2, P3, P4: Pads S1: surface SE: source SW: switching element V1, V2, Vc: through holes
圖1A是依照本發明一實施例的顯示裝置10的局部上視示意圖。 圖1B是沿圖1A的剖面線A-A’所作的剖面示意圖。 圖2A是依照本發明一實施例的顯示裝置20的局部上視示意圖。 圖2B是沿圖2A的剖面線B-B’所作的剖面示意圖。 圖3A是依照本發明一實施例的顯示裝置30的局部上視示意圖。 圖3B是沿圖3A的剖面線C-C’所作的剖面示意圖。 圖4A是依照本發明一實施例的顯示裝置40的局部上視示意圖。 圖4B是沿圖4A的剖面線D-D’所作的剖面示意圖。 FIG. 1A is a schematic partial top view of a display device 10 according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. FIG. 2A is a schematic partial top view of a display device 20 according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view taken along the section line B-B' of Fig. 2A. FIG. 3A is a schematic partial top view of a display device 30 according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along the section line C-C' of Fig. 3A. FIG. 4A is a schematic partial top view of a display device 40 according to an embodiment of the invention. Fig. 4B is a schematic cross-sectional view taken along the section line D-D' of Fig. 4A.
10:顯示裝置 10: Display device
110:電路基板 110: circuit substrate
112:底板 112: Bottom plate
114:驅動電路層 114: Drive circuit layer
120、120T:發光元件 120, 120T: light emitting element
121:第一電極 121: the first electrode
122:第二電極 122: second electrode
123:發光疊層 123: Luminous Lamination
C1、C2、C3:導電層 C1, C2, C3: conductive layer
CH:半導體層 CH: semiconductor layer
D1、D2:間距 D1, D2: Spacing
DE:汲極 DE: drain
FM:填充物 FM: filler
GE:閘極 GE: Gate
I1:緩衝層 I1: buffer layer
I2:閘極絕緣層 I2: Gate insulating layer
I3:層間絕緣層 I3: interlayer insulating layer
I4、I5、I6:絕緣層 I4, I5, I6: insulating layer
N1、N2:連接件 N1, N2: connectors
OP:開口 OP: opening
P1、P2、P3、P4:接墊 P1, P2, P3, P4: Pads
S1:表面 S1: surface
SE:源極 SE: source
SW:開關元件 SW: switching element
V1、V2:通孔 V1, V2: through hole
Claims (15)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110146879A TWI817287B (en) | 2021-12-15 | 2021-12-15 | Display device |
| CN202210111399.5A CN114464717B (en) | 2021-12-15 | 2022-01-29 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110146879A TWI817287B (en) | 2021-12-15 | 2021-12-15 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW202327065A true TW202327065A (en) | 2023-07-01 |
| TWI817287B TWI817287B (en) | 2023-10-01 |
Family
ID=81411143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW110146879A TWI817287B (en) | 2021-12-15 | 2021-12-15 | Display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114464717B (en) |
| TW (1) | TWI817287B (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11261207A (en) * | 1998-03-13 | 1999-09-24 | Advantest Corp | Printed board |
| CN201479454U (en) * | 2009-04-16 | 2010-05-19 | 惠州国展电子有限公司 | Circuit board with metal covering film of insulated rubber film attached to element surface thereof |
| CN111384079B (en) * | 2018-12-27 | 2024-04-05 | 乐金显示有限公司 | Display device |
| CN110047866B (en) * | 2019-04-30 | 2021-04-02 | 京东方科技集团股份有限公司 | Array substrate, display panel and micro LED transfer method |
| US11380815B2 (en) * | 2019-06-21 | 2022-07-05 | PlayNitride Display Co., Ltd. | Semiconductor material substrate, micro light emitting diode panel and method of fabricating the same |
| TWI729846B (en) * | 2020-06-10 | 2021-06-01 | 友達光電股份有限公司 | Light-emitting device |
-
2021
- 2021-12-15 TW TW110146879A patent/TWI817287B/en active
-
2022
- 2022-01-29 CN CN202210111399.5A patent/CN114464717B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114464717B (en) | 2023-07-04 |
| TWI817287B (en) | 2023-10-01 |
| CN114464717A (en) | 2022-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11177425B2 (en) | Driving backplane, method for manufacturing the same, and display device | |
| CN110047898B (en) | Display substrate, manufacturing method thereof and display device | |
| CN109273436B (en) | Display device | |
| US20210225901A1 (en) | Driving backplane, manufacturing method thereof, and display apparatus | |
| TWI671572B (en) | Display panel and manufacturing method thereof | |
| US11373585B2 (en) | Driving backplane, display panel and method for manufacturing the same | |
| US11665940B2 (en) | Display substrate for avoiding breaks and preparation method thereof, bonding method of display panel and display apparatus | |
| US11063108B2 (en) | Organic light emitting diode array substrate and electronic device | |
| CN103811501A (en) | Flexible display device | |
| TWI706397B (en) | Display device and method for forming the same | |
| EP3236499A1 (en) | Array substrate and manufacturing method therefor, and display device | |
| US20170373028A1 (en) | Display apparatus | |
| US20220320241A1 (en) | Display Substrate and Preparing Method Thereof, and Display Apparatus | |
| CN118173573A (en) | Display device | |
| TW201935722A (en) | Micro light emitting device | |
| CN111969006A (en) | Display device and method of manufacturing the same | |
| US20230060979A1 (en) | Array substrate and preparation method therefor, and display apparatus | |
| CN109524421A (en) | Interposer substrate and its manufacturing method, array substrate and display device | |
| TWI685694B (en) | Pixel structure | |
| JP2011003650A (en) | Multilayer wiring board, and semiconductor device having the same | |
| TWI817287B (en) | Display device | |
| US20220310887A1 (en) | Display device | |
| US20220399433A1 (en) | Display Substrate and Display Apparatus | |
| WO2021169568A1 (en) | Display mother board and preparation method therefor, display substrate and display device | |
| WO2022041022A1 (en) | Display substrate and display device |