TW202314865A - Semiconductor manufacturing platform with in-situ electrical bias and methods thereof - Google Patents

Semiconductor manufacturing platform with in-situ electrical bias and methods thereof Download PDF

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TW202314865A
TW202314865A TW111129521A TW111129521A TW202314865A TW 202314865 A TW202314865 A TW 202314865A TW 111129521 A TW111129521 A TW 111129521A TW 111129521 A TW111129521 A TW 111129521A TW 202314865 A TW202314865 A TW 202314865A
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semiconductor wafer
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蒂娜 Ｈ 特里優索
羅伯特 Ｄ 克拉克
大衛 赫爾利
伊恩 科爾根
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日商東京威力科創股份有限公司
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Abstract

A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.

Description

具有原位電偏壓的半導體製造平台及其方法Semiconductor fabrication platform with in-situ electrical biasing and method thereof

本發明係大致關於半導體處理系統及方法，且在特定實施例中，關於在晶圓的退火期間具有直接施加於晶圓之導電層範圍內之原位電偏壓之半導體處理用製造平台及方法。 [相關申請案的交互參照] The present invention relates generally to semiconductor processing systems and methods, and in particular embodiments, to manufacturing platforms and methods for semiconductor processing with an in-situ electrical bias applied directly to the confines of the conductive layers of the wafer during annealing of the wafer . [CROSS-REFERENCE TO RELATED APPLICATIONS]

本申請案主張2020年4月6日提出申請之美國非臨時申請案第16/841,342號、以及2021年8月9日提出申請之美國非臨時申請案第17/397,159號的優先權。以上引用之申請案之每一者的全部揭示內容係藉由參照而併入本文。This application claims priority to U.S. Non-Provisional Application No. 16/841,342, filed April 6, 2020, and U.S. Non-Provisional Application No. 17/397,159, filed August 9, 2021. The entire disclosure of each of the above-cited applications is hereby incorporated by reference.

通常，半導體積體電路(IC)係藉由將材料層(例如，介電質、金屬、半導體等)依序沉積於半導體基板上方、並使用微影技術及蝕刻將疊層圖案化以形成電路元件(例如，電晶體及電容器)及互連部件(例如，線、接頭、及通孔)加以製造。最小特徵部尺寸已隨著例如浸漬微影技術及多重圖案化之創新週期性縮小，以藉由增加封裝密度降低成本。元件之腳位的小型化可藉由增加元件的每單位面積輸出來提高。舉例而言，每單位寬度之電晶體驅動電流或電容器儲存電荷密度可分別藉由使用更薄之閘極介電質或更薄之電容介電質而增強。Typically, a semiconductor integrated circuit (IC) is formed by sequentially depositing layers of material (eg, dielectric, metal, semiconductor, etc.) over a semiconductor substrate and patterning the stack using lithography and etching to form a circuit Components (eg, transistors and capacitors) and interconnect features (eg, wires, contacts, and vias) are fabricated. The minimum feature size has periodically shrunk with innovations such as immersion lithography and multiple patterning to reduce cost by increasing packing density. Miniaturization of device footprints can be enhanced by increasing the output per unit area of the device. For example, transistor drive current per unit width or capacitor stored charge density can be enhanced by using thinner gate dielectrics or thinner capacitor dielectrics, respectively.

然而，小型化的優勢涉及一些在製程複雜度、電路速率、及待機功率損耗方面可能需要加以應對的代價。朝更窄的線寬及減少導體與電極之間的空間進行的縮放趨勢具有性能取捨。這些取捨中一些者可藉由使用新材料來緩解。舉例而言，由於更高的線與通孔電阻而在互連系統中增加的IR壓降與RC延遲、及增加的線間電容可藉由使用例如釕及鈷(取代鎢及銅)之金屬與例如氟矽酸鹽玻璃及碳摻雜氧化物之低k金屬間介電質(intermetal dielectric，IMD)來緩解。在電晶體中的縮小之源極至汲極間距及更薄之閘極介電質或電容器介電質可能增加待機洩漏。此問題可藉由使用高k介電質或鐵電介電材料來緩解。However, the advantages of miniaturization come with some tradeoffs that may need to be dealt with in terms of process complexity, circuit speed, and standby power loss. The scaling trend toward narrower linewidths and reduced space between conductors and electrodes has performance trade-offs. Some of these trade-offs can be mitigated through the use of new materials. For example, increased IR drop and RC delay in interconnect systems due to higher line and via resistance, and increased line-to-line capacitance can be improved by using metals such as ruthenium and cobalt (instead of tungsten and copper) and low-k intermetal dielectrics (IMDs) such as fluorosilicate glass and carbon-doped oxides for mitigation. Shrinking source-to-drain spacing and thinner gate or capacitor dielectrics in transistors can increase standby leakage. This problem can be alleviated by using high-k dielectric or ferroelectric dielectric materials.

新材料的結合需要進一步創新，以更好地利用由該新材料在IC中使用所提供的優勢。The incorporation of new materials requires further innovations to better exploit the advantages offered by the use of this new material in ICs.

根據本發明之實施例，製造半導體裝置的方法包含將半導體晶圓置於製造平台之第一沉積腔室內，該半導體晶圓包含第一導電層；在第一沉積腔室中將介電層沉積於第一導電層上；將半導體晶圓置於製造平台之第二沉積腔室中；及在第二沉積腔室中將第二導電層沉積至介電層上。該方法更包含將半導體晶圓置於製造平台之電場退火裝置的處理腔室內；及於該處理腔室中，藉由將第一導電層耦合至第一電位、且將第二導電層耦合至第二電位而將電偏壓施加在介電層範圍內；及在施加電偏壓時，將半導體晶圓退火。According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes placing a semiconductor wafer in a first deposition chamber of a manufacturing platform, the semiconductor wafer including a first conductive layer; depositing a dielectric layer in the first deposition chamber on the first conductive layer; placing a semiconductor wafer in a second deposition chamber of the manufacturing platform; and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer in a processing chamber of an electric field annealing device of a manufacturing platform; and in the processing chamber, by coupling the first conductive layer to a first potential, and coupling the second conductive layer to applying an electrical bias within the dielectric layer at a second potential; and annealing the semiconductor wafer while the electrical bias is being applied.

根據本發明之實施例，製造半導體裝置的製造平台包含第一沉積腔室，其係配置成在半導體晶圓上沉積導電層；及第二沉積腔室，其係配置成在半導體晶圓上沉積介電層。該製造平台更包含電場退火裝置的處理腔室，該處理腔室包含：基板夾持具，其係配置成支撐半導體晶圓；加熱元件，其係配置成加熱藉由基板夾持具支撐的半導體晶圓；第一電極，其係配置成可分離地附接至半導體晶圓的第一主要表面；及第一線，其將第一電極耦合至第一電位節點。According to an embodiment of the present invention, a fabrication platform for fabricating a semiconductor device includes a first deposition chamber configured to deposit a conductive layer on a semiconductor wafer; and a second deposition chamber configured to deposit a conductive layer on the semiconductor wafer dielectric layer. The fabrication platform further includes a processing chamber of an electric field annealing apparatus, the processing chamber including: a substrate holder configured to support a semiconductor wafer; a heating element configured to heat the semiconductor supported by the substrate holder a wafer; a first electrode configured to be detachably attached to the first major surface of the semiconductor wafer; and a first wire coupling the first electrode to a first potential node.

本揭示內容描述在處理期間於晶圓之兩導電層範圍內施加電偏壓時處理半導體晶圓的設備及方法。偏壓經由直接與晶圓電接觸且連接至位於處理腔室外側的電源之電極進行施加。在本文中，與電偏壓同時執行的退火製程稱為E場退火，且用於執行E場退火的處理設備稱為E場退火裝置。在示例實施例中，電偏壓用於在沉積後退火(post-deposition anneal，PDA)製程步驟期間使晶圓中之介電層受到期望強度之DC電場(E場)。The present disclosure describes apparatus and methods for processing semiconductor wafers while an electrical bias is applied across two conductive layers of the wafer during processing. The bias voltage is applied via electrodes that are in direct electrical contact with the wafer and connected to a power source located outside the processing chamber. Herein, the annealing process performed simultaneously with the electrical bias is called E-field annealing, and the processing equipment for performing the E-field annealing is called an E-field annealing device. In an example embodiment, the electrical bias is used to subject the dielectric layer in the wafer to a DC electric field (E-field) of desired strength during a post-deposition anneal (PDA) process step.

在包含例如金屬-氧化物-半導體場效電晶體(metal-oxide-semiconductor field-effect transistor，MOSFET)及/或電容器之基於鐵電介電質之電子元件的製造的一些製造製程流程中，使用E場PDA可具有優勢，如以下說明。用於形成鐵電層之製程步驟可包含沉積例如摻雜鉿氧化物、或摻雜鋯酸鉿、或例如鈦酸鍶鋇之鈣鈦礦氧化物、或鉍的鐵電氧化物。例如La、Al、Si、Sr、Gd、及Y的諸多摻雜劑已顯示藉由扭曲結晶結構而改善鐵電行為。然而，多相可能發生在HfO 2或HfZrO x的情形中。在這些材料中，沉積後退火(PDA)條件在引起具有鐵電行為之期望的非中心對稱斜方晶相上發揮重要作用。稱為鐵電退火(ferroelectric anneal，FEA)之PDA步驟可將沉積的鉿氧化物層轉變成穩定或亞穩的多晶鐵電鉿氧化物層。包括使用基於鉿氧化物之鐵電介電質之電子元件的IC之製造流程通常包含電氣循環步驟(於此稱為喚醒循環)之以獲得穩定的鐵電性質。在本揭示內容之實施例中，鐵電MOSFET(FE-FET)及鐵電電容器可使用例如包含諸如鉿氧化物之鐵電介電質來建構，其中在結晶化FEA的期間，使用以下進一步詳述的設備及方法使介電質受到上述之施加的DC E場。用於示例實施例中之E場 FEA技術可提供縮短、並在一些實施例中排除喚醒循環的優勢。喚醒效應於以下進一步詳述。據了解，使用本揭示內容之諸多實施例所述的E場FEA技術可在使用基於鉿氧化物之材料以外的材料形成鐵電層上提供類似的優勢。 In some manufacturing process flows of ferroelectric dielectric-based electronic components including, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs) and/or capacitors, the use of E-field PDAs may have advantages, as explained below. Process steps for forming the ferroelectric layer may include depositing, for example, doped hafnium oxide, or doped hafnium zirconate, or a perovskite oxide such as barium strontium titanate, or a ferroelectric oxide of bismuth. Dopants such as La, Al, Si, Sr, Gd, and Y have been shown to improve ferroelectric behavior by distorting the crystalline structure. However, heterogeneity may occur in the case of HfO2 or HfZrOx . In these materials, post-deposition annealing (PDA) conditions play an important role in inducing the desired non-centrosymmetric orthorhombic phase with ferroelectric behavior. A PDA step called ferroelectric anneal (FEA) can transform the deposited hafnium oxide layer into a stable or metastable polycrystalline ferroelectric hafnium oxide layer. The fabrication flow of ICs that include electronic components using hafnium oxide-based ferroelectric dielectrics typically includes an electrical cycling step, referred to herein as a wake-up cycle, to obtain stable ferroelectric properties. In embodiments of the present disclosure, ferroelectric MOSFETs (FE-FETs) and ferroelectric capacitors may be constructed using, for example, ferroelectric dielectrics including, for example, hafnium oxide, wherein during crystallization of the FEA, using The apparatus and method described subject a dielectric to the applied DC E field described above. The E-field FEA technique used in example embodiments may provide the advantage of shortening, and in some embodiments eliminating wake-up cycles. Arousal effects are described in further detail below. It is understood that use of E-field FEA techniques as described in various embodiments of the present disclosure may provide similar advantages in forming ferroelectric layers using materials other than hafnium oxide-based materials.

介電材料可藉由電場(E)進行極化。就中心對稱介電質而言，響應E場之電極化向量(P)通常為大致線性且對稱之電場E的函數。中心對稱介電質為非鐵電性(例如，E=0時，P=0)。然而，一些非中心對稱介電質為鐵電性，即，該介電質表現出自發或殘餘極化；E=0時，P=P R≠0，其稱為剩磁極化(P R)。反極性之矯頑電場(E C)在鐵電介電質中必須被施加以迫使P為零。鐵電P vs. E曲線為非線性、具有大致對稱的磁滯環。如本領域之技術人員所知，例如基於鉿氧化物之鐵電薄膜的若干鐵電膜表現出喚醒效應，其中使用習知處理(欠缺E場退火)所製造之原始膜具有緊縮磁滯曲線(小P R)，該曲線經過相對高正向(正電)及逆向(負電)E場的多次循環(例如，約為10 2循環至約10 5循環)後，達到穩定、更寬的磁滯環(更大P R)。一般而言，包含具有不穩定P R之原始介電層的各鐵電元件必須藉由喚醒循環加以穩定化，使得各別電路按照設計運作。因此，可察知本揭示內容所述之創新E場退火技術藉由減少喚醒循環的數量、並在一些實施例中排除喚醒循換步驟來提供顯著優勢。 Dielectric materials can be polarized by an electric field (E). For centrosymmetric dielectrics, the electric polarization vector (P) in response to the E field is generally a roughly linear and symmetric function of the electric field E. Centrosymmetric dielectrics are non-ferroelectric (eg, P=0 when E=0). However, some non-centrosymmetric dielectrics are ferroelectric, i.e., the dielectric exhibits spontaneous or remanent polarization; when E=0, P=P R ≠0, which is called remanent polarization (P R ) . A coercive electric field ( EC ) of opposite polarity must be applied in ferroelectric dielectrics to force P to zero. The ferroelectric P vs. E curve is nonlinear with roughly symmetrical hysteresis loops. As is known to those skilled in the art, several ferroelectric films such as those based on hafnium oxide exhibit a wake-up effect where pristine films produced using conventional processes (lacking E-field annealing) have a tight hysteresis curve ( small P R ), the curve reaches a stable, wider magnetic Hysteresis (larger P R ). In general, each ferroelectric element comprising an original dielectric layer with unstable P R must be stabilized by wake-up cycling so that the respective circuit operates as designed. Thus, it can be seen that the innovative E-field annealing techniques described in this disclosure provide significant advantages by reducing the number of wake-up cycles, and in some embodiments eliminating the wake-up cycling step.

在鐵電電容器之P vs. E特性中存在磁滯容許該鐵電電容器用作非揮發性記憶體(NVM)元件。舉例而言，「1」或「0」之二進位邏輯狀態可藉由迫使鐵電電容器分別進入具有高正或負電偏壓之該鐵電電容器之P vs. E磁滯環的上或下分支，而儲存到高正極化或負極化的對應狀態。在偏壓移除(E=0)後，極化的部分作為剩磁極化加以保留，其根據鐵電電容器是否被迫進入到該電容器之該鐵電電容器之P vs. E磁滯環的上或下分支而為+P R或-P R。由於在磁滯曲線之各分支中的最大位移電流(對應P vs. E之最大斜率)發生在反極性，所以可例如藉由響應給定極性之電壓斜坡感測電容器電流來檢索所儲存的資訊。由於如從上述資料儲存及檢索機制所理解的穩定且高P R之關鍵性，喚醒循環步驟通常在製造包含欠缺上述E場FEA而形成之基於鉿氧化物之鐵電NVM的IC中進行。然而，使用本揭示內容所述之E場退火裝置及E場FEA可藉由減少喚醒循環的數量、並在一些實施例中從製造流程中排除喚醒循環步驟來提供降低基於鉿氧化物之鐵電NVM的成本的優勢。 The presence of hysteresis in the P vs. E characteristic of a ferroelectric capacitor allows the ferroelectric capacitor to be used as a non-volatile memory (NVM) element. For example, a binary logic state of "1" or "0" can be achieved by forcing a ferroelectric capacitor into the upper or lower leg of the P vs. E hysteresis loop of the ferroelectric capacitor with a high positive or negative bias, respectively. , and stored to the corresponding state of high positive polarization or negative polarization. After the bias is removed (E=0), the part of the polarization remains as a remanent polarization, which depends on whether the ferroelectric capacitor is forced onto the P vs. E hysteresis loop of the ferroelectric capacitor of the capacitor. Or the lower branch is + PR or -PR . Since the maximum displacement current (corresponding to the maximum slope of P vs. E) in each branch of the hysteresis curve occurs at reverse polarity, the stored information can be retrieved, for example, by sensing capacitor current in response to a voltage ramp of a given polarity . Due to the criticality of stable and high PR as understood from the above-mentioned data storage and retrieval mechanism, the wake-up cycling step is usually performed in the fabrication of ICs comprising hafnium oxide-based ferroelectric NVM formed lacking the above-mentioned E-field FEA. However, use of the E-field annealing apparatus and E-field FEA described in this disclosure can provide reduced ferroelectric properties based on hafnium oxide by reducing the number of wake-up cycles and, in some embodiments, eliminating the wake-up cycle step from the fabrication flow. The cost advantage of NVM.

鐵電物質可用於形成FE-FET之閘極介電堆疊。若閘極介電堆疊之剩磁極化足夠高(類似於鐵電電容器)，則一旦加以程式化，電晶體就可保持其狀態且甚至在編程電壓移除後保持ON或OFF。如此FE-FET亦可用於在NVM單元中儲存數位資訊。如在以上基於鉿氧化物之鐵電NVM的上下文中所說明，基於鉿氧化物之鐵電FE-FET NVM的製造成本可藉由使用創新E-場退火裝置及E場FEA來降低。Ferroelectrics can be used to form gate dielectric stacks for FE-FETs. If the remanent magnetic polarization of the gate dielectric stack is high enough (similar to a ferroelectric capacitor), once programmed, the transistor can retain its state and remain ON or OFF even after the programming voltage is removed. Such FE-FETs can also be used to store digital information in NVM cells. As explained above in the context of hafnium oxide-based ferroelectric NVM, the manufacturing cost of hafnium oxide-based ferroelectric FE-FET NVM can be reduced by using the innovative E-field annealing device and E-field FEA.

當用於數位邏輯及類比電路時，FE-FET亦可提供相較習知(亦即，非鐵電性)MOSFET的一些優勢。用於數位邏輯及/或類比電路之FE-FET之閘極介電堆疊包含鐵電及非鐵電薄膜。當用於電路時(例如，當用作數位開關時)，閘極介電堆疊的鐵電部分提供動態電容，其在特定偏壓掃描狀態(例如，掃描率或頻率)下，可因為鐵電物質之極化的變化而導致電壓驟回(snap-back)。此驟回可導致FE-FET之理想的更急遽次臨界及更高I ON/I OFF比。在此上下文中，FE-FET已通常稱為負電容場效電晶體(negative-capacitance field-effect transistor，NCFET)。此處更加準確地將該FE-FET稱為陡坡鐵電場效電晶體(steep-slope ferro-electric field-effect transistor，SSFEFET)。然而，在閘極介電堆疊中之鐵電性質(例如，P R)及膜厚度可能需要適當調整，以達到無磁滯電晶體I-V及I-C曲線。如本領域之技術人員所知，無磁滯電晶體I-V及I-C曲線意味著穩定的電晶體運作，而磁滯的存在可能導致電路不穩定性及非預期的電振盪。據了解，從電路穩定性考慮，P R必須保持穩定並在設計窗口範圍內，以令SSFEFET在不使電路不穩定的情況下提供期望的電路優勢。因此，未包含E場FEA之SSFEFET的製造流程可結合喚醒循環步驟，然而使用本揭示內容所述之發明性E場退火技術可藉由在減少喚醒循環、並在一些實施例中不具有喚醒循環的情況下達到穩定的鐵電性質來提供降低成本的優勢。 FE-FETs may also offer some advantages over conventional (ie, non-ferroelectric) MOSFETs when used in digital logic and analog circuits. Gate dielectric stacks of FE-FETs for digital logic and/or analog circuits include ferroelectric and non-ferroelectric thin films. When used in a circuit (e.g., when used as a digital switch), the ferroelectric portion of the gate dielectric stack provides a dynamic capacitance that, under a specific bias sweep state (e.g., scan rate or frequency), can be changed due to the ferroelectric The change in the polarization of the material causes a voltage snap-back. This snapback can result in a desirable sharper subthreshold and higher I ON /I OFF ratio for the FE-FET. In this context, FE-FETs have been commonly referred to as negative-capacitance field-effect transistors (NCFETs). Here, the FE-FET is more accurately called a steep-slope ferro-electric field-effect transistor (SSFEFET). However, ferroelectric properties (eg, P R ) and film thickness in the gate dielectric stack may need to be adjusted appropriately to achieve hysteresis-free crystal IV and IC curves. As known to those skilled in the art, hysteresis-free transistor IV and IC curves imply stable transistor operation, while the presence of hysteresis may lead to circuit instability and unintended electrical oscillations. It is understood that from the perspective of circuit stability, P R must remain stable and within the design window, so that the SSFEFET can provide the desired circuit advantages without making the circuit unstable. Thus, fabrication flows for SSFEFETs that do not include E-field FEA can incorporate a wake-up cycle step, yet use of the inventive E-field annealing techniques described in this disclosure can be achieved by reducing wake-up cycles and, in some embodiments, having no wake-up cycles In the case of stable ferroelectric properties to provide the advantage of cost reduction.

在本揭示內容中，首先，E場退火技術在E場退火(例如，E場FEA)製程步驟期間使用E場退火裝置之處理腔室之剖面圖的示意性說明來描述，如圖1A及圖1B中之替代實施例所示。E場退火裝置參考圖2-5所示之E場退火裝置之裝載軌道的諸多立體圖進一步描述。在FE-FET/SSFEFET及/或MOS鐵電電容器之閘極介電層的E場FEA期間的電連接分別參考圖6A及6B所示之平面塊體互補MOS(CMOS)及絕緣體上矽(silicon-on-insulator，SOI)CMOS半導體晶圓的剖面圖進行描述。除了MOS電容器之外，通常稱為MIM電容器之IC中的電容器元件亦可針對電容器的頂部及底部電極兩者使用金屬層來形成。在本揭示內容中，縮寫區分非鐵電性及鐵電性的絕緣體；非鐵電性之絕緣體的縮寫為I、且鐵電性之絕緣體的縮寫為F。在E場FEA期間對MFM之電極作成的電連接參考圖6C所示之剖面圖進行描述。In this disclosure, first, the E-field annealing technique is described using a schematic illustration of a cross-sectional view of a processing chamber of an E-field annealing device during an E-field anneal (eg, E-field FEA) process step, as shown in FIG. 1A and FIG. An alternative embodiment is shown in 1B. The E-field annealing device is further described with reference to various perspective views of the loading rails of the E-field annealing device shown in FIGS. 2-5 . The electrical connection during the E-field FEA of the gate dielectric layer of the FE-FET/SSFEFET and/or MOS ferroelectric capacitor refers to the planar bulk complementary MOS (CMOS) and silicon-on-insulator (silicon on insulator) shown in Figures 6A and 6B, respectively. -on-insulator, SOI) The cross-sectional view of the CMOS semiconductor wafer is described. In addition to MOS capacitors, capacitor elements in ICs, commonly referred to as MIM capacitors, can also be formed using metal layers for both the top and bottom electrodes of the capacitors. In this disclosure, abbreviations distinguish between non-ferroelectric and ferroelectric insulators; non-ferroelectric insulators are abbreviated as I and ferroelectric insulators are abbreviated as F. The electrical connections made to the electrodes of the MFM during E-field FEA are described with reference to the cross-sectional view shown in FIG. 6C.

材料層之諸多組合的堆疊可形成而用於鐵電電子裝置(例如，電晶體及電容器)。堆疊可包含鐵電層、以及非鐵電介電層、金屬層、及半導體。其範例包含但不限於下列堆疊(其中疊層由上至下列出)：金屬-鐵電物質-金屬(MFM)、金屬-鐵電物質-絕緣體-金屬(MFIM)、金屬-鐵電物質-絕緣體-半導體(MFIS)、金屬-鐵電物質-金屬-半導體(MFMS)、金屬-鐵電物質-金屬-絕緣體-半導體(MFMIS)、半導體-鐵電物質-半導體(SFS)、及半導體-鐵電物質-絕緣體-半導體(SFIS)。在此揭示內容中，示例堆疊可為MFIS(例如，在FEFET/SSFEFET電晶體中)或MFM(例如，在具有頂部及底部金屬電極之電容器中)。Stacks of many combinations of material layers can be formed for ferroelectric electronic devices such as transistors and capacitors. The stack can include ferroelectric layers, as well as non-ferroelectric dielectric layers, metal layers, and semiconductors. Examples include, but are not limited to, the following stacks (where stacks are listed from top to bottom): metal-ferroelectric-metal (MFM), metal-ferroelectric-insulator-metal (MFIM), metal-ferroelectric-insulator - Semiconductor (MFIS), Metal-Ferroelectric-Metal-Semiconductor (MFMS), Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS), Semiconductor-Ferroelectric-Semiconductor (SFS), and Semiconductor-Ferroelectric Substance-Insulator-Semiconductor (SFIS). In this disclosure, example stacks may be MFIS (eg, in FEFET/SSFEFET transistors) or MFM (eg, in capacitors with top and bottom metal electrodes).

圖1A示意性顯示置於E場退火裝置之處理腔室225內側之基板夾持具10上之半導體晶圓50的剖面圖，該E場退火裝置為配備成執行E場退火的退火裝置。處理腔室225包含設計成熱處理置於處理腔室225內之晶圓的熱處理系統235。在諸多實施例中，熱處理系統235包含控制加熱及冷卻元件的溫度控制器，以藉由使用置於處理腔室225內側或外側之諸多位置的燈具、電阻元件、及其他者來維持處理腔室225內之半導體晶圓50的期望溫度。1A schematically shows a cross-sectional view of a semiconductor wafer 50 placed on a substrate holder 10 inside a processing chamber 225 of an E-field annealing apparatus, which is an annealing apparatus equipped to perform an E-field annealing. The processing chamber 225 includes a thermal processing system 235 designed to thermally treat wafers placed within the processing chamber 225 . In various embodiments, the thermal processing system 235 includes temperature controllers that control heating and cooling elements to maintain the processing chamber by using lamps, resistive elements, and others placed at various locations inside or outside the processing chamber 225 The desired temperature of the semiconductor wafer 50 within 225 .

半導體晶圓50包含半導體基板20、形成於半導體基板20上方的MOS介電層30、及形成於MOS介電層30上方的導電頂部電極層40。The semiconductor wafer 50 includes a semiconductor substrate 20 , a MOS dielectric layer 30 formed over the semiconductor substrate 20 , and a conductive top electrode layer 40 formed over the MOS dielectric layer 30 .

如圖1A示意性所示，第一E場退火裝置電極與導電頂部電極層40實體及電接觸。第一E場退火裝置電極可包含不受高溫處理影響之導電材料。在一實施例中，第一E場退火裝置電極可包含鎢。第一E場退火裝置電極包含主要電極211(例如，鎢帶)，該主要電極211使用在退火期間可加熱至高溫而不受損之適當導體(例如，鎢)的主要線110連接至DC電源130的第一端子。帶狀的主要電極211提供如同彈簧的作用，當半導體晶圓50的表面在退火製程期間加熱時，該主要電極211有助於防止滑動、並與半導體晶圓50的表面維持良好的實體連接。導電頂部電極層40的電位可使用電壓計150選用性地監測，該電壓計150係藉由監測線112(類似於主要線110)連接至另一監測電極212(例如，與導電頂部電極層40接觸而放置的另一鎢帶)。兩電極透過導電頂部電極層40電氣短路在一起。主要電極211及監測電極212可統稱為第一E場退火裝置電極210。主要線110及監測線112可統稱為兩線115。As schematically shown in FIG. 1A , the first E-field annealer electrode is in physical and electrical contact with the conductive top electrode layer 40 . The first E field annealing device electrode may comprise a conductive material that is not affected by high temperature processing. In one embodiment, the first E-field annealing device electrode may comprise tungsten. The first E-field annealing device electrode comprises a main electrode 211 (e.g., a tungsten strip) connected to a DC power source using a main wire 110 of a suitable conductor (e.g., tungsten) that can be heated to high temperatures during annealing without damage 130 of the first terminal. The strip-shaped main electrodes 211 provide a spring-like effect and help prevent slipping and maintain a good physical connection with the surface of the semiconductor wafer 50 when the surface of the semiconductor wafer 50 is heated during the annealing process. The potential of the conductive top electrode layer 40 can optionally be monitored using a voltmeter 150 connected by a monitoring line 112 (similar to the main line 110) to another monitoring electrode 212 (e.g., with the conductive top electrode layer 40). Another tungsten strip placed in contact). The two electrodes are electrically shorted together through the conductive top electrode layer 40 . The main electrode 211 and the monitoring electrode 212 can be collectively referred to as the first E-field annealing device electrode 210 . The main line 110 and the monitoring line 112 can be collectively referred to as two lines 115 .

在圖1A所示之示例實施例中，與半導體晶圓50之背側實體接觸之基板夾持具10的表面係用作第二E場退火裝置電極。基板夾持具10之表面可用適當的導電材料(例如，矽基、碳基、矽與碳複合物基、或金屬氮化物基塗層)進行塗覆，以獲得適合在退火溫度下用作電極的導電表面。半導體晶圓50的背側及與該背側鄰近的部分可為例如n型或p型摻雜矽或鍺的導電材料、且可與基板夾持具10之表面電接觸。在一些實施例中，為了在半導體晶圓50的背側與基板夾持具10的表面之間建立電接觸，可能已使用背側蝕刻以暴露背側的導電表面。In the example embodiment shown in FIG. 1A , the surface of the substrate holder 10 that is in physical contact with the backside of the semiconductor wafer 50 is used as the second E-field annealer electrode. The surface of the substrate holder 10 may be coated with a suitable conductive material (e.g., silicon-based, carbon-based, silicon-carbon composite-based, or metal nitride-based coating) to obtain an electrode suitable for use at the annealing temperature. conductive surface. The backside of the semiconductor wafer 50 and portions adjacent to the backside may be a conductive material such as n-type or p-type doped silicon or germanium and may be in electrical contact with the surface of the substrate holder 10 . In some embodiments, to establish electrical contact between the backside of semiconductor wafer 50 and the surface of substrate holder 10 , a backside etch may have been used to expose the conductive surface of the backside.

如圖1A示意性所示，基板夾持具10的表面、及因此半導體晶圓50的背側可連接至參考電位，其稱為接地且在圖1A中表示為GND。接地可使用類似於主要線110的次要線113來建立。在此實施例中，次要線113電性連接至使設備之主要結構的導電部分連接至系統接地的接地線。DC電源130的第二端子亦連接至接地(GND)，以在半導體晶圓50的範圍內施加偏壓。如本領域之技術人員所理解，並於以下進一步說明，在DC電源的兩個端子之間的電壓降可進行調整以實現在MOS介電層30中之期望範圍內具有期望極性與E場強度的E場。在諸多實施例中，DC電源130可配置成提供例如介於1V與100V之間、且在一實施例中介於3V與10V之間的適當電壓。As shown schematically in FIG. 1A , the surface of the substrate holder 10 , and thus the backside of the semiconductor wafer 50 , may be connected to a reference potential, referred to as ground and denoted GND in FIG. 1A . Grounding may be established using a secondary wire 113 similar to primary wire 110 . In this embodiment, the secondary line 113 is electrically connected to a ground line that connects the conductive portion of the primary structure of the device to system ground. A second terminal of the DC power source 130 is also connected to ground (GND) to apply a bias voltage across the semiconductor wafer 50 . As understood by those skilled in the art, and explained further below, the voltage drop between the two terminals of the DC power supply can be adjusted to achieve a desired polarity and E-field strength within a desired range in the MOS dielectric layer 30 The E field. In many embodiments, DC power supply 130 may be configured to provide a suitable voltage, for example, between 1V and 100V, and in one embodiment between 3V and 10V.

注意在退火期間的施加偏壓可為固定電壓或時變電壓，且振幅與波形可取決於材料、層厚度、退火條件、及特定裝置應用而有極大差異。上述DC偏壓僅供說明，且不應解讀為限制性。時變電壓波形可包含脈波DC、交替脈波、正弦波、鋸齒波等。進一步注意，所施加的偏壓可參考常見接地電位、一些其他固定參考電位、受控變數參考電位、時變電位、或浮接節點電位。Note that the applied bias voltage during annealing can be a fixed voltage or a time-varying voltage, and that the amplitude and waveform can vary greatly depending on the material, layer thickness, annealing conditions, and particular device application. The above DC bias voltages are for illustration only and should not be read as limiting. The time-varying voltage waveform may include pulse DC, alternating pulse, sine wave, sawtooth wave, and the like. Note further that the applied bias voltage may be referenced to a common ground potential, some other fixed reference potential, a controlled variable reference potential, a time-varying potential, or a floating node potential.

雖然圖1A之實施例顯示處理腔室225內側的單一半導體晶圓50，但是據了解，包含仿真晶圓之多個晶圓可置於適當設計的處理腔室內側。圖1A中之 E場退火裝置電極與電連接顯示為配置用於單晶圓處理。然而，E場退火裝置配置可改成使一批次的半導體晶圓退火。適用於批次處理的示例實施例示於圖1B中。Although the embodiment of FIG. 1A shows a single semiconductor wafer 50 inside a processing chamber 225, it is understood that multiple wafers, including a dummy wafer, may be placed inside a suitably designed processing chamber. The E-field annealer electrodes and electrical connections in Figure 1A are shown configured for single wafer processing. However, the E-field annealer configuration can be modified to anneal a batch of semiconductor wafers. An example embodiment suitable for batch processing is shown in Figure IB.

在圖1B中，複數個半導體晶圓50在包含不受高溫處理影響之絕緣體(例如，陶瓷絕緣體)的開槽基板夾持具14上進行水平堆疊。絕緣材料防止基板夾持具14在半導體晶圓50的導電頂側及背側之間產生電氣短路。堆疊晶圓顯示為裝載至E場退火裝置的處理腔室226內側。位在處理腔室226內側者為兩導電匯流排：第一導電匯流排108及第二導電匯流排109，其分別固定在開槽基板夾持具14之上方及下方。處理腔室226內側的溫度可藉由熱處理系統236加以控制。In FIG. 1B , a plurality of semiconductor wafers 50 are stacked horizontally on a slotted substrate holder 14 that includes an insulator (eg, a ceramic insulator) that is not affected by high temperature processing. The insulating material prevents the substrate holder 14 from creating an electrical short between the conductive topside and backside of the semiconductor wafer 50 . The stacked wafers are shown loaded inside the process chamber 226 of the E-field annealer. Located inside the processing chamber 226 are two conductive bus bars: a first conductive bus bar 108 and a second conductive bus bar 109 , which are respectively fixed above and below the slotted substrate holder 14 . The temperature inside the processing chamber 226 can be controlled by the thermal processing system 236 .

各晶圓的導電頂側顯示為藉由類似於圖1A之主要電極211的主要電極215而電連接至第一導電匯流排108。如圖1B所示，在第一導電匯流排108與主要電極215之間的連接可使用通過開槽基板夾持具14中之開口的連接線來建立。在此實施例中，第一E場退火裝置電極包含主要電極215及第一導電匯流排108。第一E場退火裝置電極使用主要線110連接至DC電源130，其與圖1A中的相同。各晶圓的導電背側可使用次要電極216與連接線連接至第二導電匯流排109(類似於頂側)。在此實施例中，包含次要電極216與第二導電匯流排109之第二E場退火裝置電極使用次要線114連接至GND。晶圓之頂側的電位可藉由使用監測線112將第一導電匯流排108連接至電壓計150進行監測，如圖1B所示。The conductive top side of each wafer is shown electrically connected to the first conductive bus bar 108 by a main electrode 215 similar to main electrode 211 of FIG. 1A . As shown in FIG. 1B , the connection between the first conductive bus bar 108 and the main electrode 215 may be established using a connection wire through an opening in the slotted substrate holder 14 . In this embodiment, the first E-field annealing device electrode includes the main electrode 215 and the first conductive bus bar 108 . The first E field annealer electrode is connected to a DC power source 130 using the main line 110, which is the same as in FIG. 1A. The conductive backside of each wafer may be connected to the second conductive busbar 109 (similar to the topside) using secondary electrodes 216 and bonding wires. In this embodiment, the second E-field annealing device electrode including the secondary electrode 216 and the second conductive bus bar 109 is connected to GND using the secondary line 114 . The potential on the top side of the wafer can be monitored by connecting the first conductive bus bar 108 to a voltmeter 150 using a monitor line 112, as shown in FIG. 1B.

上述參考圖1B之E場退火裝置適用於批次處理以水平堆疊排列的晶圓。水平處理腔室226的設計可修改成提供類似的E場退火，其中半導體晶圓50可垂直堆疊。The E-field annealing device described above with reference to FIG. 1B is suitable for batch processing wafers arranged in horizontal stacks. The design of the horizontal processing chamber 226 can be modified to provide a similar E-field anneal where the semiconductor wafers 50 can be stacked vertically.

圖2根據本發明之實施例顯示E場退火裝置之裝載軌道100的立體圖。裝載軌道100可用於將晶圓引進E場退火裝置之處理腔室225內。晶圓首先裝載到固定在裝載軌道台之基板夾持具中的槽位內(圖2)。然後，定位電極以對晶圓/各晶圓形成適當的電接觸。裝載軌道台接著用於將晶圓定位於基板夾持具中、進入爐的加熱區。FIG. 2 shows a perspective view of a loading rail 100 of an E-field annealing device according to an embodiment of the present invention. The loading rail 100 can be used to introduce the wafer into the processing chamber 225 of the E-field annealing apparatus. Wafers are first loaded into slots in substrate holders secured to the load rail table (Figure 2). The electrodes are then positioned to make appropriate electrical contact to the wafer/wafers. The load rail stage is then used to position the wafer in the substrate holder into the heating zone of the furnace.

在圖2中，兩線115(類似於圖1A之主要線110及監測線112)顯示為通向區域B 1(由圖2之虛線圓表示)。包含第一E場退火裝置210之區域B 1包括接觸半導體晶圓50之導電頂部電極層40的兩鎢帶。如以上所述，帶狀有助於在退火製程期間與半導體晶圓50維持良好實體連接。第一E場退火裝置電極210附接至兩線115之暴露的金屬(例如，暴露的鎢)的多個部分。兩線115的其他多個部分藉由絕緣材料(例如，絕緣陶瓷珠)從設備的其他多個導電部位電絕緣。兩線115的多個絕緣部分稱為絕緣導電線310。圖3顯示由圖2之虛線圓表示的區域D 1之放大立體圖中的陶瓷珠絕緣導電線310。 In FIG. 2, two lines 115 (similar to main line 110 and monitoring line 112 of FIG. 1A) are shown leading to area B1 (represented by the dashed circle in FIG. 2). Region B 1 including the first E-field annealing device 210 includes two tungsten strips contacting the conductive top electrode layer 40 of the semiconductor wafer 50 . As mentioned above, the ribbon shape helps to maintain a good physical connection with the semiconductor wafer 50 during the annealing process. The first E-field annealer electrode 210 is attached to portions of the exposed metal (eg, exposed tungsten) of the two lines 115 . Other portions of the two wires 115 are electrically insulated from other conductive parts of the device by insulating material (eg, insulating ceramic beads). The multiple insulated portions of the two wires 115 are referred to as insulated conductive wires 310 . FIG. 3 shows ceramic bead insulated conductive lines 310 in an enlarged perspective view of region D1 indicated by the dashed circle in FIG. 2 .

兩線115中的第一者通過電源饋孔120(示於圖2中)並可連接至用於提供介電層(例如，如上述半導體晶圓50的MOS介電層30)中之E場的DC電源130。兩線115(類似於圖1A之監測線112)中的另一線其一端可連接至第一E場退火裝置電極210，且相對端可連接至電壓計150，以監測半導體晶圓50之導電頂部電極層40的電位，如圖2示意性所示。包含與半導體晶圓50的背側接觸之基板夾持具(例如，圖1A之基板夾持具10)之設備之主要結構的多個導電部位藉由接地線140連接至接地GND。半導體晶圓50的基板夾持具參考圖5A於以下進一步描述，其顯示區域B 1(由圖2之虛線圓表示)之放大立體圖。 The first of the two lines 115 passes through the power feedthrough 120 (shown in FIG. 2 ) and may be connected to a circuit for providing an E-field in a dielectric layer (eg, the MOS dielectric layer 30 of the semiconductor wafer 50 described above). DC power supply 130. One end of the other of the two lines 115 (similar to the monitoring line 112 of FIG. 1A ) can be connected to the first E-field annealing device electrode 210, and the opposite end can be connected to the voltmeter 150 to monitor the conductive top of the semiconductor wafer 50. The potential of the electrode layer 40 is schematically shown in FIG. 2 . A number of conductive parts of the main structure of the apparatus including a substrate holder (eg, substrate holder 10 of FIG. 1A ) in contact with the backside of semiconductor wafer 50 are connected to ground GND by ground wire 140 . The substrate holder for semiconductor wafer 50 is described further below with reference to FIG. 5A , which shows an enlarged perspective view of area B 1 (indicated by the dashed circle in FIG. 2 ).

由圖2之箭頭C所表示裝載軌道100從不同角度的立體圖示於圖4中。圖4顯示藉由從通過兩各別開口的兩各別絕緣導電線310移除陶瓷珠而暴露之兩線115的導體。兩線115連接至第一E場退火裝置電極210之兩鎢帶，該等鎢帶與半導體晶圓50之頂面接觸。圖4之這些兩線115為圖2所示之相同線，其分別從第一E場退火裝置電極210行進至DC電源130及電壓計150。在圖4之立體圖中，第一E場退火裝置電極210位於區域C 1中(由虛線圓表示)。在圖2之立體圖中，第一E場退火裝置電極210位於區域B 1中。 Perspective views of the loading rail 100 from different angles indicated by arrow C in FIG. 2 are shown in FIG. 4 . Figure 4 shows the conductors of the two wires 115 exposed by removing the ceramic beads from the two respective insulated conductive wires 310 passing through the two respective openings. The two wires 115 are connected to the two tungsten strips of the first E-field annealer electrode 210 which are in contact with the top surface of the semiconductor wafer 50 . These two lines 115 of FIG. 4 are the same lines shown in FIG. 2, which run from the first E-field annealer electrode 210 to the DC power source 130 and the voltmeter 150, respectively. In the perspective view of FIG. 4, the first E-field annealing device electrode 210 is located in region C1 (indicated by the dashed circle). In the perspective view of FIG. 2 , the first E-field annealing device electrode 210 is located in the region B1 .

圖2之區域B 1及圖4之區域C 1分別更詳細地示於圖5A及5B所示之放大立體圖中。圖5A中之立體圖更清楚地顯示在兩線115其中一者與第一E場退火裝置電極210之間的連接。從圖5B之立體圖的角度顯示為提供與半導體晶圓50之導電頂部電極層40形成實體接觸的第一E場退火裝置210之鎢帶的更清楚示例。圖5A及5B中之半導體晶圓50顯示為透過支撐板230從底部支撐。支撐板230為圖2及圖3所示之開槽基板夾持具的一部分，且其亦可為圖1A之基板夾持具10的示例實施例。支撐板230的表面可為包括例如不鏽鋼之金屬、且其可與半導體晶圓50之導電背側實體及電接觸。在一實施例中，支撐板230可為環之形式。環狀支撐晶圓的外徑，但是使其背側表面的大部分暴露於加熱元件。支撐板230可包含連接至接地GND的導電材料。 Area B 1 of FIG. 2 and area C 1 of FIG. 4 are shown in more detail in the enlarged perspective views shown in FIGS. 5A and 5B , respectively. The perspective view in FIG. 5A more clearly shows the connection between one of the two wires 115 and the first E-field annealer electrode 210 . A clearer example of the tungsten strips of the first E-field annealing device 210 that provides physical contact with the conductive top electrode layer 40 of the semiconductor wafer 50 is shown from the perspective of the perspective view of FIG. 5B . Semiconductor wafer 50 in FIGS. 5A and 5B is shown supported from the bottom by support plate 230 . The support plate 230 is part of the slotted substrate holder shown in FIGS. 2 and 3 , and it may also be an example embodiment of the substrate holder 10 of FIG. 1A . The surface of support plate 230 may be a metal including, for example, stainless steel, and it may make physical and electrical contact with the conductive backside of semiconductor wafer 50 . In one embodiment, the support plate 230 may be in the form of a ring. The ring supports the outer diameter of the wafer, but leaves the majority of its backside surface exposed to the heating element. The support plate 230 may include a conductive material connected to the ground GND.

圖5A顯示在退火期間有助於實現在半導體晶圓50之表面範圍內之更均勻溫度分布的若干選用性緩衝晶圓240。為了清楚起見，緩衝晶圓240未示於圖4及5B中。如圖5B所示，絕緣陶瓷突出部250可沿著靠近半導體晶圓50與支撐板230之邊緣的托架軌道放置，以減少半導體晶圓50與E場退火裝置的導電表面之間意外產生不理想電氣短路的可能性。FIG. 5A shows several optional buffer wafers 240 that help achieve a more uniform temperature distribution across the surface of the semiconductor wafer 50 during annealing. Buffer wafer 240 is not shown in FIGS. 4 and 5B for clarity. As shown in FIG. 5B , insulating ceramic protrusions 250 may be placed along the carriage rails near the edge of semiconductor wafer 50 and support plate 230 to reduce accidental inconsistencies between semiconductor wafer 50 and the conductive surface of the E-field annealing device. Possibility of an ideal electrical short circuit.

在E場PDA期間可對DC電源130加以設定的DC偏壓通常不僅取決於E場PDA被執行針對之目標介電層(例如，圖1A之MOS介電層30)的厚度( t OX)，但是其亦可取決於例如用於導電頂部電極層40上之材料的其他疊層的性質；及在目標介電層下方的疊層之材料、厚度、及性質，如以下所述。在一些實施例中，DC電源130的DC偏壓可受控制以在E場退火期間保持恆定。 The DC bias voltage that can be set to the DC power supply 130 during E-field PDA generally depends not only on the thickness ( t OX ) of the target dielectric layer (eg, MOS dielectric layer 30 of FIG. 1A ) for which E-field PDA is performed, But it may also depend on the properties of other stacks such as the material used on the conductive top electrode layer 40; and the materials, thicknesses, and properties of the stack below the target dielectric layer, as described below. In some embodiments, the DC bias voltage of DC power supply 130 may be controlled to remain constant during the E-field anneal.

圖6A及6B分別顯示半導體晶圓50在平面塊體CMOS流程及平面SOI CMOS流程之E場退火步驟的剖面圖。在圖6A及6B所示之示例實施例中的E場退火步驟為E場鐵電退火(FEA)，其在導電頂部電極層40已形成於MOS介電層30上方後執行。導電頂部電極層40可用作FE-FET/SSFEFET或鐵電MOS電容器的閘極、且其可包含一或更多例如TiN、TaN、W、金屬合金等之導電材料。6A and 6B respectively show cross-sectional views of the semiconductor wafer 50 in the E-field annealing step of the planar bulk CMOS process and the planar SOI CMOS process. The E-field anneal step in the example embodiment shown in FIGS. 6A and 6B is an E-field ferroelectric anneal (FEA), which is performed after the conductive top electrode layer 40 has been formed over the MOS dielectric layer 30 . The conductive top electrode layer 40 may serve as the gate of a FE-FET/SSFEFET or a ferroelectric MOS capacitor, and it may comprise one or more conductive materials such as TiN, TaN, W, metal alloys, and the like.

在圖6A及6B中，前置閘極製程積分法可用於製造使用MOS介電層30的鐵電元件(例如，FE-FET/SSFEFET、及鐵電MOS電容器)。然而，本領域技術人員理解這些實施例的創新態樣適用於使用後置閘極(或替代閘極)製程積分法製造的各別鐵電元件。In FIGS. 6A and 6B , the pre-gate process integration method can be used to fabricate ferroelectric devices (eg, FE-FET/SSFEFET, and ferroelectric MOS capacitors) using MOS dielectric layer 30 . However, those skilled in the art understand that the novel aspects of these embodiments are applicable to individual ferroelectric devices fabricated using post-gate (or alternative gate) process integration methods.

在圖6A及6B所示之示例實施例中，MOS介電層30包含摻雜非晶質鉿氧化物膜、及鄰近半導體(例如，矽)之表面的介面介電層(例如，矽氧化物)。MOS介電層30的厚度( t OX)取決於應用且其可從約1nm變化至約100nm。可將退火溫度進行調整，使得在退火期間，摻雜非晶質鉿氧化物膜將結晶化而形成多晶鉿氧化物膜。舉例而言，E場FEA可在例如低壓之惰性氣體的環境中以約200°C至約1200°C的溫度下執行。低於200°C的溫度可能不足以將非晶層結晶化，且高於1200°C的溫度可能改變在前期製程步驟期間所形成之其他層的性質。鉿氧化物之斜方晶相為鐵電性，但是純非晶質HfO 2可自然轉換成單斜相或立方相晶粒，因為斜方晶相在純HfO 2中不穩定。然而，如本領域之技術人員所知，HfO 2的斜方晶相可藉由例如鋯、矽、或鑭原子之特定摻雜劑原子加以穩定化。因此，當使在MOS介電層30中之摻雜非晶質鉿氧化物膜結晶化時，HfO 2的斜方晶相就會形成，且其可藉由呈鐵電性之亞穩斜方晶相的摻雜劑加以穩定化。E場FEA期間的電場強度可調整為在1 MV/cm至約100 MV/cm之間。雖然E場太低可能不足以提供降低/排除喚醒循環的優勢，但是E場太高可能使MOS介電層30受損及/或使其壽命減少。在MOS介電層30中提供期望範圍內之E場之DC電源130的各別DC偏壓設定取決於製程流程是否用於塊體CMOS或SOI CMOS的製造，如以下進一步說明。 In the exemplary embodiment shown in FIGS. 6A and 6B , the MOS dielectric layer 30 includes a doped amorphous hafnium oxide film, and an interfacial dielectric layer (eg, silicon oxide) adjacent to the surface of a semiconductor (eg, silicon). ). The thickness ( t OX ) of the MOS dielectric layer 30 is application dependent and may vary from about 1 nm to about 100 nm. The annealing temperature can be adjusted so that during the annealing, the doped amorphous hafnium oxide film will crystallize to form a polycrystalline hafnium oxide film. For example, E-field FEA may be performed at a temperature of about 200°C to about 1200°C in an environment such as a low pressure inert gas. Temperatures below 200°C may not be sufficient to crystallize the amorphous layer, and temperatures above 1200°C may alter the properties of other layers formed during earlier process steps. The orthorhombic phase of hafnium oxide is ferroelectric, but pure amorphous HfO 2 can naturally transform into monoclinic or cubic phase grains, because the orthorhombic phase is unstable in pure HfO 2 . However, as known to those skilled in the art, the orthorhombic phase of HfO2 can be stabilized by specific dopant atoms such as zirconium, silicon, or lanthanum atoms. Therefore, when the doped amorphous hafnium oxide film in the MOS dielectric layer 30 is crystallized, the orthorhombic phase of HfO2 is formed, and it can be metastable orthorhombic by ferroelectricity. The crystal phase is stabilized by dopants. The electric field strength during E-field FEA can be adjusted to be between 1 MV/cm and about 100 MV/cm. While an E-field that is too low may not sufficiently provide the advantage of reducing/eliminating wake-up cycles, an E-field that is too high may damage and/or reduce the lifetime of the MOS dielectric layer 30 . The respective DC bias setting of the DC power supply 130 to provide an E-field within the desired range in the MOS dielectric layer 30 depends on whether the process flow is used for bulk CMOS or SOI CMOS fabrication, as further described below.

在圖6A-6C中，其上形成專用於鐵電元件之疊層的半導體晶圓50之疊層統稱為基板20。因此，就圖6A及6B所示之平面FE-FET/SSFEFET或鐵電MOS電容器而言，基板20包含在形成MOS介電層30之前形成的所有疊層。就圖6C所示之MFM鐵電電容器而言，基板20包含在形成MFM導電底部電極層45之前形成的所有疊層。In FIGS. 6A-6C , the stack of semiconductor wafers 50 on which the stack dedicated to the ferroelectric element is formed is collectively referred to as the substrate 20 . Thus, for the planar FE-FET/SSFEFET or ferroelectric MOS capacitor shown in FIGS. 6A and 6B , the substrate 20 includes all stack layers formed before the MOS dielectric layer 30 is formed. For the MFM ferroelectric capacitor shown in FIG. 6C , the substrate 20 includes all stack layers formed prior to the formation of the MFM conductive bottom electrode layer 45 .

平面FE-FET/SSFEFET或鐵電MOS電容器的基板20包含第一導電型(例如， p型)之第一半導體區域21、第二導電型(例如， n型)之第二半導體區域22、及稱為淺溝槽絕緣(shallow-trench isolation，STI)區域25之絕緣區域，其用於分別電氣隔絕在第一半導體區域21及第二半導體區域22中的鄰近電子元件。如本領域之技術人員所知，在第一半導體區域21及第二半導體區域22上方之導電頂部電極層40可包含藉由相同製程形成的相同材料、或包含藉由不同製程形成的相異材料。當使用不同製程時，諸多遮蔽步驟可用於遮蔽及暴露適當區域。 The substrate 20 of a planar FE-FET/SSFEFET or a ferroelectric MOS capacitor includes a first semiconductor region 21 of a first conductivity type (for example, p -type), a second semiconductor region 22 of a second conductivity type (for example, n -type), and An insulating region called a shallow-trench isolation (STI) region 25 is used to electrically isolate adjacent electronic components in the first semiconductor region 21 and the second semiconductor region 22 , respectively. As known to those skilled in the art, the conductive top electrode layer 40 over the first semiconductor region 21 and the second semiconductor region 22 may comprise the same material formed by the same process, or comprise dissimilar materials formed by a different process. . Multiple masking steps can be used to mask and expose appropriate areas when using different processes.

如圖6A所示，在塊體CMOS中，第一導電型之第一半導體區域21一直延伸至半導體晶圓50的背側、且第二導電型之第二導電區域22延伸直至與第一半導體區域21形成 p-n接面的深度。 p-n接面通常稱為n型井至p型井區接面。在SOI CMOS中，第一半導體區域21、第二半導體區域22、及STI區域25藉由包含例如矽氧化物之稱為埋入式氧化物(BOX)層15的絕緣區域而終止於下方，如圖6B所示。如本領域之技術人員所知，具有BOX層15之半導體晶圓可使用例如注氧隔離(Separation by Implantation of Oxygen，SIMOX)製程、晶片黏接製程、智切技術等之若干方法來製造。在BOX層15下方之摻雜半導體區域12一直延伸至半導體晶圓50的背側。 As shown in FIG. 6A, in bulk CMOS, the first semiconductor region 21 of the first conductivity type extends to the backside of the semiconductor wafer 50, and the second conductivity region 22 of the second conductivity type extends until it is in contact with the first semiconductor wafer. Region 21 forms the depth of the pn junction. The pn junction is often referred to as the n-well to p-well junction. In SOI CMOS, the first semiconductor region 21, the second semiconductor region 22, and the STI region 25 are terminated underneath by an insulating region called a buried oxide (BOX) layer 15 comprising, for example, silicon oxide, as Figure 6B. As known by those skilled in the art, the semiconductor wafer with the BOX layer 15 can be manufactured using several methods such as Separation by Implantation of Oxygen (SIMOX) process, die bonding process, smart slicing technology, and the like. The doped semiconductor region 12 below the BOX layer 15 extends as far as the backside of the semiconductor wafer 50 .

半導體晶圓50的背側及DC電源130的第二端子連接至接地GND、且DC電源的第一端子使用主要線110連接至E場退火裝置電極的主要電極211，如以上參考圖1A及2所述。(為了簡明起見，監測電極212及監測線112未示於圖6A-6C中。)圖6A及6B所示之主要電極211與導電頂部電極層40實體及電接觸，類似於圖1A之剖面圖及圖5A與5B之詳細立體圖。因此，藉由DC電源130提供的總DC偏壓被施加在導電頂部電極層40及半導體晶圓50之背側的範圍內。The backside of the semiconductor wafer 50 and the second terminal of the DC power supply 130 are connected to ground GND, and the first terminal of the DC power supply is connected to the main electrode 211 of the E field annealing device electrode using the main line 110, as above with reference to FIGS. 1A and 2 mentioned. (For simplicity, monitor electrode 212 and monitor line 112 are not shown in FIGS. 6A-6C.) The main electrode 211 shown in FIGS. 6A and 6B is in physical and electrical contact with the conductive top electrode layer 40, similar to the cross-section of FIG. 1A Figure and detailed perspective view of Figures 5A and 5B. Thus, the overall DC bias provided by the DC power source 130 is applied within the confines of the conductive top electrode layer 40 and the backside of the semiconductor wafer 50 .

再次參考圖6A，於塊體CMOS中，在第一半導體區域21中，在MOS介電層30之半導體側的電位與半導體晶圓50之背側的電位大致相同。因此，在MOS介電層30範圍內之電壓降藉由DC電源130提供的DC偏壓、及此區域上方在第一半導體區域21與導電頂部電極層40之間的功函數差異來判定。然而，在第二半導體區域22中，在判定MOS介電層30之半導體側的電位方面、且由此在判定MOS介電層30範圍內的電壓降方面必須包含n型井區至p型井區接面範圍內的電壓降。因此，藉由選擇透過DC電源130提供之複數個DC偏壓而使得 p-n接面變為順向偏壓來將在n型井區至p型井區接面範圍內的電壓降減至最小可為具有優勢的。在一實施例中，就MOS介電層30之約10nm的 t OX值而言，DC電源130在E場FEA期間的DC偏壓設定可為約3V至約10V。 Referring again to FIG. 6A , in bulk CMOS, in the first semiconductor region 21 , the potential on the semiconductor side of the MOS dielectric layer 30 is substantially the same as the potential on the backside of the semiconductor wafer 50 . Thus, the voltage drop across the MOS dielectric layer 30 is determined by the DC bias provided by the DC power source 130 and the work function difference between the first semiconductor region 21 and the conductive top electrode layer 40 over this region. However, in the second semiconductor region 22, it is necessary to include the n-type well region to the p-type well in determining the potential of the semiconductor side of the MOS dielectric layer 30, and thus in determining the voltage drop within the range of the MOS dielectric layer 30. The voltage drop across the area junction. Therefore, minimizing the voltage drop across the n-well to p-well junction range by selecting the plurality of DC bias voltages provided through the DC power supply 130 such that the pn junction becomes forward biased can be achieved. to be advantageous. In one embodiment, for the t OX value of the MOS dielectric layer 30 of about 10 nm, the DC bias setting of the DC power source 130 during the E-field FEA may be about 3V to about 10V.

參考圖6B，在SOI CMOS中，透過DC電源130提供之DC偏壓的一實質分數可能在BOX層15的範圍內降低，其取決於MOS介電層30與BOX層15之厚度比及介電常數比。因此，在SOI CMOS製程流程中用於E場FEA的DC偏壓可能必須相對於在塊體CMOS製程流程中的相應值而增加。Referring to FIG. 6B, in SOI CMOS, a substantial fraction of the DC bias voltage provided by the DC power supply 130 may be reduced within the BOX layer 15, depending on the thickness ratio of the MOS dielectric layer 30 to the BOX layer 15 and the dielectric constant ratio. Therefore, the DC bias voltage for E-field FEA in SOI CMOS process flow may have to be increased relative to the corresponding value in bulk CMOS process flow.

相對先進的CMOS IC可使用三維MOS結構，其稱為FinFET結構，其中閘極與閘極介電質大致包覆從半導體基板突出之細長半導體鰭片的三側。參考圖6A及6B所示之平面MOS結構而描述之在E場FEA退火期間與FE-FET/SSFEFET及MOS鐵電電容器的電連接可藉由本領域之技術人員進行調整以執行各別FinFET結構的E場FEA。Relatively advanced CMOS ICs may use a three-dimensional MOS structure, referred to as a FinFET structure, in which the gate and gate dielectric surround approximately three sides of an elongated semiconductor fin protruding from the semiconductor substrate. The electrical connections to the FE-FET/SSFEFET and MOS ferroelectric capacitors during the E-field FEA anneal described with reference to the planar MOS structures shown in FIGS. 6A and 6B can be adjusted by those skilled in the art to implement the respective FinFET structures. E field FEA.

圖6C顯示在包含MFM鐵電電容器之製造的製程流程中執行的E場FEA步驟。圖6C之MFM鐵電電容器結構包含夾於導電頂部電極層40與導電底部電極層45之間的基於摻雜鉿氧化物之鐵電介電層35。顯示為與導電頂部電極40接觸的主要電極211使用主要線110而連接至DC電源130的第一端子(未示出)。半導體晶圓50之背側及DC電源130之第二端子連接至GND，其與圖6A及6B之半導體晶圓50相同。然而，如果導電底部電極層45由於基板20中之介電層的過高累積厚度而變得與圖6C之半導體晶圓50的背側GND連接有效地電絕緣，這些連接自身可能不足以在MFM電容器之鐵電介電層35中產生足夠高的E場，如以下說明。Figure 6C shows the E-field FEA step performed in a process flow involving the fabrication of MFM ferroelectric capacitors. The MFM ferroelectric capacitor structure of FIG. 6C includes a ferroelectric dielectric layer 35 based on doped hafnium oxide sandwiched between a conductive top electrode layer 40 and a conductive bottom electrode layer 45 . The main electrode 211 , shown in contact with the conductive top electrode 40 , is connected to a first terminal (not shown) of the DC power source 130 using the main line 110 . The backside of the semiconductor wafer 50 and the second terminal of the DC power source 130 are connected to GND, which is the same as the semiconductor wafer 50 of FIGS. 6A and 6B . However, if the conductive bottom electrode layer 45 becomes effectively electrically isolated from the backside GND connections of the semiconductor wafer 50 of FIG. A sufficiently high E-field is generated in the ferroelectric dielectric layer 35 of the capacitor, as explained below.

包含導電底部電極層45之MFM電容層通常在IC製造流程之後段製程(back-end-of-life，BEOL)期間形成。由於圖6C之基板20包含所有在導電底部電極層45下方形成的疊層，其可包含實體位於MOSFET之導電半導體與閘極層上之相對厚的層間介電(ILD)層及金屬間介電(IMD)層。因此，除非在圖6C所述之製造之中間階段，導電底部電極層45藉由通孔及接點連接至MOSFET的導電半導體與閘極層，否則在半導體晶圓50之背側及導電底部電極層45之間的電氣耦合可能過於脆弱而無法於MFM電容器之鐵電介電層35中產生足夠高的E場。在如此實施例中，與半導體晶圓50之背側電接觸的基板夾持具(例如，圖1A之基板夾持具10或圖5A之支撐板230)可能不為有效的第二E場退火裝置電極。在如此示例中，可使用額外處理來產生有效的第二E場退火裝置電極連接，如以下參考圖6C所述。The MFM capacitor layer including the conductive bottom electrode layer 45 is typically formed during the back-end-of-life (BEOL) of the IC manufacturing process. Since the substrate 20 of FIG. 6C includes all layer stacks formed below the conductive bottom electrode layer 45, it may include relatively thick interlayer dielectric (ILD) layers and intermetal dielectrics physically located on the conductive semiconductor and gate layers of the MOSFET. (IMD) layer. Therefore, unless the conductive bottom electrode layer 45 is connected to the conductive semiconductor and gate layers of the MOSFET by vias and contacts at an intermediate stage of fabrication as depicted in FIG. The electrical coupling between layers 45 may be too weak to generate a sufficiently high E-field in the ferroelectric dielectric layer 35 of the MFM capacitor. In such embodiments, the substrate holder (eg, substrate holder 10 of FIG. 1A or support plate 230 of FIG. 5A ) that is in electrical contact with the backside of semiconductor wafer 50 may not be effective for the second E-field anneal. device electrodes. In such an example, additional processing may be used to create an effective second E-field annealer electrode connection, as described below with reference to FIG. 6C.

在導電底部電極層45於期望E場FEA之製程流程之中間階段從半導體晶圓50的背側電氣去耦的IC設計中，遮蔽步驟可用於將MFM電容器之鐵電介電層35及導電頂部電極層40圖案化以暴露導電底部電極層45的一部分，如圖6C所示。導電底部電極層45的暴露區域可為例如沿著半導體晶圓50邊緣呈環狀。額外的次要電極214(與圖1A之剖面圖及圖5A與5B之詳細立體圖所示之第一E場退火裝置電極210的電極結構相似)可與導電底部電極層45的暴露部分實體及電接觸而放置。直接電接觸至導電底部電極層45的次要電極214可為有效的第二E場退火裝置電極連接。如圖6C所示，額外的次要電極214可使用次要線114(類似於主要線110)連接至GND。因此，整體DC電壓於MFM電容器之鐵電介電層35範圍內降低。在一實施例中，就MFM電容器之鐵電介電層35之約10nm的 t OX 值而言，在E場FEA期間之DC電源130的DC偏壓設定可為約3V至約10V。 In IC designs where the conductive bottom electrode layer 45 is electrically decoupled from the backside of the semiconductor wafer 50 at an intermediate stage in the process flow where E-field FEA is desired, the masking step may be used to separate the ferroelectric dielectric layer 35 and the conductive top layer of the MFM capacitor. The electrode layer 40 is patterned to expose a portion of the conductive bottom electrode layer 45, as shown in FIG. 6C. The exposed area of the conductive bottom electrode layer 45 may be, for example, ring-shaped along the edge of the semiconductor wafer 50 . An additional secondary electrode 214 (similar to the electrode structure of the first E-field annealing device electrode 210 shown in the cross-sectional view of FIG. 1A and the detailed perspective views of FIGS. 5A and 5B ) may be physically and electrically connected to the exposed portion of the conductive bottom electrode layer 45. placed in contact. The secondary electrode 214 in direct electrical contact to the conductive bottom electrode layer 45 may be an effective second E-field annealer electrode connection. As shown in FIG. 6C , an additional secondary electrode 214 may be connected to GND using a secondary line 114 (similar to primary line 110 ). Therefore, the overall DC voltage is reduced within the ferroelectric dielectric layer 35 of the MFM capacitor. In one embodiment, the DC bias setting of the DC power supply 130 during the E-field FEA may be about 3V to about 10V for a tOX value of about 10 nm for the ferroelectric dielectric layer 35 of the MFM capacitor.

圖7根據本發明之實施例描述製造半導體設備的製造平台。製造平台700包含第一沉積腔室701，配置成在半導體晶圓上沉積導電層；第二沉積腔室，配置成在半導體晶圓上沉積介電層；電場退火裝置之處理腔室703；清洗腔室704；及晶圓傳送系統705。FIG. 7 depicts a fabrication platform for fabricating semiconductor devices according to an embodiment of the present invention. The manufacturing platform 700 includes a first deposition chamber 701 configured to deposit a conductive layer on a semiconductor wafer; a second deposition chamber configured to deposit a dielectric layer on a semiconductor wafer; a processing chamber 703 of an electric field annealing device; cleaning chamber 704; and wafer transfer system 705.

製造平台700的內部可維持在真空狀態下以確保清洗處理條件，且晶圓傳送系統705配置成在製造平台700的處理腔室之間轉移待處理的晶圓。清洗腔室704可配置用於在處理之前、及在處理步驟之間將氧化及汙染物從晶圓移除。The interior of the manufacturing platform 700 may be maintained in a vacuum state to ensure cleaning processing conditions, and the wafer transfer system 705 is configured to transfer wafers to be processed between processing chambers of the manufacturing platform 700 . The cleaning chamber 704 may be configured to remove oxidation and contaminants from the wafer prior to processing and between processing steps.

電場退火裝置之處理腔室703已於以上諸多實施例中描述。在實施例中，處理腔室703包含基板夾持具，配置成支撐半導體晶圓；加熱元件，配置成加熱藉由基板夾持具支撐的半導體晶圓；第一電極，配置成可分離地附接至半導體晶圓的第一主要表面；及第一線，其將第一電極耦合至第一電位節點。The processing chamber 703 of the electric field annealing device has been described in many embodiments above. In an embodiment, the processing chamber 703 includes a substrate holder configured to support a semiconductor wafer; a heating element configured to heat the semiconductor wafer supported by the substrate holder; a first electrode configured to detachably attach connected to the first major surface of the semiconductor wafer; and a first line coupling the first electrode to the first potential node.

在一實施例中，處理腔室703可包含第二電極，其耦合至基板夾持具；及第二線，其將第二電極耦合至第二電位節點。此外，處理腔室703可包含第三電極，其配置成可分離地附接至半導體晶圓的第一主要表面；電壓監測計；及第三線，其將第三電極耦合至電壓監測計。在一實施例中，處理腔室703可包含第二電極，其配置成可分離地附接至半導體晶圓之第二主要表面；及第二線，其將第二電極耦合至第二電位節點。In one embodiment, the processing chamber 703 may include a second electrode coupled to the substrate holder; and a second line coupling the second electrode to a second potential node. Additionally, the processing chamber 703 can include a third electrode configured to be detachably attached to the first major surface of the semiconductor wafer; a voltage gauge; and a third wire coupling the third electrode to the voltage gauge. In one embodiment, the processing chamber 703 may include a second electrode configured to be detachably attached to the second major surface of the semiconductor wafer; and a second line coupling the second electrode to a second potential node .

此外，處理腔室703可包含電源，其耦合至第一電位節點。在一實施例中，電源係配置用於將電偏壓施加在介電層範圍內。在一實施例中，電偏壓包含時變電壓波形。在一實施例中，電源係配置用於在加熱元件施加熱至半導體晶圓時將電偏壓施加在介電層範圍內。在一實施例中，加熱元件使半導體晶圓的溫度從第一溫度勻變至第二溫度。Additionally, the processing chamber 703 may include a power supply coupled to the first potential node. In one embodiment, the power source is configured to apply an electrical bias within the dielectric layer. In one embodiment, the electrical bias comprises a time-varying voltage waveform. In one embodiment, the power source is configured to apply an electrical bias within the dielectric layer when the heating element applies heat to the semiconductor wafer. In one embodiment, the heating element ramps the temperature of the semiconductor wafer from a first temperature to a second temperature.

根據一實施例，製造半導體裝置的方法包含將半導體晶圓置於製造平台700之第一沉積腔室701內。在一實施例中，半導體晶圓包含第一導電層。在一範例中，第一導電層可沉積於第二沉積腔室702中的晶圓上，且其後將晶圓置於第一沉積腔室701中。在另一範例中，晶圓可在將第一導電層沉積於晶圓上之前或之後於清洗腔室704中進行清洗。According to an embodiment, a method of manufacturing a semiconductor device includes placing a semiconductor wafer in a first deposition chamber 701 of a manufacturing platform 700 . In one embodiment, the semiconductor wafer includes a first conductive layer. In one example, a first conductive layer may be deposited on a wafer in the second deposition chamber 702 , and the wafer is thereafter placed in the first deposition chamber 701 . In another example, the wafer may be cleaned in the cleaning chamber 704 before or after depositing the first conductive layer on the wafer.

該方法更包含在第一沉積腔室701中將介電層沉積於第一導電層上。其後，該方法包含將半導體晶圓置於第二沉積腔室702中、並在第二沉積腔室702中將第二導電層沉積於介電層上。The method further includes depositing a dielectric layer on the first conductive layer in the first deposition chamber 701 . Thereafter, the method includes placing the semiconductor wafer in the second deposition chamber 702 and depositing a second conductive layer on the dielectric layer in the second deposition chamber 702 .

該方法更包含將半導體晶圓置於電場退火裝置的處理腔室703內。一旦在處理腔室703中，該方法便包含藉由將第一導電層耦合到第一電位、及將第二導電層耦合到第二電位而將電偏壓施加在介電層範圍內；及在施加電偏壓時將半導體晶圓退火。The method further includes placing the semiconductor wafer in the processing chamber 703 of the electric field annealing apparatus. Once in the processing chamber 703, the method includes applying an electrical bias across the dielectric layer by coupling the first conductive layer to a first potential, and coupling the second conductive layer to a second potential; and The semiconductor wafer is annealed while an electrical bias is applied.

根據一實施例，施加電偏壓包含將時變電壓施加在介電層範圍內。根據一實施例，退火包含將半導體晶圓的溫度從第一溫度勻變至第二溫度。在一範例中，第二溫度大於第一溫度。在另一範例中，第一溫度大於第二溫度。According to an embodiment, applying the electrical bias includes applying a time-varying voltage within the dielectric layer. According to one embodiment, the annealing includes ramping the temperature of the semiconductor wafer from a first temperature to a second temperature. In one example, the second temperature is greater than the first temperature. In another example, the first temperature is greater than the second temperature.

根據一實施例，退火包含在第一時段期間將半導體晶圓的溫度從第一溫度勻變至第二溫度，且此後在第二時段期間將半導體晶圓的溫度至少實質上維持在第二溫度，其中第二溫度大於第一溫度。According to an embodiment, the annealing includes ramping the temperature of the semiconductor wafer from a first temperature to a second temperature during a first period of time, and thereafter maintaining the temperature of the semiconductor wafer at least substantially at the second temperature during a second period of time , where the second temperature is greater than the first temperature.

根據一實施例，退火包含在第一時段期間將半導體晶圓的溫度至少實質上維持在第一溫度，且此後在第二時段期間將半導體晶圓的溫度從第一溫度勻變至第二溫度，其中第一溫度大於第二溫度。According to an embodiment, the annealing includes maintaining the temperature of the semiconductor wafer at least substantially at a first temperature during a first period of time, and thereafter ramping the temperature of the semiconductor wafer from the first temperature to a second temperature during a second period of time , where the first temperature is greater than the second temperature.

根據一實施例，將第一導電層耦合至第一電位包含將第一電極附接至半導體晶圓的第一主要表面，且將第二導電層耦合至第二電位包含將半導體晶圓之第二主要表面置於基板夾持具上、並將基板夾持具耦合至第二電位。According to an embodiment, coupling the first conductive layer to the first potential includes attaching the first electrode to the first major surface of the semiconductor wafer, and coupling the second conductive layer to the second potential includes attaching the first electrode to the first major surface of the semiconductor wafer. Two major surfaces are placed on the substrate holder and couple the substrate holder to a second potential.

根據一實施例，將第一導電層耦合至第一電位包含將第一電極附接至半導體晶圓的第一主要表面，且其中將第二導電層耦合至第二電位包含將第二電極附接至半導體晶圓的第二主要表面。According to an embodiment, coupling the first conductive layer to the first potential includes attaching the first electrode to the first major surface of the semiconductor wafer, and wherein coupling the second conductive layer to the second potential includes attaching the second electrode to the first major surface of the semiconductor wafer. connected to the second major surface of the semiconductor wafer.

時變電壓波形可包含脈波DC、交流脈波、正弦波、鋸齒波等。時變電壓波形的非限制性範例示於圖8A-8C中。圖8A顯示正弦電壓波形801與恆定晶圓溫度802的組合。The time-varying voltage waveform may include DC pulse, AC pulse, sine wave, sawtooth wave, and the like. Non-limiting examples of time-varying voltage waveforms are shown in Figures 8A-8C. FIG. 8A shows a sinusoidal voltage waveform 801 in combination with a constant wafer temperature 802 .

圖8B顯示脈衝電壓波形811與晶圓溫度812的組合，該晶圓溫度812在第一時段期間從第一溫度勻變至第二溫度，且此後在第二時段期間，晶圓溫度至少實質上維持在第二溫度，其中第二溫度大於第一溫度。根據另一實施例，在第一時段期間，晶圓溫度可至少實質上維持在第一溫度，且此後在第二時段期間使晶圓溫度從第一溫度勻變至第二溫度，其中第一溫度大於第二溫度。8B shows the combination of a pulsed voltage waveform 811 and a wafer temperature 812 ramped from a first temperature to a second temperature during a first period of time, and thereafter during a second period of time the wafer temperature is at least substantially maintained at a second temperature, wherein the second temperature is greater than the first temperature. According to another embodiment, during a first period of time, the temperature of the wafer may be maintained at least substantially at the first temperature, and thereafter the temperature of the wafer is ramped from the first temperature to a second temperature during a second period of time, wherein the first The temperature is greater than the second temperature.

圖8C顯示鋸齒波形821與晶圓溫度822的組合，該晶圓溫度822在第一時段期間至少實質上維持在第一溫度，且此後在第二時段期間使晶圓溫度從第一溫度勻變至第二溫度，其中第一溫度大於第二溫度。根據另一實施例，在第一時段期間，晶圓溫度可從第一溫度勻變至第二溫度，且此後在第二時段期間使晶圓溫度至少實質上維持在第二溫度，其中第二溫度大於第一溫度。8C shows a combination of a sawtooth waveform 821 and a wafer temperature 822 maintained at least substantially at a first temperature during a first period of time and thereafter ramping the wafer temperature from the first temperature during a second period of time. to a second temperature, wherein the first temperature is greater than the second temperature. According to another embodiment, the wafer temperature may be ramped from a first temperature to a second temperature during a first period of time, and thereafter maintained at least substantially at the second temperature during a second period of time, wherein the second The temperature is greater than the first temperature.

儘管本發明已參考說明性實施例進行描述，但此描述並非意圖以限制性方式加以解讀。在參照描述內容時，說明性實施例的諸多修飾與組合、以及本發明的其他實施例對本領域技術人員來說將顯而易見。因此，欲使所附申請專利範圍涵蓋任何如此修飾或實施例。While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Many modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

10:基板夾持具 12:摻雜半導體區域 14:基板夾持具 15:埋入式氧化物層 20:半導體基板 21:第一半導體區域 22:第二半導體區域 25:淺溝槽絕緣區域 30:MOS介電層 35:鐵電介電層 40:導電頂部電極層 45:導電底部電極層 50:半導體晶圓 108:第一導電匯流排 109:第二導電匯流排 100:裝載軌道 110:主要線 112:監測線 113:次要線 114:次要線 115:兩線 120:電源饋孔 130:DC電源 140:接地線 150:電壓計 210:第一E場退火裝置電極 211:主要電極 212:監測電極 214:次要電極 215:主要電極 216:次要電極 225:處理腔室 226:處理腔室 230:支撐板 235:熱處理系統 236:熱處理系統 240:緩衝晶圓 250:絕緣陶瓷突出部 310:絕緣導電線 700:製造平台 701:第一沉積腔室 702:第二沉積腔室 703:處理腔室 704:清洗腔室 705:晶圓傳送系統 801:正弦電壓波形 802:恆定晶圓溫度 811:脈衝電壓波形 812:晶圓溫度 821:鋸齒波形 822:晶圓溫度 B1:區域 C:箭頭 C1:區域 D1:區域 10: Substrate holder 12: Doped semiconductor region 14: Substrate holder 15: Buried oxide layer 20: Semiconductor substrate 21: The first semiconductor region 22: Second semiconductor region 25:Shallow trench isolation region 30:MOS dielectric layer 35: ferroelectric dielectric layer 40: Conductive top electrode layer 45: Conductive Bottom Electrode Layer 50: Semiconductor wafer 108: the first conductive bus bar 109: the second conductive bus bar 100: Loading track 110: main line 112: Monitoring line 113: Secondary line 114: Secondary line 115: two lines 120: Power feed hole 130:DC power supply 140: Ground wire 150: Voltmeter 210: Electrode of the first E-field annealing device 211: Main electrode 212: Monitoring electrode 214: Secondary electrode 215: Main electrode 216: Secondary electrode 225: processing chamber 226: processing chamber 230: support plate 235: Heat treatment system 236: Heat treatment system 240: buffer wafer 250: insulating ceramic protrusion 310: insulated conductive wire 700: Manufacturing platform 701: first deposition chamber 702: second deposition chamber 703: processing chamber 704: cleaning chamber 705:Wafer transfer system 801: Sinusoidal voltage waveform 802: Constant Wafer Temperature 811: Pulse voltage waveform 812: wafer temperature 821: sawtooth waveform 822: wafer temperature B1: area C: arrow C1: area D1: area

為了更完整地理解本發明及其優點，現參考以下敘述結合隨附圖式進行說明，其中：For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

圖1A根據本發明之實施例顯示電場退火裝置之處理腔室的剖面圖；1A shows a cross-sectional view of a processing chamber of an electric field annealing device according to an embodiment of the present invention;

圖1B根據本發明之替代實施例顯示電場退火裝置之處理腔室的剖面圖；1B shows a cross-sectional view of a processing chamber of an electric field annealing apparatus according to an alternative embodiment of the present invention;

圖2根據本發明之實施例顯示電場退火裝置之裝載軌道的立體圖；2 shows a perspective view of a loading track of an electric field annealing device according to an embodiment of the present invention;

圖3為圖2所示之立體圖之細部的放大立體圖；Figure 3 is an enlarged perspective view of the details of the perspective view shown in Figure 2;

圖4根據本發明之實施例顯示電場退火裝置之裝載軌道的立體圖；4 shows a perspective view of a loading track of an electric field annealing device according to an embodiment of the present invention;

圖5A為圖2所示之立體圖之細部的放大立體圖；Figure 5A is an enlarged perspective view of the details of the perspective view shown in Figure 2;

圖5B為圖2所示之立體圖之細部從不同定向的放大立體圖；Figure 5B is an enlarged perspective view of the details of the perspective view shown in Figure 2 from different orientations;

圖6A-6C根據本發明之實施例顯示置於電場退火裝置之處理腔室中之諸多半導體晶圓的剖面圖；6A-6C show cross-sectional views of a plurality of semiconductor wafers placed in a processing chamber of an electric field annealing apparatus according to an embodiment of the present invention;

圖7根據本發明之實施例顯示製造半導體裝置之製造平台。FIG. 7 shows a fabrication platform for fabricating a semiconductor device according to an embodiment of the present invention.

圖8A-8C根據本發明之實施例顯示在半導體晶圓退火時將電偏壓施加在介電層範圍內。8A-8C illustrate the application of an electrical bias across a dielectric layer during annealing of a semiconductor wafer in accordance with an embodiment of the present invention.

700:製造平台 700: Manufacturing platform

701:第一沉積腔室 701: first deposition chamber

702:第二沉積腔室 702: second deposition chamber

703:處理腔室 703: processing chamber

704:清洗腔室 704: cleaning chamber

705:晶圓傳送系統 705:Wafer transfer system

Claims (20)

一種製造半導體裝置的方法，該方法包含： 將半導體晶圓置於製造平台之第一沉積腔室中，該半導體晶圓包含第一導電層； 在該第一沉積腔室中將介電層沉積於第一導電層上； 將半導體晶圓置於該製造平台之第二沉積腔室中； 在該第二沉積腔室中將第二導電層沉積於該介電層上； 將半導體晶圓置於該製造平台之電場退火裝置的處理腔室中； 在該處理腔室中，藉由將該第一導電層耦合至第一電位、且將該第二導電層耦合至第二電位，而將電偏壓施加在該介電層的範圍內；及 施加該電偏壓時將該半導體晶圓退火。 A method of manufacturing a semiconductor device, the method comprising: placing a semiconductor wafer in a first deposition chamber of a fabrication platform, the semiconductor wafer comprising a first conductive layer; depositing a dielectric layer on the first conductive layer in the first deposition chamber; placing a semiconductor wafer in a second deposition chamber of the fabrication platform; depositing a second conductive layer on the dielectric layer in the second deposition chamber; placing the semiconductor wafer in the processing chamber of the electric field annealing device of the manufacturing platform; applying an electrical bias across the dielectric layer in the processing chamber by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and The semiconductor wafer is annealed while the electrical bias is applied. 如請求項1之製造半導體裝置的方法，其中施加該電偏壓包含將時變電壓波形施加在該介電層的範圍內。The method of manufacturing a semiconductor device according to claim 1, wherein applying the electrical bias comprises applying a time-varying voltage waveform within the range of the dielectric layer. 如請求項2之製造半導體裝置的方法，其中該時變電壓波形包含脈波DC、交流脈波、正弦波、或鋸齒波。The method of manufacturing a semiconductor device according to claim 2, wherein the time-varying voltage waveform includes pulse DC, AC pulse, sine wave, or sawtooth wave. 如請求項1之製造半導體裝置的方法，其中該退火包含將該半導體晶圓之該溫度從第一溫度勻變至第二溫度。The method for manufacturing a semiconductor device according to claim 1, wherein the annealing includes ramping the temperature of the semiconductor wafer from a first temperature to a second temperature. 如請求項4之製造半導體裝置的方法，其中該第二溫度大於該第一溫度。The method of manufacturing a semiconductor device as claimed in claim 4, wherein the second temperature is greater than the first temperature. 如請求項4之製造半導體裝置的方法，其中該第一溫度大於該第二溫度。The method of manufacturing a semiconductor device as claimed in claim 4, wherein the first temperature is greater than the second temperature. 如請求項1之製造半導體裝置的方法，其中該退火包含在第一時段期間將該半導體晶圓的該溫度從第一溫度勻變至第二溫度，且此後在第二時段期間將該半導體晶圓的該溫度至少實質上維持在該第二溫度，其中該第二溫度大於該第一溫度。The method of manufacturing a semiconductor device as claimed in claim 1, wherein the annealing includes ramping the temperature of the semiconductor wafer from a first temperature to a second temperature during a first period of time, and thereafter during a second period of time the semiconductor wafer The temperature of the circle is at least substantially maintained at the second temperature, wherein the second temperature is greater than the first temperature. 如請求項1之製造半導體裝置的方法，其中該介電層包含鉿氧化物。The method of manufacturing a semiconductor device as claimed in claim 1, wherein the dielectric layer comprises hafnium oxide. 如請求項1之製造半導體裝置的方法，其中該退火包含在第一時段期間將該半導體晶圓之該溫度至少實質上維持在第一溫度，且此後在第二時段期間將該半導體晶圓之該溫度從該第一溫度勻變至第二溫度，其中該第一溫度大於該第二溫度。The method of manufacturing a semiconductor device as claimed in claim 1, wherein the annealing includes maintaining the temperature of the semiconductor wafer at least substantially at the first temperature during a first period of time, and thereafter maintaining the temperature of the semiconductor wafer during a second period of time The temperature ramps from the first temperature to a second temperature, wherein the first temperature is greater than the second temperature. 如請求項1之製造半導體裝置的方法，其中將該第一導電層耦合至該第一電位包含將第一電極附接至該半導體晶圓之第一主要表面，且其中將該第二導電層耦合至該第二電位包含將該半導體晶圓之第二主要表面置於基板夾持具上、並將該基板夾持具耦合至該第二電位。The method of manufacturing a semiconductor device as claimed in claim 1, wherein coupling the first conductive layer to the first potential comprises attaching a first electrode to the first major surface of the semiconductor wafer, and wherein the second conductive layer Coupling to the second potential includes placing the second major surface of the semiconductor wafer on a substrate holder, and coupling the substrate holder to the second potential. 如請求項1之製造半導體裝置的方法，其中將該第一導電層耦合至該第一電位包含將第一電極附接至該半導體晶圓之第一主要表面，且其中將該第二導電層耦合至該第二電位包含將第二電極附接至該半導體晶圓之第二主要表面。The method of manufacturing a semiconductor device as claimed in claim 1, wherein coupling the first conductive layer to the first potential comprises attaching a first electrode to the first major surface of the semiconductor wafer, and wherein the second conductive layer Coupling to the second potential includes attaching a second electrode to the second major surface of the semiconductor wafer. 一種製造半導體裝置的製造平台，該製造平台包含： 第一沉積腔室，配置成在半導體晶圓上沉積導電層； 第二沉積腔室，配置成在該半導體晶圓上沉積介電層；及 電場退火裝置的處理腔室，該處理腔室包含： 基板夾持具，配置成支撐該半導體晶圓； 加熱元件，配置成加熱藉由該基板夾持具支撐之該半導體晶圓； 第一電極，配置成可分離地附接至該半導體晶圓之第一主要表面；及 第一線，其將該第一電極耦合至第一電位節點。 A manufacturing platform for manufacturing semiconductor devices, the manufacturing platform comprising: a first deposition chamber configured to deposit a conductive layer on a semiconductor wafer; a second deposition chamber configured to deposit a dielectric layer on the semiconductor wafer; and A processing chamber of an electric field annealing device, the processing chamber includes: a substrate holder configured to support the semiconductor wafer; a heating element configured to heat the semiconductor wafer supported by the substrate holder; a first electrode configured to be detachably attached to the first major surface of the semiconductor wafer; and a first line coupling the first electrode to a first potential node. 如請求項12之製造半導體裝置的製造平台，其中該電場退火裝置之該處理腔室更包含： 第二電極，其耦合至該基板夾持具；及 第二線，其將該第二電極耦合至第二電位節點。 The manufacturing platform for manufacturing semiconductor devices according to claim 12, wherein the processing chamber of the electric field annealing device further includes: a second electrode coupled to the substrate holder; and a second line coupling the second electrode to a second potential node. 如請求項13之製造半導體裝置的製造平台，其中該電場退火裝置之該處理腔室更包含： 第三電極，配置成可分離地附接至該半導體晶圓的該第一主要表面； 電壓監測計；及 第三線，其將該第三電極耦合至電壓監測計。 The manufacturing platform for manufacturing semiconductor devices according to claim 13, wherein the processing chamber of the electric field annealing device further includes: a third electrode configured to be detachably attached to the first major surface of the semiconductor wafer; voltage monitors; and A third wire that couples the third electrode to a voltage monitor. 如請求項12之製造半導體裝置的製造平台，其中該電場退火裝置之該處理腔室更包含： 第二電極，配置成可分離地附接至該半導體晶圓之第二主要表面；及 第二線，其將該第二電極耦合至第二電位節點。 The manufacturing platform for manufacturing semiconductor devices according to claim 12, wherein the processing chamber of the electric field annealing device further includes: a second electrode configured to be detachably attached to the second major surface of the semiconductor wafer; and a second line coupling the second electrode to a second potential node. 如請求項12之製造半導體裝置的製造平台，其中該電場退火裝置之該處理腔室更包含： 電源，其耦合至該第一電位節點。 The manufacturing platform for manufacturing semiconductor devices according to claim 12, wherein the processing chamber of the electric field annealing device further includes: a power supply coupled to the first potential node. 如請求項16之製造半導體裝置的製造平台，其中該電源係配置用於將電偏壓施加在該介電層的範圍內。The manufacturing platform for manufacturing a semiconductor device as claimed in claim 16, wherein the power supply is configured to apply an electrical bias voltage within the range of the dielectric layer. 如請求項17之製造半導體裝置的製造平台，其中該電偏壓包含時變電壓波形。The manufacturing platform for manufacturing semiconductor devices as claimed in claim 17, wherein the electrical bias comprises a time-varying voltage waveform. 如請求項16之製造半導體裝置的製造平台，其中該電源係配置用於在該加熱元件施加熱至該半導體晶圓時將電偏壓施加於該介電層的範圍內。The manufacturing platform for manufacturing a semiconductor device as claimed in claim 16, wherein the power supply is configured to apply an electrical bias within the range of the dielectric layer when the heating element applies heat to the semiconductor wafer. 如請求項19之製造半導體裝置的製造平台，其中該加熱元件使該半導體晶圓的溫度從第一溫度勻變至第二溫度。The manufacturing platform for manufacturing semiconductor devices as claimed in claim 19, wherein the heating element ramps the temperature of the semiconductor wafer from a first temperature to a second temperature.
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