TW202311834A - Electro-optic displays with ohmically conductive storage capacitors for discharging remnant voltages - Google Patents

Electro-optic displays with ohmically conductive storage capacitors for discharging remnant voltages Download PDF

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TW202311834A
TW202311834A TW111128136A TW111128136A TW202311834A TW 202311834 A TW202311834 A TW 202311834A TW 111128136 A TW111128136 A TW 111128136A TW 111128136 A TW111128136 A TW 111128136A TW 202311834 A TW202311834 A TW 202311834A
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display
electrophoretic
tft
fpl
pixel
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皮爾依夫 艾密力
德平 辛
肯尼士 R 柯羅斯
卡爾瑞蒙 艾孟森
何志祥
亞倫 陳
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美商電子墨水股份有限公司
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16766—Electrodes for active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/068—Application of pulses of alternating polarity prior to the drive pulse in electrophoretic displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

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  • Optics & Photonics (AREA)
  • Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
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Abstract

An electrophoretic display having a plurality of display pixels, each of the plurality of display pixels may include a pixel electrode for driving the display pixel, a single thin film transistor (TFT) coupled to the pixel electrode for transmitting waveforms to the pixel electrode, a front plane laminate (FPL) coupled to the single thin film transistor, and a storage capacitor coupled to the pixel electrode and placed in parallel with the FPL, where the storage capacitor is configured to be sufficiently ohmically conductive to allow the discharge of remnant voltages from the FPL through the storage capacitor.

Description

具有用於釋放殘留電壓之歐姆導電儲存電容器的電光顯示器Electro-optic displays with ohmic conductive storage capacitors for discharging residual voltage

[相關申請案的參考資料][References for related applications]

本申請案請求2021年7月29日提出且於2021年11月18日公開為美國專利公開第2021/0358424號之美國專利申請案第17/388,417號的優先權。This application claims priority to US Patent Application Serial No. 17/388,417, filed July 29, 2021 and published November 18, 2021 as US Patent Publication No. 2021/0358424.

美國專利申請案第17/388,417號與請求2017年5月30日提出的美國臨時專利申請案第62/512,212號的優先權之2000年9月25日提出的美國專利申請案第17/032,189號(現為美國專利第11,107,425號)、2020年1月17日提出的美國專利申請案第16/745,473號(現為美國專利第10,825,405號)以及2018年5月30日提出的美國專利申請案第15/992,363號(現為美國專利第10,573,257號)相關。本申請案亦與2016年2月4日提出的美國專利申請案第15/015,822號(現為美國專利第10,163,406號)；2016年2月3日提出的美國專利申請案第15/014,236號(現為美國專利第10,475,396號)；以及2016年9月15日提出的美國專利申請案第15/266,554號(現為美國專利第10,803,813號)相關。U.S. Patent Application No. 17/388,417 and U.S. Patent Application No. 17/032,189, filed September 25, 2000, claiming priority to U.S. Provisional Patent Application No. 62/512,212, filed May 30, 2017 (now U.S. Patent No. 11,107,425), U.S. Patent Application No. 16/745,473, filed January 17, 2020 (now U.S. Patent No. 10,825,405), and U.S. Patent Application No. 15/992,363 (now US Patent No. 10,573,257) related. This application is also related to U.S. Patent Application No. 15/015,822, filed February 4, 2016 (now U.S. Patent No. 10,163,406); U.S. Patent Application No. 15/014,236, filed February 3, 2016 ( now U.S. Patent No. 10,475,396); and U.S. Patent Application No. 15/266,554, filed September 15, 2016 (now U.S. Patent No. 10,803,813).

將所有以上列出的專利及申請案的全部以參照方式併入本文。All patents and applications listed above are hereby incorporated by reference in their entirety.

本文所揭露之標的物係有關於驅動電光顯示器的手段及方法。具體地，標的物係有關於用於電光顯示器的背板設計以及用於對這樣的顯示器進行驅動及/或放電之方法。The subject matter disclosed in this paper relates to means and methods for driving electro-optic displays. In particular, the subject matter relates to backplane designs for electro-optic displays and methods for driving and/or discharging such displays.

電泳顯示器或EPD通常由所謂的直流平衡波形驅動。直流平衡波形已被證實可以藉由減少嚴重的硬體退化及消除其它可靠性問題來改善EPD的長期使用。然而，直流平衡波形約束限制了可用於驅動EPD顯示器之一組可能的波形，使得透過波形模式實施有利功能變得困難或有時是不可能的。例如，當實施「無閃爍」的黑底白字顯示模式時，過多的白色邊緣累積在已轉變為黑色的灰調靠近不閃爍的黑色背景時可能變成是看得見的。為了清除這樣的邊緣，直流不平衡驅動方案可能很有效，但是這樣的驅動方案需要打破直流平衡約束。然而，直流不平衡驅動方案或波形會隨著時間的推移導致硬體退化，從而縮短顯示裝置的使用壽命。因此，需要設計能夠以直流不平衡波形或驅動方案操作而不會遭受硬體退化的電光顯示器。Electrophoretic displays, or EPDs, are typically driven by what is known as a DC balanced waveform. DC balanced waveforms have been shown to improve the long-term use of EPDs by reducing severe hardware degradation and eliminating other reliability issues. However, DC-balanced waveform constraints limit the set of possible waveforms that can be used to drive an EPD display, making it difficult or sometimes impossible to implement advantageous functions through waveform patterns. For example, when implementing a "flicker-free" white-on-black display mode, excessive white fringing buildup may become visible when gray tones that have been converted to black are close to a non-flickering black background. To clear such edges, a DC unbalanced drive scheme may be effective, but such a drive scheme needs to break the DC balance constraint. However, DC unbalanced drive schemes or waveforms can cause hardware degradation over time, thereby shortening the lifespan of the display device. Therefore, there is a need to design electro-optic displays that can operate with DC unbalanced waveforms or drive schemes without suffering from hardware degradation.

依據本文提出之標的物的一個實施例，一種電泳顯示器具有複數個顯示像素，該複數個顯示像素中的每一者可以包括：一像素電極，用於驅動該顯示像素；一單個薄膜電晶體(TFT)，其耦接至該像素電極，用於傳送波形至該像素電極；一前平面積層板(FPL)，其耦接至該單個薄膜電晶體；以及一儲存電容器，其耦接至該像素電極且與該FPL並聯放置，其中該儲存電容器係構造成具有足夠的歐姆導電性以允許從該FPL經由該儲存電容器進行殘留電壓放電。According to an embodiment of the subject matter presented herein, an electrophoretic display has a plurality of display pixels, each of the plurality of display pixels may include: a pixel electrode for driving the display pixel; a single thin film transistor ( TFT), which is coupled to the pixel electrode, for transmitting a waveform to the pixel electrode; a front plane laminate (FPL), which is coupled to the single thin film transistor; and a storage capacitor, which is coupled to the pixel electrode and placed in parallel with the FPL, wherein the storage capacitor is configured to have sufficient ohmic conductivity to allow residual voltage discharge from the FPL via the storage capacitor.

在一些其它實施例中，該儲存電容器的電阻與該FPL的電阻大致相同。In some other embodiments, the storage capacitor has approximately the same resistance as the FPL.

在一些其它實施例中，該儲存電容器的電阻值介於該FPL的電阻之三分之一與三倍之間。In some other embodiments, the resistance of the storage capacitor is between one-third and three times the resistance of the FPL.

在又另一個實施例中，該電泳顯示器可以進一步包括與該儲存電容器並聯的一放電電容器。In yet another embodiment, the electrophoretic display may further include a discharge capacitor connected in parallel with the storage capacitor.

本文揭露之標的物係有關於提高電光顯示器的耐用性。具體地，它係有關於改善光學性能變化，例如，減輕由組件應力引起的灰調偏移(gray-tone shifts)及重影偏移。The subject matter disclosed herein is related to improving the durability of electro-optic displays. In particular, it is related to improving optical performance variations, for example, mitigating gray-tone shifts and ghost shifts caused by component stress.

應用於材料或顯示器的術語「電光」在本文中以其成像技藝的傳統含義用於提及具有在至少一光學性質上不同的第一與第二顯示狀態之材料，所述材料可藉由對材料施加電場從第一顯示狀態變為第二顯示狀態。雖然光學性質通常是人眼可感知的顏色，但是它可以是另一種光學性質，例如，光透射、反射、發光或者在意欲用於機器讀取的顯示器之情況下，在可見光範圍之外的電磁波長之反射率變化的意義上之偽色。The term "electro-optic" as applied to materials or displays is used herein in its conventional sense in the imaging arts to refer to materials having first and second display states that differ in at least one optical property, which can be detected by applying The material applies an electric field from the first display state to the second display state. While an optical property is usually color perceived by the human eye, it can be another optical property such as light transmission, reflection, luminescence or, in the case of displays intended for machine reading, electromagnetic waves outside the visible range False color in the sense of long-term reflectance change.

術語「雙穩態(bistable)」及「雙穩性(bistability)」在本文中以該項技藝中之傳統含義用以提及顯示器包括具有在至少一光學性質方面係不同的第一及第二顯示狀態之顯示元件，以及以便在以有限持續時間之定址脈波驅動任何一給定元件後，呈現其第一或第二顯示狀態，以及在定址脈波終止後，那個狀態將持續至少數次，例如，至少4次；定址脈波需要最短持續時間來改變顯示元件之狀態。美國專利第7,170,670號顯示一些具有灰度能力之粒子系電泳顯示器不僅在其極端黑色及白色狀態中，而且在其中間灰色狀態中係穩定的，並且一些其它類型的電光顯示器亦同樣是如此。這種類型的顯示器可適當地稱為多穩態(multi-stable)而不是雙穩態，但是為了方便起見，術語「雙穩態」在此可以用以涵蓋雙穩態及多穩態顯示器。The terms "bistable" and "bistability" are used herein in the conventional sense in the art to refer to a display comprising first and second optical components that differ in at least one optical property. Display elements of display states, and such that after driving any given element with an address pulse of finite duration, it assumes its first or second display state, and that state will persist for at least a number of times after the address pulse has terminated , eg, at least 4 times; the addressing pulse requires the shortest duration to change the state of the display element. US Patent No. 7,170,670 shows that some particle-based electrophoretic displays with grayscale capability are stable not only in their extreme black and white states, but also in their intermediate gray states, and some other types of electro-optic displays as well. This type of display may properly be called multi-stable rather than bistable, but for convenience the term "bistable" may be used here to cover both bistable and multistable displays .

術語「灰色狀態」在本文中以其成像技藝中之傳統含義用於提及在像素之兩個極端光學狀態間的狀態，以及沒有必定意味著這兩個極端狀態間之黑色-白色過渡(black-white transition)。例如，下面提及的數個E Ink專利及公開申請案描述電泳顯示器，其中，極端狀態為白色及深藍色，以致於中間「灰色狀態」實際上是淺藍色。更確切地，如所述，光學狀態之變化可能根本不是顏色變化。術語「黑色」及「白色」在下面可以用以意指顯示器之兩個極端光學狀態，以及應該理解為通常包括不是嚴格的黑色及白色之極端光學狀態，例如，前述白色及深藍色狀態。術語「單色(monochrome)」在下面可以用以表示只將像素驅動至不具有中間灰色狀態之它們的兩個極端光學狀態之顯示或驅動方案。The term "gray state" is used herein in its traditional meaning in the imaging arts to refer to a state between two extreme optical states of a pixel, and does not necessarily imply a black-to-white transition between these two extreme states. -white transition). For example, several of the E Ink patents and published applications mentioned below describe electrophoretic displays in which the extreme states are white and dark blue, so that the intermediate "grey state" is actually light blue. Rather, as stated, the change in optical state may not be a color change at all. The terms "black" and "white" may be used below to refer to two extreme optical states of a display, and should be understood to generally include extreme optical states that are not strictly black and white, eg, the aforementioned white and dark blue states. The term "monochrome" may be used below to denote a display or drive scheme that drives pixels only to their two extreme optical states without a middle gray state.

術語「像素」在本文中以其顯示技藝中之傳統含義用於表示能夠產生顯示器本身可以顯示的所有顏色之顯示器的最小單元。在全彩顯示器中，通常每個像素由複數個子像素組成，每個子像素可以顯示的顏色少於顯示器本身可以顯示的所有顏色。例如，在大多數傳統的全彩顯示器中，每個像素由紅色子像素、綠色子像素、藍色子像素及可選的白色子像素組成，每個子像素能夠顯示從黑色到其指定顏色的最亮形式的一系列顏色。The term "pixel" is used herein in its conventional meaning in the display arts to refer to the smallest unit of a display capable of producing all the colors that the display itself can display. In a full-color display, each pixel is usually composed of a plurality of sub-pixels, and each sub-pixel can display fewer colors than all the colors that the display itself can display. For example, in most conventional full-color displays, each pixel consists of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and optionally a white sub-pixel, and each sub-pixel is capable of displaying the widest possible range from black to its assigned color. A range of colors in bright form.

已知數種類型的電光顯示器。一種類型的電光顯示器為像例如在美國專利第5,808,783；5,777,782；5,760,761；6,054,071；6,055,091；6,097,531；6,128,124；6,137,467；及6,147,791號中所述的旋轉雙色構件型(rotating bichromal member type)(雖然這類型的顯示器常常稱為一種「旋轉雙色球(rotating bichromal ball)」顯示器，但是術語「旋轉雙色構件」優選為更精確的，因為在上述一些專利中，旋轉構件不是球形的)。這樣的顯示器使用具有兩個或更多部分有不同光學特性的大量小物體(通常是球形的或圓柱形的)及一個內偶極。這些物體懸浮於基質內之填充有液體的液泡中，其中，該等液泡填充有液體，以便該等物體可以自由旋轉。藉由施加電場，因而使該等物體旋轉至各種位置及改變該等物體之哪個部分可經由一觀看面被看到，進而改變該顯示器之顯現。此類型的電光介質通常是雙穩態的。Several types of electro-optic displays are known. One type of electro-optic display is the rotating bichromal member type (although the type of this type) as described, for example, in U.S. Patent Nos. 5,808,783; 5,777,782; The display is often referred to as a "rotating bichromal ball" display, but the term "rotating bichromal member" is preferred to be more precise, since in some of the above patents the rotating member is not spherical). Such displays use a large number of small objects (usually spherical or cylindrical) with two or more parts having different optical properties and an internal dipole. These objects are suspended in liquid-filled vacuoles within the matrix, wherein the vacuoles are filled with liquid so that the objects can rotate freely. The appearance of the display is changed by applying electric fields, thereby rotating the objects to various positions and changing which part of the objects can be seen through a viewing surface. Electro-optic media of this type are usually bistable.

另一種類型的電光顯示器使用電致變色介質，例如，奈米變色薄膜之形式的電致變色介質，其包括一至少部分由半導體金屬氧化物所構成之電極及複數個附著至該電極之有可逆變色能力的染料分子；參見例如O'Regan, B., et al., Nature 1991, 353, 737；以及Wood, D., Information Display, 18(3), 24(March 2002)。亦參見Bach, U., et al., Adv. Mater., 2002, 14(11), 845。這種類型之奈米變色薄膜亦被描述於例如美國專利第6,301,038；6,870,657；及6,950,220中。這種類型之介質通常亦是雙穩態的。Another type of electro-optic display uses an electrochromic medium, for example in the form of a nanochromic film comprising an electrode at least partially composed of a semiconducting metal oxide and a plurality of reversible electrodes attached to the electrode. Dye molecules with color changing capabilities; see eg O'Regan, B., et al., Nature 1991, 353, 737; and Wood, D., Information Display, 18(3), 24 (March 2002). See also Bach, U., et al., Adv. Mater., 2002, 14(11), 845. Nanochromic films of this type are also described, for example, in US Patent Nos. 6,301,038; 6,870,657; and 6,950,220. Media of this type are also usually bistable.

另一種類型的電光顯示器為由Philips所發展出來的電潤濕顯示器(electro-wetting display)且被描述於Hayes, R.A., et al., “Video-Speed Electronic Paper Based on Electrowetting”, Nature, 425, 383-385(2003)中。美國專利第7,420,549號顯示這樣的電潤濕顯示器可製成雙穩態的。Another type of electro-optic display is the electro-wetting display developed by Philips and described in Hayes, R.A., et al., "Video-Speed Electronic Paper Based on Electrowetting", Nature, 425, 383-385 (2003). US Patent No. 7,420,549 shows that such an electrowetting display can be made bistable.

一種類型的電光顯示器數年來已成為密集研發的主題，它是粒子系電泳顯示器，其中，複數個帶電粒子在電場之影響下經由流體移動。當相較於液晶顯示器時，電泳顯示器可具有良好的亮度及對比、寬視角、狀態雙穩定性及低功率耗損之屬性。One type of electro-optic display that has been the subject of intensive research and development for several years is the particle-based electrophoretic display, in which a plurality of charged particles is moved through a fluid under the influence of an electric field. When compared to liquid crystal displays, electrophoretic displays may have the attributes of good brightness and contrast, wide viewing angles, state bistability, and low power consumption.

如上所述，電泳介質需要流體之存在。在大部分習知技藝電泳介質中，此流體係液體，但是可使用氣體流體來生產該電泳介質；參見例如，Kitamura, T., et al., Electrical toner movement for electronic paper-like display, IDW Japan, 2001, Paper HCS1-1以及Yamaguchi, Y., et al., Toner display using insulative particles charged triboelectrically, IDW Japan, 2001, Paper AMD4-4。亦參見美國專利第7,321,459及7,236,291號。當在一允許粒子沉降之方位上(例如，在垂直平面中配置介質之表現中)使用該等介質時，這樣的氣體系電泳介質似乎易受相同於液體系電泳介質之因粒子沉降所造成之類型的問題所影響。更確切地，粒子沉降似乎在氣體系電泳介質中比在液體系電泳介質中更是嚴重問題，因為相較於液體懸浮流體，氣體懸浮流體之較低黏性允許該等電泳粒子之更快速沉降。As mentioned above, the electrophoretic medium requires the presence of a fluid. In most prior art electrophoretic media, this fluid is a liquid, but gaseous fluids can be used to produce the electrophoretic media; see, e.g., Kitamura, T., et al., Electrical toner movement for electronic paper-like display, IDW Japan , 2001, Paper HCS1-1 and Yamaguchi, Y., et al., Toner display using insulating particles charged triboelectrically, IDW Japan, 2001, Paper AMD4-4. See also US Patent Nos. 7,321,459 and 7,236,291. Such gas-based electrophoretic media appear to be susceptible to the same problems as liquid-based electrophoretic media due to particle settling when the media are used in an orientation that allows particle sedimentation (e.g., in a representation in which the media is arranged in a vertical plane). types of problems. Rather, particle settling appears to be a more serious problem in gas-based electrophoretic media than in liquid-based electrophoretic media, since the lower viscosity of gas-suspended fluids allows for faster settling of the electrophoretic particles compared to liquid-based suspending fluids. .

讓渡給Massachusetts Institute of Technology (MIT)及E Ink Corporation或在它們的名義下之許多專利及申請案描述在膠囊化電泳及其它電光介質方面所使用之各種技術。這樣的膠囊化介質包括許多小膠囊，每個膠囊本身包括一包含在一流體介質中之電泳移動粒子的內相(internal phase)及一包圍該內相之膠囊壁。通常，該等膠囊本身係保持於一高分子黏結劑中，以形成一位於兩個電極間之黏著層(coherent layer)。在這些專利及申請案中所述之技術包括： (a)電泳粒子、流體及流體添加劑；參見例如美國專利第7,002,728及7,679,814號； (b)膠囊、黏結劑及膠囊化製程；參見例如美國專利第6,922,276及7,411,719號； (c)包含電光材料之薄膜及次總成(sub-assemblies)；參見例如美國專利第6,982,178及7,839,564號； (d)在顯示器中所使用之背板、黏著層及其它輔助層以及方法；參見例如美國專利第D485,294；6,124,851；6,130,773；6,177,921；6,232,950；6,252,564；6,312,304；6,312,971；6,376,828；6,392,786；6,413,790；6,422,687；6,445,374；6,480,182；6,498,114；6,506,438；6,518,949；6,521,489；6,535,197；6,545,291；6,639,578；6,657,772；6,664,944；6,680,725；6,683,333；6,724,519；6,750,473；6,816,147；6,819,471；6,825,068；6,831,769；6,842,167；6,842,279；6,842,657；6,865,010；6,873,452；6,909,532；6,967,640；6,980,196；7,012,735；7,030,412；7,075,703；7,106,296；7,110,163；7,116,318；7,148,128；7,167,155；7,173,752；7,176,880；7,190,008；7,206,119；7,223,672；7,230,751；7,256,766；7,259,744；7,280,094；7,301,693；7,304,780；7,327,511；7,347,957；7,349,148；7,352,353；7,365,394；7,365,733；7,382,363；7,388,572；7,401,758；7,442,587；7,492,497；7,535,624；7,551,346；7,554,712；7,583,427；7,598,173；7,605,799；7,636,191；7,649,674；7,667,886；7,672,040；7,688,497；7,733,335；7,785,988；7,830,592；7,843,626；7,859,637；7,880,958；7,893,435；7,898,717；7,905,977；7,957,053；7,986,450；8,009,344；8,027,081；8,049,947；8,072,675；8,077,141；8,089,453；8,120,836；8,159,636；8,208,193；8,237,892；8,238,021；8,362,488；8,373,211；8,389,381；8,395,836；8,437,069；8,441,414；8,456,589；8,498,042；8,514,168；8,547,628；8,576,162；8,610,988；8,714,780；8,728,266；8,743,077；8,754,859；8,797,258；8,797,633；8,797,636；8,830,560；8,891,155；8,969,886；9,147,364；9,025,234；9,025,238；9,030,374；9,140,952；9,152,003；9,152,004；9,201,279；9,223,164；9,285,648；及9,310,661號；以及美國專利申請案公開第2002/0060321；2004/0008179；2004/0085619；2004/0105036；2004/0112525；2005/0122306；2005/0122563；2006/0215106；2006/0255322；2007/0052757；2007/0097489；2007/0109219；2008/0061300；2008/0149271；2009/0122389；2009/0315044；2010/0177396；2011/0140744；2011/0187683；2011/0187689；2011/0292319；2013/0250397；2013/0278900；2014/0078024；2014/0139501；2014/0192000；2014/0210701；2014/0300837；2014/0368753；2014/0376164；2015/0171112；2015/0205178；2015/0226986；2015/0227018；2015/0228666；2015/0261057；2015/0356927；2015/0378235；2016/077375；2016/0103380；及2016/0187759號；以及國際申請案公開第WO 00/38000號；歐洲專利第1,099,207 B1及1,145,072 B1號； (e)顏色形成及顏色調整；參見例如美國專利第6,017,584；6,664,944；6,864,875；7,075,502；7,167,155；7,667,684；7,791,789；7,956,841；8,040,594；8,054,526；8,098,418；8,213,076；及8,363,299號；以及美國專利申請案公開第2004/0263947；2007/0109219；2007/0223079；2008/0023332；2008/0043318；2008/0048970；2009/0004442；2009/0225398；2010/0103502；2010/0156780；2011/0164307；2011/0195629；2011/0310461；2012/0008188；2012/0019898；2012/0075687；2012/0081779；2012/0134009；2012/0182597；2012/0212462；2012/0157269；及2012/0326957號； (f)用於驅動顯示器的方法；參見例如美國專利第7,012,600和7,453,445號； (g)顯示器之應用；參見例如，美國專利第7,312,784及8,009,348號； (h)非電泳顯示器，其如美國專利第6,241,921；6,950,220；7,420,549及8,319,759號；以及美國專利申請案公開第2012/0293858號； (i)微胞結構、壁材及形成微胞的方法；參見例如美國專利第7,072,095及9,279,906號； (j)用於填充及密封微胞的方法；參見例如美國專利第7,144,942及7,715,088號。 Numerous patents and applications assigned to or in the name of the Massachusetts Institute of Technology (MIT) and E Ink Corporation describe various techniques used in encapsulated electrophoresis and other electro-optic media. Such an encapsulating medium comprises a number of small capsules, each capsule itself comprising an internal phase of electrophoretically mobile particles contained in a fluid medium and a capsule wall surrounding the internal phase. Typically, the capsules themselves are held in a polymeric binder to form a coherent layer between the two electrodes. Technologies described in these patents and applications include: (a) Electrophoretic particles, fluids and fluid additives; see, eg, US Patent Nos. 7,002,728 and 7,679,814; (b) Capsules, binders and encapsulation processes; see for example US Patent Nos. 6,922,276 and 7,411,719; (c) Films and sub-assemblies comprising electro-optic materials; see, for example, US Patent Nos. 6,982,178 and 7,839,564; (d) Backplanes, adhesive layers, and other auxiliary layers and methods used in displays; see, for example, U.S. Patent Nos. D485,294; 6,124,851; 6,130,773; 6,177,921; 6,422,687；6,445,374；6,480,182；6,498,114；6,506,438；6,518,949；6,521,489；6,535,197；6,545,291；6,639,578；6,657,772；6,664,944；6,680,725；6,683,333；6,724,519；6,750,473；6,816,147；6,819,471；6,825,068；6,831,769；6,842,167；6,842,279；6,842,657；6,865,010；6,873,452； 6,909,532；6,967,640；6,980,196；7,012,735；7,030,412；7,075,703；7,106,296；7,110,163；7,116,318；7,148,128；7,167,155；7,173,752；7,176,880；7,190,008；7,206,119；7,223,672；7,230,751；7,256,766；7,259,744；7,280,094；7,301,693；7,304,780；7,327,511；7,347,957；7,349,148； 7,352,353；7,365,394；7,365,733；7,382,363；7,388,572；7,401,758；7,442,587；7,492,497；7,535,624；7,551,346；7,554,712；7,583,427；7,598,173；7,605,799；7,636,191；7,649,674；7,667,886；7,672,040；7,688,497；7,733,335；7,785,988；7,830,592；7,843,626；7,859,637；7,880,958； 7,893,435；7,898,717；7,905,977；7,957,053；7,986,450；8,009,344；8,027,081；8,049,947；8,072,675；8,077,141；8,089,453；8,120,836；8,159,636；8,208,193；8,237,892；8,238,021；8,362,488；8,373,211；8,389,381；8,395,836；8,437,069；8,441,414；8,456,589；8,498,042；8,514,168； 8,547,628；8,576,162；8,610,988；8,714,780；8,728,266；8,743,077；8,754,859；8,797,258；8,797,633；8,797,636；8,830,560；8,891,155；8,969,886；9,147,364；9,025,234；9,025,238；9,030,374；9,140,952；9,152,003；9,152,004；9,201,279；9,223,164；9,285,648；及9,310,661號；以及美國專利申請案公開第2002/0060321；2004/0008179；2004/0085619；2004/0105036；2004/0112525；2005/0122306；2005/0122563；2006/0215106；2006/0255322；2007/0052757；2007/0097489 ; 2007/0109219; 2008/0061300; 2008/0149271; 2009/0122389; 2009/0315044; 2010/0177396; 2011/0140744; 2011/0187683; 2011/0187689; 2011/0292319; 2013/0278900; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014; 2014 /0078024; 2014/0139501; 2014/0192000; 2014/0210701; 2014/0300837; 2014/0368753; 2014/0376164; 2015/0171112; 2015/0205178; 2015/0226986; 2015/0227018; 2015/02286661; 2015/026161616; ; 2015/0356927; 2015/0378235; 2016/077375; 2016/0103380; and 2016/0187759; and International Application Publication No. WO 00/38000; (e)顏色形成及顏色調整；參見例如美國專利第6,017,584；6,664,944；6,864,875；7,075,502；7,167,155；7,667,684；7,791,789；7,956,841；8,040,594；8,054,526；8,098,418；8,213,076；及8,363,299號；以及美國專利申請案公開第2004 /0263947; 2007/0109219; 2007/0223079; 2008/0023332; 2008/0043318; 2008/0048970; 2009/0004442; 2009/0225398; 2010/0103502; 2010/0156780; 2011/0164307; 2011/0195629; 2011/03104666666666666666666666666666666666666666666666666666666666666666666666666666666666610466 ; 2012/0008188; 2012/0019898; 2012/0075687; 2012/0081779; (f) methods for driving displays; see, e.g., U.S. Patent Nos. 7,012,600 and 7,453,445; (g) applications for displays; see, eg, US Patent Nos. 7,312,784 and 8,009,348; (h) Non-electrophoretic displays such as US Patent Nos. 6,241,921; 6,950,220; 7,420,549 and 8,319,759; and US Patent Application Publication No. 2012/0293858; (i) cell structures, wall materials, and methods of forming cells; see, for example, U.S. Patent Nos. 7,072,095 and 9,279,906; (j) Methods for filling and sealing micelles; see, eg, US Patent Nos. 7,144,942 and 7,715,088.

本申請案進一步與美國專利第D485,294；6,124,851；6,130,773；6,177,921；6,232,950；6,252,564；6,312,304；6,312,971；6,376,828；6,392,786；6,413,790；6,422,687；6,445,374；6,480,182；6,498,114；6,506,438；6,518,949；6,521,489；6,535,197；6,545,291；6,639,578；6,657,772；6,664,944；6,680,725；6,683,333；6,724,519；6,750,473；6,816,147；6,819,471；6,825,068；6,831,769；6,842,167；6,842,279；6,842,657；6,865,010；6,873,452；6,909,532；6,967,640；6,980,196；7,012,735；7,030,412；7,075,703；7,106,296；7,110,163；7,116,318；7,148,128；7,167,155；7,173,752；7,176,880；7,190,008；7,206,119；7,223,672；7,230,751；7,256,766；7,259,744；7,280,094；7,301,693；7,304,780；7,327,511；7,347,957；7,349,148；7,352,353；7,365,394；7,365,733；7,382,363；7,388,572；7,401,758；7,442,587；7,492,497；7,535,624；7,551,346；7,554,712；7,583,427；7,598,173；7,605,799；7,636,191；7,649,674；7,667,886；7,672,040；7,688,497；7,733,335；7,785,988；7,830,592；7,843,626；7,859,637；7,880,958；7,893,435；7,898,717；7,905,977；7,957,053；7,986,450；8,009,344；8,027,081；8,049,947；8,072,675；8,077,141；8,089,453；8,120,836；8,159,636；8,208,193；8,237,892；8,238,021；8,362,488；8,373,211；8,389,381；8,395,836；8,437,069；8,441,414；8,456,589；8,498,042；8,514,168；8,547,628；8,576,162；8,610,988；8,714,780；8,728,266；8,743,077；8,754,859；8,797,258；8,797,633；8,797,636；8,830,560；8,891,155；8,969,886；9,147,364；9,025,234；9,025,238；9,030,374；9,140,952；9,152,003；9,152,004；9,201,279；9,223,164；9,285,648；及9,310,661號；以及美國專利申請案公開第2002/0060321；2004/0008179；2004/0085619；2004/0105036；2004/0112525；2005/0122306；2005/0122563；2006/0215106；2006/0255322；2007/0052757；2007/0097489；2007/0109219；2008/0061300；2008/0149271；2009/0122389；2009/0315044；2010/0177396；2011/0140744；2011/0187683；2011/0187689；2011/0292319；2013/0250397；2013/0278900；2014/0078024；2014/0139501；2014/0192000；2014/0210701；2014/0300837；2014/0368753；2014/0376164；2015/0171112；2015/0205178；2015/0226986；2015/0227018；2015/0228666；2015/0261057；2015/0356927；2015/0378235；2016/077375；2016/0103380；及2016/0187759號；以及國際申請案公開第WO 00/38000號；歐洲專利第1,099,207 B1及1,145,072 B1號相關；將所有以上列出之申請案的全部以參照方式併入本文。本申請案進一步與美國專利第D485,294；6,124,851；6,130,773；6,177,921；6,232,950；6,252,564；6,312,304；6,312,971；6,376,828；6,392,786；6,413,790；6,422,687；6,445,374；6,480,182；6,498,114；6,506,438；6,518,949；6,521,489；6,535,197；6,545,291； 6,639,578；6,657,772；6,664,944；6,680,725；6,683,333；6,724,519；6,750,473；6,816,147；6,819,471；6,825,068；6,831,769；6,842,167；6,842,279；6,842,657；6,865,010；6,873,452；6,909,532；6,967,640；6,980,196；7,012,735；7,030,412；7,075,703；7,106,296；7,110,163；7,116,318； 7,148,128；7,167,155；7,173,752；7,176,880；7,190,008；7,206,119；7,223,672；7,230,751；7,256,766；7,259,744；7,280,094；7,301,693；7,304,780；7,327,511；7,347,957；7,349,148；7,352,353；7,365,394；7,365,733；7,382,363；7,388,572；7,401,758；7,442,587；7,492,497；7,535,624； 7,551,346；7,554,712；7,583,427；7,598,173；7,605,799；7,636,191；7,649,674；7,667,886；7,672,040；7,688,497；7,733,335；7,785,988；7,830,592；7,843,626；7,859,637；7,880,958；7,893,435；7,898,717；7,905,977；7,957,053；7,986,450；8,009,344；8,027,081；8,049,947；8,072,675； 8,077,141；8,089,453；8,120,836；8,159,636；8,208,193；8,237,892；8,238,021；8,362,488；8,373,211；8,389,381；8,395,836；8,437,069；8,441,414；8,456,589；8,498,042；8,514,168；8,547,628；8,576,162；8,610,988；8,714,780；8,728,266；8,743,077；8,754,859；8,797,258；8,797,633； 8,797,636；8,830,560；8,891,155；8,969,886；9,147,364；9,025,234；9,025,238；9,030,374；9,140,952；9,152,003；9,152,004；9,201,279；9,223,164；9,285,648；及9,310,661號；以及美國專利申請案公開第2002/0060321；2004/0008179；2004/0085619 ；2004/0105036；2004/0112525；2005/0122306；2005/0122563；2006/0215106；2006/0255322；2007/0052757；2007/0097489；2007/0109219；2008/0061300；2008/0149271；2009/0122389；2009 /0315044; 2010/0177396; 2011/0140744; 2011/0187683; 2011/0187689; 2011/0292319; 2013/0250397; 2013/0278900; 2014/0078024; 2014/0139501; 2014/019210701; 2014/03008373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737373737,; 2014/0210701; ; 2014/0368753; 2015/0171112; 2015/0205178; 2015/0226986; 2015/0227018; 2015/02286666; 2015/0261057; 2015/0356927; 2015/0378235; 2016/077375; and 2016/0103380; and 2016/0187759; and International Application Publication No. WO 00/38000; European Patent Nos. 1,099,207 B1 and 1,145,072 B1 related; all applications listed above are hereby incorporated by reference in their entirety.

本申請案亦與美國專利第5,930,026；6,445,489；6,504,524；6,512,354；6,531,997；6,753,999；6,825,970；6,900,851；6,995,550；7,012,600；7,023,420；7,034,783；7,061,166；7,061,662；7,116,466；7,119,772；7,177,066；7,193,625；7,202,847；7,242,514；7,259,744；7,304,787；7,312,794；7,327,511；7,408,699；7,453,445；7,492,339；7,528,822；7,545,358；7,583,251；7,602,374；7,612,760；7,679,599；7,679,813；7,683,606；7,688,297；7,729,039；7,733,311；7,733,335；7,787,169；7,859,742；7,952,557；7,956,841；7,982,479；7,999,787；8,077,141；8,125,501；8,139,050；8,174,490；8,243,013；8,274,472；8,289,250；8,300,006；8,305,341；8,314,784；8,373,649；8,384,658；8,456,414；8,462,102；8,537,105；8,558,783；8,558,785；8,558,786；8,558,855；8,576,164；8,576,259；8,593,396；8,605,032；8,643,595；8,665,206；8,681,191；8,730,153；8,810,525；8,928,562；8,928,641；8,976,444；9,013,394；9,019,197；9,019,198；9,019,318；9,082,352；9,171,508；9,218,773；9,224,338；9,224,342；9,224,344；9,230,492；9,251,736；9,262,973；9,269,311；9,299,294；9,373,289；9,390,066；9,390,661；及9,412,314號；以及美國專利申請案公開第2003/0102858；2004/0246562；2005/0253777；2007/0070032；2007/0076289；2007/0091418；2007/0103427；2007/0176912；2007/0296452；2008/0024429；2008/0024482；2008/0136774；2008/0169821；2008/0218471；2008/0291129；2008/0303780；2009/0174651；2009/0195568；2009/0322721；2010/0194733；2010/0194789；2010/0220121；2010/0265561；2010/0283804；2011/0063314；2011/0175875；2011/0193840；2011/0193841；2011/0199671；2011/0221740；2012/0001957；2012/0098740；2013/0063333；2013/0194250；2013/0249782；2013/0321278；2014/0009817；2014/0085355；2014/0204012；2014/0218277；2014/0240210；2014/0240373；2014/0253425；2014/0292830；2014/0293398；2014/0333685；2014/0340734；2015/0070744；2015/0097877；2015/0109283；2015/0213749；2015/0213765；2015/0221257；2015/0262255；2016/0071465；2016/0078820；2016/0093253；2016/0140910；及2016/0180777號相關；將所有以上列出之申請案的全部以參照方式併入本文。本申請案亦與美國專利第5,930,026；6,445,489；6,504,524；6,512,354；6,531,997；6,753,999；6,825,970；6,900,851；6,995,550；7,012,600；7,023,420；7,034,783；7,061,166；7,061,662；7,116,466；7,119,772；7,177,066；7,193,625；7,202,847；7,242,514；7,259,744； 7,304,787；7,312,794；7,327,511；7,408,699；7,453,445；7,492,339；7,528,822；7,545,358；7,583,251；7,602,374；7,612,760；7,679,599；7,679,813；7,683,606；7,688,297；7,729,039；7,733,311；7,733,335；7,787,169；7,859,742；7,952,557；7,956,841；7,982,479；7,999,787；8,077,141； 8,125,501；8,139,050；8,174,490；8,243,013；8,274,472；8,289,250；8,300,006；8,305,341；8,314,784；8,373,649；8,384,658；8,456,414；8,462,102；8,537,105；8,558,783；8,558,785；8,558,786；8,558,855；8,576,164；8,576,259；8,593,396；8,605,032；8,643,595；8,665,206；8,681,191； 8,730,153；8,810,525；8,928,562；8,928,641；8,976,444；9,013,394；9,019,197；9,019,198；9,019,318；9,082,352；9,171,508；9,218,773；9,224,338；9,224,342；9,224,344；9,230,492；9,251,736；9,262,973；9,269,311；9,299,294；9,373,289；9,390,066；9,390,661；及9,412,314號；以及美國專利申請案公開第2003/0102858；2004/0246562；2005/0253777；2007/0070032；2007/0076289；2007/0091418；2007/0103427；2007/0176912；2007/0296452；2008/0024429；2008/0024482 ；2008/0136774；2008/0169821；2008/0218471；2008/0291129；2008/0303780；2009/0174651；2009/0195568；2009/0322721；2010/0194733；2010/0194789；2010/0220121；2010/0265561；2010 /0283804；2011/0063314；2011/0175875；2011/0193840；2011/0193841；2011/0199671；2011/0221740；2012/0001957；2012/0098740；2013/0063333；2013/0194250；2013/0249782；2013/0321278 ; 2014/0009817; 2014; 2014/0204012; 2014/0218277; 2014/0240210; 2014/0240373; 2014/0253425; 2014/0292830; 2014/02933398; 2014/03333685; 2014/0340734; 20150070744; /0097877; 2015/0109283; 2015/0213749; 2015/0213765; 2015/0221257; 2015/0262255; The entirety of the filed application is incorporated herein by reference.

許多上述專利及申請案認識到在膠囊化電泳介質中包圍離散微膠囊的壁可以由連續相來取代，從而產生所謂的聚合物分散型電泳顯示器，其中電泳介質包含複數個離散小滴的電泳流體及連續相的聚合材料，並且即使沒有離散的膠囊膜與每個個別小滴相關聯，在這樣的聚合物分散型電泳顯示器內之離散小滴的電泳流體可以被視為膠囊或微膠囊；參見例如前述美國專利第6,866,760號。於是，基於本申請案的目的，這樣的聚合物分散型電泳介質被視為膠囊化電泳介質的亞種。Many of the aforementioned patents and applications recognize that the walls surrounding discrete microcapsules in an encapsulated electrophoretic medium can be replaced by a continuous phase, resulting in a so-called polymer dispersed electrophoretic display, where the electrophoretic medium comprises a plurality of discrete droplets of electrophoretic fluid and continuous phase of polymeric material, and the discrete droplets of electrophoretic fluid within such polymer-dispersed electrophoretic displays can be viewed as capsules or microcapsules even though there is no discrete capsule membrane associated with each individual droplet; see For example, the aforementioned US Patent No. 6,866,760. Thus, for the purposes of this application, such polymer-dispersed electrophoretic media are considered a subspecies of encapsulated electrophoretic media.

一種相關類型之電泳顯示器係所謂的「微胞電泳顯示器」。在微胞電泳顯示器中，沒有將帶電粒子及流體裝入微膠囊中，而是將其保持在載體介質(carrier medium)(通常是聚合膜)內所形成之複數個空腔(cavities)中。參見例如美國專利第6,672,921及6,788,449號，這兩件專利係讓渡給Sipix Imaging Inc.。A related type of electrophoretic display is the so-called "cell electrophoretic display". In microcell electrophoretic displays, charged particles and fluids are not encapsulated in microcapsules, but are held in cavities formed within a carrier medium (usually a polymeric film). See, eg, US Patent Nos. 6,672,921 and 6,788,449, both assigned to Sipix Imaging Inc.

雖然電泳介質可能是不透光的(因為，例如，在許多電泳介質中，粒子大致阻擋通過顯示器之可見光的傳輸)且在反射模式中操作，但是可使一些電泳顯示器在所謂「光柵模式(shutter mode)」中操作，在該光柵模式中，一顯示狀態係大致不透光的，而一顯示狀態係透光的。參見例如，美國專利第5,872,552；6,130,774；6,144,361；6,172,798；6,271,823；6,225,971；以及6,184,856號。介電泳顯示器(dielectrophoretic displays)(其相似於電泳顯示器，但是依賴電場強度之變化)可在相似模式中操作；參見美國專利第4,418,346號。其它類型之電光顯示器亦能夠在光柵模式中操作。以光柵模式操作的電光介質可以用於全彩顯示器的多層結構中；在這樣的結構中，與顯示器的觀看表面相鄰的至少一層以光柵模式操作，以暴露或隱藏離觀看表面更遠的第二層。While electrophoretic media may be opaque (because, for example, in many electrophoretic media, the particles substantially block the transmission of visible light through the display) and operate in reflective mode, some electrophoretic displays can be made to operate in a so-called "shutter mode". mode) in which one display state is substantially opaque and one display state is transmissive. See, eg, US Patent Nos. 5,872,552; 6,130,774; 6,144,361; 6,172,798; 6,271,823; 6,225,971; Dielectrophoretic displays (which are similar to electrophoretic displays, but rely on changes in electric field strength) can operate in a similar mode; see US Patent No. 4,418,346. Other types of electro-optic displays can also operate in raster mode. Electro-optic media that operate in a raster mode can be used in multilayer structures for full-color displays; in such structures, at least one layer adjacent to the viewing surface of the display operates in a raster mode to expose or hide a first second floor.

一種膠囊化電泳顯示器通常沒有遭遇傳統電泳裝置之群集(clustering)及沉降(settling)故障模式且提供另外的優點，例如，將顯示器印刷或塗佈在各種撓性及剛性基板上之能力。(文字「印刷」之使用意欲包括所有形式之印刷及塗佈，其包括但不侷限於：預計量式塗佈(pre-metered coatings)(例如：方塊擠壓式塗佈(patch die coating)、狹縫型或擠壓型塗佈(slot or extrusion coating)、斜板式或級聯式塗佈(slide or cascade coating)及淋幕式塗佈(curtain coating))；滾筒式塗佈(roll coating)(例如：輥襯刮刀塗佈(knife over roll coating及正反滾筒式塗佈(forward and reverse roll coating))；雕型塗佈(gravure coating)；濕式塗佈(dip coating)；噴灑式塗佈(spray coating)；彎月形塗佈(meniscus coating)；旋轉塗佈(spin coating)；刷塗式塗佈(brush coating)；氣刀塗佈(air-knife coating)；絲網印刷製程(silk screen printing processes)；靜電印刷製程(electrostatic printing processes)；熱印刷製造(thermal printing processes)；噴墨印刷製程(ink jet printing processes)；電泳沉積(electrophoretic deposition)(參見美國專利第7,339,715號)；以及其它相似技術)。因此，結果的顯示器可以是可撓性的。再者，因為可(使用各種方法)印刷顯示介質，所以可便宜地製造顯示器本身。An encapsulated electrophoretic display generally does not suffer from the clustering and settling failure modes of conventional electrophoretic devices and offers additional advantages, such as the ability to print or coat the display on a variety of flexible and rigid substrates. (The use of the word "printing" is intended to include all forms of printing and coating, including but not limited to: pre-metered coatings (e.g. patch die coating, Slot or extrusion coating, slide or cascade coating and curtain coating); roll coating (For example: knife over roll coating and forward and reverse roll coating); engraved coating (gravure coating); wet coating (dip coating); spray coating Spray coating; meniscus coating; spin coating; brush coating; air-knife coating; screen printing process ( silk screen printing processes); electrostatic printing processes; thermal printing processes; ink jet printing processes; electrophoretic deposition (see U.S. Patent No. 7,339,715); and other similar techniques). Thus, the resulting display can be flexible. Furthermore, since the display medium can be printed (using various methods), the display itself can be cheaply manufactured.

其它類型的電光材料亦可以使用於本發明中。Other types of electro-optic materials can also be used in the present invention.

電泳顯示器通常包括一層電泳材料及至少兩個設置在電泳材料相對側上的其它層，這兩個層中的一個是電極層。在大多數這樣的顯示器中，這兩層都是電極層，並且電極層之一或兩者都被圖案化以限定顯示器的像素。例如，一個電極層可以被圖案化成數個細長列電極，而另一個被圖案化成與列電極成直角延伸的數個細長行電極，像素由列電極及行電極的交叉點來限定。或者，更常見的是，一個電極層具有單個連續電極的形式，而另一個電極層被圖案化成像素電極矩陣，每個像素電極界定顯示器的一個像素。在意欲與與顯示器分離的觸控筆、列印頭或類似可移動電極一起使用的另一種類型的電泳顯示器中，只有與電泳層相鄰的一個層包含電極，位於電泳層的相對側之層通常是意欲用於防止可移動電極損壞電泳層的保護層。Electrophoretic displays generally comprise a layer of electrophoretic material and at least two other layers, one of which is an electrode layer, disposed on opposite sides of the electrophoretic material. In most such displays, both layers are electrode layers, and one or both of the electrode layers are patterned to define the pixels of the display. For example, one electrode layer may be patterned with elongated column electrodes and the other patterned with elongated row electrodes extending at right angles to the column electrodes, with pixels defined by the intersections of the column and row electrodes. Alternatively, and more commonly, one electrode layer is in the form of a single continuous electrode, while the other electrode layer is patterned into a matrix of pixel electrodes, each pixel electrode defining a pixel of the display. In another type of electrophoretic display intended for use with a stylus, print head, or similar movable electrodes separate from the display, only one layer adjacent to the electrophoretic layer contains electrodes, and the layer on the opposite side of the electrophoretic layer Usually a protective layer intended to prevent the movable electrode from damaging the electrophoretic layer.

在例如美國專利第6,704,133號所述的又另一個實施例中，電泳顯示器可以由兩個連續電極以及電極之間的電泳層和光電泳層構成。因為光電泳材料隨著光子的吸收而改變電阻率，所以可以使用入射光來改變電泳介質的狀態。這樣的裝置被例示在圖1中。如美國專利第6,704,133號所述，圖1的裝置在由發射源驅動時效果是最佳的，例如，LCD顯示器，發射源是位於顯示器與觀看表面相對的一側。在一些實施例中，美國專利第6,704,133號的裝置在前電極與光電泳材料之間併入特殊的阻障層，以減少由來自顯示器正面的入射光通過反射電光介質洩漏而引起的「暗電流」。In yet another embodiment, such as that described in US Pat. No. 6,704,133, an electrophoretic display may consist of two consecutive electrodes with an electrophoretic layer and a photophoretic layer between the electrodes. Because electrophoretic materials change resistivity as photons are absorbed, incident light can be used to change the state of the electrophoretic medium. Such a device is illustrated in FIG. 1 . As described in US Pat. No. 6,704,133, the device of FIG. 1 works best when driven by an emitting source, such as an LCD display, on the side of the display opposite the viewing surface. In some embodiments, the device of U.S. Patent No. 6,704,133 incorporates a special barrier layer between the front electrode and the electrophoretic material to reduce the "dark current" caused by leakage of incident light from the front side of the display through the reflective electro-optic medium. ".

前述美國專利第6,982,178號描述一種組裝固態電光顯示器(包括膠囊化電泳顯示器)的方法，所述方法非常適合於大量生產。實質上，此專利描述一種所謂的「前平面積層板」(「FPL」)，其依序包括透光導電層；與導電層電接觸的固體電光介質層；黏著層；以及離型片。通常，透光導電層會被承載在透光基板上，透光基板較佳地是可撓性的，在這種意義上，基板可以手動纏繞在直徑為(例如)10英寸(254mm)的滾筒上而不會永久變形。術語「透光的」在本專利及本文中用於意指如此表示的層透射足夠的光，以使觀察者能夠看透此層，以觀看電光介質的顯示狀態之變化，所述變化通常可以透過導電層及相鄰基板(如果存在)來觀看；在電光介質在不可見波長下顯示反射率變化之情況下，術語「透光的」當然應該解釋為意指相關不可見波長的透射。基板通常是聚合物膜，並且通常具有約1至約25密耳(25至634μm)，較佳地，約2至約10密耳(51至254μm)的厚度。導電層傳統上是薄金屬或金屬氧化層，例如，鋁或ITO，或者可以是導電聚合物。塗佈有鋁或ITO的聚(對酞酸乙二酯)(PET)薄膜在市場上係可購得的，例如，來自EI du Pont de Nemours & Company, Wilmington DE的「鋁化Mylar」(「Mylar」是註冊商標)，以及這樣的商品材料可以使用在前平面積層板中且具有良好的結果。使用前平面積層板形成電光顯示器的製程可以包括使用熱層壓製程以將FPL或雙離型膜附接至背板。背板可以屬於具有一個以上的圖案化導電走線的直接驅動分段種類或者可以屬於非線性電路種類(例如，主動矩陣)。The aforementioned US Patent No. 6,982,178 describes a method of assembling solid-state electro-optic displays, including encapsulated electrophoretic displays, which is well suited for mass production. Essentially, this patent describes a so-called "front planar laminate" ("FPL") comprising, in order, a light-transmitting conductive layer; a solid electro-optic dielectric layer in electrical contact with the conductive layer; an adhesive layer; and a release sheet. Typically, the light-transmissive conductive layer will be carried on a light-transmissive substrate, which is preferably flexible, in the sense that the substrate can be hand-wound on a roll of, for example, 10 inches (254 mm) in diameter without permanent deformation. The term "optical transmissive" is used in this patent and herein to mean that a layer so denoted transmits sufficient light to enable a viewer to see through the layer to observe changes in the displayed state of the electro-optic medium, which typically can be transmitted through the The conductive layer and the adjacent substrate (if present) are viewed; in the case of electro-optic media that exhibit changes in reflectivity at non-visible wavelengths, the term "light-transmissive" should of course be interpreted to mean transmission of the relevant non-visible wavelengths. The substrate is typically a polymeric film and typically has a thickness of about 1 to about 25 mils (25 to 634 μm), preferably about 2 to about 10 mils (51 to 254 μm). The conductive layer is traditionally a thin metal or metal oxide layer, eg aluminum or ITO, or may be a conductive polymer. Poly(ethylene terephthalate) (PET) films coated with aluminum or ITO are commercially available, e.g., "Aluminized Mylar" from EI du Pont de Nemours & Company, Wilmington DE (" Mylar” is a registered trademark), and such commercial materials can be used in front planar laminates with good results. The process of forming an electro-optic display using a front plane build-up board may include using a thermal lamination process to attach the FPL or dual release film to the backplane. The backplane may be of the direct drive segmented variety with more than one patterned conductive trace or may be of the non-linear circuit variety (eg active matrix).

前述美國專利第6,982,178號亦描述一種在將前平面積層板結合至顯示器中之前測試前平面積層板中之電光介質的方法。在此測試方法中，離型片設置有導電層，並且將足以改變電光介質的光學狀態之電壓施加在此導電層與電光介質的相對側上之導電層之間。然後，對電光介質的觀察會揭示介質中的任何缺陷，從而避免將有缺陷的電光介質層壓至顯示器中而產生報廢整個顯示器而不僅僅是有缺陷的前面板積層板之最終成本。The aforementioned US Patent No. 6,982,178 also describes a method of testing the electro-optic medium in a front-plane laminate prior to incorporating the front-plane laminate into a display. In this test method, a release sheet is provided with a conductive layer, and a voltage sufficient to change the optical state of the electro-optic medium is applied between this conductive layer and the conductive layer on the opposite side of the electro-optic medium. Observation of the electro-optic medium would then reveal any defects in the medium, avoiding the eventual cost of laminating defective electro-optic media into a display with the eventual cost of scrapping the entire display rather than just a defective front laminate.

前述美國專利第6,982,178號亦描述用於藉由在離型片上放置靜電荷從而在電光介質上形成影像來測試前平面積層板中的電光介質之第二種方法。然後，以與以前相同的方式觀看此影像，以偵測電光介質中的任何缺陷。The aforementioned US Patent No. 6,982,178 also describes a second method for testing electro-optic media in front plane laminates by placing an electrostatic charge on the release sheet to form an image on the electro-optic media. This image is then viewed in the same manner as before to detect any defects in the electro-optic medium.

使用這樣的前平面積層板之電光顯示器的組裝可以藉由從前平面積層板移除離型片並在有效使黏著層黏附至背板的條件下使黏著層與背板接觸來實現，從而確保將黏著層、電光介質層及導電層固定至背板。這種方法非常適合於大量生產，因為前平面積層板可以大量生產(通常使用捲對捲塗佈(roll-to-roll coating)技術)，然後切割成與特定背板一起使用所需之任何尺寸的片段。Assembly of an electro-optic display using such a front-plane build-up can be accomplished by removing the release liner from the front-plane build-up and bringing the adhesive into contact with the backsheet under conditions effective to cause the adhesive to adhere to the backsheet, thereby ensuring that the The adhesive layer, the electro-optic medium layer and the conductive layer are fixed to the backplane. This method is well-suited for high-volume production, as front-flat laminates can be produced in large quantities (often using roll-to-roll coating techniques) and then cut to any size required for use with a specific backsheet fragments.

美國專利第7,561,324號描述一種所謂的「雙離型片」，其實質上是前述美國專利第6,982,178號的前平面積層板之簡化版本。一種形式的雙離型片包括夾在兩個黏著層之間的一層固體電泳介質，其中這兩個黏著層中之一者或兩者被離型片覆蓋。另一種形式的雙離型片包括夾在兩個離型片之間的一層固體電光介質。兩種形式的雙離型膜意欲使用在與從已經描述的前平面積層板組裝電光顯示器的方法大體上類似的方法中，但是涉及兩次單獨的層壓；通常，在第一次層壓中，將雙離型片層壓至前電極，以形成前次總成，以及然後，在第二次層壓中，將前次總成層壓至背板，以形成最終顯示器，但是如果需要，可以顛倒這兩次層壓的順序。US Patent No. 7,561,324 describes a so-called "dual release sheet", which is essentially a simplified version of the front planar laminate of the aforementioned US Patent No. 6,982,178. One form of dual release liner includes a layer of solid electrophoretic medium sandwiched between two adhesive layers, either or both of which are covered by a release liner. Another form of dual release sheet includes a layer of solid electro-optic media sandwiched between two release sheets. Both forms of dual release film are intended for use in a method substantially similar to that of assembling electro-optic displays from front-plane laminates already described, but involving two separate laminations; typically, in the first lamination , the double release liner is laminated to the front electrode to form the front subassembly, and then, in a second lamination, the front subassembly is laminated to the backplane to form the final display, but if desired, can Reverse the order of these two laminations.

美國專利第7,839,564號描述一種所謂的「倒置前平面積層板」，它是前述美國專利第6,982,178號中所述之前平面積層板的變型。此倒置前平面積層板依次包括透光保護層及透光導電層中之至少一者；黏著層；固體電光介質層；以及離型片。這種倒置前平面積層板用於形成電光顯示器，其在電光層與前電極或前基板之間具有層壓黏著層；在電光層與背板之間可能存在或不存在通常是薄的第二黏著層。這樣的電光顯示器可以結合良好的解析度與良好的低溫性能。US Patent No. 7,839,564 describes a so-called "inverted front planar laminate" which is a variation of the front planar laminate described in aforementioned US Patent No. 6,982,178. The inverted front plane laminate sequentially includes at least one of a light-transmitting protective layer and a light-transmitting conductive layer; an adhesive layer; a solid electro-optic medium layer; and a release sheet. This inverted front-plane build-up is used to form electro-optic displays with a laminated adhesive layer between the electro-optic layer and the front electrode or front substrate; there may or may not be a usually thin second Adhesive layer. Such electro-optic displays can combine good resolution with good low temperature performance.

某些顏料的光電泳特性在不久前就已經得到認可。例如，美國專利第3,383,993號揭露一種光電泳成像設備，此設備可用於在介質(通常是透明電極，例如，ITO)上再現投影圖像。然而，‘993專利及施樂公司的其它相關專利中描述的光電泳製程是不可逆的，因為光電泳製程涉及光電泳粒子遷移至「注入電極」，在那裡它們將附著在電極上。由於缺乏可逆性以及設置的成本及複雜性，這種現象並未廣泛地商業化。The electrophoretic properties of certain pigments have been recognized not long ago. For example, US Patent No. 3,383,993 discloses an electrophoretic imaging device that can be used to reproduce a projected image on a medium (usually a transparent electrode such as ITO). However, the photophoretic process described in the '993 patent and other related Xerox patents is irreversible because the photophoretic process involves the migration of photophoretic particles to an "injection electrode" where they will attach to the electrode. This phenomenon has not been widely commercialized due to lack of reversibility and the cost and complexity of setup.

雖然本發明的顯示器意欲以很少或沒有能量輸入的情況下長時間顯示影像，但是上述環形顯示器(looped displays)可用於在與發射顯示器(例如，大型LED顯示器)相同的時間尺度上更新內容。本發明的顯示器可以在不到一小時(例如，在不到10分鐘，例如，在不到五分鐘，例如，在不到兩分鐘)內顯示兩個不同的影像。再者，更新期間可以錯開，這取決於顯示器的使用。例如，可以每五分鐘更新一次交通時刻表，其中持續30秒的廣告，之後再返回另一個五分鐘期間的交通時刻表。While the displays of the present invention are intended to display images for extended periods of time with little or no power input, the looped displays described above can be used to update content on the same time scale as emissive displays (eg, large LED displays). The display of the present invention can display two different images in less than one hour (eg, in less than 10 minutes, eg, in less than five minutes, eg, in less than two minutes). Again, the update periods can be staggered, depending on display usage. For example, a traffic schedule may be updated every five minutes with a 30-second advertisement and then back to the traffic schedule for another five-minute period.

在某些情況下，一種能夠使用直流不平衡波形的方法是在主動更新後對顯示模組進行放電。放電涉及使顯示器的成像膜短路，以排出因直流不平衡驅動而積聚在成像膜(例如，電泳材料層)上的殘餘電荷。更新後驅動放電(在本文中稱為uPDD或UPD)的使用已成功地顯示殘餘電荷積累(用殘留電壓來測量)及會導致成像膜因電化學而永久退化之相應模塊極化的減少。In some cases, one way to be able to use the DC unbalanced waveform is to discharge the display module after an active update. Discharging involves shorting the imaging films of the display to discharge residual charge accumulated on the imaging films (eg, electrophoretic material layer) due to DC unbalanced drive. The use of post-refresh drive discharge (referred to herein as uPDD or UPD) has successfully demonstrated a reduction in residual charge accumulation (measured as residual voltage) and corresponding module polarization that would lead to permanent electrochemical degradation of the imaged film.

現在已經發現，殘留電壓的原因及影響在電泳顯示器及其它脈衝驅動的電光顯示器中是一種更普遍的現象。亦發現到直流不平衡可能會導致一些電泳顯示器的長期壽命退化。It has now been found that the cause and effect of residual voltage is a more common phenomenon in electrophoretic displays and other pulse-driven electro-optic displays. It has also been found that DC imbalance may cause long-term lifetime degradation of some electrophoretic displays.

殘留電壓有多個可能來源。相信(但是一些實施例決不受此信念限制)殘留電壓的主要原因是在形成顯示器之各種層的材料內之離子極化。There are several possible sources of residual voltage. It is believed (but some embodiments are by no means limited by this belief) that the primary cause of residual voltage is ionic polarization within the materials forming the various layers of the display.

這樣的極化以各種方式發生。在第一種(為方便起見，表示為「I型」)極化中，跨過或鄰近材料界面產生離子雙層。例如，氧化銦錫(「ITO」)電極處的正電位可能在相鄰層壓黏著劑中產生相應的負離子極化層。這樣的極化層的衰減率與層壓黏著層中之分離離子的復合相關聯。這樣的極化層之幾何形狀由界面的形狀來決定，但本質上可以是平面的。Such polarization occurs in various ways. In the first (for convenience, denoted "Type I") polarization, an ionic double layer is created across or adjacent to a material interface. For example, a positive potential at an indium tin oxide ("ITO") electrode may produce a corresponding negative ion polarized layer in the adjacent lamination adhesive. The decay rate of such a polarized layer is related to the recombination of separated ions in the laminate adhesive layer. The geometry of such a polarizing layer is determined by the shape of the interface, but may be planar in nature.

在第二種類型(「II型」)極化中，單一材料內的結節、晶體或其它種類的材料異質性會導致離子可移動或比周圍材料移動的速度慢之區域。不同的離子遷移速率會導致介質主體內之不同的的電荷極化程度，因此極化可能發生在單個顯示組件內。這樣的極化可以在本質上呈局部化或分散在整個層中。In the second type ("Type II") polarization, nodules, crystals, or other kinds of material heterogeneity within a single material result in regions where ions can move or move more slowly than the surrounding material. Different ion migration rates result in different charge polarization levels within the media bulk, and thus polarization may occur within a single display component. Such polarization may be localized or dispersed throughout the layer in nature.

在第三種類型(「III型」)極化中，極化可以發生在代表任何特定類型離子的電荷傳輸障礙之任何界面處。在微腔電泳顯示器中之這樣的界面之一個實例是包含懸浮介質及粒子的電泳懸浮液(「內相」)與包含壁、黏著劑及黏結劑的周圍介質(「外相」)之間的邊界。在許多電泳顯示器中，內相是疏水液體，而外相是聚合物，例如，明膠。存在於內相中的離子在外相中可能是不溶的及不可擴散的，反之亦然。在施加垂直於這樣的界面之電場時，相反符號的極化層將在界面的任一側積累。當移除所施加的電場時，所得的非平衡電荷分佈將導致隨鬆弛時間(relaxation time)衰減之可測量殘留電壓電位，其中上述鬆弛時間由界面兩側上的兩相中之離子的遷移率來決定。In the third type ("Type III") polarization, polarization can occur at any interface that represents a charge transport barrier for any particular type of ion. An example of such an interface in a microcavity electrophoretic display is the boundary between the electrophoretic suspension ("inner phase") comprising the suspending medium and particles and the surrounding medium ("outer phase") comprising walls, adhesives and binders . In many electrophoretic displays, the inner phase is a hydrophobic liquid and the outer phase is a polymer, eg, gelatin. Ions present in the inner phase may be insoluble and non-diffusible in the outer phase, and vice versa. On application of an electric field perpendicular to such an interface, polarized layers of opposite sign will accumulate on either side of the interface. When the applied electric field is removed, the resulting non-equilibrium charge distribution will result in a measurable residual voltage potential that decays with relaxation time determined by the mobility of ions in the two phases on both sides of the interface. to decide.

極化可能發生在一個驅動脈衝期間。每次影像更新是可能影響殘留電壓的事件。取決於特定的電光顯示器，正波形電壓可以在電光介質上產生具有相同或相反極性(或幾乎為零)的殘留電壓。Polarization may occur during a drive pulse. Each image update is an event that may affect the residual voltage. Depending on the particular electro-optic display, a positive waveform voltage can produce a residual voltage of the same or opposite polarity (or nearly zero) across the electro-optic medium.

從前面的論述可以明顯看出，極化可能發生在電泳或其它電光顯示器內的多個位置處，每個位置具有其本身的衰減時間特徵譜，主要是發生在界面材料異質性處。取決於這些電壓源(換句話說，極化電荷分佈)相對於電活性部分(例如，電泳懸浮液)的位置以及每種電荷分佈間的電耦合程度及粒子通過懸浮液的運動或其它電光活動，各種極化或多或少會產生有害影響。因為電泳顯示器藉由帶電粒子的運動而進行操作，這本就會導致電光層的極化，所以在某種意義來說，較佳的電泳顯示器不是顯示器中始終不存在殘留電壓的顯示器，而是殘留電壓不會引起令人反感的電光行為的顯示器。理想地，殘留脈衝將被最小化，並且殘留電壓將在1秒內(最好在50ms內)降至1V以下(優較佳是0.2V以下)，以致於藉由在影像更新之間引入最小停頓，電泳顯示器可以影響光學狀態之間的所有過渡，而無需考慮殘留電壓的影響。對於以視頻速率或低於+/-15V的電壓操作的電泳顯示器，應該相應地減少這些理想值。類似的考慮適用於其它類型的電光顯示器。From the foregoing discussion it is evident that polarization may occur at multiple locations within an electrophoretic or other electro-optic display, each with its own decay time profile, primarily at interfacial material heterogeneity. Depends on the location of these voltage sources (in other words, polarized charge distributions) relative to the electroactive part (e.g., electrophoretic suspension) and the degree of electrical coupling between each charge distribution and the movement of particles through the suspension or other electro-optic activity , various polarizations have more or less detrimental effects. Because electrophoretic displays operate by the movement of charged particles, which inherently leads to polarization of the electro-optic layer, a better electrophoretic display is not, in a sense, one in which there is always no residual voltage in the display, but one in which A display in which residual voltages do not cause objectionable electro-optic behaviour. Ideally, the residual pulse will be minimized and the residual voltage will drop below 1V (preferably below 0.2V) within 1 second (preferably within 50ms), so that by introducing a minimum Paused, electrophoretic displays can affect all transitions between optical states regardless of residual voltage effects. For electrophoretic displays operating at video rates or at voltages lower than +/-15V, these ideal values should be reduced accordingly. Similar considerations apply to other types of electro-optic displays.

總而言之，作為一種現象的殘留電壓至少實質上是在顯示材料成分內發生在界面處或在材料本身內的的離子極化的結果。當這樣的極化持續大約50ms至大約一個小時或更長時間的中間時間尺度(meso time scale))時，它們尤其成問題。殘留電壓會以多種方式將自身呈現為影像重影或視覺偽影，其嚴重程度會隨著影像更新之間經過的時間而變化。殘留電壓亦會產生直流不平衡並縮短最終的顯示壽命。殘留電壓的影響因而可能對電泳或其它電光裝置的品質有害，因此希望將殘留電壓本身以及裝置的光學狀態對殘留電壓影響的敏感度降至最低。In summary, residual voltage as a phenomenon is at least substantially the result of ionic polarization within the display material components occurring at interfaces or within the material itself. They are especially problematic when such polarizations last on a meso time scale of about 50 ms to about an hour or more. Residual voltage can manifest itself as image ghosting or visual artifacts in a number of ways, the severity of which varies with the time elapsed between image updates. Residual voltage also creates a DC imbalance and shortens the eventual display life. The effects of residual voltage can thus be detrimental to the quality of electrophoretic or other electro-optical devices, and it is therefore desirable to minimize the sensitivity of the residual voltage itself, as well as the optical state of the device, to the effects of residual voltage.

在實際上，由於上述極化效應而在電泳材料內積累的電荷可以被釋放或排出以減輕殘留電壓的影響。在一些實施例中，這樣的放電可以在更新或驅動序列之後進行。In practice, charges accumulated in the electrophoretic material due to the above-mentioned polarization effect can be released or discharged to alleviate the influence of residual voltage. In some embodiments, such discharging may follow a refresh or drive sequence.

在一些實施例中，可以使用用於EPD及EPD的控制器電路之容易獲得的薄膜電晶體(TFT)背板100來執行驅動後或更新後放電，如圖1所示。在使用中，每個顯示像素可以包括一個薄膜電晶體UPD(例如，TFT (upd))102，其可以構造成提供一定程度的導電性，使得顯示器的頂板106及源極(或資料)線Vs保持在相同的電壓電位(例如，接地)達一段時間。在此全部併入本文中的上述專利申請案第15/014,236號更詳細地論述這樣的驅動方法。如本文所示的顯示像素100以及下面所示的各種實施例通常包括位於像素電極104與頂板106之間的電泳材料108，其中頂板106可以包括基板及共同電極，並且共同電極可以是透明導電層。通常，TFT (upd)102被設計成作為用於提供或傳輸驅動波形至像素的像素電極104之像素控制電晶體。因此，TFT (upd)102通常構造成與在非導通狀態(亦即，「OFF」狀態)下相比在導通狀態(亦即，「ON」狀態)下操作非常短的時間，例如，「ON」時間與「OFF」時間的比例超過1：1000。雖然使用uPDD會根據uPDD配置將此比例更改為大約1：2或1：50，這會導致長期使用後產生正偏壓應力，但是在某些情況下，這種用法會相當於通常由數萬或更多的影像更新所造成的應力。已知正偏壓應力會導致非晶矽TFT中的臨界電壓偏移是永久性的。臨界電壓的偏移會導致受影響的TFT及TFT背板之行為改變，進而導致EPD的光學性能之光學偏移。已觀察到因uPDD而引起的光學偏移，如圖2A及2B所示。如圖所示，由於uPDD，顯示灰調(圖2A)及重影偏移(圖2B)值會在數萬次更新週期後的兩年期間內顯著增加。 In some embodiments, post-drive or post-refresh discharge can be performed using a readily available thin film transistor (TFT) backplane 100 for the EPD and the EPD's controller circuit, as shown in FIG. 1 . In use, each display pixel may include a thin film transistor UPD (eg, TFT (upd) ) 102, which may be configured to provide a degree of electrical conductivity such that the display's top plate 106 and source (or data) line Vs Stay at the same voltage potential (eg, ground) for a period of time. The aforementioned patent application Ser. No. 15/014,236, which is hereby incorporated in its entirety, discusses such drive methods in more detail. Display pixels 100 as shown herein and the various embodiments shown below generally include an electrophoretic material 108 between a pixel electrode 104 and a top plate 106, where the top plate 106 can include a substrate and a common electrode, and the common electrode can be a transparent conductive layer . Generally, the TFT (upd) 102 is designed as a pixel control transistor for providing or transmitting a driving waveform to the pixel electrode 104 of the pixel. Accordingly, TFT (upd) 102 is typically configured to operate in a conducting state (ie, "ON" state) for a very short period of time compared to a non-conducting state (ie, "OFF" state), eg, "ON ” time to “OFF” time ratio exceeds 1:1000. While using a uPDD changes this ratio to approximately 1:2 or 1:50 depending on the uPDD configuration, which can lead to positive bias stress after long-term use, in some cases this usage can be equivalent to Stress caused by more image updates. Positive bias stress is known to cause permanent threshold voltage shifts in amorphous silicon TFTs. Shifts in the threshold voltage lead to changes in the behavior of the affected TFTs and TFT backplanes, resulting in optical shifts in the optical performance of the EPD. Optical shifts due to uPDD have been observed, as shown in Figures 2A and 2B. As shown, the display grayscale (Fig. 2A) and ghost shift (Fig. 2B) values increase significantly over a two-year period after tens of thousands of update cycles due to uPDD.

在僅使用單個TFT(例如，圖1中所示的TFT (upd)102)的情況下，正常影像更新及uPDD都以相同的TFT(亦即，TFT (upd))來實現。或者，在一些實施例中，可以將額外的TFT添加至每個像素並單獨用於uPDD放電方案。雖然整體放電方案保持不變，但是用於正常顯示操作的像素TFT(例如，圖1的TFT (upd)102)將僅用於主動顯示更新，就像在不包含放電之EPD的標準主動矩陣驅動中一樣。這種配置保證用於正常顯示操作之像素TFT的性能穩定且不受放電影響。雖然用於放電的額外TFT可能經歷因正偏壓應力而引起的臨界電壓偏移，但是這不會導致EPD中的光學偏移，並且這不會影響放電操作，只要在放電期間使TFT導通(亦即只要放電方案考量可能的臨界電壓偏移)。這樣的配置可以允許穩定的顯示操作而沒有光學響應偏移，同時允許藉由後驅動放電致能的直流不平衡波形(DC-imbalanced)。 Where only a single TFT (eg, TFT (upd) 102 shown in FIG. 1 ) is used, both normal image update and uPDD are implemented with the same TFT (ie, TFT (upd) ). Alternatively, in some embodiments, additional TFTs can be added to each pixel and used separately for the uPDD discharge scheme. While the overall discharge scheme remains the same, the pixel TFTs used for normal display operation (e.g., TFT (upd) 102 of Figure 1) will only be used for active display update, just like in a standard active matrix drive with an EPD that does not include discharge same as in. This configuration ensures that the performance of the pixel TFT for normal display operation is stable and not affected by discharge. Although an additional TFT used for discharge may experience a threshold voltage shift due to positive bias stress, this will not cause an optical shift in the EPD, and this will not affect discharge operation as long as the TFT is turned on during discharge ( That is, as long as the discharge scheme considers the possible threshold voltage shift). Such a configuration may allow stable display operation without optical response shift, while allowing DC-imbalanced waveforms enabled by post-drive discharge.

在圖3中例示依據上述概念的一個示例性實施例。除了標準像素TFT(例如，TFT (upd)302)之外，顯示像素300可以包括專用於從電泳膜314排出殘留電壓或過量電荷的主動組件。此主動組件可以是任何類型的電晶體(例如，TFT、CMOS等)或可以藉由施加電能(例如，電壓)或光能來啟動或導通的任何其它組件、諸如二極體或光偵測器/二極體的裝置或者任何一般的電/光啟動開關。為了說明一般概念，在此使用TFT(例如，n型TFT)，但是應該理解，這並不意味著用作限制。如圖3所示，指定電晶體TFT (dis)304可以用於釋放電泳成像膜314內殘留電壓的電荷。在這種配置中，TFT (upd)302的閘極連接至來自閘極驅動器輸出的選擇線(例如，Vg (upd)308)，而TFT (dis)304的閘極連接至放電選擇線(例如，Vg (dis)306)，其中此選擇線可用於在閘極處導通及關斷TFT (dis)304(例如，藉由經由選擇線施加電壓至電晶體的閘極，以影響閘極-源極或閘極-汲極電位)。在一個實施例中，用於多個像素的所有像素放電選擇線可以一起連接至單個顯示輸出，例如以同時導通顯示器之所有顯示像素的所有像素放電TFT(例如，TFT (dis)304)電晶體，以便進行整個顯示器的同時放電。在一些實施例中，TFT (upd)302及TFT (dis)304的源極線可以都連接至資料線Vs 310。在操作期間，TFT (dis)304可以為了所有像素被關斷，而TFT (upd)302用於顯示器的主動更新。在放電期間，TFT (dis)304可以被導通，而TFT (upd)302可以被關斷。在一些實施例中，TFT (upd)302及TFT (dis)304中之任一者或兩者可以是n型電晶體。在那種情況下，TFT (upd)302的源極可以電耦接至源極線Vs 310，而TFT (upd)302的汲極可以耦接至顯示像素300的像素電極312。此外，如果TFT (dis)304係n型電晶體，則其源極可耦接至源極線Vs 310，而其汲極可耦接至像素電極312。實際上，當TFT (dis)304被導通時，來自電泳膜314的電荷可以經由TFT (dis)304及/或源極線Vs 310排出或釋放。 An exemplary embodiment according to the above concept is illustrated in FIG. 3 . In addition to standard pixel TFTs (eg, TFT (upd) 302 ), display pixel 300 may include active components dedicated to draining residual voltage or excess charge from electrophoretic film 314 . The active component can be any type of transistor (eg, TFT, CMOS, etc.) or any other component that can be activated or turned on by the application of electrical energy (eg, voltage) or light energy, such as a diode or a photodetector /diode device or any general electrical/optical activated switch. To illustrate general concepts, TFTs (eg, n-type TFTs) are used here, but it should be understood that this is not meant to be limiting. As shown in FIG. 3 , the designated transistor TFT (dis) 304 can be used to discharge the charge of residual voltage in the electrophoretic imaging film 314 . In this configuration, the gate of TFT (upd) 302 is connected to a select line from the gate driver output (e.g. Vg (upd) 308), while the gate of TFT (dis) 304 is connected to a discharge select line (e.g. , Vg (dis ) 306), where this select line can be used to turn on and off the TFT (dis) 304 at the gate (for example, by applying a voltage to the gate of the transistor through the select line to affect the gate-source electrode or gate-drain potential). In one embodiment, all pixel discharge select lines for multiple pixels may be connected together to a single display output, e.g., to simultaneously turn on all pixel discharge TFT (e.g., TFT (dis) 304 ) transistors of all display pixels of the display , so that the entire display can be discharged simultaneously. In some embodiments, the source lines of TFT (upd) 302 and TFT (dis) 304 can both be connected to data line Vs 310 . During operation, TFT (dis) 304 can be turned off for all pixels, while TFT (upd) 302 is used for active updating of the display. During discharge, TFT (dis) 304 may be turned on and TFT (upd) 302 may be turned off. In some embodiments, either or both of TFT (upd) 302 and TFT (dis) 304 may be n-type transistors. In that case, the source of TFT (upd) 302 may be electrically coupled to source line Vs 310 , and the drain of TFT (upd) 302 may be coupled to pixel electrode 312 of display pixel 300 . In addition, if the TFT (dis) 304 is an n-type transistor, its source can be coupled to the source line Vs 310 , and its drain can be coupled to the pixel electrode 312 . Actually, when the TFT (dis) 304 is turned on, the charges from the electrophoretic film 314 can be discharged or released through the TFT (dis) 304 and/or the source line Vs 310 .

圖4例示依據本文提出之標的物的顯示像素400之另一個實施例。在此實施例中，如圖4所示，放電TFT (dis)402可以電耦接至EPD的頂板404(例如，連接至EPD的共同電極)及Vcom 406電壓線(例如，放電TFT 402的汲極直接耦接至EPD的頂板404，而其源極耦接至像素的像素電極408)。在這種配置中，顯示模組的放電不經過源極驅動器(例如，Vs 410)，而是直接經過頂板接線來完成。此外，使用這種設置，可以在更新期間藉由使放電TFT (dis)402處於弱導通狀態以充當用於放電的電阻或導電路徑來對顯示器進行放電，因為Vs 410在此情況下未連接至放電TFT (dis)402及因而不影響其操作。在此配置中，TFT (dis)402可以經由選擇線Vg (dis)412來進行啟動，而電晶體TFT (upd)414可以經由選擇線Vg (upd)416來進行啟動，其中兩條選擇線(亦即，可以選擇性地不使Vg (dis)412及Vg (upd)416電耦接)。 FIG. 4 illustrates another embodiment of a display pixel 400 in accordance with the subject matter presented herein. In this embodiment, as shown in FIG. 4, the discharge TFT (dis) 402 may be electrically coupled to the top plate 404 of the EPD (e.g., to the common electrode of the EPD) and the Vcom 406 voltage line (e.g., to the drain of the discharge TFT 402). The pole is directly coupled to the top plate 404 of the EPD, while its source is coupled to the pixel electrode 408 of the pixel). In this configuration, the discharge of the display module does not pass through the source driver (for example, Vs 410 ), but is directly completed through the top board wiring. Also, with this setup, the display can be discharged during refresh by leaving the discharge TFT (dis) 402 in a weak on-state to act as a resistive or conductive path for discharge, since Vs 410 is not connected to Discharging the TFT (dis) 402 and thus does not affect its operation. In this configuration, TFT (dis) 402 can be activated via select line Vg (dis) 412, and transistor TFT (upd) 414 can be activated via select line Vg (upd) 416, where the two select lines ( That is, Vg (dis) 412 and Vg (upd) 416 may be selectively decoupled).

圖5例示可適用於圖3及圖4中提出的兩種像素設計中之任一種的示例性電壓序列。所述電壓序列忽略從一個電壓切換至另一個電壓時可能出現或在例如電源切斷(power down)期間可能引進的RC時間限制。Vg (upd)連接至選擇線，就像在標準主動矩陣驅動中一樣，在高電壓與低電壓之間切換，以導通及關斷TFT。在主動更新期間，Vcom可以保持固定在通常等於TFT (upd)的回踢電壓(kickback voltage)之電壓。Vs連接至用於提供資料信號以用期望波形更新像素的資料線。Vg (dis)連接至低電壓，以保持TFT (dis)關斷。在主動更新後的放電期間，關閉Vg (upd)，並且Vcom及Vs保持在0V。打開Vg (dis)，以便經由TFT (dis)使電泳成像膜短路。圖5中所示的電壓序列是使用新的TFT像素設計之放電方案的示例性說明。這種新的TFT像素設計足夠靈活，以適應更複雜的放電方案的實施。主要概念是藉由使專用TFT導通來進行放電，同時將用於正常顯示操作的像素TFT排除在放電操作之外。次要影響可能包括TFT (dis)在放電結束時關斷的時候所經歷之回踢電壓可能會影響顯示器的放電效率或光學性能。可以藉由為具有一定RC衰減的Vg (dis)實施適當設計的斷電電路來減輕這樣的影響，以便防止或最小化這樣的影響。 FIG. 5 illustrates an exemplary voltage sequence applicable to either of the two pixel designs presented in FIGS. 3 and 4 . The voltage sequence ignores RC time constraints that may occur when switching from one voltage to another or may be introduced during eg power down. Vg (upd) is connected to the select line, which switches between high and low voltages to turn the TFTs on and off, as in standard active-matrix drives. During active refresh, Vcom can be kept fixed at a voltage typically equal to the kickback voltage of the TFT (upd) . Vs is connected to a data line for providing a data signal to update the pixels with the desired waveform. Vg (dis) is connected to a low voltage to keep TFT (dis) off. During discharge after active refresh, Vg (upd) is turned off, and Vcom and Vs are kept at 0V. Vg (dis) is turned on to short-circuit the electrophoretic imaging film via TFT (dis) . The voltage sequence shown in Figure 5 is an exemplary illustration of the discharge scheme using the new TFT pixel design. This new TFT pixel design is flexible enough to accommodate the implementation of more complex discharge schemes. The main concept is to perform discharge by turning on a dedicated TFT while excluding pixel TFTs used for normal display operation from the discharge operation. Secondary effects may include the kickback voltage experienced by the TFT (dis) when it turns off at the end of discharge, which may affect the discharge efficiency or optical performance of the display. Such effects can be mitigated by implementing a properly designed power down circuit for Vg (dis) with some RC attenuation in order to prevent or minimize such effects.

在上面的描述中，TFT (upd)及TFT (dis)都是N型TFT。這些電晶體亦可以都是P型TFT或者各別是N型TFT及P型TFT。根據圖3中的電路之一個實例顯示在圖6中，其中TFT (upd)604及TFT (dis)602係P型TFT。可以對圖4中的電路執行相同的操作(此處未顯示)。 In the above description, both TFT (upd) and TFT (dis) are N-type TFTs. These transistors can also all be P-type TFTs or be N-type TFTs and P-type TFTs respectively. An example of the circuit according to FIG. 3 is shown in FIG. 6, where TFT (upd) 604 and TFT (dis) 602 are P-type TFTs. The same can be done for the circuit in Figure 4 (not shown here).

或者，代替諸如TFT的主動組件，亦可以採用被動組件對EPD進行放電。圖7顯示本文提出之標的物的另一種可能實施方式，其中電阻器Rdis 702與像素的儲存電容器Cs 704並聯放置。如圖所示，電阻器Rdis 702亦耦接至像素電極706及共同電極708。此電阻器的用途是提供在一個驅動週期結束時從電泳成像膜釋放剩餘電壓的路徑。這種像素設計的益處在於不需要添加額外的線Vgdis來控制第二個TFT。然而，因為Rdis 702現在具有固定的電阻值，所以需要適當地設計Rdis 702的電阻值。例如，與將Rdis 702添加至包括像素電極及儲存電容器的像素電路相關聯之RC常數需要大於驅動訊框時間，以便在訊框時間內實現所需的像素電壓保持特性。RC常數亦需要足夠低，以在驅動週期結束時提供充分的放電。在一些其他實施例中，Rdis702亦可以以使用非晶矽的場可切換分路電阻器或提供與電泳成像膜並聯的適當電阻以用於放電而不妨礙正常驅動操作的任何其它技術來取代。除了提供一個僅用於放電的專用TFT及另一個僅用於顯示更新的TFT以避免因正偏壓應力而導致顯示性能的光學偏移之外，本文提出之標的物亦允許如下所述之有益的一些額外使用模式。Alternatively, instead of active components such as TFTs, passive components may also be used to discharge the EPD. Fig. 7 shows another possible implementation of the subject matter presented herein, where a resistor Rdis 702 is placed in parallel with the storage capacitor Cs 704 of the pixel. As shown, the resistor Rdis 702 is also coupled to the pixel electrode 706 and the common electrode 708 . The purpose of this resistor is to provide a path to discharge residual voltage from the electrophoretic imaging film at the end of a drive cycle. The benefit of this pixel design is that there is no need to add an extra line Vgdis to control the second TFT. However, since Rdis 702 now has a fixed resistance value, the resistance value of Rdis 702 needs to be properly designed. For example, the RC constant associated with adding Rdis 702 to the pixel circuit including the pixel electrode and storage capacitor needs to be greater than the drive frame time in order to achieve the desired pixel voltage retention characteristics within the frame time. The RC constant also needs to be low enough to provide sufficient discharge at the end of the drive cycle. In some other embodiments, Rdis 702 can also be replaced with a field switchable shunt resistor using amorphous silicon or any other technique that provides a suitable resistance in parallel with the electrophoretic imaging film for discharge without interfering with normal driving operation. In addition to providing a dedicated TFT for discharge only and another TFT for display refresh only to avoid optical shifts in display performance due to positive bias stress, the subject matter presented herein also allows for the beneficial Some additional usage patterns for .

圖8顯示僅適用於圖3所示之電路的示例性電壓序列，其中TFT upd302及TFT dis304具有專用閘極線。在此電壓序列中，TFT upd302及TFT dis304兩者在主動更新階段期間被導通，而為了放電TFT dis304在更新結束時可能被導通或不被導通。在這種使用模式下，TFT dis304可以為了可以允許例如更高的訊框率驅動之更快的像素充電而提供額外的電流。再者，在所提出的像素設計中之TFT dis304亦可以用作全域更新電晶體。藉由導通TFT dis304及關斷TFT upd302，我們可以防止在執行全域更新時TFT upd302上的長期正偏壓。 Figure 8 shows an exemplary voltage sequence applicable only to the circuit shown in Figure 3, where TFT upd 302 and TFT dis 304 have dedicated gate lines. In this voltage sequence, both TFT upd 302 and TFT dis 304 are turned on during the active refresh phase, while TFT dis 304 may or may not be turned on at the end of the refresh for discharge. In this mode of use, the TFT dis 304 may provide additional current for faster pixel charging which may allow eg higher frame rate drives. Furthermore, the TFT dis 304 in the proposed pixel design can also be used as a global update transistor. By turning on TFT dis 304 and turning off TFT upd 302, we can prevent long-term positive bias on TFT upd 302 when performing a global update.

圖9例示本文揭露之標的物的另一個實施例。與圖7中呈現的設置類似，顯示設備900可以使用連接FPL 904層的兩端之電阻器Rd 902，以釋放殘留電荷及/或殘留電壓，從而使像素TFT 906免除因必須導通以釋放殘留電荷而引起的額外應力及裝置退化。在一些實施例中，電阻器Rd 902可以與儲存電容器Cs 908並聯放置，以產生用於排出殘留電荷的路徑。或者，儲存電容器Cs 908本身可以構造成是「漏電的」及提供用於排出殘留電荷的路徑。其中，術語「漏電的」在本文中被定義為電容器(例如，Cs 908)的介電電阻已經降低到電容器可以歐姆傳導足夠電流以允許殘留電荷被排出或釋放的程度。FIG. 9 illustrates another embodiment of the subject matter disclosed herein. Similar to the setup presented in FIG. 7, the display device 900 may use a resistor Rd 902 connected across the FPL 904 layer to discharge the residual charge and/or residual voltage, thereby exempting the pixel TFT 906 from having to be turned on to discharge the residual charge The additional stress and device degradation caused by it. In some embodiments, resistor Rd 902 may be placed in parallel with storage capacitor Cs 908 to create a path for draining residual charge. Alternatively, storage capacitor Cs 908 may itself be configured to be "leakage" and provide a path for draining residual charge. Therein, the term "leakage" is defined herein as a capacitor (eg, Cs 908 ) whose dielectric resistance has been reduced to the point that the capacitor can ohmically conduct sufficient current to allow residual charge to be drained or released.

實際上，電阻器Rd的電阻值或電容器的介電電阻值可以被選擇為FPL 904層的電阻之1/3至3倍之間，或者 R FPL/3＜Rd＜R FPL*3 其中R FPL是FPL 904層的電阻。圖10及圖11例示殘留電荷釋放的一些實驗資料。圖10a顯示一個實驗裝置，其中FPL測試玻璃連接至外部電路，以模擬在主動矩陣顯示器上具有與儲存電容器(例如，Cs=7nF/cm 2)並聯之電阻路徑(Rd)的效果。並且，在-15V下為了25個訊框進行驅動的直流不平衡波形之後是如圖10b所示的接地訊框(grounding frame)，或者如圖10c所示之沒有將接地訊框施加於實驗電路。圖10d例示每個訊框包括將FPL電壓VFPL保持在期望位準達1ms，然後浮動(亦即，沒有電流施加至電路)達9ms，以模擬主動矩陣驅動方案。其中，如本文所述的前平面積層板或FPL層可以包括透光導電層；與導電層電接觸的固體電光介質層；黏著層；以及離型片。在一些其它實施例中，FPL層可以包括另一個透光導電層來代替離型片。 In practice, the resistance value of the resistor Rd or the dielectric resistance value of the capacitor can be chosen to be between 1/3 and 3 times the resistance of the FPL 904 layer, or R FPL /3<Rd<R FPL *3 where R FPL is the resistance of the FPL 904 layer. 10 and 11 illustrate some experimental data of residual charge release. Figure 10a shows an experimental setup where the FPL test glass is connected to an external circuit to simulate the effect of having a resistive path (Rd) in parallel with a storage capacitor (eg, Cs = 7nF/cm 2 ) on an active matrix display. And, the DC unbalanced waveform driven for 25 frames at -15V is followed by a grounding frame as shown in Figure 10b, or no grounding frame is applied to the experimental circuit as shown in Figure 10c . Figure 10d illustrates that each frame includes holding the FPL voltage VFPL at the desired level for 1 ms and then floating (ie, no current applied to the circuit) for 9 ms to simulate an active matrix driving scheme. Wherein, the front plane build-up board or FPL layer as described herein may include a light-transmitting conductive layer; a solid electro-optical medium layer electrically contacting with the conductive layer; an adhesive layer; and a release sheet. In some other embodiments, the FPL layer may include another light-transmitting conductive layer instead of a release liner.

得到的測量FPL電壓呈現在圖11a至11e中。其中，圖11a例示在驅動階段期間之測量FPL電壓，而圖11b例示在驅動階段期間的顯示亮度；圖11c例示在浮動階段期間之測量FPL電壓，而圖11d例示在浮動階段期間的亮度；以及圖11e例示針對四個不同Rd值及兩個不同測試波形在浮動階段結束時測量的FPL電壓(亦即，殘留電荷)。The resulting measured FPL voltages are presented in Figures 11a to 11e. Among them, Figure 11a illustrates the measured FPL voltage during the driving phase, while Figure 11b illustrates the display brightness during the driving phase; Figure 11c illustrates the measured FPL voltage during the floating phase, and Figure 11d illustrates the brightness during the floating phase; and Figure 11e illustrates the measured FPL voltage (ie, residual charge) at the end of the float phase for four different Rd values and two different test waveforms.

從實驗資料可以看出，較小的Rd電阻值可能會在浮動階段期間產生更快的FPL電壓衰減，從而導致較小的殘留電壓積累。然而，亦希望Rd不要太小，以免在驅動階段期間因儲存電容器Cs放電過快而導致墨水切換速度的下降，這會在浮動階段期間導致更多的光學回踢。因此，儲存電容器的電容通常被選擇成足以在訊框時間(Cs*R FPL＞＞訊框時間)期間維持FPL電壓，並且Rd的電阻值與FPL電阻值R FPL相比最好不要太小，以防止FPL電壓在訊框時間期間快速放電而導致在驅動階段期間墨水速度的損失。當然，Rd的電阻值與R FPL電阻值相比亦不能太大，否則會削弱具有這種被動放電路徑的益處。 From the experimental data, it can be seen that a smaller Rd resistance value may produce a faster FPL voltage decay during the floating phase, resulting in a smaller residual voltage accumulation. However, it is also desirable that Rd is not too small to avoid a drop in ink switching speed due to too fast discharge of the storage capacitor Cs during the drive phase, which would cause more optical kickback during the float phase. Therefore, the capacitance of the storage capacitor is usually chosen to be sufficient to maintain the FPL voltage during the frame time (Cs*R FPL >> frame time), and the resistance value of Rd is preferably not too small compared to the FPL resistance value R FPL , To prevent the rapid discharge of the FPL voltage during the frame time resulting in loss of ink velocity during the drive phase. Of course, the resistance value of Rd should not be too large compared to the resistance value of R FPL , otherwise the benefit of having such a passive discharge path will be weakened.

在一些實施例中，Rd的電阻值或儲存電容器的歐姆電阻可以被選擇為 R FPL/3＜Rd＜R FPL*3 ，以實現殘留電壓降低，同時維持光學性能。在一些其它實施例中，可以將Rd或儲存電容器的歐姆電阻值設定為與R FPL值大致相同。例如，儲存電容器的歐姆電阻可以構造成在R FPL值的90%至110%之間；或者儲存電容器的歐姆電阻可以構造成在R FPL值的80%至120%之間；或者儲存電容器的歐姆電阻可以構造成在R FPL值的70%至130%之間；或者儲存電容器的歐姆電阻可以構造成在R FPL值的50%至150%之間；或者儲存電容器的歐姆電阻可以構造成大約在R FPL值的三分之一至三倍之間。再者，如圖11e所示，這種配置允許殘留電壓的釋放，同時無需使用接地訊框來結束波形。例如，再次參考圖11e，對於具有RFPL~24MΩcm 2的電阻R FPL之FPL，相較於Rd=∞及波形以接地訊框作為結束的情況，約15MΩcm 2的Rd即使在沒有以接地訊框來結束波形時亦可以將積累的殘留電壓降低80%。此外，這種配置亦減少光學回踢且允許白色狀態更白(參見圖11d)，從而實現更佳的對比度。 In some embodiments, the resistance value of Rd or the ohmic resistance of the storage capacitor may be selected such that R FPL /3<Rd<R FPL *3 to achieve residual voltage reduction while maintaining optical performance. In some other embodiments, the value of Rd or the ohmic resistance of the storage capacitor may be set to be approximately the same as the R FPL value. For example, the ohmic resistance of the storage capacitor can be configured to be between 90% and 110% of the R FPL value; or the ohmic resistance of the storage capacitor can be configured to be between 80% and 120% of the R FPL value; or the ohmic resistance of the storage capacitor The resistor can be configured to be between 70% and 130% of the value of R FPL ; or the ohmic resistance of the storage capacitor can be configured to be between 50% and 150% of the value of R FPL ; or the ohmic resistance of the storage capacitor can be configured to be between approximately Between one-third and three times the R FPL value. Furthermore, as shown in Fig. 11e, this configuration allows the discharge of the residual voltage without using a ground frame to end the waveform. For example , referring again to FIG. 11e , for an FPL with a resistance R FPL of RFPL~24MΩcm 2 , an Rd of about 15MΩcm even without a ground frame is compared to Rd=∞ and the waveform ends with a grounded frame It can also reduce the accumulated residual voltage by 80% when ending the waveform. Furthermore, this configuration also reduces optical kickback and allows whiter states to be whiter (see Figure 11d), resulting in better contrast.

在一些實施例中，本文所述的Rd放電路徑可以藉由使像素儲存電容器成「漏電的」來實現，其中儲存電容器的介電電阻已降低到電容器可以歐姆傳導足夠電流以允許殘留電荷被排出或釋放的程度。現在參考圖12，顯示像素1200可以包括位於玻璃基板1206上且與儲存電容器1204相鄰的像素TFT 1202。其中，TFT 1202可以包括源極1206、汲極1210及閘極1212。儲存電容器1204可以經由像素電極1214(例如，ITO)連接至TFT 1202的汲極1210。在此配置中，儲存電容器1204可以例如摻雜有摻質以充分降低其介電電阻，以便允許殘留電荷被釋放。In some embodiments, the Rd discharge path described herein can be achieved by making the pixel storage capacitor "leaky", where the dielectric resistance of the storage capacitor has been reduced to the point where the capacitor can ohmically conduct enough current to allow residual charge to be drained or degree of release. Referring now to FIG. 12 , a display pixel 1200 may include a pixel TFT 1202 on a glass substrate 1206 adjacent to a storage capacitor 1204 . Wherein, the TFT 1202 may include a source 1206 , a drain 1210 and a gate 1212 . The storage capacitor 1204 may be connected to the drain 1210 of the TFT 1202 via a pixel electrode 1214 (eg, ITO). In this configuration, the storage capacitor 1204 may, for example, be doped with a dopant to lower its dielectric resistance sufficiently to allow residual charge to be released.

或者，可以將附加電容器添加至顯示像素並構造成是漏電的以產生用於釋放殘留電壓的路徑。現在參考圖13，放電電容器1302可以與儲存電容器1304並聯放置，並且放電電容器1302可構造成是漏電的，使得它可以歐姆傳導足夠的電流，以允許殘留電荷被釋放。實際上，現在參考圖14，放電電容器1400可以位於同一個基板1402上且與儲存電容器1404及像素TFT 1406相鄰。TFT 1406可以具有源極1408、汲極1410及閘極1412，其中汲極1410可以經由像素電極1414電耦接至放電電容器1400及儲存電容器1404。Alternatively, additional capacitors can be added to the display pixels and configured to be leaky to create a path for discharging residual voltage. Referring now to FIG. 13 , discharge capacitor 1302 may be placed in parallel with storage capacitor 1304 , and discharge capacitor 1302 may be configured to be leaky such that it can ohmically conduct sufficient current to allow residual charge to be discharged. Indeed, referring now to FIG. 14 , discharge capacitor 1400 may be located on the same substrate 1402 adjacent to storage capacitor 1404 and pixel TFT 1406 . The TFT 1406 can have a source 1408 , a drain 1410 and a gate 1412 , wherein the drain 1410 can be electrically coupled to the discharge capacitor 1400 and the storage capacitor 1404 via the pixel electrode 1414 .

熟悉該項技藝者將顯而易見的是，在不脫離本發明的範圍之情況下，可以對上述本發明的具體實施例進行多種改變及修改。於是，前面描述的全部內容應該被解釋為例示性的而不是限制性的。It will be apparent to those skilled in the art that various changes and modifications can be made to the specific embodiments of the invention described above without departing from the scope of the invention. Accordingly, the entirety of the foregoing description should be interpreted as illustrative and not restrictive.

100:薄膜電晶體(TFT)背板 102:薄膜電晶體UPD 104:像素電極 106:頂板 108:電泳材料 300:顯示像素 302:TFT (upd)304:電晶體TFT (dis)306:Vg (dis)308:Vg (upd)310:資料線Vs(源極線Vs) 312:像素電極 314:電泳膜 400:顯示像素 402:放電TFT (dis)404:頂板 406:Vcom 408:像素電極 410:Vs 412:選擇線Vg (dis)414:電晶體TFT (upd)416:選擇線Vg (upd)602:TFT (dis)604:TFT (upd)702:電阻器Rdis 704:儲存電容器Cs 706:像素電極 708:共同電極 900:顯示設備 902:電阻器Rd 904:FPL 906:像素TFT 908:儲存電容器Cs 1200:顯示像素 1202:像素TFT 1204:儲存電容器 1206:源極 1208:玻璃基板 1210:汲極 1212:閘極 1214:像素電極 1302:放電電容器 1304:儲存電容器 1400:放電電容器 1402:基板 1404:儲存電容器 1406:像素TFT 1408:源極 1410:汲極 1412:閘極 1414:像素電極 Vs:源極(或資料)線 100: thin film transistor (TFT) backplane 102: thin film transistor UPD 104: pixel electrode 106: top plate 108: electrophoretic material 300: display pixel 302: TFT (upd) 304: transistor TFT (dis) 306: Vg (dis ) 308: Vg (upd) 310: data line Vs (source line Vs) 312: pixel electrode 314: electrophoretic film 400: display pixel 402: discharge TFT (dis) 404: top plate 406: Vcom 408: pixel electrode 410: Vs 412: Selection line Vg (dis) 414: Transistor TFT (upd) 416: Selection line Vg (upd) 602: TFT (dis) 604: TFT (upd) 702: Resistor Rdis 704: Storage capacitor Cs 706: Pixel electrode 708: common electrode 900: display device 902: resistor Rd 904: FPL 906: pixel TFT 908: storage capacitor Cs 1200: display pixel 1202: pixel TFT 1204: storage capacitor 1206: source 1208: glass substrate 1210: drain 1212 : gate 1214: pixel electrode 1302: discharge capacitor 1304: storage capacitor 1400: discharge capacitor 1402: substrate 1404: storage capacitor 1406: pixel TFT 1408: source 1410: drain 1412: gate 1414: pixel electrode Vs: source (or data) line

圖1係依據本文提出之標的物的顯示像素之等效電路的一個實施例；FIG. 1 is an embodiment of an equivalent circuit of a display pixel according to the subject matter proposed herein;

圖2A及2B係例示由於TFT性能變化所引起之顯示器的灰調及重影偏移之曲線圖；2A and 2B are graphs illustrating gray tone and ghost shift of a display caused by changes in TFT performance;

圖3係依據本文提出之標的物的示例性像素設計，以能夠在不引入光學偏移的情況下使用後驅動放電(post-drive discharging)；Figure 3 is an exemplary pixel design in accordance with the subject matter presented herein to enable the use of post-drive discharging without introducing optical offset;

圖4係依據本文提出之標的物的另一種像素設計，以能夠在不引入光學偏移的情況下使用後驅動放電；Figure 4 is another pixel design according to the subject matter proposed herein to enable the use of post-drive discharge without introducing optical offset;

圖5係主動更新後進行發電的電壓序列；Figure 5 is the voltage sequence for power generation after active updating;

圖6係依據本文提出之標的物的另一種像素設計，以能夠在不引入光學偏移的情況下使用後驅動放電；Figure 6 is another pixel design according to the subject matter proposed herein to enable the use of post-drive discharge without introducing optical offset;

圖7係依據本文提出之標的物的又另一種像素設計，以能夠在不引入光學偏移的情況下使用後驅動放電；Figure 7 is yet another pixel design in accordance with the subject matter presented herein to enable the use of post-drive discharge without introducing optical offset;

圖8係主動更新後進行放電的電壓序列；Figure 8 is the voltage sequence for discharging after active updating;

圖9係依據本文提出之標的物的另一種像素設計；Figure 9 is another pixel design based on the subject matter proposed in this paper;

圖10a例示一種用於測量FPL電壓的實驗裝置；Figure 10a illustrates an experimental setup for measuring FPL voltage;

圖10b至10c例示使用圖10a中所例示之裝置測量的FPL電壓；Figures 10b to 10c illustrate FPL voltages measured using the device illustrated in Figure 10a;

圖10d例示在驅動階段期間模擬的主動矩陣驅動之一個實例；Figure 10d illustrates an example of an active matrix drive simulated during the drive phase;

圖11a至11e例示使用圖10a中所述之裝置以不同Rd值測量的FPL電壓及顯示亮度；Figures 11a to 11e illustrate FPL voltage and display brightness measured at different values of Rd using the device described in Figure 10a;

圖12例示依據本文提出之標的物的顯示像素之一種配置的剖面圖；Figure 12 illustrates a cross-sectional view of one configuration of display pixels in accordance with the subject matter presented herein;

圖13例示依據本文提出之標的物的又另一種像素設計；以及Figure 13 illustrates yet another pixel design in accordance with the subject matter presented herein; and

圖14例示依據本文提出之標的物的顯示像素之另一種配置的剖面圖。14 illustrates a cross-sectional view of another configuration of display pixels in accordance with the subject matter presented herein.

100:薄膜電晶體(TFT)背板 100: Thin film transistor (TFT) backplane

102:薄膜電晶體UPD 102: Thin film transistor UPD

104:像素電極 104: Pixel electrode

106:頂板 106: top plate

108:電泳材料 108: Electrophoretic material

Claims (6)

一種電泳顯示器，其具有複數個顯示像素，該複數個顯示像素中的每一者包括： 一像素電極，用於驅動該顯示像素； 一單個薄膜電晶體(TFT)，其耦接至該像素電極，用於傳送波形至該像素電極； 一前平面積層板(FPL)，其耦接至該單個薄膜電晶體；以及 一儲存電容器，其耦接至該像素電極且與該FPL並聯放置， 其中該儲存電容器係構造成具有足夠的歐姆導電性以允許從該FPL經由該儲存電容器進行殘留電壓放電。 An electrophoretic display having a plurality of display pixels, each of the plurality of display pixels comprising: a pixel electrode for driving the display pixel; a single thin film transistor (TFT), which is coupled to the pixel electrode and used to transmit a waveform to the pixel electrode; a front plane build-up (FPL) coupled to the single thin film transistor; and a storage capacitor coupled to the pixel electrode and placed in parallel with the FPL, Wherein the storage capacitor is configured to have sufficient ohmic conductivity to allow residual voltage discharge from the FPL via the storage capacitor. 如請求項1之電泳顯示器，其中該儲存電容器的電阻與該FPL的電阻大致相同。The electrophoretic display according to claim 1, wherein the resistance of the storage capacitor is substantially the same as the resistance of the FPL. 如請求項1之電泳顯示器，其中該儲存電容器的電阻值介於該FPL的電阻之三分之一與三倍之間。The electrophoretic display according to claim 1, wherein the resistance of the storage capacitor is between one-third and three times the resistance of the FPL. 如請求項1之電泳顯示器，進一步包括與該儲存電容器並聯的一放電電容器。The electrophoretic display according to claim 1, further comprising a discharge capacitor connected in parallel with the storage capacitor. 如請求項1之電泳顯示器，其中該FPL包含一電泳材料。The electrophoretic display according to claim 1, wherein the FPL comprises an electrophoretic material. 如請求項5之電泳顯示器，其中該電泳材料包括一膠囊化電泳材料，該膠囊化電泳材料包含在一流體介質中的帶電顏料粒子。The electrophoretic display according to claim 5, wherein the electrophoretic material comprises an encapsulated electrophoretic material comprising charged pigment particles in a fluid medium.
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