TW202310091A - 具有深金屬線的半導體結構及用於形成該半導體結構的方法 - Google Patents
具有深金屬線的半導體結構及用於形成該半導體結構的方法 Download PDFInfo
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Abstract
一半導體結構包括基板、介電層、第一導電特徵件和第二導電特徵件。該基板包括半導體裝置。該介電層設置於該基板上。該第一導電特徵件形成於該介電層中。該第二導電特徵件穿透該第一導電特徵件與該介電層,且電性連接至該第一導電特徵件與該半導體裝置。
Description
本揭露內容實施例係有關於具有深金屬線的半導體結構及用於形成該半導體結構的方法。
半導體積體電路(IC)工業在過去幾十年經歷極大進展,且仍在經歷著蓬勃的發展。隨著IC設計的顯著進步,新世代的積體電路具有更小且更複雜的電路。鑲嵌製程,例如單鑲嵌或雙鑲嵌,是用於形成BEOL(後段製程)互連線結構的技術中的一種。互連線結構對於新世代IC的小型化及電氣效能扮演重要角色。因此,業界非常著重於互連線結構的發展。
本揭露內容的一態樣係提出一種半導體結構,包括一基板、一介電層、一第一導電特徵件、與一第二導電特徵件。該基板包括一半導體裝置。該介電層設置於該基板上。該第一導電特徵件形成於該介電層中。該第二導電特徵件穿透該第一導電特徵件與該介電層,且電性連接至該第一導電特徵件與該半導體裝置。
本揭露內容的另一態樣係提出一種半導體結構,包括一基板、一第一介電層、一互連線結構、與一第二導電特徵件。基板包含一電晶體。該第一介電層設置於該基板上。該互連線結構包括:一第一導電特徵件,其設置於該第一介電層上並相反於該基板;以及一第二介電層,其圍繞該第一導電特徵件。該第二導電特徵件穿透該互連線結構,且電性連接至該第一導電特徵件與該電晶體。
本揭露內容的又一態樣係提出一種半導體結構的製造方法,包含:提供一基板,其包含一半導體裝置;在該基板上形成一介電層;在該介電層中形成一第一導電特徵件,該第一導體特徵件與該基板分開;形成一通孔,其穿透該第一導電特徵件及該介電層以暴露出該半導體裝置之一接觸件;以及在該通孔中形成一第二導電特徵件,使該第二導電特徵件電性連接至該半導體裝置的該第一導電特徵件及該接觸件。
以下揭露內容提供許多不同實施例或範例,用於實現本揭露的不同特徵。為簡化本揭露,以下描述具體的元件及排列的具體例子。當然,這些僅為範例且非意欲作為限制。舉例來說,在以下敘述中,一第一特徵件形成於一第二特徵件之上或上方,可能包含形成直接接觸的第一與第二特徵件的實施例,亦可能包含有形成於第一與第二特徵件之間的附加特徵的實施例,而使第一與第二特徵件可能未直接接觸。此外,本揭露可能會在不同例子中重複參考符號和/或字母。前述作法本身並不表示所討論的各種實施例及/或配置之間的關係。
此外,為便於描述,可在本文中使用諸如「在...下面」、「在...下方」、「下」、「在...上方」、「上」及類似者之空間相對術語來描述如圖所說明之一個元件或特徵與另一(些)元件或特徵之關係。除圖形中描繪之方向外,空間相對用語意圖是涵蓋裝置在使用或操作中之不同的方向。設備可被以其他方式定向(旋轉90度或其他方位),且文中所使用的空間相對形容詞也將據此來解釋。
圖1至4係說明形成半導體結構的步驟之示意圖。
參考圖1,提供基板10,其形成有複數個電晶體101,每一個電晶體包括源極102、汲極103、連接在源極102與汲極103之間的通道104及閘極105。電晶體101可藉由隔離特徵件106分離,如淺溝槽隔離(STI)或類似者。然後在基板10上形成第一介電層11,接著將第一介電層11圖案化以形成通孔111,以暴露出電晶體101中的至少一者之源極102、汲極103和閘極105的至少一者。參考圖2,在形成及圖案化第一介電層11之後,藉由合適的沉積技術,例如化學氣相沉積(CVD)或類似者,在第一介電層11與通孔111 (見圖1)中沉積導電材料,以填充通孔111,而後進行合適的平坦化技術,例如化學機械拋光(CMP)或類似者,以將沉積的導電材料薄化,以在通孔111 (見圖1)中形成接觸插塞12。參考圖3,在形成接觸插塞12之後,在第一介電層11上形成第二介電層13,接著將第二介電層13圖案化,以形成通孔131,以暴露出接觸插塞12。在第一介電層11中形成多個通孔111且隨後在此等通孔111中形成多個接觸插塞12之情況下,藉由圖案化第二介電層13形成之通孔131可暴露接觸插塞12之一或多者。參考圖4,在形成及圖案化第二介電層13之後,藉由諸如物理氣相沉積或類似者之合適沉積技術在第二介電層13上沉積導電材料以填充通孔131(見圖3),繼之以執行諸如CMP或類似者的合適平坦化技術以薄化經沉積的導電材料以形成導線14。
圖6示意性地說明出半導體結構300的佈局,其包括複數個半導體裝置(例如電晶體301)。每一個半導體裝置包括至少兩個MD結構302和一MG結構303。在一些實施例中,MD指的是OD(oxide-defining region,氧化物定義區域)上金屬,其可連接至一個電晶體301的源極或汲極區(未繪示)。在一些實施例中,MG是指金屬閘極,其可由金屬或多晶矽製成,且是一個電晶體301的閘極結構的一部分。圖7至圖16說明根據一些實施例的形成半導體結構300的中間步驟的示意圖。圖7至圖16中之各者顯示在製造半導體結構300期間分別從圖6之線AA及BB截取的兩個示意性剖視圖。對應的製程也反映在圖5所示的流程圖200中。
參考圖6與圖7,依據某些實施例,提供一基板30。此製程被說明於圖5所示流程圖200中的製程202。在一些實施例中,電晶體301部分形成於基板30中。在一些實施例中,基於實際應用,電晶體301之各者可為互補式金屬氧化物半導體(complementary metal-oxide semiconductor;CMOS)電晶體、平面或垂直多閘極電晶體(例如,FinFET裝置)、環繞式閘極(gate-all-around;GAA)裝置、記憶體元件(例如,NAND快閃記憶體、NOR快閃記憶體,或類似者)或類似者。於一些實施例中,基板30可為半導體基板,例如元素半導體(elemental semiconductor)或化合物半導體(compound semiconductor)。元素半導體由單一種類的原子組成,例如在週期表IV族中的矽(Si)與鍺(Ge)。化合物半導體由二或更多個元素組成,諸如碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)、矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)、磷砷化鎵銦(GaInAsP)或類似物。化合物半導體可具有梯度特徵,其中組成由一位置之一比例改變為在化合物半導體中之另一位置的另一比例。化合物半導體可形成於矽基板上。化合物半導體可為應變的。在一些實施例中,基板30可包括多層的化合物半導體結構。或者,基板30可包含非半導體材料,例如玻璃、熔融石英或氟化鈣。再者,在某些實施例中,基板30可為絕緣層上半導體(SOI)(例如絕緣層上矽鍺(SGOI))。一般而言,SOI基板包括一層半導體材料如磊晶矽(Si)、鍺(Ge),矽鍺(SiGe),或其等的組合。如本技術領域中已知的,基板30可摻雜p型摻質如硼(Br)、鋁(Al)、鎵(Ga)、或類似者,或亦可摻雜n型摻質。在一些實施例中,基板30可包括摻雜磊晶層。淺溝槽隔離(shallow trench isolation, STI)區域(未繪示)可形成於基板30內,以隔離基板30內的主動區。此外,可形成延伸進入基板30的穿孔(through-vias)(未繪示),以電性連接基板30之相對側上的特徵件。
根據一些實施例,每一電晶體301的源極區和汲極區和MG結構303的頂部可形成有矽化物特徵件(未繪示),以改善與後續形成的電性連接特徵件的電性連接。在一些實施例中,矽化物特徵件可以包括鈷矽化物(cobalt silicide)、鈦矽化物(titanium silicide)、鎢矽化物(tungsten silicide)、鎳矽化物(nickel silicide)、鉬矽化物(molybdenum silicide)、鉭矽化物(tantalum silicide)、鉑矽化物(platinum silicide)、鈀矽化物(palladium silicide),或類似者。在一些實施例中,MD結構302與MG結構303可被複數個間隔物304、305隔開,其可由合適的材料製成,例如氮化矽、氧化矽或類似者。在一些實施方式中,間隔物304及305可由不同材料製備。
依據一些實施例,電晶體301中每一者的MG結構303可被第一介電層331(可被稱為第一自對準接觸(SAC)介電體或SAC1層)覆蓋,且電晶體301中每一者的MD結構302可被第二介電層332(可被稱為第二自對準接觸(SAC)介電體或SAC2層)覆蓋。在一些實施例中,第一介電層331和第二介電層332可被第三介電層333(可以被稱為層間介電 (ILD2)層)覆蓋。第一、第二和第三介電層331、332、333中的每一者可包括多個子層(未繪示),且可由適當的介電材料製成,例如氧化矽、氮化矽、碳化矽(包括未摻雜碳化矽(UDC)、摻雜氧的碳化矽(ODC)、摻雜氮的碳化矽(NDC)或類似者)、氮氧化矽(silicon oxynitride)、碳氧化矽(silicon oxycarbide)(包括SiOCH) 、碳氮化矽(silicon carbonitride)、碳氧化矽的氮化物(silicon oxycarbide nitride)、氧化鋁、氮氧化鋁(aluminum oxynitride)、氮化鋁、氧化鋯、氮氧化鋁鋯 (zirconium aluminum oxynitride)、非晶矽或其等的組合。在一些實施例中,氧化矽可由四乙基正矽酸鹽(TEOS)所製成。在一些實施例中,第一介電層331、第二介電層332以及第三介電層333可由不同材料製成。第一介電層331、第二介電層332、與第三介電層333各自的形成方法可為任何合適製程如CVD(例如可流動CVD(FCVD)、低壓CVD(LPCVD)、電漿增強CVD(PECVD)、或類似者)、PVD、ALD、旋轉塗佈、及/或其他合適技術,且可具有任何合適厚度。
參考圖6與圖8,根據一些實施例,形成第一導電特徵件341於第三介電層333上。此製程於圖5所示流程圖200中的製程204被說明。在一些實施例中,在形成第一導電特徵件341之前,黏著層342可形成於第三介電層333上,且可包含鉭、氮化鉭、鈷、釕、鈦、氮化鈦、氮化錳、鎢、鋁、鉬、銥、銠、石墨烯、導電自組裝單層體或類似者。可使用合適的技術沉積黏著層342,像是PVD、CVD、原子層沉積(ALD)等。在一些實施例中,第一導電特徵件341為金屬層,且可由銅、釕、鎢、鈦、鋁、鈷、鉬、銥、銠、鈷-鎢-磷(cobalt-tungsten-phosphorus)、其等的組合、或類似物製成。在一些實施例中,第一導電特徵件341可由合適技術所形成,比如PVD、CVD、ALD、無電沉積(ELD)、PVD及電化學電鍍(ECP)的組合、或類似者。
參考圖9,在形成黏著層342與第一導電特徵件341之後,於第一導電特徵件341上形成遮罩層35。之後,將遮罩層35圖案化為所期望的形狀。此製程說明於圖5所示的流程圖200中的製程206。在一些實施例中,遮罩層35可具有範圍自約50 Å至約400 Å的厚度。根據一些實施例,遮罩層35可包括多個子層(如第一子層352與第二子層353),其各自由合適的材料組成,比如氮化鈦、氧化矽、氮化矽、氮氧化矽(silicon oxynitride)、碳化鎢、氮化鉭、矽(如非晶矽)、碳氧化矽(silicon oxycarbide)(包括SiOCH)、碳化矽(silicon carbide)(包括UDC、ODC、NDC或類似者)、或其等的組合。在一些實施例中,第一子層352可由氮化矽製成,並且第二子層353可以由氮化鈦製成。遮罩層35的可由合適的技術形成,比如旋轉塗佈、CVD(如FCVD、LPCVD、PECVD、或類似者)、ALD、或類似者。
根據一些實施例,光阻(未繪示)可用於圖案化遮罩層35。先於遮罩層35上形成光阻,接著採用圖案化遮罩圖案化光阻。光阻可包括光敏材料,當曝露於光時其經歷性質改變。性質改變可在微影圖案化製程中選擇性地移除光阻曝光部份或未曝光部份。在一些實施例中,微影系統將光阻暴露至輻射。通過圖案化遮罩的輻射光照射光阻,以藉此將圖案化遮罩的佈局轉移至光阻。在一些實施例中,使用直接寫入或無遮罩微影技術,例如雷射圖案化、電子束圖案化、離子束圖案化或類似者,將光阻圖案化。在曝光步驟後,接著使光阻顯影,保留光阻的曝光部份,或在其他範例中,保留光阻的未曝光部份。在一些實施例中,圖案化製程可包括多個步驟,比如光阻的軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、與乾燥(如硬烘烤)。該等步驟之每一者可根據實際需求重複或省略。圖案化的光阻暴露出遮罩層35將被蝕刻的部分。在一些實施例中,蝕刻製程可包含非等向(如方向性)蝕刻,其被配置以垂直蝕刻穿過遮罩層35而實質上不水平蝕刻。因此,蝕刻製程可包括任何適合的蝕刻技術,例如乾蝕刻、濕蝕刻、反應離子蝕刻(RIE)、灰化或類似者。蝕刻製程可使用任何合適的蝕刻劑,且特定的蝕刻劑或複數蝕刻劑可取決於所使用的遮罩層35的材料。
參考圖10,在形成並圖案化遮罩層35之後,採用圖案化的遮罩層35作為遮罩,圖案化第一導電特徵件341以形成通孔結構343。根據一些實施例,在此步驟中亦圖案化黏著層342。此製程說明於圖5所示的流程圖200中的製程208。第一導電特徵件341由合適的技術如含氯的氧化電漿或類似者進行圖案化。在一些實施例中,黏著層342或第三介電層333可作為蝕刻第一導電特徵件341的蝕刻停止層。
參考圖11,在圖案化第一導電特徵件341之後,於遮罩層35上形成第四介電層36並填入通孔結構343(見圖10)。此製程說明於圖5所示流程圖200中的製程212。在一些實施例中,氣隙361可被形成,且可鄰近或鄰接於第一導電特徵件341。在某些實施例中,氣隙361可由第四介電層36、第一導電特徵件341、及第三介電層333所定義。第四介電層36係由合適的介電材料形成,例如氧化矽、氮化矽、碳化矽(包括UDC、ODC、NDC或類似者)、氮氧化矽(silicon oxynitride)、碳氧化矽(silicon oxycarbide) (包括SiOCH)、碳氧化矽的氮化物(silicon oxycarbide nitride)、氧化鋁、氮氧化鋁、氮化鋁、氧化鋯、氮氧化鋁鋯(zirconium aluminum oxynitride)、非晶矽或其等的組合。在一些實施例中,二氧化矽可由TEOS製成。介電層36可使用合適的技術形成,像是旋轉塗佈、CVD(例如FCVD、LPCVD、PECVD、或類似者)、ALD、或類似者。
根據一些實施例,在形成介電層36之前,可保形地(conformally)形成阻障/襯墊層37,以覆蓋圖案化的遮罩層35並且環繞通孔結構343 (見圖10)。此製程說明於圖5所示之流程圖200中的製程210。在一些實施例中,阻障/襯墊層37由合適的氧化物材料、ODC、氮化矽(例如碳氮化矽)、氧化鋁、氮化鋁或類似者製成,且可透過合適的技術形成,例如CVD(例如FCVD、LPCVD、PECVD或類似者)、ALD(包含電漿增強ALD(PEALD))或類似者。
參考圖12,在形成介電層36之後,對介電層36和阻障/襯墊層37進行合適的平坦化製程,例如電漿乾蝕刻、CMP或類似者。此製程說明於圖5所示的流程圖200中的製程214。在一些實施例中,移除形成於圖案化遮罩層35之上表面351上的介電層36的一部份與阻障/襯墊層37的一部分。在某些實施例中,圖案化遮罩層35的第一子層352的一部分也被移除。在一些實施例中,可完全移除第一子層352,並且可移除第二子層353的一部分。
參考圖13,在平坦化製程之後,光阻52形成於圖案化的遮罩層35上方。在某些實施例中,在形成光阻52之前,可在圖案化的遮罩層35上方形成一中間層(ML)與一底層(BL),其為圖13中的標號51所標示。在一些實施例中,中間層可以是含矽抗反射塗層(SiARC),例如SiCxHyOz或類似者,並且底層可以是光學平坦化層,例如CxHyOz或類似者。在形成光阻52與中間層與底層51之後,可圖案化光阻52以形成開口53。
參考圖14,在圖13所說明的製程之後,形成穿透圖案化的遮罩層35、第一導電特徵件341、黏著層342、第三介電層333和第二介電層332的通孔38,以露出對應之電晶體301(請見圖6)的MD結構302。圖13與圖14所說明的製程,被一起說明於圖5所示的流程圖200中的製程216。通孔38之形成可藉由任何適合蝕刻技術進行,諸如電容耦合電漿(CCP)、感應耦合電漿(ICP)、變壓器耦合電漿(TCP)或類似者。在一些實施例中,第一介電層331和第二介電層332可由不同材料組成以具有不同的蝕刻選擇性,如此一來,在蝕刻製程中,第一介電層331被蝕刻穿透,而第二介電層332實質上保持未蝕刻或僅被輕微蝕刻。在一些實施例中,第一介電層331由氧化矽組成,第二介電層332由氮化矽組成,且氧化矽相對氮化矽的蝕刻速率可大於10。在一些實施例中,在形成通孔38期間MD結構302可被稍微蝕刻。
參考圖15,在形成通孔38之後,形成一阻障層391,其後在阻障層391上形成一襯墊層392。此製程說明於圖5所示之流程圖200中的製程218。在某些實施例中,阻障層391係形成於圖案化遮罩層35之上表面351 (見圖12)及圖案化介電層36之上表面362 (見圖12)上,並圍繞通孔38 (見圖14)。在一些實施例中,阻障層391及襯墊層392之各者係由一導電材料製成,包含鉭、氮化鉭、鈷、釕、鈦、氮化鈦、氮化錳或其等的組合。阻障層391及襯層392之各者可藉由合適的技術形成,諸如CVD(例如,FCVD、LPCVD、PECVD或類似者)、ALD(包括PEALD)或類似者。
在形成阻障層391及襯墊層392之後,在襯墊層392上方形成第二導電特徵件393。此製程說明於圖5所示流程圖200的製程220中。在一些實施例中,第二導電特徵件393係一金屬層,且可由包含銅、釕、鎢、鈦、鋁、鈷、鉬、銥、銠、鈷-鎢-磷(cobalt-tungsten-phosphorus)或其等之組合之一材料製成。在一些實施例中,可藉由合適的技術形成第二導電特徵件393,例如PVD、CVD、ALD、ELD、PVD和ECP的組合或類似者。在一些實施例中,第二導電特徵件393電性連接至對應的電晶體301 (見圖6)的MD結構302。
參考圖16,在形成第二導電特徵件393之後,藉由適合技術,諸如電漿乾蝕刻、CMP或類似者,對第二導電特徵件393進行平坦化。此製程說明於圖5所示之流程圖200中的製程222。在一些實施例中,第二導電特徵件393的一部分、阻障層391和襯墊層392的一部分、第四介電層36的一部分、阻障/襯墊層37的一部分和圖案化的遮罩層35被移除,以得到半導體結構300。在一些實施例中,襯墊層392圍繞且連接至第二導電特徵件393,阻障層391圍繞且連接至襯墊層392,且第二導電特徵件393經由襯墊層392及阻障層391而連接至第一導電特徵件341。在一些實施例中,依據實際應用,第一導電特徵件341與第二導電特徵件393可由相同或不同的材料所組成。如圖16中所示,在一些實施例中,第二導電特徵件393可部分地落在在對應的電晶體301 (見圖6)的MD結構302上。在其他實施例中,第二導電特徵件393可完全落在對應電晶體301的MD結構302上。在某些實施例中,形成於通孔38中的第二導電特徵件393(見圖14),可對應至形成於光阻52中的開口53。在一些實施例中,第二導電特徵件393之俯視圖如圖6中所展示。
在一些實施例中,可對半導體結構300進行後續的互連線結構形成製程,例如單一或雙鑲嵌製程,以於半導體結構300上形成多個互連線層,以實現半導體結構300所需的電性連接。參考圖6,根據一些實施例,相應電晶體301的MG結構303可經由電性連接結構,例如貫孔70,電性連接至第一導電特徵件341。
參考圖6、圖16及圖17,在一些實施例中,通孔結構343包括複數個通孔343' (見圖10),其將第一導電特徵件341分成複數個導電組件341'。第二導電特徵件393穿透導電組件341'中的對應一者。在一些實施例中,在得到半導體結構300之後,圖案化的介電層36、阻障/襯墊層37與氣隙361共同地定義一隔離特徵件41。在一些實施例中,在鄰近的兩個隔離特徵件41之間的最小間距(P)在約12 nm至約42 nm的範圍內,但也可以在此範圍外。在一些實施例中,隔離特徵件41的深寬比, 其定義為隔離特徵件41的高度(H2)除以隔離特徵件41的直徑(D2),可以在約1至約4的範圍內,但也可以在此範圍外。在一些實施例中,隔離特徵件41的高度(H2)在約10 nm至約35 nm的範圍內,但也可以在此範圍外。在一些實施例中,隔離特徵件41的直徑(D2)在約5 nm至約20 nm的範圍內,但也可以在此範圍外。在一些實施例中,導電特徵件42被定義以包括阻障層391、襯墊層392和第二導電特徵件393。在一些實施例中,導電特徵件42的直徑(D1)可在約10 nm至約100 nm的範圍,但也可以在此範圍外。在其他實施例中,導電特徵件42的直徑(D1)可在約3 nm至約20 nm的範圍,但也可以在此範圍外。在一些實施例中,導電特徵件42的高度(H1)可在約20 nm至約100 nm的範圍,但也可以在此範圍外。在一些實施例中,導電特徵件42的深寬比,其由導電特徵件42的高度(H1)除以導電特徵件42的直徑(D1)所定義,可以在約0.5至約5的範圍內,但也可以在此範圍外。在其他實施例中,導電特徵件42的深寬比可以在約1至約10的範圍,但也可以在此範圍外。在一些實施例中,第二導電特徵件393具有外壁394,其與相應電晶體301(見圖6)的MD結構302形成夾角(A),且夾角(A)的範圍可為約72度至約90度。在一些實施例中,通孔38 (見圖14)由孔洞定義壁50來界定,其由第一導電特徵件341、黏著層342、第二介電層332、第三介電層333及對應電晶體301之MD結構302共同界定。阻障層391是保形地形成在孔洞定義壁50上。在一些實施例中,孔洞定義壁50與對應電晶體301的MD結構302形成夾角(B),且夾角(B)的範圍從約72度至約90度,使得形成於由孔洞定義壁50所界定的通孔38中的第二導電特徵件393具有與對應電晶體301的MD結構302形成72度至90度夾角(A)的外壁394。
參考圖18,在一些實施例中,導電特徵件42具有連接至電晶體301的MD結構302的底表面422,以及與底表面422相對的頂表面421,並且與第一導電特徵件341之相應的導電組件341'之頂表面實質上齊平,導電特徵件42穿透此頂表面。在一些實施例中,導電特徵件42的頂表面421具有佔第一導電特徵件341的導電組件341'之對應一者的頂表面面積約20%至約100%的面積。圖18顯示在一些實施例中,導電特徵件42的頂表面421的面積佔第一導電特徵件341的導電組件341'之對應一者的頂表面的面積100%。換言之,導電特徵件42的直徑(D1)等於與導電特徵件42相鄰之隔離特徵件41之間的最小距離(S)。在一些實施例中,對於導電特徵件42,頂表面421的面積可以等於或大於底表面422的面積。
圖19至圖21示意性地顯示氣隙361之不同範例。在一些實施例中,在一個通孔343'中(見圖10),氣隙361之體積為通孔343'之體積的約20%至約90%,且介電層36之體積為通孔343'之體積的約10%至約80%。參考圖19,在一些實施例中,在介電層36的形成期間,介電層36的頂部部分363可以在通孔343'被介電層36完全填充之前密封通孔343',藉此在通孔343'內留下氣隙361。
參考圖20,在一些實施例中,合適的蝕刻停止層60係形成在通孔343'的底部(見圖10)。在此等實施例中,在形成介電層36之前,在通孔343'之底部上形成蝕刻終止層60,接著藉由熱可降解的或UV 可降解的材料(未繪示)填充通孔343'以形成可降解的元件。熱或UV 可降解的材料可由含聚脲材料、含丙烯酸酯材料、含羧酸鹽材料或類似者製成。可以合適的技術形成熱或紫外光可降解的材料,例如ALD(包含PEALD)、CVD(例如FCVD、LPCVD、PECVD或類似者)、分子層沉積(MLD)、旋轉塗佈或類似者。接著,蝕刻可降解的元件(例如,使用非等向性乾式蝕刻)直到蝕刻終止層60,以在可降解的元件中形成一中空空間(未繪示),接著用介電層36填充該中空空間。最後,藉由熱處理或UV輻射移除熱可降解的或UV 可降解的材料之剩餘部分以形成氣隙361。在一些實施例中,可在約200℃至約400℃範圍內之溫度下進行熱處理約10秒至約10分鐘。在一些實施例中,可在自約10 mJ/cm2至約100 J/cm2之範圍內的輻射能下進行UV輻射約10秒至約10分鐘。
參考圖21,在一些實施例中,熱可降解的或UV 可降解的材料形成於通孔343'之底部部分處(見圖10),接著用介電層36完全填充通孔343'。隨後,藉由合適的熱處理或UV輻射移除熱可降解的或UV 可降解的材料以形成氣隙361。
在一些實施例中,隔離特徵件41可能不包含氣隙361。參考圖22,在一些實施例中,介電層36可包含第一子層364和第二子層365。在一些實施例中,首先在通孔343' (見圖10)中形成第一子層364,之後形成第二子層365以完全填充通孔343'。
參考圖23,在一些實施例中,蝕刻停止層60形成於通孔343'之底部處(見圖10)。之後,形成第一子層364以填充通孔343',之後蝕刻(例如,使用非等向性乾式蝕刻)第一子層364直至蝕刻終止層60而於第一子層364內形成中空空間(未繪示)。接著,中空空間被第二子層365填充。
依據實際需求,第一子層364和第二子層365可由不同的介電材料構成。在一些實施例中,第一子層364的材料可更佳地黏著至阻障/襯墊層37或第一導電特徵件341。在一些實施例中,第二子層365可由低介電常數介電材料製成。在一些實施例中,第一子層364之組成可為摻雜氮化物的碳化矽,而第二子層365之組成可為氧化矽、氮化矽、碳化矽(包含UDC、ODC、NDC、或類似者)、氮氧化矽、碳氧化矽(silicon oxycarbide) (包括SiOCH)、碳氧化矽的氮化物(silicon oxycarbide nitride)、氧化鋁、氮氧化鋁、氮化鋁、氧化鋯、氮氧化鋁鋯 (zirconium aluminum oxynitride)、非晶矽、或其等的組合。
本揭露的實施例具有一些有利特徵。藉由形成第二導電特徵件以穿透第一導電特徵件和電性連接至第一導電特徵件和下方半導體裝置,第二導電特徵件可以取代第一導電特徵件和半導體裝置之間的接觸插塞,藉此消除接觸插塞和第一導電特徵件之間的界面,以降低第一導電特徵件和半導體裝置之間的電阻。第二導電特徵件可形成為長形軌道結構,其可取代多個接觸插塞且簡化整體製造製程。第二導電特徵件可形成為用於第一導電特徵件與半導體裝置之間的電性連接的接觸件;另一方面,第二導電特徵件可為深電源軌,其提供足夠的電力至半導體裝置,可改善因為導電線路尺寸縮減而供電不足所造成的電壓降低問題。第二導電特徵件可由基於第一導電特徵件材料所選擇的材料製成,並且根據實際需求,例如超低電阻、低電容、可靠度或其他變化,其允許半導體結構依據實際需求而靈活地設計。半導體結構可與介電層之氣隙或多個填入第一導電特徵件通孔結構的子層整合,以降低半導體結構整體的介電常數。
根據一些實施例,一半導體結構包括一基板、一介電層、一第一導電特徵件、與一第二導電特徵件。該基板包括一半導體裝置。該介電層設置於該基板上。該第一導電特徵件形成於該介電層中。該第二導電特徵件穿透該第一導電特徵件與該介電層,且電性連接至該第一導電特徵件與該半導體裝置。
根據一些實施例,該第一導電特徵件與該第二導電特徵件由不同材料組成。
根據一些實施例,該第一導電特徵件的組成材料包括銅、釕、鎢、鈦、鋁、鈷、鉬、銥、銠、石墨烯、或其等的組合。該第二導電特徵件由包括銅、釕、鎢、鈦、鋁、鈷、鉬、銥、銠、鈷-鎢-磷(cobalt-tungsten-phosphorus)或其等的組合的材料製成。
根據一些實施例,該半導體結構更包括一襯墊層,其圍繞並連接至該第二導電特徵件;以及一阻障層,其圍繞並連接至該襯墊層。該第二導電特徵件透過該襯墊層和該阻障層連接至該第一導電特徵件。
根據一些實施例,該阻障層及該襯墊層之各者係由導電材料所製成,包括鉭、氮化鉭、鈷、釕、鈦、氮化鈦、氮化錳或其等的組合。
根據一些實施例,該第二導電特徵件具有與該半導體裝置形成夾角的一外壁。該夾角的範圍從約72度到約90度。
根據一些實施例,該介電層具有鄰近該第一導電特徵件的一氣隙。
根據一些實施例,一半導體結構包括一基板、一第一介電層、一互連線結構、與一第二導電特徵件。基板包含一電晶體。該第一介電層設置於該基板上。該互連線結構包括:一第一導電特徵件,其設置於該第一介電層上並相反於該基板;以及一第二介電層,其圍繞該第一導電特徵件。該第二導電特徵件穿透該互連線結構,且電性連接至該第一導電特徵件與該電晶體。
根據一些實施例,該半導體結構更包括一黏著層與一襯墊/阻障層。該黏著層設置於該第一介電層與該第一導電特徵件之間,且延伸於大致平行該基板的方向。襯墊/阻障層為連接並圍繞第二導電特徵件。
根據一些實施例,該第一導電特徵件包括多個導電組件,其藉由該第二介電層彼此隔開。
根據一些實施例,該第一導電特徵件的一底表面連接至該第一介電層。該第二導電特徵件的一底表面連接至該電晶體的一接觸件,並且低於該第一導電特徵件的底表面。
根據一些實施例,該第二導電特徵件的底表面低於該電晶體的一頂表面。
根據一些實施例,該第二導電特徵件電連接至該電晶體的多個接觸件。
根據一些實施例,一種半導體結構的製造方法包含:提供一基板,其包含一半導體裝置;在該基板上形成一介電層;在該介電層中形成一第一導電特徵件,該第一導體特徵件與該基板分開;形成一通孔,其穿透該第一導電特徵件及該介電層以暴露出該半導體裝置之一接觸件;以及在該通孔中形成一第二導電特徵件,使該第二導電特徵件電性連接至該半導體裝置的該第一導電特徵件及該接觸件。
根據一些實施例,該第一導電特徵件與該第二導電特徵件由不同材料組成。
根據一些實施例,該第一導電特徵件之組成材料包括銅、釕、鎢、鈦、鋁、鈷、鉬、銥、銠、鈷-鎢-磷或其等的組合。該第二導電特徵件由包括銅、釕、鎢、鈦、鋁、鈷、鉬、銥、銠、鈷-鎳-磷(cobalt-tungsten-phosphorus)或其等的組合的材料製成。
根據一些實施例,該通孔由一孔洞定義壁界定。該方法更包括:在形成該通孔之後且在形成該第二導電特徵件之前,在該孔洞定義壁上保形地形成一導電阻障層,並且在該阻障層上保形地形成一導電襯墊層;以及在形成該第二導電特徵件之後,該第二導電特徵件被襯墊層圍繞且連接該襯墊層。
根據一些實施例,形成該通孔之步驟係藉由使用一光阻作為一遮罩以蝕刻穿過該第一導電特徵件及該介電層而進行。
根據一些實施例,在形成該通孔之步驟中,該通孔係由與該半導體裝置形成一夾角之一孔洞定義壁所界定。該夾角係在從約72度至約90度的範圍內,以使填充該通孔之該第二導電特徵件具有與該半導體裝置形成另一夾角的一外壁。該外壁與該半導體裝置之間的另一夾角之範圍係自約72度至約90度。
根據一些實施例,在形成通孔的步驟中,部分地移除半導體裝置的接觸件。
上文概述若干實施例之特徵,使得熟習此項技術者可更好地理解本揭露之態樣。所屬領域具有通常知識者應當理解,他們可輕易地以本揭露內容為基礎設計或修改以用於執行與本文介紹的實施例具有相同目的及/或實現相同優點的其它製程及結構。所屬技術領域中具有通常知識者也應理解到,此類等效的製程和結構並無悖離本發明的精神與範圍,且他們能在不違背本揭露內容之精神和範圍之下,做各式各樣的改變、取代和替換。
10:基板
11:第一介電層
12:接觸插塞
13:第二介電層
14:導線
30:基板
35:遮罩層
36:第四介電層
37:阻障/襯墊層
38:通孔
41:隔離特徵件
42:導電特徵件
50:孔洞定義壁
51:中間層、底層
52:光阻
53:開口
60:蝕刻停止層
70:貫孔
101:電晶體
102:源極
103:汲極
104:通道
105:閘極
106:隔離特徵件
111:通孔
131:通孔
200:流程圖
202:製程
204:製程
206:製程
208:製程
210:製程
212:製程
214:製程
216:製程
218:製程
220:製程
222:製程
300:半導體結構
301:電晶體
302:MD結構
303:MG結構
304:間隔物
305:間隔物
331:第一介電層
332:第二介電層
333:第三介電層
341:第一導電特徵件
341':導電組件
342:黏著層
343:通孔結構
343':通孔
351:上表面
352:第一子層
353:第二子層
361:氣隙
362:上表面
363:頂部部分
364:第一子層
365:第二子層
391:阻障層
392:襯墊層
393:第二導電特徵件
394:外壁
421:頂表面
422:底表面
A:夾角
AA:線
B:夾角
BB:線
D1:直徑
D2:直徑
H1:高度
H2:高度
P:最小間距
S:最小距離
當結合附圖閱讀時,自以下詳細描述可最佳理解本揭露之態樣。請注意為遵循業界標準作法,各種特徵沒有按比例繪製。事實上,為使討論內容清楚,各種特徵的尺寸可任意地放大或縮小。
圖1至圖4是根據一些實施例,說明半導體結構之形成中各個階段的示意圖。
圖5是根據一些實施例,說明製造半導體結構的製程流程。
圖6說明根據一些實施例的半導體結構的佈局。
圖7至圖16是根據一些實施例的一半導體結構的形成的各階段的示意圖。
圖17為根據一些實施例的半導體結構的放大剖面示意圖。
圖18說明對圖16中描述的結構的替代例。
圖19至圖21說明根據一些實施例的隔離特徵件的各種範例。
圖22及圖23說明根據一些實施例繪示出隔離特徵件的其他範例。
36:第四介電層
37:阻障/襯墊層
41:隔離特徵件
300:半導體結構
302:MD結構
303:MG結構
304:間隔物
305:間隔物
331:第一介電層
332:第二介電層
333:第三介電層
341:第一導電特徵件
342:黏著層
361:氣隙
391:阻障層
392:襯墊層
393:第二導電特徵件
AA:線
BB:線
D1:直徑
D2:直徑
P:最小間距
S:最小距離
Claims (1)
- 一種半導體結構,包含: 一基板,其包括一半導體裝置; 一介電層,其被設置在該基板上; 一第一導電特徵件,形成於該介電層中;以及 一第二導電特徵件,穿過該第一導電特徵件及該介電層,且電性連接至該第一導電特徵件及該半導體裝置。
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