TW202306317A - Clock generator device and clock generation method - Google Patents
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本案是關於時脈產生裝置,尤其是關於可縮短系統開機時間的時脈產生裝置與時脈產生方法。This case is about a clock generating device, especially about a clock generating device and a clock generating method that can shorten system start-up time.
在一些需要即時時鐘(real time clock, RTC)的應用中,當系統開機後,系統中的數位電路需要穩定的時脈訊號才可以開始進行運作。然而,一般振盪器電路的工作電壓較高。當供應電壓未達到振盪器電路的最低工作電壓前,振盪器電路無法提供合適的時脈訊號。因此,在供應電壓之位準升高至最低工作電壓後,數位電路才能獲得合適的時脈訊號。如此一來,數位電路在系統開機後需等候一段時間才能開始運作,無法滿足需快速啟動系統的應用場景。In some applications that require a real time clock (RTC), when the system is powered on, the digital circuits in the system need a stable clock signal to start operating. However, generally oscillator circuits operate at relatively high voltages. When the supply voltage does not reach the minimum operating voltage of the oscillator circuit, the oscillator circuit cannot provide a proper clock signal. Therefore, the digital circuit can obtain a proper clock signal only after the level of the supply voltage rises to the minimum operating voltage. As a result, the digital circuit needs to wait for a period of time before starting to operate after the system is turned on, which cannot meet the application scenarios where the system needs to be quickly started.
於一些實施態樣中,時脈產生裝置包含第一時脈產生電路、第二時脈產生電路、第一偵測電路以及選擇電路。第一時脈產生電路具有一第一啟動電壓,並響應一供應電壓產生一第一時脈訊號。第二時脈產生電路具有一第二啟動電壓,並響應該供應電壓產生一第二時脈訊號。第一偵測電路偵測該第二時脈訊號,以產生一生效訊號。選擇電路根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。該第一啟動電壓低於該第二啟動電壓。In some embodiments, the clock generating device includes a first clock generating circuit, a second clock generating circuit, a first detecting circuit and a selecting circuit. The first clock generating circuit has a first startup voltage and generates a first clock signal in response to a supply voltage. The second clock generating circuit has a second startup voltage and generates a second clock signal in response to the supply voltage. The first detection circuit detects the second clock signal to generate a validation signal. The selection circuit selects to output one of the first clock signal and the second clock signal according to the validation signal. The first startup voltage is lower than the second startup voltage.
於一些實施態樣中,時脈產生方法包含下列操作:利用一第一時脈產生電路以響應一供應電壓產生一第一時脈訊號,其中該第一時脈產生電路具有第一啟動電壓;利用一第二時脈產生電路以響應該供應電壓產生一第二時脈訊號,其中該第二時脈產生電路具有第二啟動電壓,且該第一啟動電壓低於該第二啟動電壓;偵測該第二時脈訊號,以產生一生效訊號;以及根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。In some implementation aspects, the clock generation method includes the following operations: using a first clock generation circuit to generate a first clock signal in response to a supply voltage, wherein the first clock generation circuit has a first start-up voltage; Using a second clock generating circuit to generate a second clock signal in response to the supply voltage, wherein the second clock generating circuit has a second startup voltage, and the first startup voltage is lower than the second startup voltage; detecting measuring the second clock signal to generate a validation signal; and selecting to output one of the first clock signal and the second clock signal according to the validation signal.
於一些實施態樣中,時脈產生裝置包含第一時脈產生電路、第二時脈產生電路、第一偵測電路以及選擇電路。第一時脈產生電路在一供應電壓大於或等於一第一位準時產生一第一時脈訊號。第二時脈產生電路在供應電壓大於或等於一第二位準時產生一第二時脈訊號,其中該第一位準低於該第二位準。偵測電路偵測該第二時脈訊號,以產生一生效訊號。選擇電路根據該生效訊號選擇輸出該第一時脈訊號與該第二時脈訊號中之一者。In some embodiments, the clock generating device includes a first clock generating circuit, a second clock generating circuit, a first detecting circuit and a selecting circuit. The first clock generating circuit generates a first clock signal when a supply voltage is greater than or equal to a first level. The second clock generating circuit generates a second clock signal when the supply voltage is greater than or equal to a second level, wherein the first level is lower than the second level. The detection circuit detects the second clock signal to generate a validation signal. The selection circuit selects to output one of the first clock signal and the second clock signal according to the validation signal.
有關本案的特徵、實作與功效,茲配合圖式作較佳實施例詳細說明如下。About the feature, implementation and effect of this case, hereby cooperate with drawing as preferred embodiment and describe in detail as follows.
本文所使用的所有詞彙具有其通常的意涵。上述之詞彙在普遍常用之字典中之定義,在本案的內容中包含任一於此討論的詞彙之使用例子僅為示例,不應限制到本案之範圍與意涵。同樣地,本案亦不僅以於此說明書所示出的各種實施例為限。All terms used herein have their ordinary meanings. The definitions of the above-mentioned terms in commonly used dictionaries, and the use examples of any terms discussed here in the content of this case are only examples, and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.
關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。如本文所用,用語『電路』可為由至少一個電晶體與/或至少一個主被動元件按一定方式連接以處理訊號的裝置。As used herein, "coupling" or "connection" can refer to two or more elements in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two or more components. Components operate or act on each other. As used herein, the term "circuit" can be a device that is connected in a certain way to process signals by at least one transistor and/or at least one active and passive element.
圖1A為根據本案一些實施例繪製的一種時脈產生裝置100的示意圖。於一些實施例中,時脈產生裝置100可應用於影像處理晶片。例如,時脈產生裝置100可提供最終時脈訊號CKF給一安防晶片,以讓安防晶片具有較短的啟動時間來開始監控環境。FIG. 1A is a schematic diagram of a clock generating
時脈產生裝置100包含時脈產生電路110、時脈產生電路120、偵測電路130以及選擇電路140。於一些實施例中,時脈產生電路110具有第一啟動電壓,時脈產生電路120具有第二啟動電壓,且第一啟動電壓低於第二啟動電壓。於一些實施例中,時脈產生電路120產生的時脈訊號CK2的精準度高於時脈產生電路110產生的時脈訊號CK1的精準度。於一些實施例中,時脈訊號CK1的頻率接近於(或相同於)時脈訊號CK2的頻率。The
例如,時脈產生電路110可為(但不限於)自由運行(free running)振盪器,其可響應供應電壓VDD產生時脈訊號CK1。時脈產生電路120可為(但不限於)石英振盪器,其可響應供應電壓VDD產生時脈訊號CK2。於一些實施例中,時脈產生電路110工作電壓的範圍約為0.5~3.3伏特,時脈產生電路120工作電壓的範圍約為0.9~3.3伏特,由此可知,時脈產生電路110的第一啟動電壓為0.5伏特,而時脈產生電路120的第二啟動電壓為0.9伏特。當供應電壓VDD大於或等於第一啟動電壓時,時脈產生電路110開始運作以產生時脈訊號CK1。當供應電壓VDD大於或等於第二啟動電壓時,時脈產生電路120開始運作以產生時脈訊號CK2。藉由上述設置方式,當時脈產生裝置100上電時,供應電壓VDD會由低電壓位準開始上升,由於第一啟動電壓低於第二啟動電壓,因此,時脈產生電路110產生時脈訊號CK1的時間會早於時脈產生電路120產生時脈訊號CK2的時間。For example, the
偵測電路130用以偵測時脈訊號CK2是否穩定並偵測時脈訊號CK2的特性(例如為頻率)是否合適,以產生生效訊號SV。於一些實施例中,如圖2A所示,偵測電路130可由類比電路實施。於一些實施例中,如圖2B所示,偵測電路130可由數位電路實施。於另一些實施例中,偵測電路130可由混合訊號電路實施。The
選擇電路140可根據生效訊號SV選擇輸出時脈訊號CK1與時脈訊號CK2中之一者為最終時脈訊號CKF。例如,當時脈產生裝置100上電時,供應電壓VDD開始升高。當供應電壓VDD大於或等於第一啟動電壓時,時脈產生電路110可開始運作以產生時脈訊號CK1,且時脈產生電路120尚未啟動。於此條件下,偵測電路130輸出具有第一邏輯值(例如為邏輯值0)的生效訊號SV。選擇電路140可根據此生效訊號SV選擇輸出時脈訊號CK1為最終時脈訊號CKF。當供應電壓VDD大於或等於第二啟動電壓時,時脈產生電路120開始運作以輸出時脈訊號CK2。於此條件下,偵測電路130輸出具有第二邏輯值(例如為邏輯值1)的生效訊號SV。選擇電路140可根據此生效訊號SV選擇輸出時脈訊號CK2為最終時脈訊號CKF。藉由上述設置方式,時脈產生裝置100可於開機過程中更快地提供最終時脈訊號CKF,以加快系統中其他電路的開始運作時間。於一些實施例中,選擇電路140可為多工器電路。The
圖1B為根據本案一些實施例繪製時脈產生裝置100A之示意圖。相較於圖1A,圖1B的時脈產生裝置100A更包含偵測電路150,其可用於確認時脈產生電路110是否開始輸出時脈訊號CK1,以產生控制訊號SC1。於一些實施例中,控制訊號SC1可用於致能系統中的周邊電路(未示出)。例如,當時脈產生電路110開始輸出時脈訊號CK1,控制訊號SC1由第一邏輯值切換至第二邏輯值。響應此控制訊號SC1,系統中的電源控制(power-on control)電路被致能以開始提供電源至周邊電路。如此,周邊電路可以更快地開始運作。FIG. 1B is a schematic diagram of a clock generating
圖2A為根據本案一些實施例繪製圖1A或圖1B中的偵測電路130之示意圖。偵測電路130包含電流源210、開關220、電容230以及反相器240。FIG. 2A is a schematic diagram of the
電流源210的第一端接收供應電壓VDD,且電流源210的第二端耦接至開關220的第一端。開關220的第二端接收地電壓GND,且開關220的控制端接收時脈訊號CK2。電容230的第一端耦接至電流源210的第二端,且電容230的第二端接收地電壓GND。反相器240的輸入端耦接至電容230的第一端,且反相器240的輸出端用以輸出生效訊號SV。電流源210用以提供電流訊號SI。開關220用以根據時脈訊號CK2選擇性導通。電容230用以經由電流訊號SI充電並經由開關220放電,以產生偵測訊號SD。反相器240用以根據偵測訊號SD輸出生效訊號SV。A first terminal of the
詳細而言,在時脈產生電路120尚未產生時脈訊號CK2時,開關220不導通,且電容230經由電流訊號SI被充電,以產生具有高位準的偵測訊號SD。響應於此偵測訊號SD,反相器240輸出具有低位準(對應於邏輯值0)的生效訊號SV。或者,當時脈產生電路120開始產生合適的時脈訊號CK2時,代表時脈訊號CK2穩定地具有一定數量的脈波。開關220響應該些脈波依序被導通而使得電容230開始放電,以產生具有低位準的偵測訊號SD。響應於此偵測訊號SD,反相器240輸出具有高位準(對應於邏輯值1)的生效訊號SV。如此一來,生效訊號SV可用於指示時脈產生電路120是否有穩定地產生合適的時脈訊號CK2。In detail, when the
於此例中,可利用電容230的容值C調整具有高位準的生效訊號SV之產生時間,進而設定自輸出時脈訊號CK1切換至輸出時脈訊號CK2的時間(後稱切換時間T)。於一些實施例中,切換時間T可依據時脈訊號CK2的應用要求來決定。例如,切換時間T可依據時脈訊號CK2所需的頻率來決定。In this example, the capacitance C of the
於一些實施例中,切換時間T與容值C符合下式:
其中,供應電壓VDD可為前述的第二啟動電壓所對應的電壓範圍,Q為電容230儲存的電荷量,I為電容230的放電電流,T
CK2為時脈訊號CK2的週期,M為預定數值。上式表示電容C在預定期間(其對應於M個時脈訊號CK2的週期)放電使得電容C的第一端之位準為地電壓GND。根據上式,可藉由調整電容230的容值C或是電流訊號SI(影響電容C的放電電流I)來設定切換時間T。
In some embodiments, the switching time T and the capacitance C conform to the following formula: Wherein, the supply voltage VDD can be the voltage range corresponding to the aforementioned second start-up voltage, Q is the amount of charge stored in the
圖2B為根據本案一些實施例繪製圖1A或圖1B中的偵測電路130之示意圖。偵測電路130包含計數器250以及比較器260。計數器250用以對時脈訊號CK2計數以產生計數值CT。於一些實施例中,計數器250可為上數計數器、下數計數器、漣波(ripple)計數器或其他類型的計數器。比較器260用以在計數值等於臨界值TH時輸出生效訊號SV。FIG. 2B is a schematic diagram of the
例如,計數器250為上數計數器,其用以響應時脈訊號CK2的一個脈波進行上數以產生計數值CT。當計數值CT增加至相同於臨界值TH時,代表時脈產生電路120可穩定地輸出時脈訊號CK2。於此條件下,比較器260輸出具有特定邏輯值的生效訊號SV。相較於圖2A,於此例中,可藉由調整臨界值TH來設定時脈訊號CK2的頻率及穩定度。For example, the
於一些實施例中,偵測電路150與偵測電路130具有類似或相同電路設置方式。偵測電路150之設置方式可參照圖2A或圖2B,故不再重複贅述。若是以圖2A的例子來實施偵測電路150,上式中的供應電壓VDD可為時脈產生電路110的工作電壓所對應的電壓範圍。或者,若是以圖2B的例子來實施偵測電路150,偵測電路150所使用的臨界值TH可不同於偵測電路130所使用的臨界值TH。In some embodiments, the
圖3為根據本案一些實施例繪製時脈產生裝置300的示意圖。相較於圖1B,於此例中,生效訊號SV可用以控制時脈產生電路110。例如,時脈產生電路110為具有電源閘控(power gating)的環形振盪器電路,其可根據生效訊號SV致能或禁能。FIG. 3 is a schematic diagram of a
於一些實施例中,生效訊號SV的初始值為第一邏輯值。響應具有第一邏輯值的生效訊號SV,時脈產生電路110被致能,以根據供應電壓VDD開始產生時脈訊號CK1。當時脈產生裝置300上電時,供應電壓VDD由零位準開始爬升至一預定位準。當供應電壓VDD高於或等於該第一啟動電壓時,時脈產生電路110開始產生時脈訊號CK1。響應具有第一邏輯值的生效訊號SV,選擇電路140輸出時脈訊號CK1為最終時脈訊號CKF。當供應電壓VDD高於或等於第二啟動電壓時,時脈產生電路120開始產生時脈訊號CK2。偵測電路130確認時脈產生電路120可以穩定地產生合適的時脈訊號CK2,並產生具有第二邏輯值的生效訊號SV。響應具有第二邏輯值的生效訊號SV,選擇電路140切換為輸出時脈訊號CK2為最終時脈訊號CKF。另一方面,時脈產生電路110可響應具有第二邏輯值的生效訊號SV關閉,以節省系統功耗。當時脈產生電路110被關閉,時脈產生電路110停止輸出時脈訊號CK1。於此條件下,偵測電路150輸出具有第一邏輯值的控制訊號SC1。In some embodiments, the initial value of the validation signal SV is a first logic value. In response to the validation signal SV having a first logic value, the
再者,相較於圖1B,時脈產生裝置300更包含邏輯閘電路310。邏輯閘電路310用以根據生效訊號SV與控制訊號SC1產生控制訊號SC2。控制訊號SC2可用以控制系統中的數位電路,舉例來說,控制訊號SC2可用以控制電源控制電路,以決定是否對數位電路供電。Moreover, compared with FIG. 1B , the
於一些實施例中,邏輯閘電路310可為(但不限於)互斥或(XOR)閘電路。當供應電壓VDD上電時,時脈產生電路110先輸出時脈訊號CK1(相較於時脈產生電路120)。於此條件下,控制訊號SC1具有第二邏輯值且生效訊號SV具有第一邏輯值。邏輯閘電路310響應此控制訊號SC1與生效訊號SV產生具有第二邏輯值的控制訊號SC2。電源控制電路可響應此控制訊號SC2提供電源給數位電路。當時脈產生電路120輸出合適的時脈訊號CK2時,偵測電路130輸出具有第二邏輯值的生效訊號SV。於此條件下,時脈產生電路110被關閉而停止輸出時脈訊號CK1,且偵測電路150據此輸出具有第一邏輯值的控制訊號SC1。響應此生效訊號SV與控制訊號SC1,邏輯閘電路310產生具有第二邏輯值的控制訊號SC2,電源控制電路可持續提供電源給數位電路。In some embodiments, the
圖4A為根據本案一些實施例繪製時脈產生裝置400的示意圖。相較於圖3中的時脈產生裝置300, 時脈產生裝置400更包含延遲電路410與延遲電路420。延遲電路410用以延遲生效訊號SV產生訊號S1。延遲電路420用以延遲控制訊號SC1產生訊號S2。邏輯閘電路310用以根據訊號S1與訊號S2產生控制訊號SC2。於一些實施例中,延遲電路420的延遲時間可小於延遲電路410的延遲時間。於此例中,控制訊號SC2可用於控制相關於即時時鐘(real time clock)應用的數位電路。例如,數位電路可包含具有重置功能的正反器電路,其可根據控制訊號SC2被重置,以重置數位電路的設定值或參數。FIG. 4A is a schematic diagram of a
為說明時脈產生裝置400的操作,參照圖4B,圖4B為根據本案一些實施例繪製圖4A中的時脈產生裝置400之時序示意圖。在時脈產生裝置400上電後,於時間T0,時脈產生電路110輸出時脈訊號CK1,且選擇電路140輸出時脈訊號CK1為最終時脈訊號CKF。於時間T1,偵測電路150判斷時脈產生電路110可穩定地輸出時脈訊號CK1,並輸出具有第二邏輯值(對應於高位準)的控制訊號SC1。於時間T2,時脈產生電路120輸出時脈訊號CK2。於時間T3,偵測電路130判斷時脈產生電路120可穩定地輸出合適的時脈訊號CK2,並輸出具有第二邏輯值(對應於高位準)的生效訊號SV。響應於此生效訊號SV,時脈產生電路110被關閉而停止輸出時脈訊號CK1。於此條件下,偵測電路150判斷時脈產生電路110未輸出時脈訊號CK1,並輸出具有第一邏輯值(對應於低位準)的控制訊號SC1。延遲電路410延遲生效訊號SV以輸出訊號S1。延遲電路420延遲控制訊號SC1以輸出訊號S2。邏輯閘電路310可根據訊號S1與訊號S2產生控制訊號SC2。藉由上述設置方式,如圖4B所示,控制訊號SC2具有重置期間TR。於重置期間TR,RTC電路的數位電路部分之操作將被重置。如此一來,可避免數位電路部分之操作受到時脈訊號的切換過程之影響(例如,突波(glitch)),進而提高整體系統的操作穩定度。To illustrate the operation of the
圖5為根據本案一些實施例繪製一種時脈產生方法500的流程圖。於一些實施例中,時脈產生方法500可由(但不限於)圖1A、圖1B、圖3或圖4中的時脈產生裝置執行。FIG. 5 is a flowchart of a
於操作S510,利用一第一時脈產生電路以響應供應電壓產生第一時脈訊號,其中該第一時脈產生電路具有第一啟動電壓。於操作S520,利用一第二時脈產生電路以響應該供應電壓產生第二時脈訊號,其中該第二時脈產生電路具有第二啟動電壓,且該第一啟動電壓低於該第二啟動電壓。於操作S530,偵測該第二時脈訊號,以產生生效訊號。於操作S540,根據生效訊號選擇輸出第一時脈訊號與第二時脈訊號中之一者為最終時脈訊號。In operation S510, a first clock generating circuit is utilized to generate a first clock signal in response to a supply voltage, wherein the first clock generating circuit has a first start-up voltage. In operation S520, a second clock generating circuit is utilized to generate a second clock signal in response to the supply voltage, wherein the second clock generating circuit has a second startup voltage, and the first startup voltage is lower than the second startup voltage. Voltage. In operation S530, the second clock signal is detected to generate a validation signal. In operation S540, one of the first clock signal and the second clock signal is selected to be output as the final clock signal according to the validation signal.
上述操作S510至操作S540之說明可參照前述各個實施例,故不重複贅述。上述時脈產生方法500的多個操作僅為示例,並非限定需依照此示例中的順序執行。在不違背本案的各實施例的操作方式與範圍下,在時脈產生方法500下的各種操作當可適當地增加、替換、省略或以不同順序執行。或者,在時脈產生方法500下的一或多個操作可以是同時或部分同時執行。For the description of the above operation S510 to operation S540, reference may be made to the foregoing embodiments, so the description is not repeated. The multiple operations of the above
綜上所述,本案一些實施例中的時脈產生裝置與時脈產生方法可以更快地輸出時脈訊號,以加快系統開始運作的時間。如此,可以降低RTC應用的相關電路或晶片的開始運作時間。To sum up, the clock generating device and the clock generating method in some embodiments of the present case can output clock signals faster, so as to speed up the time for the system to start operating. In this way, the start-up time of related circuits or chips for RTC applications can be reduced.
雖然本案之實施例如上所述,然而該些實施例並非用來限定本案,本技術領域具有通常知識者可依據本案之明示或隱含之內容對本案之技術特徵施以變化,凡此種種變化均可能屬於本案所尋求之專利保護範疇,換言之,本案之專利保護範圍須視本說明書之申請專利範圍所界定者為準。Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical characteristics of this case according to the explicit or implied content of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be subject to the definition of the scope of patent application in this specification.
100, 100A:時脈產生裝置
110, 120:時脈產生電路
130, 150:偵測電路
140:選擇電路
210:電流源
220:開關
230:電容
240:反相器
250:計數器
260:比較器
300, 400:時脈產生裝置
310:邏輯閘電路
410, 420:延遲電路
500:時脈產生方法
CK1, CK2:時脈訊號
CKF:最終時脈訊號
CT:計數值
GND:地電壓
S1, S2:訊號
S510, S520, S530, S540:操作
SC1, SC2:控制訊號
SD:偵測訊號
SV:生效訊號
T0~T3:時間
TH:臨界值
TR:重置期間
VDD:供應電壓
100, 100A:
[圖1A]為根據本案一些實施例繪製時脈產生裝置的示意圖; [圖1B]為根據本案一些實施例繪製時脈產生裝置之示意圖; [圖2A]為根據本案一些實施例繪製圖1A或圖1B中的偵測電路之示意圖; [圖2B]為根據本案一些實施例繪製圖1A或圖1B中的偵測電路之示意圖; [圖3]為根據本案一些實施例繪製時脈產生裝置的示意圖; [圖4A]為根據本案一些實施例繪製時脈產生裝置的示意圖; [圖4B]為根據本案一些實施例繪製圖4A中的時脈產生裝置之時序示意圖;以及 [圖5]為根據本案一些實施例繪製時脈產生方法的流程圖。 [Fig. 1A] is a schematic diagram of a clock generating device according to some embodiments of the present case; [Fig. 1B] is a schematic diagram of a clock generating device according to some embodiments of the present invention; [Fig. 2A] is a schematic drawing of the detection circuit in Fig. 1A or Fig. 1B according to some embodiments of the present case; [Fig. 2B] is a schematic drawing of the detection circuit in Fig. 1A or Fig. 1B according to some embodiments of the present case; [Figure 3] is a schematic diagram of a clock generating device according to some embodiments of this case; [Fig. 4A] is a schematic diagram of a clock generating device according to some embodiments of the present case; [FIG. 4B] is a schematic diagram of the timing sequence of the clock generating device in FIG. 4A according to some embodiments of the present invention; and [ FIG. 5 ] is a flowchart of a clock generation method according to some embodiments of the present case.
100:時脈產生裝置 100: clock generator
110,120:時脈產生電路 110,120: clock generation circuit
130:偵測電路 130: Detection circuit
140:選擇電路 140: Select circuit
CK1,CK2:時脈訊號 CK1, CK2: clock signal
CKF:最終時脈訊號 CKF: final clock signal
SV:生效訊號 SV: Validation signal
VDD:供應電壓 VDD: supply voltage
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