TW202222022A - Active clamp flyback converter - Google Patents

Abstract

An active clamp flyback converter includes a transformer, a main switch, a clamp switch, a switching current indication circuit and a controller. The switching current indication circuit generates a switching current indication signal according to a switching voltage of a primary circuit of the transformer. The controller includes a parameter generation circuit, a delay control circuit and an on-time control circuit. The parameter generation circuit is configured to measure a target current value, a harmonic extremum value and a switching current value. The delay control circuit is configured to adjust a delay time signal according to the switching current value and the harmonic extremum value, and turn on the main switch according to the delay time signal upon applying an enabling pulse to the clamp switch. The on-time control circuit is configured to adjust a pulse width of the enabling pulse according to the target current value the harmonic extremum value, and apply the enabling pulse to the clamp switch in the next harmonic period.

Description

主動箝位返馳式轉換器Active Clamp Flyback Converter

本發明關於電源供應，特別是一種主動箝位返馳式轉換器。The present invention relates to power supply, especially an active clamp flyback converter.

返馳式轉換器(flyback converter)是輸入輸出互相隔離的電壓轉換器，適用於各種電源供應器。大致上，返馳式轉換器由電力開關控制能量的儲存及轉移。當電力開關導通時，返馳式轉換器中之一次電路會儲存能量，二次電路會被設置於逆向偏壓狀態而不會充電。當電力開關斷路時，返馳式轉換器中之一次電路會將能量轉移至二次電路，二次電路會被設置於順向偏壓狀態而進行充電。A flyback converter is a voltage converter whose input and output are isolated from each other, and is suitable for various power supplies. Basically, a flyback converter controls the storage and transfer of energy by a power switch. When the power switch is turned on, the primary circuit in the flyback converter stores energy, and the secondary circuit is set in a reverse biased state without charging. When the power switch is disconnected, the primary circuit in the flyback converter will transfer energy to the secondary circuit, and the secondary circuit will be set in a forward biased state for charging.

返馳式轉換器可配備箝位裝置及箝位開關以減低電力開關之兩端的壓差，進而減少箝位損失。然而當電力開關及箝位開關被開啟或關閉時，仍會造成開關損失。The flyback converter can be equipped with a clamping device and a clamping switch to reduce the voltage difference across the power switch, thereby reducing the clamping loss. However, when the power switch and clamp switch are turned on or off, switching losses still occur.

本發明實施例提供一種主動箝位返馳式轉換器，用以提供輸出電壓至負載，包含變壓器、主開關、箝位開關、箝位電容及控制器。變壓器包含一次電路及二次線圈。一次電路包含一次線圈，包含第一端，用以接收輸入電壓，及第二端。二次線圈包含第一端，用以輸出輸出電壓，及第二端。主開關包含控制端，第一端，耦接於一次線圈之第二端，及第二端。箝位開關包含控制端，第一端，及第二端，耦接於一次線圈之第二端。箝位電容包含第一端，耦接於一次線圈之第一端，及第二端，耦接於箝位開關之第一端。開關電流指示電路耦接於變壓器，用以依據一次電路之開關電壓產生開關電流指示訊號。控制器耦接於分壓器、主開關之控制端及箝位開關之控制端，包含參數產生電路及延遲控制電路。參數產生電路用以在諧振期間中箝位開關被施加致能脈衝後，測得開關電流指示訊號之一諧振極值，及在主開關由截止被轉換為導通狀態過程中，產生主開關於截止狀態下最後量測所得的開關電流指示訊號之切換電流值。延遲控制電路用以依據切換電流值及諧振極值調整延遲時間訊號，在箝位開關被施加另一致能脈衝後，依據延遲時間訊號導通主開關。Embodiments of the present invention provide an active clamp flyback converter for providing an output voltage to a load, including a transformer, a main switch, a clamp switch, a clamp capacitor and a controller. The transformer includes a primary circuit and a secondary coil. The primary circuit includes a primary coil, a first terminal for receiving an input voltage, and a second terminal. The secondary coil includes a first terminal for outputting the output voltage, and a second terminal. The main switch includes a control terminal, a first terminal, a second terminal coupled to the primary coil, and a second terminal. The clamping switch includes a control terminal, a first terminal, and a second terminal, which are coupled to the second terminal of the primary coil. The clamping capacitor includes a first end coupled to the first end of the primary coil, and a second end coupled to the first end of the clamping switch. The switching current indicating circuit is coupled to the transformer and used for generating a switching current indicating signal according to the switching voltage of the primary circuit. The controller is coupled to the voltage divider, the control terminal of the main switch and the control terminal of the clamping switch, and includes a parameter generating circuit and a delay control circuit. The parameter generating circuit is used to measure a resonant extreme value of the switch current indication signal after the clamp switch is applied with an enabling pulse during the resonance period, and to generate the main switch in the process of being switched from the off state to the on state. The switching current value of the switching current indicating signal obtained by the last measurement in the state. The delay control circuit is used for adjusting the delay time signal according to the switching current value and the resonance extreme value. After another enabling pulse is applied to the clamping switch, the main switch is turned on according to the delay time signal.

本發明實施例提供另一種主動箝位返馳式轉換器，用以提供輸出電壓至負載，包含變壓器、主開關、箝位開關、箝位電容及控制器。變壓器包含一次電路及二次線圈。一次電路包含一次線圈，包含第一端，用以接收輸入電壓，及第二端。二次線圈包含第一端，用以輸出輸出電壓，及第二端。主開關包含控制端，第一端，耦接於一次線圈之第二端，及第二端。箝位開關包含控制端，第一端，及第二端，耦接於一次線圈之第二端。箝位電容包含第一端，耦接於一次線圈之第一端，及第二端，耦接於箝位開關之第一端。開關電流指示電路耦接於變壓器，用以依據一次電路之開關電壓產生開關電流指示訊號。控制器耦接於分壓器、主開關之控制端及箝位開關之控制端，包含參數產生電路及導通時間控制電路。參數產生電路用以在主開關被導通時測得開關電流指示訊號之目標電流值，及在諧振期間中箝位開關被施加致能脈衝後，測得開關電流指示訊號之諧振極值。導通時間控制電路用以依據目標電流值及諧振極值調整另一致能脈衝之一脈寬，及在下一諧振期間中對箝位開關施加另一致能脈衝。Embodiments of the present invention provide another active clamp flyback converter for providing an output voltage to a load, including a transformer, a main switch, a clamp switch, a clamp capacitor, and a controller. The transformer includes a primary circuit and a secondary coil. The primary circuit includes a primary coil, a first terminal for receiving an input voltage, and a second terminal. The secondary coil includes a first terminal for outputting the output voltage, and a second terminal. The main switch includes a control terminal, a first terminal, a second terminal coupled to the primary coil, and a second terminal. The clamping switch includes a control terminal, a first terminal, and a second terminal, which are coupled to the second terminal of the primary coil. The clamping capacitor includes a first end coupled to the first end of the primary coil, and a second end coupled to the first end of the clamping switch. The switching current indicating circuit is coupled to the transformer and used for generating a switching current indicating signal according to the switching voltage of the primary circuit. The controller is coupled to the voltage divider, the control terminal of the main switch and the control terminal of the clamping switch, and includes a parameter generating circuit and an on-time control circuit. The parameter generating circuit is used to measure the target current value of the switch current indication signal when the main switch is turned on, and to measure the resonant extreme value of the switch current indication signal after the clamp switch is applied with an enabling pulse during the resonance period. The on-time control circuit is used for adjusting a pulse width of another enabling pulse according to the target current value and the resonance extreme value, and applying another enabling pulse to the clamping switch in the next resonance period.

本發明實施例提供另一種主動箝位返馳式轉換器，用以提供輸出電壓至負載，包含變壓器、主開關、箝位開關、箝位電容及控制器。變壓器包含一次電路及二次線圈。一次電路包含一次線圈，包含第一端，用以接收輸入電壓，及第二端。二次線圈包含第一端，用以輸出輸出電壓，及第二端。主開關包含控制端，第一端，耦接於一次線圈之第二端，及第二端。箝位開關包含控制端，第一端，及第二端，耦接於一次線圈之第二端。箝位電容包含第一端，耦接於一次線圈之第一端，及第二端，耦接於箝位開關之第一端。開關電流指示電路耦接於變壓器，用以依據一次電路之開關電壓產生開關電流指示訊號。控制器耦接於分壓器、主開關之控制端及箝位開關之控制端，包含參數產生電路、延遲控制電路及導通時間控制電路。參數產生電路用以在主開關被導通時測得開關電流指示訊號之目標電流值，在諧振期間中箝位開關被施加致能脈衝後，測得開關電流指示訊號之諧振極值，並且用以在主開關由截止被轉換為導通狀態過程中，產生主開關於截止狀態下最後量測所得的開關電流指示訊號之切換電流值。延遲控制電路用以依據切換電流值及諧振極值調整延遲時間訊號，在箝位開關被施加另一致能脈衝後，依據延遲時間訊號導通主開關。導通時間控制電路用以依據目標電流值及諧振極值調整另一致能脈衝之一脈寬，及在下一諧振期間中對箝位開關施加另一致能脈衝。Embodiments of the present invention provide another active clamp flyback converter for providing an output voltage to a load, including a transformer, a main switch, a clamp switch, a clamp capacitor, and a controller. The transformer includes a primary circuit and a secondary coil. The primary circuit includes a primary coil, a first terminal for receiving an input voltage, and a second terminal. The secondary coil includes a first terminal for outputting the output voltage, and a second terminal. The main switch includes a control terminal, a first terminal, a second terminal coupled to the primary coil, and a second terminal. The clamping switch includes a control terminal, a first terminal, and a second terminal, which are coupled to the second terminal of the primary coil. The clamping capacitor includes a first end coupled to the first end of the primary coil, and a second end coupled to the first end of the clamping switch. The switching current indicating circuit is coupled to the transformer and used for generating a switching current indicating signal according to the switching voltage of the primary circuit. The controller is coupled to the voltage divider, the control terminal of the main switch and the control terminal of the clamping switch, and includes a parameter generating circuit, a delay control circuit and an on-time control circuit. The parameter generating circuit is used to measure the target current value of the switch current indication signal when the main switch is turned on, and after the clamp switch is applied with an enabling pulse during the resonance period, the resonant extreme value of the switch current indication signal is measured, and used for During the process of the main switch being switched from the off state to the on state, the switching current value of the switch current indicating signal obtained by the last measurement of the main switch in the off state is generated. The delay control circuit is used for adjusting the delay time signal according to the switching current value and the resonance extreme value. After another enabling pulse is applied to the clamping switch, the main switch is turned on according to the delay time signal. The on-time control circuit is used for adjusting a pulse width of another enabling pulse according to the target current value and the resonance extreme value, and applying another enabling pulse to the clamping switch in the next resonance period.

第1圖係為本發明實施例中一種主動箝位返馳式轉換器1之電路示意圖。主動箝位返馳式轉換器1可從電壓源11接收電壓Vsrc以進行降壓或升壓轉換而產生輸出電壓VOUT，及將輸出電壓VOUT提供至負載L。電壓Vsrc為交流電壓。輸出電壓VOUT可為直流電壓。FIG. 1 is a schematic circuit diagram of an active clamp flyback converter 1 according to an embodiment of the present invention. The active clamp flyback converter 1 can receive the voltage Vsrc from the voltage source 11 for buck or boost conversion to generate the output voltage VOUT, and provide the output voltage VOUT to the load L. The voltage Vsrc is an alternating voltage. The output voltage VOUT may be a DC voltage.

主動箝位返馳式轉換器1包含電容Cin1、電容Cin2、整流器13、變壓器10、主開關Mm、箝位開關Mc、箝位電容Cc、控制器12、電阻Rs、同步整流器Msr、電容Cout、接地端14及16、及開關電流指示電路18。控制器12可控制主開關Mm及箝位開關Mc之切換。當主開關Mm在導通與截止兩狀態間切換，且每次主開關Mm切換係開啟導通一固定時段長度時，可自返馳式轉換器1的一次側傳遞實質相同的電能到轉換器1的二次側；在負載L為輕載抽取較少電能時，控制器12可控制主開關Mm以較低切換頻率，即較長的切換週期，單位時間內主開關Mm開啟導通次數較少方式運作；在負載L為重載抽取較多電能時，控制器12可控制主開關Mm以較高切換頻率，即以較短的切換週期，單位時間內主開關Mm開啟導通次數較多方式運作。控制器12可判定箝位開關Mc之導通時間及主開關Mm之導通時間，藉以達成主開關Mm之零電壓切換(zero voltage switching)以減少開關損失。The active clamp flyback converter 1 includes a capacitor Cin1, a capacitor Cin2, a rectifier 13, a transformer 10, a main switch Mm, a clamp switch Mc, a clamp capacitor Cc, a controller 12, a resistor Rs, a synchronous rectifier Msr, a capacitor Cout, The ground terminals 14 and 16 , and the switch current indicating circuit 18 . The controller 12 can control the switching of the main switch Mm and the clamping switch Mc. When the main switch Mm is switched between on and off states, and each time the main switch Mm is switched on for a fixed period of time, substantially the same power can be transferred from the primary side of the flyback converter 1 to the converter 1 . Secondary side; when the load L is a light load and draws less power, the controller 12 can control the main switch Mm to operate at a lower switching frequency, that is, a longer switching period, and the number of times the main switch Mm is turned on per unit time is less. When the load L is a heavy load and draws more power, the controller 12 can control the main switch Mm to operate at a higher switching frequency, that is, with a shorter switching period, and the main switch Mm is turned on and turned on more times per unit time. The controller 12 can determine the on-time of the clamp switch Mc and the on-time of the main switch Mm, so as to achieve zero voltage switching of the main switch Mm to reduce switching loss.

變壓器10包含一次線圈WP，包含第一端N1，用以接收輸入電壓VIN，及第二端N2；輔助線圈WA，包含第一端，及第二端；及二次線圈WS，包含第一端，用以將輸出電壓VOUT進行輸出，及第二端。一次線圈WP及輔助線圈WA屬於一次電路，二次線圈WS屬於二次電路。主開關Mm包含第一控制端，第一端，耦接於一次線圈WP之第二端N2，及第二端。電阻Rs耦接於主開關Mm之第二端及接地端14之間。主開關Mm之第一端具有開關電壓VD，輔助線圈WA之第一端具有輔助線圈電壓VA。開關電壓VD可為600~700V。箝位開關Mc包含第二控制端，第一端，及第二端，耦接於一次線圈WP之第二端N2。箝位電容Cc耦接於一次線圈WP之第一端N1及箝位開關Mc之第一端之間。開關電流指示電路18包含第一端，耦接於輔助線圈WA之第一端，第二端，用以輸出開關電流指示訊號IVS，及第三端，耦接於接地端14。控制器12耦接於主開關Mm之第一控制端、開關電流指示電路18之第二端及箝位開關Mc之第二控制端。電容Cin1耦接於接地端14。整流器13包含第一端，耦接於電容Cin1，及第二端，耦接於接地端14。電容Cin2耦接於整流器13及接地端14之間。同步整流器Msr包含第三控制端，第一端，耦接於二次線圈WS之第二端，及第二端，耦接於接地端16。電容Cout耦接於二次線圈WS之第一端及接地端16之間。接地端14及16可不互相耦接，用以維持一次側及二次側之間的隔絕。The transformer 10 includes a primary coil WP, including a first end N1, for receiving the input voltage VIN, and a second end N2; an auxiliary coil WA, including a first end and a second end; and a secondary coil WS, including the first end , used to output the output voltage VOUT, and the second terminal. The primary coil WP and the auxiliary coil WA belong to the primary circuit, and the secondary coil WS belongs to the secondary circuit. The main switch Mm includes a first control terminal, a first terminal, a second terminal N2 coupled to the primary coil WP, and a second terminal. The resistor Rs is coupled between the second terminal of the main switch Mm and the ground terminal 14 . The first terminal of the main switch Mm has the switching voltage VD, and the first terminal of the auxiliary coil WA has the auxiliary coil voltage VA. The switching voltage VD can be 600~700V. The clamping switch Mc includes a second control terminal, a first terminal, and a second terminal, and is coupled to the second terminal N2 of the primary coil WP. The clamping capacitor Cc is coupled between the first end N1 of the primary coil WP and the first end of the clamping switch Mc. The switch current indication circuit 18 includes a first end coupled to the first end of the auxiliary coil WA, a second end for outputting the switch current indication signal IVS, and a third end coupled to the ground end 14 . The controller 12 is coupled to the first control terminal of the main switch Mm, the second terminal of the switch current indicating circuit 18 and the second control terminal of the clamping switch Mc. The capacitor Cin1 is coupled to the ground terminal 14 . The rectifier 13 includes a first terminal coupled to the capacitor Cin1 and a second terminal coupled to the ground terminal 14 . The capacitor Cin2 is coupled between the rectifier 13 and the ground terminal 14 . The synchronous rectifier Msr includes a third control terminal, a first terminal, a second terminal coupled to the secondary coil WS, and a second terminal coupled to the ground terminal 16 . The capacitor Cout is coupled between the first end of the secondary coil WS and the ground end 16 . The ground terminals 14 and 16 may not be coupled to each other to maintain isolation between the primary side and the secondary side.

電容Cin1可濾除電壓Vsrc中之高頻雜訊，整流器13可對電壓Vsrc進行整流，電容Cin2可使整流後之電壓Vsrc平緩以產生輸入電壓VIN。一次線圈WP及二次線圈WS之匝數比可為P:1，P係為正數。在一些實施例中，P可大於1，且變壓器10可為下轉換(step-down)變壓器10。一次線圈WP之極性及二次線圈WS之極性可相反。一次線圈WP及輔助線圈WA之匝數比可為Q:1，Q係為大於1之正數。一次線圈WP具有一次互感Lp1及漏感，二次線圈WS具有二次互感Ls，輔助線圈WA具有輔助互感Lp2。因為一次線圈WP及輔助線圈WA存在匝數比關係，當開關電壓VD變化時，輔助線圈WA上可依據匝數比Q:1對應產生輔助線圈電壓VA。輔助線圈電壓VA及開關電壓VD之極性可相反，且輔助線圈電壓VA可與開關電壓VD的絕對值依據1/Q的比例成正相關(VA = -VD/Q)。The capacitor Cin1 can filter out high frequency noise in the voltage Vsrc, the rectifier 13 can rectify the voltage Vsrc, and the capacitor Cin2 can smooth the rectified voltage Vsrc to generate the input voltage VIN. The turns ratio of the primary coil WP and the secondary coil WS may be P:1, and P is a positive number. In some embodiments, P may be greater than 1 and the transformer 10 may be a step-down transformer 10 . The polarity of the primary coil WP and the polarity of the secondary coil WS may be opposite. The turns ratio of the primary coil WP and the auxiliary coil WA may be Q:1, where Q is a positive number greater than 1. The primary coil WP has a primary mutual inductance Lp1 and a leakage inductance, the secondary coil WS has a secondary mutual inductance Ls, and the auxiliary coil WA has an auxiliary mutual inductance Lp2. Because the primary coil WP and the auxiliary coil WA have a turns ratio relationship, when the switching voltage VD changes, the auxiliary coil WA can correspondingly generate the auxiliary coil voltage VA according to the turns ratio Q:1. The polarities of the auxiliary coil voltage VA and the switching voltage VD may be opposite, and the auxiliary coil voltage VA may be positively related to the absolute value of the switching voltage VD according to the ratio of 1/Q (VA = -VD/Q).

開關電流指示電路18可依據輔助線圈電壓VA建立分壓VA’，及依據分壓VA’提供開關電流指示訊號IVS至控制器12。開關電流指示電路18可為分壓器，包含電阻R1及R2。電阻R1可耦接於開關電流指示電路18。電阻R2可耦接於電阻R1及接地端14之間。The switch current indication circuit 18 can establish a voltage division VA' according to the auxiliary coil voltage VA, and provide the switch current indication signal IVS to the controller 12 according to the voltage division VA'. The switch current indicating circuit 18 may be a voltage divider including resistors R1 and R2. The resistor R1 can be coupled to the switch current indicating circuit 18 . The resistor R2 can be coupled between the resistor R1 and the ground terminal 14 .

控制器12可依據電流指示訊號IVS來控制主開關Mm及箝位開關Mc。以下段落中使用電流指示訊號IVS控制主開關Mm及箝位開關Mc來說明主動箝位返馳式轉換器1的運作。和直接使用開關電壓VD產生電流指示訊號IVS相比，由於輔助線圈電壓VA之最大絕對值小於開關電壓VD之最大絕對值，控制器12可使用耐壓較小之半導體元件(device)來接收電流指示訊號IVS來進行開關控制，進而節省電路面積。The controller 12 can control the main switch Mm and the clamping switch Mc according to the current instruction signal IVS. In the following paragraphs, the operation of the active clamp flyback converter 1 is described by using the current indicating signal IVS to control the main switch Mm and the clamp switch Mc. Compared with directly using the switching voltage VD to generate the current indicating signal IVS, since the maximum absolute value of the auxiliary coil voltage VA is smaller than the maximum absolute value of the switching voltage VD, the controller 12 can use a semiconductor device with a lower withstand voltage to receive the current. The indication signal IVS is used for switching control, thereby saving circuit area.

主開關Mm及箝位開關Mc可由N型金屬氧化物半導體場效電晶體(metal-oxide- semiconductor field-effect transistor, MOSFET)實現。同步整流器Msr可由N型MOSFET、NPN型雙極性電晶體(bipolar junction transistor, BJT)、絕緣閘雙極晶體管(insulated-gate bipolar transistor, IGBT)或其他種類之開關元件實現。在一些實施例中，同步整流器Msr可由二極體替代。The main switch Mm and the clamping switch Mc can be implemented by an N-type metal-oxide-semiconductor field-effect transistor (MOSFET). The synchronous rectifier Msr can be implemented by an N-type MOSFET, an NPN-type bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT) or other types of switching elements. In some embodiments, the synchronous rectifier Msr may be replaced by a diode.

主開關Mm可控制能量的儲存及轉移。箝位開關Mc可控制回收漏感儲存的能量及產生負向磁化電流(magnetizing current)Im(由一次互感Lp1的第二端N2流向一次互感Lp1的第一端N1)。The main switch Mm can control the storage and transfer of energy. The clamp switch Mc can control to recover the energy stored in the leakage inductance and generate a negative magnetizing current Im (flowing from the second terminal N2 of the primary mutual inductance Lp1 to the first terminal N1 of the primary mutual inductance Lp1 ).

(1) 充電期間：當控制器12藉由控制訊號GL導通主開關Mm一段預定時段以產生主開關脈波時，變壓器10之一次側的電流及磁通增加，能量儲存在變壓器電感中；亦即通過一次互感Lp1之正向磁化電流Im(由一次互感Lp1的第一端N1流向一次互感Lp1的第二端N2)增加；同時控制器12截止變壓器10之二次側的同步整流器Msr，因此二次互感Ls不會產生有二次感應電流，而是由電容Cout提供輸出電壓VOUT至負載L。如此對變壓器10進行能量儲存之期間可稱為充電期間。於充電期間，控制器12可藉由控制訊號GH截止箝位開關Mc。(1) During charging: when the controller 12 turns on the main switch Mm for a predetermined period of time through the control signal GL to generate the main switch pulse, the current and magnetic flux of the primary side of the transformer 10 increase, and the energy is stored in the transformer inductance; That is, the forward magnetizing current Im through the primary mutual inductance Lp1 (flowing from the first terminal N1 of the primary mutual inductance Lp1 to the second terminal N2 of the primary mutual inductance Lp1 ) increases; at the same time, the controller 12 turns off the synchronous rectifier Msr on the secondary side of the transformer 10, so The secondary mutual inductance Ls does not generate secondary induced current, but the capacitor Cout provides the output voltage VOUT to the load L. The period during which energy is stored in the transformer 10 in this way may be referred to as a charging period. During the charging period, the controller 12 can turn off the clamp switch Mc through the control signal GH.

(2) 放電期間：當正向磁化電流Im已到達預定值、或主開關Mm導通時間已到達預定時段，則控制器12可藉由控制訊號GL截止主開關Mm，使得變壓器10之一次側的電流及磁通減少，一次線圈WP及二次線圈WS之極性會被反向；且二次側控制器(未圖示)導通同步整流器Msr，於二次側產生二次感應電流。如此可使儲存於變壓器10之一次線圈WP中之能量被轉移至二次側，二次感應電流對電容Cout充電並提供輸出電壓VOUT至負載L。如此自變壓器10釋出能量進行能量轉移之期間亦可稱為放電期間。同步整流器Msr可由控制訊號GSR控制，控制訊號GSR可依據二次線圈WS之第二端之電壓產生。(2) Discharge period: when the forward magnetizing current Im has reached a predetermined value, or the conduction time of the main switch Mm has reached a predetermined period, the controller 12 can turn off the main switch Mm by the control signal GL, so that the primary side of the transformer 10 When the current and magnetic flux decrease, the polarities of the primary coil WP and the secondary coil WS are reversed; and the secondary side controller (not shown) turns on the synchronous rectifier Msr to generate a secondary induced current on the secondary side. In this way, the energy stored in the primary winding WP of the transformer 10 can be transferred to the secondary side, and the secondary induced current charges the capacitor Cout and provides the output voltage VOUT to the load L. The period during which energy is released from the transformer 10 for energy transfer can also be referred to as a discharge period. The synchronous rectifier Msr can be controlled by the control signal GSR, and the control signal GSR can be generated according to the voltage of the second end of the secondary coil WS.

(3) 諧振期間：在放電期間之後，當儲存於變壓器10之一次線圈WP中之能量被釋放完畢時，開關電壓VD會以輸入電壓VIN為中心上下震盪而產生複數個波峰，如此可稱為諧振期間。(3) Resonance period: After the discharge period, when the energy stored in the primary coil WP of the transformer 10 is released, the switching voltage VD will oscillate up and down around the input voltage VIN to generate multiple peaks, which can be called as during resonance.

一旦主開關Mm截止後，主動箝位返馳式轉換器1進入放電期間，開關電壓VD會先增加，稍後可能以一電壓準位為中心值而經歷複數個諧波震盪，當開關電壓VD到達電壓準位(VIN+Vclamp)時，正向磁化電流Im會流經漏感、一次互感Lp1、箝位開關Mc之內接二極體(body diode)、箝位電容Cc而將儲存於漏感之能量轉移至箝位電容Cc，進而將箝位電容Cc充電至電壓準位(VIN+N*VOUT)，電壓Vclamp係為箝位電壓。在複數個諧波震盪結束後，開關電壓VD會維持於實質上固定之電壓準位(VIN+N*VOUT)。例如在第2圖中，於主開關脈衝Pm11結束(時間點t2)後，開關電壓VD會先增加，稍後再以電壓準位(VIN+N*VOUT)為中心值而經歷複數個諧波震盪。在複數個諧波震盪結束(時間點t3)後，開關電壓VD會維持於實質上固定之電壓準位(VIN+N*VOUT)。Once the main switch Mm is turned off, the active clamp flyback converter 1 enters the discharge period, the switch voltage VD will increase first, and then may experience multiple harmonic oscillations with a voltage level as the center value. When the switch voltage VD When reaching the voltage level (VIN+Vclamp), the forward magnetizing current Im will flow through the leakage inductance, the primary mutual inductance Lp1, the body diode connected to the clamping switch Mc, and the clamping capacitor Cc, and will be stored in the leakage The inductive energy is transferred to the clamping capacitor Cc, and then the clamping capacitor Cc is charged to the voltage level (VIN+N*VOUT), and the voltage Vclamp is the clamping voltage. After the multiple harmonic oscillations are over, the switching voltage VD is maintained at a substantially fixed voltage level (VIN+N*VOUT). For example, in Fig. 2, after the main switching pulse Pm11 ends (time point t2), the switching voltage VD will increase first, and then experience a plurality of harmonics with the voltage level (VIN+N*VOUT) as the center value. shock. After the multiple harmonic oscillations end (time point t3 ), the switching voltage VD is maintained at a substantially fixed voltage level (VIN+N*VOUT).

於放電期間，控制器12可在控制訊號GH中***能量回收脈波，用以導通箝位開關Mc以將儲存於漏感之能量轉移至箝位電容Cc。控制器12可於偵測到開關電壓VD達到穩態時或於放電期間內的固定時間點***能量回收脈波。能量回收脈波可具有實質上固定之脈寬。固定時間點可為主開關Mm被截止後之預定時間。During the discharge period, the controller 12 can insert an energy recovery pulse into the control signal GH to turn on the clamp switch Mc to transfer the energy stored in the leakage inductance to the clamp capacitor Cc. The controller 12 may insert an energy recovery pulse when it is detected that the switching voltage VD reaches a steady state or at a fixed time point during the discharge period. The energy recovery pulse wave may have a substantially fixed pulse width. The fixed time point may be a predetermined time after the main switch Mm is turned off.

於諧振期間，當輔助線圈電壓VA接近波峰時，控制器12可對箝位開關Mc施加致能脈衝，用以導通箝位開關Mc以產生負向磁化電流Im，利用此負向磁化電流Im以拉低開關電壓VD，及於當開關電壓VD趨近於0V時，控制器12可對主開關Mm施加主開關脈衝，使主開關Mm在後續充電期間開始時達成零電壓切換。於放電期間及諧振期間，控制器12可藉由控制訊號GL截止主開關Mm。控制器12可調整致能脈衝之脈寬以控制負向磁化電流Im之大小。當致能脈衝之脈寬過小時，負向磁化電流Im會過小而無法將開關電壓VD拉低至0V，使主開關Mm無法達成零電壓切換，增加開關損失。當致能脈衝之脈寬過大時，負向磁化電流Im會過早將開關電壓VD拉低至0V並持續產生能量消耗，增加能量損失。控制器12可調整致能脈衝之脈寬以產生合適之負向磁化電流Im，使主開關Mm達成零電壓切換時不過早將開關電壓VD拉低至0V，大幅減少切換主開關Mm及負向磁化電流Im造成之能量損失。在致能脈衝結束後，控制器12可延遲主開關脈衝一段延遲時間以於開關電壓VD實質上等於0V或趨近於0V時導通主開關Mm，達成零電壓切換及減少開關損失。During the resonance period, when the auxiliary coil voltage VA is close to the peak, the controller 12 can apply an enabling pulse to the clamping switch Mc to turn on the clamping switch Mc to generate a negative magnetizing current Im, and use the negative magnetizing current Im to The switch voltage VD is pulled down, and when the switch voltage VD approaches 0V, the controller 12 can apply a main switch pulse to the main switch Mm, so that the main switch Mm achieves zero voltage switching at the beginning of the subsequent charging period. During the discharge period and the resonance period, the controller 12 can turn off the main switch Mm by the control signal GL. The controller 12 can adjust the pulse width of the enabling pulse to control the magnitude of the negative magnetizing current Im. When the pulse width of the enabling pulse is too small, the negative magnetizing current Im will be too small to pull the switching voltage VD down to 0V, so that the main switch Mm cannot achieve zero-voltage switching, increasing the switching loss. When the pulse width of the enabling pulse is too large, the negative magnetizing current Im will pull down the switching voltage VD to 0V prematurely and continue to consume energy, increasing the energy loss. The controller 12 can adjust the pulse width of the enable pulse to generate a suitable negative magnetizing current Im, so that the switch voltage VD is not pulled down to 0V prematurely when the main switch Mm achieves zero-voltage switching, which greatly reduces the switching of the main switch Mm and the negative direction. Energy loss due to magnetizing current Im. After the enabling pulse ends, the controller 12 can delay the main switching pulse for a delay time to turn on the main switch Mm when the switching voltage VD is substantially equal to 0V or approaching 0V to achieve zero voltage switching and reduce switching loss.

第2圖係為主動箝位返馳式轉換器1之一種設置情況下之訊號波形圖，依序顯示第一充電期間Tglon1、放電期間Tdis1、諧振期間Tres1及第二充電期間Tglon2。第一充電期間Tglon1、放電期間Tdis1及諧振期間Tres1構成第1個轉換週期，第二充電期間Tglon2屬於後續之第2個轉換週期。針對第1個轉換週期，控制器12於時間點t1至t2在控制訊號GL中***主開關脈衝Pm11，於時間點t3至t4在控制訊號GH中***能量回收脈波Pc11，及於時間點t6至t7在控制訊號GH中***致能脈衝Pc12。針對第2個轉換週期，控制器12於時間點t9至t10在控制訊號GL中***主開關脈衝Pm21，及稍後在控制訊號GH中***能量回收脈波與致能脈衝(未圖示)。控制器12可調整：(1)致能脈衝Pc12之脈寬TGH2，及(2)介於致能脈衝Pc12結束與主開關脈衝Pm21之間的一段延遲時間TD。藉由調整該段延遲時間TD，可以確保當開關電壓VD趨近於0V時(時間點t9)再次導通主開關Mm。致能脈衝Pc12之脈寬TGH2、能量回收脈波Pc11之脈寬TGH1，及主開關脈衝Pm11，Pm21之脈寬彼此之間並沒有一定大小關係；第2圖僅為一例示關係：致能脈衝Pc12之脈寬TGH2可大於能量回收脈波Pc11之脈寬TGH1，及可小於主開關脈衝Pm11，Pm21之脈寬，但不以此為限。FIG. 2 is a signal waveform diagram of a configuration of the active clamp flyback converter 1 , showing the first charging period Tglon1 , the discharging period Tdis1 , the resonance period Tres1 and the second charging period Tglon2 in sequence. The first charging period Tglon1, the discharging period Tdis1 and the resonance period Tres1 constitute the first conversion period, and the second charging period Tglon2 belongs to the subsequent second conversion period. For the first conversion cycle, the controller 12 inserts the main switching pulse Pm11 into the control signal GL at time points t1 to t2, inserts the energy recovery pulse Pc11 into the control signal GH at time points t3 to t4, and at time point t6 To t7, the enable pulse Pc12 is inserted into the control signal GH. For the second conversion cycle, the controller 12 inserts the main switching pulse Pm21 into the control signal GL from time points t9 to t10, and inserts an energy recovery pulse and an enabling pulse (not shown) into the control signal GH later. The controller 12 can adjust: (1) the pulse width TGH2 of the enable pulse Pc12, and (2) a delay time TD between the end of the enable pulse Pc12 and the main switching pulse Pm21. By adjusting the delay time TD, it can be ensured that the main switch Mm is turned on again when the switch voltage VD approaches 0V (time point t9). The pulse width TGH2 of the enable pulse Pc12, the pulse width TGH1 of the energy recovery pulse Pc11, and the pulse widths of the main switching pulses Pm11 and Pm21 do not have a certain size relationship with each other; Figure 2 is only an example of the relationship: the enable pulse The pulse width TGH2 of Pc12 can be larger than the pulse width TGH1 of the energy recovery pulse Pc11, and can be smaller than the pulse widths of the main switching pulses Pm11 and Pm21, but not limited thereto.

控制器12可包含參數產生電路120、導通時間控制電路122及延遲控制電路124。參數產生電路120可依據開關電流指示訊號IVS產生開關電流指示訊號IVS之目標電流值、諧振極值及切換電流值。具體而言，參數產生電路120可在主開關Mm被導通時測得開關電流指示訊號IVS之目標電流值，在諧振期間中箝位開關Mc被施加致能脈衝後，測得開關電流指示訊號IVS之諧振極值，並且可在主開關Mm由截止被轉換為導通狀態過程中，產生主開關Mm於截止狀態下最後量測所得的開關電流指示訊號IVS之切換電流值。The controller 12 may include a parameter generation circuit 120 , an on-time control circuit 122 and a delay control circuit 124 . The parameter generating circuit 120 can generate the target current value, the resonance extreme value and the switching current value of the switching current indicating signal IVS according to the switching current indicating signal IVS. Specifically, the parameter generating circuit 120 can measure the target current value of the switch current indication signal IVS when the main switch Mm is turned on, and measure the switch current indication signal IVS after the clamp switch Mc is applied with an enabling pulse during the resonance period and can generate the switching current value of the switching current indicating signal IVS obtained by the last measurement of the main switch Mm in the off state when the main switch Mm is switched from the off state to the on state.

參考第2圖說明三項參數電流值：Refer to Figure 2 to illustrate the three parameter current values:

(1)        目標電流值IVS_GL：例如可為於第一充電期間Tglon1或第二充電期間Tglon2內，主開關Mm開啟導通而使開關電壓VD下降至一最低電壓時，所測得之開關電流指示訊號IVS的電流值。(1) Target current value IVS_GL: for example, in the first charging period Tglon1 or the second charging period Tglon2, when the main switch Mm is turned on and the switch voltage VD drops to a minimum voltage, the measured switch current indication signal IVS current value.

(2)        諧振極值IVSP：例如可為於諧振期間Tres1中箝位開關Mc被施加具有脈寬TGH2的致能脈衝Pc12後，所測得開關電流指示訊號IVS之最大值，如圖示時間點t8之波形最大值，亦即諧振極值IVSP代表對應開關電壓VD所能達到之最小電壓值Vmin。當調整致能脈衝Pc12的脈寬TGH2時，諧振極值IVSP也會隨之改變。當諧振極值IVSP等於該目標電流值IVS_GL時，表示致能脈衝Pc12具有足夠的脈寬TGH2，足以使開關電壓VD下拉至該最低電位。(2) Resonance extreme value IVSP: for example, it can be the maximum value of the switch current indication signal IVS measured after the clamp switch Mc is applied with the enable pulse Pc12 with the pulse width TGH2 during the resonance period Tres1, as shown at the time point shown in the figure The maximum value of the waveform at t8, that is, the resonant extreme value IVSP represents the minimum voltage value Vmin that can be achieved by the corresponding switching voltage VD. When the pulse width TGH2 of the enabling pulse Pc12 is adjusted, the resonance extreme value IVSP will also change accordingly. When the resonance extreme value IVSP is equal to the target current value IVS_GL, it means that the enabling pulse Pc12 has a sufficient pulse width TGH2 to pull down the switch voltage VD to the lowest level.

(3)        切換電流值IVS_GLR：例如可為於時間點t9主開關Mm被主開關脈衝Pm21開啟導通之前(immediately before)，主開關Mm於截止狀態下最後量測所得的開關電流指示訊號IVS。搭配(1)(2)條件--諧振極值IVSP會接近目標電流值IVS_GL，當切換電流值IVS_GLR接近該目標電流值IVS_GL時，也代表主開關Mm開啟導通時間點(對應切換電流值IVS_GLR)接近該諧振極值IVSP發生時間點。如此可避免自諧振極值IVSP發生時間點延遲較久時間，等到開關電流指示訊號IVS較大幅度衰減後才開啟導通主開關Mm。(3) The switching current value IVS_GLR: for example, at the time point t9, the main switch Mm is turned on immediately before the main switch pulse Pm21 is turned on (immediately before), and the main switch Mm is in the off state. The switch current indication signal IVS finally measured. With (1) (2) conditions - the resonance extreme value IVSP will be close to the target current value IVS_GL, when the switching current value IVS_GLR is close to the target current value IVS_GL, it also represents the turn-on time point of the main switch Mm (corresponding to the switching current value IVS_GLR) It is close to the time point when the resonance extreme value IVSP occurs. In this way, a long delay in the occurrence of the self-resonant extreme value IVSP can be avoided, and the main switch Mm is turned on only after the switch current indicating signal IVS is attenuated to a large extent.

導通時間控制電路122可依據目標電流值IVS_GL及諧振極值IVSP調整另一致能脈衝之脈寬，及在稍後轉換週期的下一諧振期間中對箝位開關Mc施加此調整後的另一致能脈衝。導通時間控制電路122可調整另一致能脈衝之脈寬以使諧振極值IVSP實質上等於目標電流值IVS_GL，進而使負向磁化電流Im足以將開關電壓VD拉低至0V及達成主開關Mm之零電壓切換。The on-time control circuit 122 can adjust the pulse width of another enable pulse according to the target current value IVS_GL and the resonance extreme value IVSP, and apply the adjusted another enable pulse to the clamping switch Mc in the next resonance period of the later conversion cycle pulse. The on-time control circuit 122 can adjust the pulse width of the other enable pulse so that the resonant extreme value IVSP is substantially equal to the target current value IVS_GL, so that the negative magnetizing current Im is sufficient to pull down the switch voltage VD to 0V and reach the main switch Mm. Zero voltage switching.

延遲控制電路124可依據切換電流值IVS_GLR及諧振極值IVSP調整延遲時間訊號，在稍後轉換週期中，箝位開關Mc被施加另一致能脈衝後，依據此調整後的延遲時間訊號導通主開關Mm。延遲時間訊號可用於判定延遲時間TD。延遲控制電路124可調整延遲時間訊號以使切換電流值IVS_GLR實質上等於諧振極值IVSP，進而減小主開關Mm之開關損失。The delay control circuit 124 can adjust the delay time signal according to the switching current value IVS_GLR and the resonant extreme value IVSP. In a later switching cycle, after another enabling pulse is applied to the clamp switch Mc, the main switch is turned on according to the adjusted delay time signal. Mm. The delay time signal can be used to determine the delay time TD. The delay control circuit 124 can adjust the delay time signal to make the switching current value IVS_GLR substantially equal to the resonance extreme value IVSP, thereby reducing the switching loss of the main switch Mm.

第3圖係為主動箝位返馳式轉換器1之另一種設置情況下之訊號波形圖，包含3轉換週期，第1個轉換週期係介於時間點t1至t9之間，第2個轉換週期係介於時間點t9至t17之間，第3個轉換週期係介於時間點t17至t24之間。Figure 3 is a signal waveform diagram of another setting of the active clamp flyback converter 1, including 3 conversion cycles, the first conversion cycle is between time points t1 and t9, and the second conversion cycle The period is between time points t9 and t17, and the third conversion period is between time points t17 and t24.

在第1個轉換週期中，控制器12依據預設設定於時間點t1至t2之間對主開關Mm施加主開關脈衝Pm11，於時間點t3至t4之間對箝位開關Mc施加能量回收脈波Pc11及於時間點t6至t7之間對箝位開關Mc施加致能脈衝Pc12；參數產生電路120於時間點t1至t2之間測得目標電流值IVS_GL，於時間點t8測得諧振極值IVSP，及於時間點t9之前測得切換電流值IVS_GLR。諧振極值IVSP顯著小於目標電流值IVS_GL，切換電流值IVS_GLR顯著小於諧振極值IVSP。In the first conversion cycle, the controller 12 applies the main switching pulse Pm11 to the main switch Mm between the time points t1 and t2 according to the preset setting, and applies the energy recovery pulse to the clamping switch Mc between the time points t3 and t4. The wave Pc11 and the enabling pulse Pc12 is applied to the clamping switch Mc between the time points t6 and t7; the parameter generating circuit 120 measures the target current value IVS_GL between the time points t1 and t2, and measures the resonance extreme value at the time point t8 IVSP, and the switching current value IVS_GLR is measured before time point t9. The resonance extreme value IVSP is significantly smaller than the target current value IVS_GL, and the switching current value IVS_GLR is significantly smaller than the resonance extreme value IVSP.

在第2個轉換週期中，控制器12於時間點t9至t10之間對主開關Mm施加主開關脈衝Pm21及於時間點t11至t12之間對箝位開關Mc施加能量回收脈波Pc21；由於第1個轉換週期中的時間點t8量測所得之諧振極值IVSP小於目標電流值IVS_GL，導通時間控制電路122會增加對箝位開關Mc施加之致能脈衝Pc22的脈寬TGH22，使脈寬TGH22大於脈寬TGH12。同時由於第1個轉換週期中的時間點t9量測所得之切換電流值IVS_GLR小於諧振極值IVSP，延遲控制電路124會縮短延遲時間訊號之脈寬，使延遲時間TD2小於延遲時間TD1，在施加致能脈衝Pc22後經過延遲時間TD2時即對主開關Mm施加主開關脈衝Pm31，如此縮減主開關Mm導通時間點(時間點t17)與諧振極值IVSP時間點(時間點t16)兩者的時間間隔。參數產生電路120於第2個轉換週期中的時間點t9至t10之間再次測得目標電流值IVS_GL，於時間點t16再次測得諧振極值IVSP，及於時間點t17之前再次測得切換電流值IVS_GLR。判定第2個轉換週期中的諧振極值IVSP小於目標電流值IVS_GL，切換電流值IVS_GLR小於諧振極值IVSP，因此於第3個轉換週期需要進一步增加致能脈衝Pc32的脈寬TGH32，並縮短延遲時間TD3。In the second conversion cycle, the controller 12 applies the main switching pulse Pm21 to the main switch Mm between the time points t9 and t10, and applies the energy recovery pulse Pc21 to the clamping switch Mc between the time points t11 and t12; The resonance extreme value IVSP measured at the time point t8 in the first conversion cycle is smaller than the target current value IVS_GL, and the on-time control circuit 122 increases the pulse width TGH22 of the enable pulse Pc22 applied to the clamp switch Mc to make the pulse width TGH22 is greater than the pulse width TGH12. At the same time, since the switching current value IVS_GLR measured at the time point t9 in the first conversion cycle is smaller than the resonance extreme value IVSP, the delay control circuit 124 will shorten the pulse width of the delay time signal, so that the delay time TD2 is smaller than the delay time TD1. When the delay time TD2 elapses after the enabling pulse Pc22, the main switch pulse Pm31 is applied to the main switch Mm, thus reducing the time between the conduction time point (time point t17) of the main switch Mm and the resonance extreme value IVSP time point (time point t16) interval. The parameter generation circuit 120 measures the target current value IVS_GL again between the time points t9 and t10 in the second conversion cycle, measures the resonance extreme value IVSP again at the time point t16, and measures the switching current again before the time point t17 Value IVS_GLR. It is determined that the resonance extreme value IVSP in the second conversion cycle is less than the target current value IVS_GL, and the switching current value IVS_GLR is less than the resonance extreme value IVSP. Therefore, in the third conversion cycle, it is necessary to further increase the pulse width TGH32 of the enable pulse Pc32 and shorten the delay Time TD3.

在第3個轉換週期中，控制器12於時間點t17至t18之間對主開關Mm施加主開關脈衝Pm31及於時間點t19至t20之間對箝位開關Mc施加能量回收脈波Pc31；由於第2個轉換週期中之諧振極值IVSP小於目標電流值IVS_GL，導通時間控制電路122會於時間點t22至t23增加對箝位開關Mc施加之致能脈衝Pc32之脈寬TGH32，使脈寬TGH32大於脈寬TGH22；由於第2個轉換週期中之切換電流值IVS_GLR小於諧振極值IVSP，延遲控制電路124會縮短延遲時間訊號之脈寬，使延遲時間TD3小於延遲時間TD2，在施加致能脈衝Pc32後經過延遲時間TD3時即對主開關Mm施加主開關脈衝Pm41，如此進一步縮減主開關Mm導通時間點與諧振極值IVSP時間點兩者的時間間隔，使兩者幾乎都位在時間點t24；參數產生電路120於第3個轉換週期中的時間點t17至t18之間再次測得目標電流值IVS_GL，於時間點t24再次測得諧振極值IVSP，及於時間點t24之前再次測得切換電流值IVS_GLR。判定第3個轉換週期中的諧振極值IVSP實質上等於目標電流值IVS_GL，切換電流值IVS_GLR實質上等於諧振極值IVSP，亦即依據目前的致能脈衝脈寬與延遲時間設定下，負向磁化電流Im足以將開關電壓VD拉低至0V且主開關Mm可進行零電壓切換。因此在稍後的轉換週期中，導通時間控制電路122可實質上維持目前設定的致能脈衝之脈寬，延遲控制電路124可實質上維持目前設定的延遲時間訊號之脈寬。In the third conversion cycle, the controller 12 applies the main switching pulse Pm31 to the main switch Mm between the time points t17 and t18 and applies the energy recovery pulse Pc31 to the clamping switch Mc between the time points t19 and t20; The resonance extreme value IVSP in the second conversion cycle is smaller than the target current value IVS_GL, and the on-time control circuit 122 increases the pulse width TGH32 of the enable pulse Pc32 applied to the clamp switch Mc from the time point t22 to t23, so that the pulse width TGH32 is greater than the pulse width TGH22; since the switching current value IVS_GLR in the second conversion cycle is smaller than the resonant extreme value IVSP, the delay control circuit 124 will shorten the pulse width of the delay time signal, so that the delay time TD3 is smaller than the delay time TD2. When the delay time TD3 elapses after Pc32, the main switch pulse Pm41 is applied to the main switch Mm, so that the time interval between the conduction time point of the main switch Mm and the resonance extreme value IVSP time point is further shortened, so that both are almost at the time point t24. ; The parameter generation circuit 120 measures the target current value IVS_GL again between the time points t17 and t18 in the third conversion cycle, measures the resonance extreme value IVSP again at the time point t24, and measures the switching again before the time point t24 Current value IVS_GLR. It is determined that the resonance extreme value IVSP in the third conversion cycle is substantially equal to the target current value IVS_GL, and the switching current value IVS_GLR is substantially equal to the resonance extreme value IVSP. The magnetizing current Im is sufficient to pull the switch voltage VD down to 0V and the main switch Mm can perform zero-voltage switching. Therefore, in a later conversion cycle, the on-time control circuit 122 can substantially maintain the currently set pulse width of the enable pulse, and the delay control circuit 124 can substantially maintain the currently set pulse width of the delay time signal.

第4圖係為第1圖中導通時間控制電路122之電路示意圖。導通時間控制電路122包含比較電壓電路40、延遲電壓電路42、箝位器44及致能脈衝電路46。比較電壓電路40耦接於箝位器44，箝位器44及延遲電壓電路42耦接於致能脈衝電路46。導通時間控制電路122可依據致能脈衝啓始訊號GH2S觸發而產生致能脈衝SGH2(如第3圖之致能脈衝Pc12、Pc22、Pc32)，及依據目標電流值IVS_GL及諧振極值IVSP判定致能脈衝SGH2之結束時間點。導通時間控制電路122可調整致能脈衝SGH2之結束時間點，進而調整致能脈衝SGH2之脈寬，以使諧振極值IVSP實質上等於目標電流值IVS_GL。FIG. 4 is a schematic circuit diagram of the on-time control circuit 122 in FIG. 1 . The on-time control circuit 122 includes a comparison voltage circuit 40 , a delay voltage circuit 42 , a clamp 44 and an enable pulse circuit 46 . The comparison voltage circuit 40 is coupled to the clamp 44 , and the clamp 44 and the delay voltage circuit 42 are coupled to the enabling pulse circuit 46 . The on-time control circuit 122 can generate an enable pulse SGH2 (such as the enable pulses Pc12, Pc22, and Pc32 in FIG. 3) according to the enable pulse start signal GH2S, and determine the result according to the target current value IVS_GL and the resonance extreme value IVSP. The end time point of the energy pulse SGH2. The on-time control circuit 122 can adjust the end time point of the enable pulse SGH2, and further adjust the pulse width of the enable pulse SGH2, so that the resonance extreme value IVSP is substantially equal to the target current value IVS_GL.

比較電壓電路40可依據目標電流值IVS_GL及諧振極值IVSP建立比較電壓Vc1。具體而言，比較電壓電路40可將目標電流值IVS_GL乘以N以產生偏移目標電流值(IVS_GL*N)，及持續調整比較電壓Vc1直到諧振極值IVSP實質上等於偏移目標電流值(IVS_GL*N)為止，N係為小於或等於1之正數，偏移目標電流值(IVS_GL*N)為目標電流值IVS_GL之等比縮小值或相等值，例如可選擇N為介於0.97~0.98範圍區間數值，如此持續保留和目標電流值IVS_GL之間存在有2%~3% 差值，也確保諧振極值IVSP不會超過目標電流值IVS_GL。當諧振極值IVSP小於偏移目標電流值(IVS_GL*N)時，比較電壓電路40會增加比較電壓Vc1；當諧振極值IVSP大於偏移目標電流值(IVS_GL*N)時，比較電壓電路40會降低比較電壓Vc1；當諧振極值IVSP實質上等於偏移目標電流值(IVS_GL*N)時，比較電壓電路40會維持比較電壓Vc1。當比較電壓電路40係使用偏移目標電流值(IVS_GL*N)產生比較電壓Vc1，且N為介於0.97~0.98範圍區間數值時，則當致能脈衝SGH2之脈寬逐漸增加到使諧振極值IVSP達到目標電流值IVS_GL*0.99時，比較電壓電路40就會開始調整縮小致能脈衝SGH2之脈寬，如此可確保存在回調縮小致能脈衝SGH2脈寬的電壓區間。The comparison voltage circuit 40 can establish the comparison voltage Vc1 according to the target current value IVS_GL and the resonance extreme value IVSP. Specifically, the comparison voltage circuit 40 can multiply the target current value IVS_GL by N to generate the offset target current value (IVS_GL*N), and continuously adjust the comparison voltage Vc1 until the resonance extreme value IVSP is substantially equal to the offset target current value ( IVS_GL*N), N is a positive number less than or equal to 1, and the offset target current value (IVS_GL*N) is the proportional reduction value or the equivalent value of the target current value IVS_GL, for example, N can be selected to be between 0.97~0.98 There is a 2%~3% difference between the continuous retention and the target current value IVS_GL, and it also ensures that the resonance extreme value IVSP does not exceed the target current value IVS_GL. When the resonance extreme value IVSP is smaller than the offset target current value (IVS_GL*N), the comparison voltage circuit 40 increases the comparison voltage Vc1; when the resonance extreme value IVSP is greater than the offset target current value (IVS_GL*N), the comparison voltage circuit 40 increases the comparison voltage Vc1 The comparison voltage Vc1 will be lowered; when the resonance extreme value IVSP is substantially equal to the offset target current value (IVS_GL*N), the comparison voltage circuit 40 will maintain the comparison voltage Vc1. When the comparison voltage circuit 40 uses the offset target current value (IVS_GL*N) to generate the comparison voltage Vc1, and N is a value in the range of 0.97-0.98, the pulse width of the enable pulse SGH2 is gradually increased to make the resonant pole When the value IVSP reaches the target current value IVS_GL*0.99, the comparison voltage circuit 40 will start to adjust the pulse width of the shrink enable pulse SGH2 , so as to ensure that there is a voltage range in which the pulse width of the shrink enable pulse SGH2 is adjusted back.

比較電壓電路40可包含電流產生器400及406、開關402及404及電容C1。電流產生器400耦接於供電端41，電流產生器406耦接於接地端14，供電端41可提供第一電流I1。開關402包含第一端，耦接於電流產生器400，及第二端。開關404包含第一端，及第二端，耦接於電流產生器406。電容C1包含第一端，耦接於開關402之第二端及開關404之第一端，及第二端，耦接於接地端14。電流產生器400及406可為電流控制電流源。電流產生器400可依據偏移目標電流值(IVS_GL*N)及第一電流I1產生第一差值電流。電流產生器406可依據諧振極值IVSP及第二電流I2產生第二差值電流。開關402及404可依據短脈衝訊號Ps而被導通或截止。當開關402及404被導通時，電流產生器400可產生偏移目標電流值(IVS_GL*N)及第一電流之間之第一差值電流，電流產生器406可產生諧振極值IVSP及第二電流I2之間之第二差值電流，第一差值電流可對電容C1充電及第二差值電流可使電容C1放電以於電容C1建立比較電壓Vc1。若第一電流I1實質上等於第二電流I2，則比較電壓Vc1可與偏移目標電流值(IVS_GL*N)及諧振極值IVSP之間之差值成正相關。當開關402及404被截止時，電容C1可維持比較電壓Vc1。使用短脈衝訊號Ps控制開關402及404可降低電容C1所需之電容值，逐漸將比較電壓Vc1調整至穩定值而不至於一次調整太多。在一些實施例中，可將開關402及404由比較電壓電路40中移除，電容C1之第一端耦接於電流產生器400及電流產生器406。箝位器44耦接於電容C1之第一端，可將比較電壓Vc1限制於箝位範圍之內以產生箝位電壓Vc1’。箝位範圍可為電壓上限VH1及電壓下限VL1之間的範圍，用以界定致能脈衝SGH2之脈寬的範圍。在一些實施例中，箝位器44亦可由導通時間控制電路122中省略而使電容C1之第一端耦接於致能脈衝電路46。The comparison voltage circuit 40 may include current generators 400 and 406, switches 402 and 404, and a capacitor C1. The current generator 400 is coupled to the power supply terminal 41 , the current generator 406 is coupled to the ground terminal 14 , and the power supply terminal 41 can provide the first current I1 . The switch 402 includes a first terminal coupled to the current generator 400 and a second terminal. The switch 404 includes a first terminal and a second terminal, which are coupled to the current generator 406 . The capacitor C1 includes a first terminal coupled to the second terminal of the switch 402 and the first terminal of the switch 404 , and a second terminal coupled to the ground terminal 14 . Current generators 400 and 406 may be current controlled current sources. The current generator 400 can generate the first difference current according to the offset target current value (IVS_GL*N) and the first current I1. The current generator 406 can generate the second difference current according to the resonance extreme value IVSP and the second current I2. The switches 402 and 404 can be turned on or off according to the short pulse signal Ps. When the switches 402 and 404 are turned on, the current generator 400 can generate a first difference current between the offset target current value (IVS_GL*N) and the first current, and the current generator 406 can generate the resonance extreme value IVSP and the first difference current. The second difference current between the two currents I2, the first difference current can charge the capacitor C1 and the second difference current can discharge the capacitor C1 to establish the comparison voltage Vc1 on the capacitor C1. If the first current I1 is substantially equal to the second current I2, the comparison voltage Vc1 may be positively correlated with the difference between the offset target current value (IVS_GL*N) and the resonance extreme value IVSP. When the switches 402 and 404 are turned off, the capacitor C1 can maintain the comparison voltage Vc1. Using the short pulse signal Ps to control the switches 402 and 404 can reduce the capacitance value required by the capacitor C1 and gradually adjust the comparison voltage Vc1 to a stable value without adjusting too much at one time. In some embodiments, the switches 402 and 404 can be removed from the comparison voltage circuit 40 , and the first terminal of the capacitor C1 is coupled to the current generator 400 and the current generator 406 . The clamp 44 is coupled to the first end of the capacitor C1, and can limit the comparison voltage Vc1 within the clamping range to generate the clamping voltage Vc1'. The clamping range can be the range between the upper voltage limit VH1 and the lower voltage limit VL1, and is used to define the range of the pulse width of the enable pulse SGH2. In some embodiments, the clamp 44 can also be omitted from the on-time control circuit 122 so that the first end of the capacitor C1 is coupled to the enable pulse circuit 46 .

延遲電壓電路42可建立延遲電壓Vc2，延遲電壓Vc2自致能脈衝SGH2之開始時間點開始遞增，直到延遲電壓Vc2實質上等於箝位電壓Vc1’為止。延遲電壓電路42包含電流產生器420、開關422及424及電容C2。開關422包含第一端，耦接於電流產生器420，及第二端。開關424包含第一端，耦接於開關422之第二端，及第二端，耦接於接地端14。電容C2包含第一端，耦接於開關422之第二端，及第二端，耦接於接地端。The delay voltage circuit 42 can establish the delay voltage Vc2, which increases from the start time point of the enable pulse SGH2 until the delay voltage Vc2 is substantially equal to the clamping voltage Vc1'. The delay voltage circuit 42 includes a current generator 420, switches 422 and 424, and a capacitor C2. The switch 422 includes a first terminal, coupled to the current generator 420, and a second terminal. The switch 424 includes a first terminal coupled to the second terminal of the switch 422 , and a second terminal coupled to the ground terminal 14 . The capacitor C2 includes a first terminal coupled to the second terminal of the switch 422, and a second terminal coupled to the ground terminal.

電流產生器420可產生預定電流I3，預定電流I3可與第一電流I1相同或不同。開關422可依據致能脈衝SGH2而被導通或截止，開關424可依據反向致能脈衝SGH2B而被導通或截止，致能脈衝SGH2及反向致能脈衝SGH2B可互為反相。當開關422被致能脈衝SGH2導通且開關424被反向致能脈衝SGH2B截止時，預定電流I3可對電容C2充電，藉以建立比較電壓Vc2；當開關422被致能脈衝SGH2截止且開關424被反向致能脈衝SGH2B導通時，電容C2經由開關424而放電。由於C2* Vc2=I3*t，C2為電容C2之電容值，Vc2為比較電壓，I3為電容C2之充電電流，電容C2之充電時間t可與比較電壓Vc2成正相關。比較電壓Vc2越大，充電時間t越長。The current generator 420 may generate a predetermined current I3, which may be the same as or different from the first current I1. The switch 422 can be turned on or off according to the enable pulse SGH2, and the switch 424 can be turned on or off according to the reverse enable pulse SGH2B, and the enable pulse SGH2 and the reverse enable pulse SGH2B can be mutually inverse. When the switch 422 is turned on by the enable pulse SGH2 and the switch 424 is turned off by the reverse enable pulse SGH2B, the predetermined current I3 can charge the capacitor C2 to establish the comparison voltage Vc2; when the switch 422 is turned off by the enable pulse SGH2 and the switch 424 is turned off When the reverse enable pulse SGH2B is turned on, the capacitor C2 is discharged through the switch 424 . Since C2* Vc2=I3*t, C2 is the capacitance value of the capacitor C2, Vc2 is the comparison voltage, I3 is the charging current of the capacitor C2, and the charging time t of the capacitor C2 can be positively correlated with the comparison voltage Vc2. The larger the comparison voltage Vc2 is, the longer the charging time t is.

致能脈衝電路46可依據箝位電壓Vc1’及延遲電壓Vc2決定致能脈衝SGH2之結束時間點。致能脈衝電路46包含比較器460及正反器462。比較器460包含第一輸入端，耦接於延遲電壓電路42，第二輸入端，耦接於比較電壓電路40，及輸出端，用以輸出比較訊號GH2R。正反器462包含輸入端S，可接收脈衝開始訊號GH2S，重置端R耦接於比較器460之輸出端，用以依據比較訊號GH2R重置正反器462，及輸出端，耦接於開關422之控制端，用以輸出致能脈衝SGH2。脈衝開始訊號GH2S之開始時間可依據負載L所消耗之消耗能量或負載阻抗決定。在一些實施例中，脈衝開始訊號GH2S之開始時間可依據負載L所消耗之消耗能量決定，當負載L所消耗之能量減少時，脈衝開始訊號GH2S之開始時間也隨之延後；當負載所消耗之能量增加時，脈衝開始訊號GH2S之開始時間也隨之提前。在另一些實施例中，脈衝開始訊號GH2S之開始時間可依據負載L之負載阻抗決定，當輸出電壓VOUT為實質上固定的值時，若負載阻抗較大時，負載L所抽取的電流較小，脈衝開始訊號GH2S之開始時間也隨之延後；當負載阻抗較小時，負載L所抽取的電流較大，脈衝開始訊號GH2S之開始時間也隨之提前。比較器460可依據延遲電壓Vc2及箝位電壓Vc1’產生比較訊號GH2R。正反器462可由致能脈衝啓始訊號GH2S觸發產生致能脈衝SGH2，及由比較訊號GH2R重置致能脈衝SGH2。於收到致能脈衝啓始訊號GH2S之後，正反器462可產生致能脈衝SGH2直到被比較訊號GH2R重置為止。The enabling pulse circuit 46 can determine the end time point of the enabling pulse SGH2 according to the clamping voltage Vc1' and the delay voltage Vc2. The enabling pulse circuit 46 includes a comparator 460 and a flip-flop 462 . The comparator 460 includes a first input terminal coupled to the delay voltage circuit 42, a second input terminal coupled to the comparison voltage circuit 40, and an output terminal for outputting the comparison signal GH2R. The flip-flop 462 includes an input terminal S, which can receive the pulse start signal GH2S, a reset terminal R, which is coupled to the output terminal of the comparator 460 for resetting the flip-flop 462 according to the comparison signal GH2R, and an output terminal, which is coupled to the output terminal of the comparator 460. The control terminal of the switch 422 is used to output the enable pulse SGH2. The start time of the pulse start signal GH2S can be determined according to the power consumption consumed by the load L or the load impedance. In some embodiments, the start time of the pulse start signal GH2S can be determined according to the energy consumed by the load L. When the energy consumed by the load L decreases, the start time of the pulse start signal GH2S is also delayed; When the consumed energy increases, the start time of the pulse start signal GH2S also advances. In other embodiments, the start time of the pulse start signal GH2S can be determined according to the load impedance of the load L. When the output voltage VOUT is a substantially fixed value, if the load impedance is relatively large, the current drawn by the load L is relatively small. , the start time of the pulse start signal GH2S is also delayed; when the load impedance is small, the current drawn by the load L is larger, and the start time of the pulse start signal GH2S is also advanced. The comparator 460 can generate the comparison signal GH2R according to the delay voltage Vc2 and the clamping voltage Vc1'. The flip-flop 462 can be triggered by the enable pulse start signal GH2S to generate the enable pulse SGH2, and the enable pulse SGH2 is reset by the comparison signal GH2R. After receiving the enable pulse start signal GH2S, the flip-flop 462 can generate the enable pulse SGH2 until it is reset by the comparison signal GH2R.

當偏移目標電流值(IVS_GL*N)小於諧振極值IVSP時，第一差值電流會小於第二差值電流，比較電壓Vc1會下降，比較訊號GH2R較早發生，進而使致能脈衝SGH2之脈寬縮短；當偏移目標電流值(IVS_GL*N)大於諧振極值IVSP時，第一差值電流會大於第二差值電流，比較電壓Vc1會上升，比較訊號GH2R較晚發生，進而使致能脈衝SGH2之脈寬加長；當偏移目標電流值(IVS_GL*N)等於諧振極值IVSP時，第一差值電流會等於第二差值電流，比較電壓Vc1會維持實質穩定，進而使致能脈衝SGH2之脈寬維持不變。When the offset target current value (IVS_GL*N) is smaller than the resonance extreme value IVSP, the first difference current will be smaller than the second difference current, the comparison voltage Vc1 will drop, the comparison signal GH2R will be generated earlier, and the enable pulse SGH2 will be enabled When the offset target current value (IVS_GL*N) is greater than the resonance extreme value IVSP, the first difference current will be greater than the second difference current, the comparison voltage Vc1 will rise, the comparison signal GH2R will be generated later, and then The pulse width of the enabling pulse SGH2 is lengthened; when the offset target current value (IVS_GL*N) is equal to the resonance extreme value IVSP, the first difference current will be equal to the second difference current, the comparison voltage Vc1 will remain substantially stable, and then The pulse width of the enabling pulse SGH2 remains unchanged.

第5圖係為第1圖中延遲控制電路124之電路示意圖。延遲控制電路124包含比較電壓電路50、延遲電壓電路52、箝位器54及延遲時間電路56。延遲控制電路124可依據反向致能脈衝SGH2B觸發而產生延遲時間訊號Sdly，及依據諧振極值IVSP及切換電流值IVS_GLR判定延遲時間訊號Sdly之結束時間點。延遲控制電路124可調整延遲時間訊號Sdly之結束時間點以使切換電流值IVS_GLR實質上等於諧振極值IVSP。FIG. 5 is a schematic circuit diagram of the delay control circuit 124 in FIG. 1 . The delay control circuit 124 includes a comparison voltage circuit 50 , a delay voltage circuit 52 , a clamp 54 and a delay time circuit 56 . The delay control circuit 124 can generate the delay time signal Sdly according to the reverse enabling pulse SGH2B, and determine the end time point of the delay time signal Sdly according to the resonance extreme value IVSP and the switching current value IVS_GLR. The delay control circuit 124 can adjust the end time point of the delay time signal Sdly so that the switching current value IVS_GLR is substantially equal to the resonance extreme value IVSP.

比較電壓電路50包含電流產生器500、開關502、開關504、電流產生器506及電容CR。電流產生器500耦接於供電端41，電流產生器506耦接於接地端14。開關502包含第一端，耦接於電流產生器500，及第二端。開關504包含第一端，耦接於開關502之第二端，及第二端，耦接於電流產生器506。電容CR包含第一端，耦接於開關502之第二端及開關504之第一端，及第二端，耦接於接地端14。電流產生器500可產生預定電流Iset。電流產生器506可為電流控制電流源，及可依據諧振極值IVSP及切換電流值IVS_GLR產生差值電流(IVSP-IVS_GLR)。開關502及504可依據短脈衝訊號Ps而被導通或截止。當開關502及504被導通時，電流產生器500可產生預定電流Iset，電流產生器506可產生諧振極值IVSP及切換電流值IVS_GLR之間之差值電流(IVSP-IVS_GLR)，預定電流Iset可對電容CR充電及差值電流(IVSP-IVS_GLR)可使電容CR放電以於電容CR建立比較電壓VCR。當開關502及504被截止時，電容CR可維持比較電壓VCR。使用短脈衝訊號Ps控制開關502及504可降低電容CR所需之電容值，逐漸將比較電壓VCR調整至穩定值而不至於一次調整太多。在一些實施例中，可將開關502及504由比較電壓電路50中移除，電容CR之第一端耦接於電流產生器500及電流產生器506。箝位器54耦接於電容CR之第一端，可將比較電壓VCR限制於箝位範圍之內以產生箝位電壓VRTD。箝位範圍可為電壓上限VH及電壓下限VL之間的範圍，用以界定延遲時間訊號Sdly之脈寬的範圍。在一些實施例中，箝位器54亦可由延遲控制電路124中省略而使電容CR之第一端耦接於延遲時間電路56。The comparison voltage circuit 50 includes a current generator 500 , a switch 502 , a switch 504 , a current generator 506 and a capacitor CR. The current generator 500 is coupled to the power supply terminal 41 , and the current generator 506 is coupled to the ground terminal 14 . The switch 502 includes a first terminal, coupled to the current generator 500, and a second terminal. The switch 504 includes a first end coupled to the second end of the switch 502 , and a second end coupled to the current generator 506 . The capacitor CR includes a first terminal coupled to the second terminal of the switch 502 and the first terminal of the switch 504 , and a second terminal coupled to the ground terminal 14 . The current generator 500 may generate a predetermined current Iset. The current generator 506 can be a current-controlled current source, and can generate a differential current (IVSP-IVS_GLR) according to the resonance extreme value IVSP and the switching current value IVS_GLR. The switches 502 and 504 can be turned on or off according to the short pulse signal Ps. When the switches 502 and 504 are turned on, the current generator 500 can generate a predetermined current Iset, the current generator 506 can generate a difference current (IVSP-IVS_GLR) between the resonance extreme value IVSP and the switching current value IVS_GLR, and the predetermined current Iset can be Charging the capacitor CR and the differential current (IVSP-IVS_GLR) can discharge the capacitor CR to establish the comparison voltage VCR on the capacitor CR. When the switches 502 and 504 are turned off, the capacitor CR can maintain the comparison voltage VCR. Using the short pulse signal Ps to control the switches 502 and 504 can reduce the capacitance value required by the capacitor CR, and gradually adjust the comparison voltage VCR to a stable value without adjusting too much at one time. In some embodiments, the switches 502 and 504 can be removed from the comparison voltage circuit 50 , and the first terminal of the capacitor CR is coupled to the current generator 500 and the current generator 506 . The clamp 54 is coupled to the first end of the capacitor CR, and can limit the comparison voltage VCR within the clamping range to generate the clamping voltage VRTD. The clamping range can be a range between the upper voltage limit VH and the lower voltage limit VL, and is used to define the range of the pulse width of the delay time signal Sdly. In some embodiments, the clamp 54 can also be omitted from the delay control circuit 124 so that the first end of the capacitor CR is coupled to the delay time circuit 56 .

延遲電壓電路52可建立延遲電壓VCA，延遲電壓VCA自致能脈衝SGH2之結束時間點(反向致能脈衝SGH2之開始時間點)開始遞增，直到延遲電壓VCA實質上等於箝位電壓VRTD為止。延遲電壓電路52包含電流產生器520、開關522、開關524及電容CA。電流產生器520可產生預定電流ITD。開關522包含第一端，耦接於電流產生器520，第二端，及控制端。開關524包含第一端，耦接於開關522之第二端，及第二端，耦接於接地端14。電容CA可依據預定電流ITD建立延遲電壓，包含第一端，耦接於開關522之第二端，及第二端，耦接於接地端14。開關524可接收致能脈衝SGH2用以控制其導通和截止。開關522之控制端係耦接於延遲時間電路56之正反器562的輸入端，開關522之控制端及正反器562的輸入端均接收反向致能脈衝SGH2B。反向致能脈衝SGH2B與致能脈衝SGH2互為反相。由於CA*VCA=ITD*t，CA為電容CA之電容值，VCA為延遲電壓，ITD為電容CA之充電電流，電容CA之充電時間t可與比較電壓VCA成正相關。比較電壓VCA越大，充電時間t越長。The delay voltage circuit 52 can establish a delay voltage VCA that increases from the end time point of the enable pulse SGH2 (the start time point of the reverse enable pulse SGH2 ) until the delay voltage VCA is substantially equal to the clamping voltage VRTD. The delay voltage circuit 52 includes a current generator 520, a switch 522, a switch 524, and a capacitor CA. The current generator 520 may generate a predetermined current ITD. The switch 522 includes a first terminal coupled to the current generator 520, a second terminal, and a control terminal. The switch 524 includes a first terminal coupled to the second terminal of the switch 522 , and a second terminal coupled to the ground terminal 14 . The capacitor CA can establish a delay voltage according to the predetermined current ITD, and includes a first terminal coupled to the second terminal of the switch 522 and a second terminal coupled to the ground terminal 14 . The switch 524 can receive the enable pulse SGH2 to control its turn-on and turn-off. The control terminal of the switch 522 is coupled to the input terminal of the flip-flop 562 of the delay time circuit 56 . The control terminal of the switch 522 and the input terminal of the flip-flop 562 both receive the reverse enabling pulse SGH2B. The reverse enabling pulse SGH2B and the enabling pulse SGH2 are mutually inverse. Since CA*VCA=ITD*t, CA is the capacitance value of the capacitor CA, VCA is the delay voltage, ITD is the charging current of the capacitor CA, and the charging time t of the capacitor CA can be positively correlated with the comparison voltage VCA. The larger the comparison voltage VCA, the longer the charging time t.

延遲時間電路56耦接於延遲電壓電路52及箝位器54，可依據箝位電壓VRTD及延遲電壓VCA產生延遲時間訊號Sdly。延遲時間電路56包含比較器560及正反器562。比較器560可依據延遲電壓VCA及箝位電壓VRTD產生比較訊號Vcp，包含第一輸入端，耦接於延遲電壓電路52，第二輸入端，耦接於箝位器54，及輸出端，用以輸出比較訊號Vcp。比較訊號Vcp可正相關於延遲電壓VCA及箝位電壓VRTD之間之差值。正反器562包含輸入端，用以接收反向致能脈衝SGH2B，重置端，耦接於比較器560之輸出端，用以依據比較訊號Vcp重置正反器562，及輸出端，用以輸出延遲時間訊號Sdly。延遲時間訊號Sdly自致能脈衝SGH2之結束時間點開始，持續到當延遲電壓VCA遞增到大於箝位電壓VRTD時結束。The delay time circuit 56 is coupled to the delay voltage circuit 52 and the clamper 54, and can generate the delay time signal Sdly according to the clamp voltage VRTD and the delay voltage VCA. Delay time circuit 56 includes comparator 560 and flip-flop 562 . The comparator 560 can generate the comparison signal Vcp according to the delay voltage VCA and the clamping voltage VRTD, and includes a first input terminal coupled to the delay voltage circuit 52, a second input terminal coupled to the clamper 54, and an output terminal for to output the comparison signal Vcp. The comparison signal Vcp may be positively related to the difference between the delay voltage VCA and the clamping voltage VRTD. The flip-flop 562 includes an input terminal for receiving the reverse enabling pulse SGH2B, a reset terminal, coupled to the output terminal of the comparator 560 for resetting the flip-flop 562 according to the comparison signal Vcp, and an output terminal for using To output the delay time signal Sdly. The delay time signal Sdly starts from the end time point of the enable pulse SGH2 and lasts until the delay voltage VCA increases to be greater than the clamping voltage VRTD.

當差值電流(IVSP-IVS_GLR)等於預定電流Iset時，比較電壓VCR維持實質穩定，延遲時間訊號Sdly之脈寬維持實質不變；當差值電流(IVSP-IVS_GLR)大於預定電流Iset時，比較電壓VCR下降，比較訊號Vcp較早發生，進而使延遲時間訊號Sdly之脈寬縮短；當差值電流(IVSP-IVS_GLR)小於預定電流Iset時，比較電壓VCR上升，比較訊號Vcp較晚發生，進而使延遲時間訊號Sdly加長。舉例而言，當差值電流(IVSP-IVS_GLR)等於0A時，預定電流Iset會使比較電壓VCR增加，進而使延遲時間訊號Sdly之脈寬加長；如此確保主開關Mm導通時間點是在諧振極值IVSP發生時間點後，至少具有對應於預定電流Iset的延遲時間間隔；避免延遲時間訊號Sdly之脈寬過短，導致主開關Mm斷路關閉狀態下且已經施加致能脈衝後的開關電流指示訊號IVS尚未上升到達最大值前，過早施加主開關脈衝Pm。When the difference current (IVSP-IVS_GLR) is equal to the predetermined current Iset, the comparison voltage VCR remains substantially stable, and the pulse width of the delay time signal Sdly remains substantially unchanged; when the difference current (IVSP-IVS_GLR) is greater than the predetermined current Iset, the comparison When the voltage VCR drops, the comparison signal Vcp occurs earlier, thereby shortening the pulse width of the delay time signal Sdly; when the difference current (IVSP-IVS_GLR) is less than the predetermined current Iset, the comparison voltage VCR rises, the comparison signal Vcp occurs later, and then Make the delay time signal Sdly longer. For example, when the difference current (IVSP-IVS_GLR) is equal to 0A, the predetermined current Iset will increase the comparison voltage VCR, thereby lengthening the pulse width of the delay time signal Sdly; this ensures that the main switch Mm is turned on at the resonant pole. After the time point when the value IVSP occurs, there is at least a delay time interval corresponding to the predetermined current Iset; avoid that the pulse width of the delay time signal Sdly is too short, resulting in the switch current indication signal when the main switch Mm is in the open-circuit closed state and the enable pulse has been applied The main switching pulse Pm is applied prematurely before IVS has risen to the maximum value.

第1圖至第5圖之實施例依據輔助線圈電壓VA產生開關電流指示訊號IVS，依據開關電流指示訊號IVS之目標電流值IVS_GL及諧振極值IVSP調整施加於箝位開關之致能脈衝之脈寬，及依據開關電流指示訊號IVS之諧振極值IVSP及切換電流值IVS_GLR調整延遲時間以於延遲時間之後對主開關施加主開關脈衝，藉以達成主開關之零電壓切換，及降低主動箝位返馳式轉換器之能量損失。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The embodiments in FIGS. 1 to 5 generate the switch current indication signal IVS according to the auxiliary coil voltage VA, and adjust the pulse of the enable pulse applied to the clamp switch according to the target current value IVS_GL and the resonance extreme value IVSP of the switch current indication signal IVS and adjust the delay time according to the resonant extreme value IVSP of the switch current indication signal IVS and the switching current value IVS_GLR to apply the main switch pulse to the main switch after the delay time, so as to achieve zero voltage switching of the main switch and reduce the active clamp return. energy loss in the galvanic converter. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

1:主動箝位返馳式轉換器 10:變壓器 11:電壓源 12:控制器 120:參數產生電路 122:導通時間控制電路 124:延遲控制電路 13:整流器 14,16:接地端 18:開關電流指示電路 40,50:比較電壓電路 400,406,420,500,506,520:電流產生器 402,404,422,424,502,504,522,524:開關 42,52:延遲電壓電路 44,54:箝位器 46:致能脈衝電路 56:延遲時間電路 Cc:箝位電容 Cin1,Cin2,Cout,C1,C2,CA,CR:電容 GH,GL,GSR:控制訊號 GH2S:脈衝開始訊號 GH2R,Vcp:比較訊號 Im:磁化電流 I1:第一電流 I2:第二電流 I3,Iset,ITD:預定電流 IVS:開關電流指示訊號 IVS_GL:目標電流值 IVS_GLR:切換電流值 IVSP:諧振極值 L:負載 Lp1:一次互感 Ls:二次互感 Mc:箝位開關 Mm:主開關 Msr:同步整流器 Pm11至Pm41,Pc11,Pc12,Pc21,Pc22,Pc31,Pc32:脈衝 Ps:短脈衝訊號 R1,R2,Rs:電阻 Sdly:延遲時間訊號 SGH2:致能脈衝 SGH2B:反向致能脈衝 TD,TD1至TD3:延遲時間 TGH1,TGH2,TGH12至TGH32:脈寬 Tdis1至Tdis3:放電期間 Tglon1至Tglon3:充電期間 Tres1至Tres3:諧振期間 t1至t24:時間點 VA:輔助線圈電壓 VA’:分壓 Vc1,VCR:比較電壓 Vc1’,VRTD:箝位電壓 Vc2,VCA:延遲電壓 VD:開關電壓 VIN:輸入電壓 Vsrc:電壓 VH1,VH:上限 VL1,VL:下限 VOUT:輸出電壓 WP:一次線圈 WS:二次線圈 WA:輔助線圈 1: Active clamp flyback converter 10: Transformer 11: Voltage source 12: Controller 120: Parameter generation circuit 122: On-time control circuit 124: Delay control circuit 13: Rectifier 14,16: Ground terminal 18: switch current indication circuit 40,50: Comparing Voltage Circuits 400, 406, 420, 500, 506, 520: Current Generators 402, 404, 422, 424, 502, 504, 522, 524: switch 42,52: Delay Voltage Circuit 44,54: Clamp 46: Enable pulse circuit 56: Delay time circuit Cc: Clamping Capacitor Cin1, Cin2, Cout, C1, C2, CA, CR: Capacitor GH,GL,GSR: Control signal GH2S: Pulse start signal GH2R, Vcp: Comparison signal Im: magnetizing current I1: the first current I2: second current I3, Iset, ITD: predetermined current IVS: switch current indication signal IVS_GL: target current value IVS_GLR: Switching current value IVSP: Resonant Extreme Value L: load Lp1: a mutual inductance Ls: Secondary mutual inductance Mc: Clamp switch Mm: main switch Msr: Synchronous Rectifier Pm11 to Pm41, Pc11, Pc12, Pc21, Pc22, Pc31, Pc32: Pulse Ps: short pulse signal R1, R2, Rs: resistance Sdly: Delay time signal SGH2: enable pulse SGH2B: reverse enable pulse TD, TD1 to TD3: Delay time TGH1, TGH2, TGH12 to TGH32: Pulse width Tdis1 to Tdis3: During discharge Tglon1 to Tglon3: During charging Tres1 to Tres3: During resonance t1 to t24: time point VA: Auxiliary coil voltage VA’: partial pressure Vc1, VCR: Compare voltage Vc1', VRTD: clamping voltage Vc2, VCA: delay voltage VD: switch voltage VIN: input voltage Vsrc: Voltage VH1, VH: upper limit VL1,VL: lower limit VOUT: output voltage WP: Primary Coil WS: Secondary coil WA: Auxiliary coil

第1圖係為本發明實施例中一種主動箝位返馳式轉換器之電路示意圖。 第2圖係為第1圖中主動箝位返馳式轉換器之一種運作設置的訊號波形圖。 第3圖係為第1圖中主動箝位返馳式轉換器之另一種運作設置的訊號波形圖。 第4圖係為第1圖中導通時間控制電路之電路示意圖。 第5圖係為第1圖中延遲控制電路之電路示意圖。 FIG. 1 is a schematic circuit diagram of an active clamp flyback converter according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram of an operating setup of the active clamp flyback converter in FIG. 1 . Figure 3 is a signal waveform diagram of another operating setup of the active clamp flyback converter in Figure 1. FIG. 4 is a schematic circuit diagram of the on-time control circuit in FIG. 1 . FIG. 5 is a schematic circuit diagram of the delay control circuit in FIG. 1 .

GH,GL:控制訊號 GH,GL: control signal

IVS:開關電流指示訊號 IVS: switch current indication signal

IVS_GL:目標電流值 IVS_GL: target current value

IVS_GLR:切換電流值 IVS_GLR: Switching current value

IVSP:諧振極值 IVSP: Resonant Extreme Value

Pm11至Pm41,Pc11,Pc12,Pc21,Pc22,Pc31,Pc32:脈衝 Pm11 to Pm41, Pc11, Pc12, Pc21, Pc22, Pc31, Pc32: Pulse

TD1至TD3:延遲時間 TD1 to TD3: Delay time

TGH12至TGH32:脈寬 TGH12 to TGH32: Pulse width

Tdis1至Tdis3:放電期間 Tdis1 to Tdis3: During discharge

Tglon1至Tglon3:充電期間 Tglon1 to Tglon3: During charging

Tres1至Tres3:諧振期間 Tres1 to Tres3: During resonance

t1至t24:時間點 t1 to t24: time points

VD:開關電壓 VD: switch voltage

Claims (20)

一種主動箝位返馳式轉換器，用以提供一輸出電壓至一負載，包含: 一變壓器，包含: 一一次電路，包含: 一一次線圈，包含一第一端，用以接收一輸入電壓，及一第二端；及 一二次線圈，包含一第一端，用以輸出一輸出電壓，及一第二端； 一主開關，包含一控制端，一第一端，耦接於該一次線圈之該第二端，及一第二端，該主開關之該第一端具有一開關電壓； 一箝位開關，包含一控制端，一第一端，及一第二端，耦接於該一次線圈之該第二端； 一箝位電容，包含一第一端，耦接於該一次線圈之該第一端，及一第二端，耦接於該箝位開關之第一端； 一開關電流指示電路，耦接於該變壓器，用以依據該開關電壓產生一開關電流指示訊號；及 一控制器，耦接於該開關電流指示電路、該主開關之該控制端及該箝位開關之該控制端，包含: 一參數產生電路，用以在一諧振期間中該箝位開關被施加一致能脈衝後，測得該開關電流指示訊號之一諧振極值，及在該主開關由截止被轉換為導通狀態過程中，產生該主開關於截止狀態下最後量測所得的該開關電流指示訊號之一切換電流值；及 一延遲控制電路，用以依據該切換電流值及該諧振極值調整一延遲時間訊號，在該箝位開關被施加另一致能脈衝後，依據該延遲時間訊號導通該主開關。 An active clamp flyback converter for providing an output voltage to a load, comprising: A transformer, containing: A primary circuit, including: a primary coil, comprising a first end for receiving an input voltage, and a second end; and a secondary coil, comprising a first end for outputting an output voltage, and a second end; a main switch, comprising a control terminal, a first terminal coupled to the second terminal of the primary coil, and a second terminal, the first terminal of the main switch has a switching voltage; a clamping switch, comprising a control terminal, a first terminal, and a second terminal, coupled to the second terminal of the primary coil; a clamping capacitor, comprising a first end coupled to the first end of the primary coil, and a second end coupled to the first end of the clamping switch; a switch current indication circuit, coupled to the transformer, for generating a switch current indication signal according to the switch voltage; and A controller, coupled to the switch current indicating circuit, the control terminal of the main switch and the control terminal of the clamping switch, includes: a parameter generating circuit for measuring a resonant extreme value of the switch current indicating signal after the clamping switch is applied with an enabling pulse during a resonance period, and when the main switch is switched from off to on state , generating a switching current value of the switch current indicating signal obtained by the last measurement of the main switch in the off state; and A delay control circuit is used for adjusting a delay time signal according to the switching current value and the resonance extreme value. After another enabling pulse is applied to the clamping switch, the main switch is turned on according to the delay time signal. 如請求項1所述之主動箝位返馳式轉換器，其中該延遲控制電路包含: 一比較電壓電路，用以依據該諧振極值及該切換電流值產生一差值電流，及依據該差值電流建立一比較電壓； 一延遲電壓電路，用以建立一延遲電壓，該延遲電壓自該致能脈衝結束時間點開始遞增；及 一延遲時間電路，耦接於該比較電壓電路及該延遲電壓電路，用以依據該比較電壓及該延遲電壓產生該延遲時間訊號。 The actively clamped flyback converter of claim 1, wherein the delay control circuit comprises: a comparison voltage circuit for generating a difference current according to the resonance extreme value and the switching current value, and establishing a comparison voltage according to the difference current; a delay voltage circuit for establishing a delay voltage, the delay voltage increasing from the end time point of the enable pulse; and A delay time circuit, coupled to the comparison voltage circuit and the delay voltage circuit, is used for generating the delay time signal according to the comparison voltage and the delay voltage. 如請求項2所述之主動箝位返馳式轉換器，其中該比較電壓電路包含: 一第一電流產生器，用以產生一第一預定電流； 一第二電流產生器，用以依據該諧振極值及該切換電流值產生該差值電流；及 一第一電容，用以依據該第一預定電流及該差值電流建立該比較電壓，包含一第一端，耦接於該第一電流產生器及該第二電流產生器，及一第二端，耦接於一接地端。 The active clamp flyback converter of claim 2, wherein the comparing voltage circuit comprises: a first current generator for generating a first predetermined current; a second current generator for generating the difference current according to the resonance extreme value and the switching current value; and a first capacitor for establishing the comparison voltage according to the first predetermined current and the difference current, comprising a first end coupled to the first current generator and the second current generator, and a second The terminal is coupled to a ground terminal. 如請求項3所述之主動箝位返馳式轉換器，其中: 當該差值電流等於該第一預定電流時，該比較電壓維持實質穩定； 當該差值電流大於該第一預定電流時，該比較電壓下降，進而使該延遲時間訊號縮短； 當該差值電流小於該第一預定電流時，該比較電壓上升，進而使該延遲時間訊號加長。 The actively clamped flyback converter of claim 3, wherein: When the difference current is equal to the first predetermined current, the comparison voltage remains substantially stable; When the difference current is greater than the first predetermined current, the comparison voltage drops, thereby shortening the delay time signal; When the difference current is smaller than the first predetermined current, the comparison voltage rises, thereby lengthening the delay time signal. 如請求項3所述之主動箝位返馳式轉換器，該比較電壓電路另包含: 一第一開關，包含一第一端，耦接於該第一電流產生器，及一第二端，耦接於該第一電容之該第一端；及 一第二開關，包含一第一端，耦接於該第一電容之該第一端，及一第二端，耦接於該第二電流產生器； 其中該第一開關及該第二開關係依據一短脈衝訊號而導通或截止。 The active-clamp flyback converter as claimed in claim 3, the voltage comparison circuit further comprising: a first switch including a first end coupled to the first current generator, and a second end coupled to the first end of the first capacitor; and a second switch including a first end coupled to the first end of the first capacitor, and a second end coupled to the second current generator; The relationship between the first switch and the second switch is turned on or off according to a short pulse signal. 如請求項2所述之主動箝位返馳式轉換器，其中該延遲電壓電路包含: 一第三電流產生器，用以產生一第二預定電流； 一第三開關，包含一第一端，耦接於該第三電流產生器，一第二端，及一控制端； 一第四開關，包含一第一端，耦接於該第三開關之該第二端，及一第二端，耦接於一接地端；及 一第二電容，用以依據該第二預定電流建立該延遲電壓，包含一第一端，耦接於該第三開關之該第二端，及一第二端，耦接於該接地端。 The actively clamped flyback converter of claim 2, wherein the delay voltage circuit comprises: a third current generator for generating a second predetermined current; a third switch including a first end coupled to the third current generator, a second end, and a control end; a fourth switch including a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to a ground terminal; and A second capacitor for establishing the delay voltage according to the second predetermined current includes a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal. 如請求項6所述之主動箝位返馳式轉換器，其中: 該第三開關之該控制端係耦接於該正反器的該輸入端；及 該致能脈衝係用以控制該第四開關之導通和截止。 The actively clamped flyback converter of claim 6, wherein: The control terminal of the third switch is coupled to the input terminal of the flip-flop; and The enabling pulse is used to control the turn-on and turn-off of the fourth switch. 如請求項2所述之主動箝位返馳式轉換器，其中該延遲時間電路包含: 一比較器，用以依據該延遲電壓及該比較電壓產生一比較訊號，包含一第一輸入端，耦接於該延遲電壓電路，一第二輸入端，耦接於該比較電壓電路，及一輸出端，用以輸出該比較訊號；及 一正反器，包含一輸入端，用以接收一反向致能脈衝，一重置端，耦接於該比較器之該輸出端，用以依據該比較訊號重置該正反器，及一輸出端，用以輸出該延遲時間訊號，該反向致能脈衝與該致能脈衝互為反相。 The actively clamped flyback converter of claim 2, wherein the delay time circuit comprises: a comparator for generating a comparison signal according to the delay voltage and the comparison voltage, comprising a first input terminal coupled to the delay voltage circuit, a second input terminal coupled to the comparison voltage circuit, and a an output terminal for outputting the comparison signal; and a flip-flop comprising an input terminal for receiving a reverse enabling pulse, a reset terminal coupled to the output terminal of the comparator for resetting the flip-flop according to the comparison signal, and An output terminal is used for outputting the delay time signal, and the reverse enabling pulse and the enabling pulse are mutually inverse. 如請求項2所述之主動箝位返馳式轉換器，其中該延遲時間訊號自該致能脈衝之一結束時間點開始，持續到當該延遲電壓遞增到大於該比較電壓時結束。The active clamp flyback converter of claim 2, wherein the delay time signal starts from an end time point of the enable pulse and lasts until the delay voltage increases to be greater than the comparison voltage. 一種主動箝位返馳式轉換器，用以提供一輸出電壓至一負載，包含: 一變壓器，包含: 一一次電路，包含: 一一次線圈，一第一端，用以接收一輸入電壓，及一第二端；及 一二次線圈，包含一第一端，用以輸出一輸出電壓，及一第二端； 一主開關，包含一控制端，一第一端，耦接於該一次線圈之該第二端，及一第二端，該主開關之該第一端具有一開關電壓； 一箝位開關，包含一控制端，一第一端，及一第二端，耦接於該一次線圈之該第二端； 一箝位電容，包含一第一端，耦接於該一次線圈之該第一端，及一第二端，耦接於該箝位開關之第一端； 一開關電流指示電路，耦接於該變壓器，用以依據該開關電壓產生一開關電流指示訊號；及 一控制器，耦接於該開關電流指示電路、該主開關之該控制端及該箝位開關之該控制端，包含: 一參數產生電路，用以在該主開關被導通時測得該開關電流指示訊號之一目標電流值，及在一諧振期間中該箝位開關被施加一致能脈衝後，測得該開關電流指示訊號之一諧振極值；及 一導通時間控制電路，用以依據該目標電流值及該諧振極值調整另一致能脈衝(TGH2)之一脈寬，及在下一諧振期間中對該箝位開關施加該另一致能脈衝。 An active clamp flyback converter for providing an output voltage to a load, comprising: A transformer, containing: A primary circuit, including: a primary coil, a first terminal for receiving an input voltage, and a second terminal; and a secondary coil, comprising a first end for outputting an output voltage, and a second end; a main switch, comprising a control terminal, a first terminal coupled to the second terminal of the primary coil, and a second terminal, the first terminal of the main switch has a switching voltage; a clamping switch, comprising a control terminal, a first terminal, and a second terminal, coupled to the second terminal of the primary coil; a clamping capacitor, comprising a first end coupled to the first end of the primary coil, and a second end coupled to the first end of the clamping switch; a switch current indication circuit, coupled to the transformer, for generating a switch current indication signal according to the switch voltage; and A controller, coupled to the switch current indicating circuit, the control terminal of the main switch and the control terminal of the clamping switch, includes: A parameter generating circuit is used to measure a target current value of the switch current indication signal when the main switch is turned on, and to measure the switch current indication after an enabling pulse is applied to the clamp switch during a resonance period a resonant extreme of the signal; and an on-time control circuit for adjusting a pulse width of another enable pulse (TGH2) according to the target current value and the resonance extreme value, and applying the other enable pulse to the clamp switch in the next resonance period. 如請求項10所述之主動箝位返馳式轉換器，其中該導通時間控制電路包含: 一比較電壓電路，用以依據該目標電流值及該諧振極值建立一比較電壓； 一延遲電壓電路，用以建立一延遲電壓，該延遲電壓自該致能脈衝開始時間點開始遞增；及 一致能脈衝電路，耦接於該比較電壓電路及該延遲電壓電路，用以依據一致能脈衝啓始訊號觸發而產生另一致能脈衝，依據該比較電壓及該延遲電壓決定該另一致能脈衝結束時間點。 The active clamp flyback converter of claim 10, wherein the on-time control circuit comprises: a comparison voltage circuit for establishing a comparison voltage according to the target current value and the resonance extreme value; a delay voltage circuit for establishing a delay voltage, the delay voltage increasing from the start time point of the enable pulse; and an enable pulse circuit, coupled to the comparison voltage circuit and the delay voltage circuit, used for triggering according to an enable pulse start signal to generate another enable pulse, and determining the end of the other enable pulse according to the comparison voltage and the delay voltage point in time. 如請求項11所述之主動箝位返馳式轉換器，其中該比較電壓電路包含: 一第一電流產生器，用以依據該目標電流值及一第一電流產生一第一差值電流； 一第二電流產生器，用以依據該諧振極值及一第二電流產生一第二差值電流；及 一第一電容，用以建立該比較電壓，包含一第一端，耦接於該第一電流產生器及該第二電流產生器，及一第二端，耦接於一接地端。 The actively clamped flyback converter of claim 11, wherein the comparison voltage circuit comprises: a first current generator for generating a first difference current according to the target current value and a first current; a second current generator for generating a second difference current according to the resonance extreme value and a second current; and A first capacitor for establishing the comparison voltage includes a first terminal coupled to the first current generator and the second current generator, and a second terminal coupled to a ground terminal. 如請求項12所述之主動箝位返馳式轉換器，其中: 該比較電壓電路用以將該目標電流值乘以N以產生一偏移目標電流值，N係為小於或等於1之一正數；及 該第一電流產生器用以產生該偏移目標電流值及該第一電流之間之該第一差值電流。 The actively clamped flyback converter of claim 12, wherein: The comparison voltage circuit is used for multiplying the target current value by N to generate an offset target current value, where N is a positive number less than or equal to 1; and The first current generator is used for generating the first difference current between the offset target current value and the first current. 如請求項12所述之主動箝位返馳式轉換器，該比較電壓電路另包含: 一第一開關，包含一第一端，耦接於該第一電流產生器，及一第二端，耦接於該第一電容之該第一端；及 一第二開關，包含一第一端，耦接於該第一電容之該第一端，及一第二端，耦接於該第二電流產生器； 其中該第一開關及該第二開關係依據一短脈衝訊號而導通或截止。 The active-clamp flyback converter of claim 12, the voltage comparison circuit further comprising: a first switch including a first end coupled to the first current generator, and a second end coupled to the first end of the first capacitor; and a second switch including a first end coupled to the first end of the first capacitor, and a second end coupled to the second current generator; The relationship between the first switch and the second switch is turned on or off according to a short pulse signal. 如請求項12所述之主動箝位返馳式轉換器，其中： 當該第一差值電流等於該第二差值電流時，該比較電壓維持實質穩定； 當該第一差值電流小於該第二差值電流時，該比較電壓下降，進而使該另一致能脈衝之該脈寬縮短； 當該第一差值電流大於該第二差值電流時，該比較電壓上升，進而使該該另一致能脈衝之該脈寬加長。 The actively clamped flyback converter of claim 12, wherein: When the first difference current is equal to the second difference current, the comparison voltage remains substantially stable; When the first difference current is smaller than the second difference current, the comparison voltage drops, thereby shortening the pulse width of the other enabling pulse; When the first difference current is greater than the second difference current, the comparison voltage increases, thereby lengthening the pulse width of the other enabling pulse. 如請求項11所述之主動箝位返馳式轉換器，其中該延遲電壓電路包含: 一第三電流產生器，用以產生該預定電流； 一第三開關，包含一第一端，耦接於該第三電流產生器，及一第二端； 一第四開關，包含一第一端，耦接於該第三開關之該第二端，及一第二端，耦接於該接地端；及 一第二電容，用以建立該延遲電壓，包含一第一端，耦接於該第三開關之該第二端，及一第二端，耦接於該接地端； 其中該致能脈衝及一反向致能脈衝係分別用以控制該第三開關與該第四開關之導通和截止，該致能脈衝及該反向致能脈衝係互為反相。 The actively clamped flyback converter of claim 11, wherein the delay voltage circuit comprises: a third current generator for generating the predetermined current; a third switch, comprising a first end coupled to the third current generator, and a second end; a fourth switch including a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal; and a second capacitor for establishing the delay voltage, comprising a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to the ground terminal; The enabling pulse and a reverse enabling pulse are respectively used to control the turn-on and turn-off of the third switch and the fourth switch, and the enabling pulse and the reverse enabling pulse are mutually inverse. 如請求項11所述之主動箝位返馳式轉換器，其中該致能脈衝電路包含: 一比較器，用以依據該延遲電壓及該比較電壓產生一比較訊號，包含一第一輸入端，耦接於該延遲電壓電路，一第二輸入端，耦接於該比較電壓電路，及一輸出端，用以輸出該比較訊號；及 一正反器，包含一輸入端，用以接收一脈衝開始訊號，一重置端，耦接於該比較器之該輸出端，用以依據該比較訊號重置該正反器，及一輸出端，用以輸出該另一致能脈衝。 The active clamp flyback converter of claim 11, wherein the enable pulse circuit comprises: a comparator for generating a comparison signal according to the delay voltage and the comparison voltage, comprising a first input terminal coupled to the delay voltage circuit, a second input terminal coupled to the comparison voltage circuit, and a an output terminal for outputting the comparison signal; and a flip-flop, comprising an input terminal for receiving a pulse start signal, a reset terminal coupled to the output terminal of the comparator for resetting the flip-flop according to the comparison signal, and an output terminal for outputting the other enable pulse. 如請求項1或10所述之主動箝位返馳式轉換器，其中: 該開關電流指示電路包含一輔助線圈與一分壓器； 該輔助線圈包含一第一端，用以提供一輔助線圈電壓，該輔助線圈電壓係正相關於該開關電壓，及一第二端，耦接於一接地端；及 該分壓器包含一第一阻抗，包含一第一端，用以接收該輔助線圈電壓，及一第二端；及一第二阻抗，包含一第一端，耦接於該第一阻抗之該第二端，及一第二端，耦接於一接地端，該輔助線圈電壓經過該分壓器而於該分壓器第一端輸出該開關電流指示訊號。 An actively clamped flyback converter as claimed in claim 1 or 10, wherein: The switch current indicating circuit includes an auxiliary coil and a voltage divider; the auxiliary coil includes a first end for providing an auxiliary coil voltage, the auxiliary coil voltage is positively related to the switching voltage, and a second end coupled to a ground terminal; and The voltage divider includes a first impedance including a first end for receiving the auxiliary coil voltage, and a second end; and a second impedance including a first end coupled to the first end of the impedance The second terminal and a second terminal are coupled to a ground terminal, and the auxiliary coil voltage passes through the voltage divider to output the switch current indication signal at the first terminal of the voltage divider. 一種主動箝位返馳式轉換器，用以提供一輸出電壓至一負載，包含: 一變壓器，包含: 一一次電路，包含: 一一次線圈，一第一端，用以接收一輸入電壓，及一第二端；及 一二次線圈，包含一第一端，用以輸出一輸出電壓，及一第二端； 一主開關，包含一控制端，一第一端，耦接於該一次線圈之該第二端，及一第二端； 一箝位開關，包含一控制端，一第一端，及一第二端，耦接於該一次線圈之該第二端； 一箝位電容，包含一第一端，耦接於該一次線圈之該第一端，及一第二端，耦接於該箝位開關之第一端； 一開關電流指示電路，耦接於該變壓器，用以依據該一次電路之一開關電壓產生一開關電流指示訊號；及 一控制器，耦接於該開關電流指示電路、該主開關之該控制端及該箝位開關之該控制端，包含: 一參數產生電路，用以在該主開關被導通時測得該開關電流指示訊號之一目標電流值，在一諧振期間中該箝位開關被施加一致能脈衝後，測得該開關電流指示訊號之一諧振極值，並且用以在該主開關由截止被轉換為導通狀態過程中，產生該主開關於截止狀態下最後量測所得的該開關電流指示訊號之一切換電流值； 一延遲控制電路，用以依據該切換電流值及該諧振極值調整一延遲時間訊號，在該箝位開關被施加另一致能脈衝後，依據該延遲時間訊號導通該主開關；以及 一導通時間控制電路，用以依據該目標電流值及該諧振極值調整另一致能脈衝之一脈寬，及在下一諧振期間中對該箝位開關施加該另一致能脈衝。 An active clamp flyback converter for providing an output voltage to a load, comprising: A transformer, containing: A primary circuit, including: a primary coil, a first terminal for receiving an input voltage, and a second terminal; and a secondary coil, comprising a first end for outputting an output voltage, and a second end; a main switch, comprising a control terminal, a first terminal coupled to the second terminal of the primary coil, and a second terminal; a clamping switch, comprising a control terminal, a first terminal, and a second terminal, coupled to the second terminal of the primary coil; a clamping capacitor, comprising a first end coupled to the first end of the primary coil, and a second end coupled to the first end of the clamping switch; a switching current indicating circuit, coupled to the transformer, for generating a switching current indicating signal according to a switching voltage of the primary circuit; and A controller, coupled to the switch current indicating circuit, the control terminal of the main switch and the control terminal of the clamping switch, includes: a parameter generating circuit for measuring a target current value of the switch current indicating signal when the main switch is turned on, and measuring the switch current indicating signal after an enabling pulse is applied to the clamp switch during a resonance period a resonance extreme value, and is used to generate a switching current value of the switch current indicating signal obtained by the last measurement of the main switch in the off state during the process of the main switch being converted from the off state to the on state; a delay control circuit for adjusting a delay time signal according to the switching current value and the resonance extreme value, and turning on the main switch according to the delay time signal after another enabling pulse is applied to the clamping switch; and An on-time control circuit is used for adjusting a pulse width of another enabling pulse according to the target current value and the resonance extreme value, and applying the other enabling pulse to the clamping switch in the next resonance period. 如請求項19所述之主動箝位返馳式轉換器，其中: 該延遲控制電路包含一第一比較電壓電路，該第一比較電壓電路依據該諧振極值及該切換電流值產生一第一差值電流，該延遲控制電路調整使該第一差值電流趨近一第一預定電流，進而改變該延遲時間訊號；及 該導通時間控制電路包含一第二比較電壓電路，該第二比較電壓電路依據該諧振極值及該目標電流值產生一第二差值電流，該導通時間控制電路調整使該第二差值電流小於該目標電流值之一固定比例，進而改變該另一致能脈衝之一脈寬。 The actively clamped flyback converter of claim 19, wherein: The delay control circuit includes a first comparison voltage circuit, the first comparison voltage circuit generates a first difference current according to the resonance extreme value and the switching current value, and the delay control circuit adjusts the first difference current to approach a first predetermined current, thereby changing the delay time signal; and The on-time control circuit includes a second comparison voltage circuit, the second comparison voltage circuit generates a second difference current according to the resonance extreme value and the target current value, and the on-time control circuit adjusts the second difference current A fixed ratio smaller than the target current value, thereby changing a pulse width of the other enabling pulse.

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